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Power10 test lsb by byte operation
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
5d57bc3f
AM		 12020-05-11 Alan Modra <amodra@gmail.com>
2
3 * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
4
66ef5847
AM		 52020-05-11 Alan Modra <amodra@gmail.com>
6
7 * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
8 vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
9
4f3e9537
PB		 102020-05-11 Peter Bergner <bergner@linux.ibm.com>
11
12 * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
13 mnemonics.
14
ec40e91c
AM		 152020-05-11 Alan Modra <amodra@gmail.com>
16
17 * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
18 (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
19 vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
20 (prefix_opcodes): Add xxeval.
21
d7e97a76
AM		 222020-05-11 Alan Modra <amodra@gmail.com>
23
24 * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
25 xxgenpcvwm, xxgenpcvdm.
26
fdefed7c
AM		 272020-05-11 Alan Modra <amodra@gmail.com>
28
29 * ppc-opc.c (MP, VXVAM_MASK): Define.
30 (VXVAPS_MASK): Use VXVA_MASK.
31 (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
32 vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
33 vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
34 vcntmbb, vcntmbh, vcntmbw, vcntmbd.
35
aa3c112f
AM		 362020-05-11 Alan Modra <amodra@gmail.com>
37 Peter Bergner <bergner@linux.ibm.com>
38
39 * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
40 New functions.
41 (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
42 YMSK2, XA6a, XA6ap, XB6a entries.
43 (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
44 (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
45 (PPCVSX4): Define.
46 (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
47 xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
48 xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
49 xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
50 xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
51 xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
52 xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
53 (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
54 pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
55 pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
56 pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
57 pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
58 pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
59 pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
60
6edbfd3b
AM		 612020-05-11 Alan Modra <amodra@gmail.com>
62
63 * ppc-opc.c (insert_imm32, extract_imm32): New functions.
64 (insert_xts, extract_xts): New functions.
65 (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
66 (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
67 (VXRC_MASK, VXSH_MASK): Define.
68 (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
69 vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
70 vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
71 vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
72 vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
73 (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
74 xxblendvh, xxblendvw, xxblendvd, xxpermx.
75
c7d7aea2
AM		 762020-05-11 Alan Modra <amodra@gmail.com>
77
78 * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
79 vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
80 vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
81 vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
82 xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
83
94ba9882
AM		 842020-05-11 Alan Modra <amodra@gmail.com>
85
86 * ppc-opc.c (insert_xtp, extract_xtp): New functions.
87 (XTP, DQXP, DQXP_MASK): Define.
88 (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
89 (prefix_opcodes): Add plxvp and pstxvp.
90
f4791f1a
AM		 912020-05-11 Alan Modra <amodra@gmail.com>
92
93 * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
94 vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
95 vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
96
3ff0a5ba
PB		 972020-05-11 Peter Bergner <bergner@linux.ibm.com>
98
99 * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
100
afef4fe9
PB		 1012020-05-11 Peter Bergner <bergner@linux.ibm.com>
102
103 * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
104 (L1OPT): Define.
105 (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
106
1224c05d
PB		 1072020-05-11 Peter Bergner <bergner@linux.ibm.com>
108
109 * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
110
6bbb0c05
AM		 1112020-05-11 Alan Modra <amodra@gmail.com>
112
113 * ppc-dis.c (powerpc_init_dialect): Default to "power10".
114
7c1f4227
AM		 1152020-05-11 Alan Modra <amodra@gmail.com>
116
117 * ppc-dis.c (ppc_opts): Add "power10" entry.
118 (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
119 * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
120
73199c2b
NC		 1212020-05-11 Nick Clifton <nickc@redhat.com>
122
123 * po/fr.po: Updated French translation.
124
09c1e68a
AC		 1252020-04-30 Alex Coplan <alex.coplan@arm.com>
126
127 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
128 * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
129 (operand_general_constraint_met_p): validate
130 AARCH64_OPND_UNDEFINED.
131 * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
132 for FLD_imm16_2.
133 * aarch64-asm-2.c: Regenerated.
134 * aarch64-dis-2.c: Regenerated.
135 * aarch64-opc-2.c: Regenerated.
136
9654d51a
NC		 1372020-04-29 Nick Clifton <nickc@redhat.com>
138
139 PR 22699
140 * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
141 and SETRC insns.
142
c2e71e57
NC		 1432020-04-29 Nick Clifton <nickc@redhat.com>
144
145 * po/sv.po: Updated Swedish translation.
146
5c936ef5
NC		 1472020-04-29 Nick Clifton <nickc@redhat.com>
148
149 PR 22699
150 * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
151 IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
152 * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
153 IMM0_8U case.
154
bb2a1453
AS		 1552020-04-21 Andreas Schwab <schwab@linux-m68k.org>
156
157 PR 25848
158 * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
159 cmpi only on m68020up and cpu32.
160
c2e5c986
SD		 1612020-04-20 Sudakshina Das <sudi.das@arm.com>
162
163 * aarch64-asm.c (aarch64_ins_none): New.
164 * aarch64-asm.h (ins_none): New declaration.
165 * aarch64-dis.c (aarch64_ext_none): New.
166 * aarch64-dis.h (ext_none): New declaration.
167 * aarch64-opc.c (aarch64_print_operand): Update case for
168 AARCH64_OPND_BARRIER_PSB.
169 * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
170 (AARCH64_OPERANDS): Update inserter/extracter for
171 AARCH64_OPND_BARRIER_PSB to use new dummy functions.
172 * aarch64-asm-2.c: Regenerated.
173 * aarch64-dis-2.c: Regenerated.
174 * aarch64-opc-2.c: Regenerated.
175
8a6e1d1d
SD		 1762020-04-20 Sudakshina Das <sudi.das@arm.com>
177
178 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
179 (aarch64_feature_ras, RAS): Likewise.
180 (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
181 (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
182 autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
183 autiaz, autiasp, autibz, autibsp to be CORE_INSN.
184 * aarch64-asm-2.c: Regenerated.
185 * aarch64-dis-2.c: Regenerated.
186 * aarch64-opc-2.c: Regenerated.
187
e409955d
FS		 1882020-04-17 Fredrik Strupe <fredrik@strupe.net>
189
190 * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
191 (print_insn_neon): Support disassembly of conditional
192 instructions.
193
c54a9b56
DF		 1942020-02-16 David Faust <david.faust@oracle.com>
195
196 * bpf-desc.c: Regenerate.
197 * bpf-desc.h: Likewise.
198 * bpf-opc.c: Regenerate.
199 * bpf-opc.h: Likewise.
200
bb651e8b
CL		 2012020-04-07 Lili Cui <lili.cui@intel.com>
202
203 * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
204 (prefix_table): New instructions (see prefixes above).
205 (rm_table): Likewise
206 * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
207 CPU_ANY_TSXLDTRK_FLAGS.
208 (cpu_flags): Add CpuTSXLDTRK.
209 * i386-opc.h (enum): Add CpuTSXLDTRK.
210 (i386_cpu_flags): Add cputsxldtrk.
211 * i386-opc.tbl: Add XSUSPLDTRK insns.
212 * i386-init.h: Regenerate.
213 * i386-tbl.h: Likewise.
214
4b27d27c
L		 2152020-04-02 Lili Cui <lili.cui@intel.com>
216
217 * i386-dis.c (prefix_table): New instructions serialize.
218 * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
219 CPU_ANY_SERIALIZE_FLAGS.
220 (cpu_flags): Add CpuSERIALIZE.
221 * i386-opc.h (enum): Add CpuSERIALIZE.
222 (i386_cpu_flags): Add cpuserialize.
223 * i386-opc.tbl: Add SERIALIZE insns.
224 * i386-init.h: Regenerate.
225 * i386-tbl.h: Likewise.
226
832a5807
AM		 2272020-03-26 Alan Modra <amodra@gmail.com>
228
229 * disassemble.h (opcodes_assert): Declare.
230 (OPCODES_ASSERT): Define.
231 * disassemble.c: Don't include assert.h. Include opintl.h.
232 (opcodes_assert): New function.
233 * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
234 (bfd_h8_disassemble): Reduce size of data array. Correctly
235 calculate maxlen. Omit insn decoding when insn length exceeds
236 maxlen. Exit from nibble loop when looking for E, before
237 accessing next data byte. Move processing of E outside loop.
238 Replace tests of maxlen in loop with assertions.
239
4c4addbe
AM		 2402020-03-26 Alan Modra <amodra@gmail.com>
241
242 * arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
243
a18cd0ca
AM		 2442020-03-25 Alan Modra <amodra@gmail.com>
245
246 * z80-dis.c (suffix): Init mybuf.
247
57cb32b3
AM		 2482020-03-22 Alan Modra <amodra@gmail.com>
249
250 * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
251 successflly read from section.
252
beea5cc1
AM		 2532020-03-22 Alan Modra <amodra@gmail.com>
254
255 * arc-dis.c (find_format): Use ISO C string concatenation rather
256 than line continuation within a string. Don't access needs_limm
257 before testing opcode != NULL.
258
03704c77
AM		 2592020-03-22 Alan Modra <amodra@gmail.com>
260
261 * ns32k-dis.c (print_insn_arg): Update comment.
262 (print_insn_ns32k): Reduce size of index_offset array, and
263 initialize, passing -1 to print_insn_arg for args that are not
264 an index. Don't exit arg loop early. Abort on bad arg number.
265
d1023b5d
AM		 2662020-03-22 Alan Modra <amodra@gmail.com>
267
268 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
269 * s12z-opc.c: Formatting.
270 (operands_f): Return an int.
271 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
272 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
273 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
274 (exg_sex_discrim): Likewise.
275 (create_immediate_operand, create_bitfield_operand),
276 (create_register_operand_with_size, create_register_all_operand),
277 (create_register_all16_operand, create_simple_memory_operand),
278 (create_memory_operand, create_memory_auto_operand): Don't
279 segfault on malloc failure.
280 (z_ext24_decode): Return an int status, negative on fail, zero
281 on success.
282 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
283 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
284 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
285 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
286 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
287 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
288 (loop_primitive_decode, shift_decode, psh_pul_decode),
289 (bit_field_decode): Similarly.
290 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
291 to return value, update callers.
292 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
293 Don't segfault on NULL operand.
294 (decode_operation): Return OP_INVALID on first fail.
295 (decode_s12z): Check all reads, returning -1 on fail.
296
340f3ac8
AM		 2972020-03-20 Alan Modra <amodra@gmail.com>
298
299 * metag-dis.c (print_insn_metag): Don't ignore status from
300 read_memory_func.
301
fe90ae8a
AM		 3022020-03-20 Alan Modra <amodra@gmail.com>
303
304 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
305 Initialize parts of buffer not written when handling a possible
306 2-byte insn at end of section. Don't attempt decoding of such
307 an insn by the 4-byte machinery.
308
833d919c
AM		 3092020-03-20 Alan Modra <amodra@gmail.com>
310
311 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
312 partially filled buffer. Prevent lookup of 4-byte insns when
313 only VLE 2-byte insns are possible due to section size. Print
314 ".word" rather than ".long" for 2-byte leftovers.
315
327ef784
NC		 3162020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
317
318 PR 25641
319 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
320
1673df32
JB		 3212020-03-13 Jan Beulich <jbeulich@suse.com>
322
323 * i386-dis.c (X86_64_0D): Rename to ...
324 (X86_64_0E): ... this.
325
384f3689
L		 3262020-03-09 H.J. Lu <hongjiu.lu@intel.com>
327
328 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
329 * Makefile.in: Regenerated.
330
865e2027
JB		 3312020-03-09 Jan Beulich <jbeulich@suse.com>
332
333 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
334 3-operand pseudos.
335 * i386-tbl.h: Re-generate.
336
2f13234b
JB		 3372020-03-09 Jan Beulich <jbeulich@suse.com>
338
339 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
340 vprot*, vpsha*, and vpshl*.
341 * i386-tbl.h: Re-generate.
342
3fabc179
JB		 3432020-03-09 Jan Beulich <jbeulich@suse.com>
344
345 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
346 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
347 * i386-tbl.h: Re-generate.
348
3677e4c1
JB		 3492020-03-09 Jan Beulich <jbeulich@suse.com>
350
351 * i386-gen.c (set_bitfield): Ignore zero-length field names.
352 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
353 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
354 * i386-tbl.h: Re-generate.
355
4c4898e8
JB		 3562020-03-09 Jan Beulich <jbeulich@suse.com>
357
358 * i386-gen.c (struct template_arg, struct template_instance,
359 struct template_param, struct template, templates,
360 parse_template, expand_templates): New.
361 (process_i386_opcodes): Various local variables moved to
362 expand_templates. Call parse_template and expand_templates.
363 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
364 * i386-tbl.h: Re-generate.
365
bc49bfd8
JB		 3662020-03-06 Jan Beulich <jbeulich@suse.com>
367
368 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
369 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
370 register and memory source templates. Replace VexW= by VexW*
371 where applicable.
372 * i386-tbl.h: Re-generate.
373
4873e243
JB		 3742020-03-06 Jan Beulich <jbeulich@suse.com>
375
376 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
377 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
378 * i386-tbl.h: Re-generate.
379
672a349b
JB		 3802020-03-06 Jan Beulich <jbeulich@suse.com>
381
382 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
383 * i386-tbl.h: Re-generate.
384
4ed21b58
JB		 3852020-03-06 Jan Beulich <jbeulich@suse.com>
386
387 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
388 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
389 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
390 VexW0 on SSE2AVX variants.
391 (vmovq): Drop NoRex64 from XMM/XMM variants.
392 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
393 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
394 applicable use VexW0.
395 * i386-tbl.h: Re-generate.
396
643bb870
JB		 3972020-03-06 Jan Beulich <jbeulich@suse.com>
398
399 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
400 * i386-opc.h (Rex64): Delete.
401 (struct i386_opcode_modifier): Remove rex64 field.
402 * i386-opc.tbl (crc32): Drop Rex64.
403 Replace Rex64 with Size64 everywhere else.
404 * i386-tbl.h: Re-generate.
405
a23b33b3
JB		 4062020-03-06 Jan Beulich <jbeulich@suse.com>
407
408 * i386-dis.c (OP_E_memory): Exclude recording of used address
409 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
410 addressed memory operands for MPX insns.
411
a0497384
JB		 4122020-03-06 Jan Beulich <jbeulich@suse.com>
413
414 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
415 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
416 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
417 (ptwrite): Split into non-64-bit and 64-bit forms.
418 * i386-tbl.h: Re-generate.
419
b630c145
JB		 4202020-03-06 Jan Beulich <jbeulich@suse.com>
421
422 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
423 template.
424 * i386-tbl.h: Re-generate.
425
a847e322
JB		 4262020-03-04 Jan Beulich <jbeulich@suse.com>
427
428 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
429 (prefix_table): Move vmmcall here. Add vmgexit.
430 (rm_table): Replace vmmcall entry by prefix_table[] escape.
431 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
432 (cpu_flags): Add CpuSEV_ES entry.
433 * i386-opc.h (CpuSEV_ES): New.
434 (union i386_cpu_flags): Add cpusev_es field.
435 * i386-opc.tbl (vmgexit): New.
436 * i386-init.h, i386-tbl.h: Re-generate.
437
3cd7f3e3
L		 4382020-03-03 H.J. Lu <hongjiu.lu@intel.com>
439
440 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
441 with MnemonicSize.
442 * i386-opc.h (IGNORESIZE): New.
443 (DEFAULTSIZE): Likewise.
444 (IgnoreSize): Removed.
445 (DefaultSize): Likewise.
446 (MnemonicSize): New.
447 (i386_opcode_modifier): Replace ignoresize/defaultsize with
448 mnemonicsize.
449 * i386-opc.tbl (IgnoreSize): New.
450 (DefaultSize): Likewise.
451 * i386-tbl.h: Regenerated.
452
b8ba1385
SB		 4532020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
454
455 PR 25627
456 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
457 instructions.
458
10d97a0f
L		 4592020-03-03 H.J. Lu <hongjiu.lu@intel.com>
460
461 PR gas/25622
462 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
463 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
464 * i386-tbl.h: Regenerated.
465
dc1e8a47
AM		 4662020-02-26 Alan Modra <amodra@gmail.com>
467
468 * aarch64-asm.c: Indent labels correctly.
469 * aarch64-dis.c: Likewise.
470 * aarch64-gen.c: Likewise.
471 * aarch64-opc.c: Likewise.
472 * alpha-dis.c: Likewise.
473 * i386-dis.c: Likewise.
474 * nds32-asm.c: Likewise.
475 * nfp-dis.c: Likewise.
476 * visium-dis.c: Likewise.
477
265b4673
CZ		 4782020-02-25 Claudiu Zissulescu <claziss@gmail.com>
479
480 * arc-regs.h (int_vector_base): Make it available for all ARC
481 CPUs.
482
bd0cf5a6
NC		 4832020-02-20 Nelson Chu <nelson.chu@sifive.com>
484
485 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
486 changed.
487
fa164239
JW		 4882020-02-19 Nelson Chu <nelson.chu@sifive.com>
489
490 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
491 c.mv/c.li if rs1 is zero.
492
272a84b1
L		 4932020-02-17 H.J. Lu <hongjiu.lu@intel.com>
494
495 * i386-gen.c (cpu_flag_init): Replace CpuABM with
496 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
497 CPU_POPCNT_FLAGS.
498 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
499 * i386-opc.h (CpuABM): Removed.
500 (CpuPOPCNT): New.
501 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
502 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
503 popcnt. Remove CpuABM from lzcnt.
504 * i386-init.h: Regenerated.
505 * i386-tbl.h: Likewise.
506
1f730c46
JB		 5072020-02-17 Jan Beulich <jbeulich@suse.com>
508
509 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
510 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
511 VexW1 instead of open-coding them.
512 * i386-tbl.h: Re-generate.
513
c8f8eebc
JB		 5142020-02-17 Jan Beulich <jbeulich@suse.com>
515
516 * i386-opc.tbl (AddrPrefixOpReg): Define.
517 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
518 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
519 templates. Drop NoRex64.
520 * i386-tbl.h: Re-generate.
521
b9915cbc
JB		 5222020-02-17 Jan Beulich <jbeulich@suse.com>
523
524 PR gas/6518
525 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
526 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
527 into Intel syntax instance (with Unpsecified) and AT&T one
528 (without).
529 (vcvtneps2bf16): Likewise, along with folding the two so far
530 separate ones.
531 * i386-tbl.h: Re-generate.
532
ce504911
L		 5332020-02-16 H.J. Lu <hongjiu.lu@intel.com>
534
535 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
536 CPU_ANY_SSE4A_FLAGS.
537
dabec65d
AM		 5382020-02-17 Alan Modra <amodra@gmail.com>
539
540 * i386-gen.c (cpu_flag_init): Correct last change.
541
af5c13b0
L		 5422020-02-16 H.J. Lu <hongjiu.lu@intel.com>
543
544 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
545 CPU_ANY_SSE4_FLAGS.
546
6867aac0
L		 5472020-02-14 H.J. Lu <hongjiu.lu@intel.com>
548
549 * i386-opc.tbl (movsx): Remove Intel syntax comments.
550 (movzx): Likewise.
551
65fca059
JB		 5522020-02-14 Jan Beulich <jbeulich@suse.com>
553
554 PR gas/25438
555 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
556 destination for Cpu64-only variant.
557 (movzx): Fold patterns.
558 * i386-tbl.h: Re-generate.
559
7deea9aa
JB		 5602020-02-13 Jan Beulich <jbeulich@suse.com>
561
562 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
563 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
564 CPU_ANY_SSE4_FLAGS entry.
565 * i386-init.h: Re-generate.
566
6c0946d0
JB		 5672020-02-12 Jan Beulich <jbeulich@suse.com>
568
569 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
570 with Unspecified, making the present one AT&T syntax only.
571 * i386-tbl.h: Re-generate.
572
ddb56fe6
JB		 5732020-02-12 Jan Beulich <jbeulich@suse.com>
574
575 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
576 * i386-tbl.h: Re-generate.
577
5990e377
JB		 5782020-02-12 Jan Beulich <jbeulich@suse.com>
579
580 PR gas/24546
581 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
582 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
583 Amd64 and Intel64 templates.
584 (call, jmp): Likewise for far indirect variants. Dro
585 Unspecified.
586 * i386-tbl.h: Re-generate.
587
50128d0c
JB		 5882020-02-11 Jan Beulich <jbeulich@suse.com>
589
590 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
591 * i386-opc.h (ShortForm): Delete.
592 (struct i386_opcode_modifier): Remove shortform field.
593 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
594 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
595 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
596 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
597 Drop ShortForm.
598 * i386-tbl.h: Re-generate.
599
1e05b5c4
JB		 6002020-02-11 Jan Beulich <jbeulich@suse.com>
601
602 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
603 fucompi): Drop ShortForm from operand-less templates.
604 * i386-tbl.h: Re-generate.
605
2f5dd314
AM		 6062020-02-11 Alan Modra <amodra@gmail.com>
607
608 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
609 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
610 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
611 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
612 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
613
5aae9ae9
MM		 6142020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
615
616 * arm-dis.c (print_insn_cde): Define 'V' parse character.
617 (cde_opcodes): Add VCX* instructions.
618
4934a27c
MM		 6192020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
620 Matthew Malcomson <matthew.malcomson@arm.com>
621
622 * arm-dis.c (struct cdeopcode32): New.
623 (CDE_OPCODE): New macro.
624 (cde_opcodes): New disassembly table.
625 (regnames): New option to table.
626 (cde_coprocs): New global variable.
627 (print_insn_cde): New
628 (print_insn_thumb32): Use print_insn_cde.
629 (parse_arm_disassembler_options): Parse coprocN args.
630
4b5aaf5f
L		 6312020-02-10 H.J. Lu <hongjiu.lu@intel.com>
632
633 PR gas/25516
634 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
635 with ISA64.
636 * i386-opc.h (AMD64): Removed.
637 (Intel64): Likewose.
638 (AMD64): New.
639 (INTEL64): Likewise.
640 (INTEL64ONLY): Likewise.
641 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
642 * i386-opc.tbl (Amd64): New.
643 (Intel64): Likewise.
644 (Intel64Only): Likewise.
645 Replace AMD64 with Amd64. Update sysenter/sysenter with
646 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
647 * i386-tbl.h: Regenerated.
648
9fc0b501
SB		 6492020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
650
651 PR 25469
652 * z80-dis.c: Add support for GBZ80 opcodes.
653
c5d7be0c
AM		 6542020-02-04 Alan Modra <amodra@gmail.com>
655
656 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
657
44e4546f
AM		 6582020-02-03 Alan Modra <amodra@gmail.com>
659
660 * m32c-ibld.c: Regenerate.
661
b2b1453a
AM		 6622020-02-01 Alan Modra <amodra@gmail.com>
663
664 * frv-ibld.c: Regenerate.
665
4102be5c
JB		 6662020-01-31 Jan Beulich <jbeulich@suse.com>
667
668 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
669 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
670 (OP_E_memory): Replace xmm_mdq_mode case label by
671 vex_scalar_w_dq_mode one.
672 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
673
825bd36c
JB		 6742020-01-31 Jan Beulich <jbeulich@suse.com>
675
676 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
677 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
678 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
679 (intel_operand_size): Drop vex_w_dq_mode case label.
680
c3036ed0
RS		 6812020-01-31 Richard Sandiford <richard.sandiford@arm.com>
682
683 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
684 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
685
0c115f84
AM		 6862020-01-30 Alan Modra <amodra@gmail.com>
687
688 * m32c-ibld.c: Regenerate.
689
bd434cc4
JM		 6902020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
691
692 * bpf-opc.c: Regenerate.
693
aeab2b26
JB		 6942020-01-30 Jan Beulich <jbeulich@suse.com>
695
696 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
697 (dis386): Use them to replace C2/C3 table entries.
698 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
699 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
700 ones. Use Size64 instead of DefaultSize on Intel64 ones.
701 * i386-tbl.h: Re-generate.
702
62b3f548
JB		 7032020-01-30 Jan Beulich <jbeulich@suse.com>
704
705 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
706 forms.
707 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
708 DefaultSize.
709 * i386-tbl.h: Re-generate.
710
1bd8ae10
AM		 7112020-01-30 Alan Modra <amodra@gmail.com>
712
713 * tic4x-dis.c (tic4x_dp): Make unsigned.
714
bc31405e
L		 7152020-01-27 H.J. Lu <hongjiu.lu@intel.com>
716 Jan Beulich <jbeulich@suse.com>
717
718 PR binutils/25445
719 * i386-dis.c (MOVSXD_Fixup): New function.
720 (movsxd_mode): New enum.
721 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
722 (intel_operand_size): Handle movsxd_mode.
723 (OP_E_register): Likewise.
724 (OP_G): Likewise.
725 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
726 register on movsxd. Add movsxd with 16-bit destination register
727 for AMD64 and Intel64 ISAs.
728 * i386-tbl.h: Regenerated.
729
7568c93b
TC		 7302020-01-27 Tamar Christina <tamar.christina@arm.com>
731
732 PR 25403
733 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
734 * aarch64-asm-2.c: Regenerate
735 * aarch64-dis-2.c: Likewise.
736 * aarch64-opc-2.c: Likewise.
737
c006a730
JB		 7382020-01-21 Jan Beulich <jbeulich@suse.com>
739
740 * i386-opc.tbl (sysret): Drop DefaultSize.
741 * i386-tbl.h: Re-generate.
742
c906a69a
JB		 7432020-01-21 Jan Beulich <jbeulich@suse.com>
744
745 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
746 Dword.
747 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
748 * i386-tbl.h: Re-generate.
749
26916852
NC		 7502020-01-20 Nick Clifton <nickc@redhat.com>
751
752 * po/de.po: Updated German translation.
753 * po/pt_BR.po: Updated Brazilian Portuguese translation.
754 * po/uk.po: Updated Ukranian translation.
755
4d6cbb64
AM		 7562020-01-20 Alan Modra <amodra@gmail.com>
757
758 * hppa-dis.c (fput_const): Remove useless cast.
759
2bddb71a
AM		 7602020-01-20 Alan Modra <amodra@gmail.com>
761
762 * arm-dis.c (print_insn_arm): Wrap 'T' value.
763
1b1bb2c6
NC		 7642020-01-18 Nick Clifton <nickc@redhat.com>
765
766 * configure: Regenerate.
767 * po/opcodes.pot: Regenerate.
768
ae774686
NC		 7692020-01-18 Nick Clifton <nickc@redhat.com>
770
771 Binutils 2.34 branch created.
772
07f1f3aa
CB		 7732020-01-17 Christian Biesinger <cbiesinger@google.com>
774
775 * opintl.h: Fix spelling error (seperate).
776
42e04b36
L		 7772020-01-17 H.J. Lu <hongjiu.lu@intel.com>
778
779 * i386-opc.tbl: Add {vex} pseudo prefix.
780 * i386-tbl.h: Regenerated.
781
2da2eaf4
AV		 7822020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
783
784 PR 25376
785 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
786 (neon_opcodes): Likewise.
787 (select_arm_features): Make sure we enable MVE bits when selecting
788 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
789 any architecture.
790
d0849eed
JB		 7912020-01-16 Jan Beulich <jbeulich@suse.com>
792
793 * i386-opc.tbl: Drop stale comment from XOP section.
794
9cf70a44
JB		 7952020-01-16 Jan Beulich <jbeulich@suse.com>
796
797 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
798 (extractps): Add VexWIG to SSE2AVX forms.
799 * i386-tbl.h: Re-generate.
800
4814632e
JB		 8012020-01-16 Jan Beulich <jbeulich@suse.com>
802
803 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
804 Size64 from and use VexW1 on SSE2AVX forms.
805 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
806 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
807 * i386-tbl.h: Re-generate.
808
aad09917
AM		 8092020-01-15 Alan Modra <amodra@gmail.com>
810
811 * tic4x-dis.c (tic4x_version): Make unsigned long.
812 (optab, optab_special, registernames): New file scope vars.
813 (tic4x_print_register): Set up registernames rather than
814 malloc'd registertable.
815 (tic4x_disassemble): Delete optable and optable_special. Use
816 optab and optab_special instead. Throw away old optab,
817 optab_special and registernames when info->mach changes.
818
7a6bf3be
SB		 8192020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
820
821 PR 25377
822 * z80-dis.c (suffix): Use .db instruction to generate double
823 prefix.
824
ca1eaac0
AM		 8252020-01-14 Alan Modra <amodra@gmail.com>
826
827 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
828 values to unsigned before shifting.
829
1d67fe3b
TT		 8302020-01-13 Thomas Troeger <tstroege@gmx.de>
831
832 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
833 flow instructions.
834 (print_insn_thumb16, print_insn_thumb32): Likewise.
835 (print_insn): Initialize the insn info.
836 * i386-dis.c (print_insn): Initialize the insn info fields, and
837 detect jumps.
838
5e4f7e05
CZ		 8392012-01-13 Claudiu Zissulescu <claziss@gmail.com>
840
841 * arc-opc.c (C_NE): Make it required.
842
b9fe6b8a
CZ		 8432012-01-13 Claudiu Zissulescu <claziss@gmail.com>
844
845 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
846 reserved register name.
847
90dee485
AM		 8482020-01-13 Alan Modra <amodra@gmail.com>
849
850 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
851 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
852
febda64f
AM		 8532020-01-13 Alan Modra <amodra@gmail.com>
854
855 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
856 result of wasm_read_leb128 in a uint64_t and check that bits
857 are not lost when copying to other locals. Use uint32_t for
858 most locals. Use PRId64 when printing int64_t.
859
df08b588
AM		 8602020-01-13 Alan Modra <amodra@gmail.com>
861
862 * score-dis.c: Formatting.
863 * score7-dis.c: Formatting.
864
b2c759ce
AM		 8652020-01-13 Alan Modra <amodra@gmail.com>
866
867 * score-dis.c (print_insn_score48): Use unsigned variables for
868 unsigned values. Don't left shift negative values.
869 (print_insn_score32): Likewise.
870 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
871
5496abe1
AM		 8722020-01-13 Alan Modra <amodra@gmail.com>
873
874 * tic4x-dis.c (tic4x_print_register): Remove dead code.
875
202e762b
AM		 8762020-01-13 Alan Modra <amodra@gmail.com>
877
878 * fr30-ibld.c: Regenerate.
879
7ef412cf
AM		 8802020-01-13 Alan Modra <amodra@gmail.com>
881
882 * xgate-dis.c (print_insn): Don't left shift signed value.
883 (ripBits): Formatting, use 1u.
884
7f578b95
AM		 8852020-01-10 Alan Modra <amodra@gmail.com>
886
887 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
888 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
889
441af85b
AM		 8902020-01-10 Alan Modra <amodra@gmail.com>
891
892 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
893 and XRREG value earlier to avoid a shift with negative exponent.
894 * m10200-dis.c (disassemble): Similarly.
895
bce58db4
NC		 8962020-01-09 Nick Clifton <nickc@redhat.com>
897
898 PR 25224
899 * z80-dis.c (ld_ii_ii): Use correct cast.
900
40c75bc8
SB		 9012020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
902
903 PR 25224
904 * z80-dis.c (ld_ii_ii): Use character constant when checking
905 opcode byte value.
906
d835a58b
JB		 9072020-01-09 Jan Beulich <jbeulich@suse.com>
908
909 * i386-dis.c (SEP_Fixup): New.
910 (SEP): Define.
911 (dis386_twobyte): Use it for sysenter/sysexit.
912 (enum x86_64_isa): Change amd64 enumerator to value 1.
913 (OP_J): Compare isa64 against intel64 instead of amd64.
914 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
915 forms.
916 * i386-tbl.h: Re-generate.
917
030a2e78
AM		 9182020-01-08 Alan Modra <amodra@gmail.com>
919
920 * z8k-dis.c: Include libiberty.h
921 (instr_data_s): Make max_fetched unsigned.
922 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
923 Don't exceed byte_info bounds.
924 (output_instr): Make num_bytes unsigned.
925 (unpack_instr): Likewise for nibl_count and loop.
926 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
927 idx unsigned.
928 * z8k-opc.h: Regenerate.
929
bb82aefe
SV		 9302020-01-07 Shahab Vahedi <shahab@synopsys.com>
931
932 * arc-tbl.h (llock): Use 'LLOCK' as class.
933 (llockd): Likewise.
934 (scond): Use 'SCOND' as class.
935 (scondd): Likewise.
936 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
937 (scondd): Likewise.
938
cc6aa1a6
AM		 9392020-01-06 Alan Modra <amodra@gmail.com>
940
941 * m32c-ibld.c: Regenerate.
942
660e62b1
AM		 9432020-01-06 Alan Modra <amodra@gmail.com>
944
945 PR 25344
946 * z80-dis.c (suffix): Don't use a local struct buffer copy.
947 Peek at next byte to prevent recursion on repeated prefix bytes.
948 Ensure uninitialised "mybuf" is not accessed.
949 (print_insn_z80): Don't zero n_fetch and n_used here,..
950 (print_insn_z80_buf): ..do it here instead.
951
c9ae58fe
AM		 9522020-01-04 Alan Modra <amodra@gmail.com>
953
954 * m32r-ibld.c: Regenerate.
955
5f57d4ec
AM		 9562020-01-04 Alan Modra <amodra@gmail.com>
957
958 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
959
2c5c1196
AM		 9602020-01-04 Alan Modra <amodra@gmail.com>
961
962 * crx-dis.c (match_opcode): Avoid shift left of signed value.
963
2e98c6c5
AM		 9642020-01-04 Alan Modra <amodra@gmail.com>
965
966 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
967
567dfba2
JB		 9682020-01-03 Jan Beulich <jbeulich@suse.com>
969
5437a02a
JB		 970 * aarch64-tbl.h (aarch64_opcode_table): Use
971 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
972
9732020-01-03 Jan Beulich <jbeulich@suse.com>
974
975 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
567dfba2
JB		 976 forms of SUDOT and USDOT.
977
8c45011a
JB		 9782020-01-03 Jan Beulich <jbeulich@suse.com>
979
5437a02a 980 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
8c45011a
JB		 981 uzip{1,2}.
982 * opcodes/aarch64-dis-2.c: Re-generate.
983
f4950f76
JB		 9842020-01-03 Jan Beulich <jbeulich@suse.com>
985
5437a02a 986 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
f4950f76
JB		 987 FMMLA encoding.
988 * opcodes/aarch64-dis-2.c: Re-generate.
989
6655dba2
SB		 9902020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
991
992 * z80-dis.c: Add support for eZ80 and Z80 instructions.
993
b14ce8bf
AM		 9942020-01-01 Alan Modra <amodra@gmail.com>
995
996 Update year range in copyright notice of all files.
997
0b114740 998For older changes see ChangeLog-2019
3499769a 999\f
0b114740 1000Copyright (C) 2020 Free Software Foundation, Inc.
3499769a
AM		 1001
1002Copying and distribution of this file, with or without modification,
1003are permitted in any medium without royalty provided the copyright
1004notice and this notice are preserved.
1005
1006Local Variables:
1007mode: change-log
1008left-margin: 8
1009fill-column: 74
1010version-control: never
1011End:
GDB Binutils - Deliverables
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