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x86: adjust st(<N>) parsing
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
6288d05f
JB		 12021-03-30 Jan Beulich <jbeulich@suse.com>
2
3 * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Adjust values.
4 * i386-reg.tbl (st): Move down.
5 (st(0)): Delete. Extend comment.
6 * i386-tbl.h: Re-generate.
7
bbe1eca6
JB		 82021-03-29 Jan Beulich <jbeulich@suse.com>
9
10 * i386-opc.tbl (movq, movabs): Move next to mov counterparts.
11 (cmpsd): Move next to cmps.
12 (movsd): Move next to movs.
13 (cmpxchg16b): Move to separate section.
14 (fisttp, fisttpll): Likewise.
15 (monitor, mwait): Likewise.
16 * i386-tbl.h: Re-generate.
17
c8cad9d3
JB		 182021-03-29 Jan Beulich <jbeulich@suse.com>
19
20 * i386-opc.tbl (psadbw): Add <sse2:comm>.
21 (vpsadbw): Add C.
22 * i386-tbl.h: Re-generate.
23
5cdaf100
JB		 242021-03-29 Jan Beulich <jbeulich@suse.com>
25
26 * i386-opc.tbl (mmx, sse, sse2, sse3, ssse3, sse41, sse42, aes,
27 pclmul, gfni): New templates. Use them wherever possible. Move
28 SSE4.1 pextrw into respective section.
29 * i386-tbl.h: Re-generate.
30
73e45eb2
JB		 312021-03-29 Jan Beulich <jbeulich@suse.com>
32
33 * i386-gen.c (output_i386_opcode): Widen type of "opcode". Use
34 strtoull(). Bump upper loop bound. Widen masks. Sanity check
35 "length".
36 * i386-opc.tbl (Prefix_0X66, Prefix_0XF2, Prefix_0XF3): Delete.
37 Convert all of their uses to representation in opcode.
38
9df6f676
JB		 392021-03-29 Jan Beulich <jbeulich@suse.com>
40
41 * i386-opc.h (struct insn_template): Shrink base_opcode to 16
42 bits. Shrink extension_opcode to 9 bits. Make it signed. Change
43 value of None. Shrink operands to 3 bits.
44
389d00a5
JB		 452021-03-29 Jan Beulich <jbeulich@suse.com>
46
47 * i386-gen.c (process_i386_opcode_modifier): New parameter
48 "space".
49 (output_i386_opcode): New local variable "space". Adjust
50 process_i386_opcode_modifier() invocation.
51 (process_i386_opcodes): Adjust process_i386_opcode_modifier()
52 invocation.
53 * i386-tbl.h: Re-generate.
54
63b4cc53
AM		 552021-03-29 Alan Modra <amodra@gmail.com>
56
57 * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
58 (fp_qualifier_p, get_data_pattern): Likewise.
59 (aarch64_get_operand_modifier_from_value): Likewise.
60 (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
61 (operand_variant_qualifier_p): Likewise.
62 (qualifier_value_in_range_constraint_p): Likewise.
63 (aarch64_get_qualifier_esize): Likewise.
64 (aarch64_get_qualifier_nelem): Likewise.
65 (aarch64_get_qualifier_standard_value): Likewise.
66 (get_lower_bound, get_upper_bound): Likewise.
67 (aarch64_find_best_match, match_operands_qualifier): Likewise.
68 (aarch64_print_operand): Likewise.
69 * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
70 (operand_need_sign_extension, operand_need_shift_by_two): Likewise.
71 (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
72 * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
73 * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
74 (print_insn_tic6x): Likewise.
75
3d7d6c1b
AM		 762021-03-29 Alan Modra <amodra@gmail.com>
77
78 * arc-dis.c (extract_operand_value): Correct NULL cast.
79 * frv-opc.h: Regenerate.
80
c3344b62
JB		 812021-03-26 Jan Beulich <jbeulich@suse.com>
82
83 * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to
84 MMX form.
85 * i386-tbl.h: Re-generate.
86
efa30ac3
HAQ		 872021-03-25 Abid Qadeer <abidh@codesourcery.com>
88
89 * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
90 immediate in br.n instruction.
91
596a02ff
JB		 922021-03-25 Jan Beulich <jbeulich@suse.com>
93
94 * i386-dis.c (XMGatherD, VexGatherD): New.
95 (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
96 (print_insn): Check masking for S/G insns.
97 (OP_E_memory): New local variable check_gather. Extend mandatory
98 SIB check. Check register conflicts for (EVEX-encoded) gathers.
99 Extend check for disallowed 16-bit addressing.
100 (OP_VEX): New local variables modrm_reg and sib_index. Convert
101 if()s to switch(). Check register conflicts for (VEX-encoded)
102 gathers. Drop no longer reachable cases.
103 * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
104 vgatherdp*.
105
53642852
JB		 1062021-03-25 Jan Beulich <jbeulich@suse.com>
107
108 * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
109 zeroing-masking without masking.
110
c0e54661
JB		 1112021-03-25 Jan Beulich <jbeulich@suse.com>
112
113 * i386-opc.tbl (invlpgb): Fix multi-operand form.
114 (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
115 single-operand forms as deprecated.
116 * i386-tbl.h: Re-generate.
117
5a403766
AM		 1182021-03-25 Alan Modra <amodra@gmail.com>
119
120 PR 27647
121 * ppc-opc.c (XLOCB_MASK): Delete.
122 (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
123 XLBH_MASK.
124 (powerpc_opcodes): Accept a BH field on all extended forms of
125 bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
126
9a182d04
JB		 1272021-03-24 Jan Beulich <jbeulich@suse.com>
128
129 * i386-gen.c (output_i386_opcode): Drop processing of
130 opcode_length. Calculate length from base_opcode. Adjust prefix
131 encoding determination.
132 (process_i386_opcodes): Drop output of fake opcode_length.
133 * i386-opc.h (struct insn_template): Drop opcode_length field.
134 * i386-opc.tbl: Drop opcode length field from all templates.
135 * i386-tbl.h: Re-generate.
136
35648716
JB		 1372021-03-24 Jan Beulich <jbeulich@suse.com>
138
139 * i386-gen.c (process_i386_opcode_modifier): Return void. New
140 parameter "prefix". Drop local variable "regular_encoding".
141 Record prefix setting / check for consistency.
142 (output_i386_opcode): Parse opcode_length and base_opcode
143 earlier. Derive prefix encoding. Drop no longer applicable
144 consistency checking. Adjust process_i386_opcode_modifier()
145 invocation.
146 (process_i386_opcodes): Adjust process_i386_opcode_modifier()
147 invocation.
148 * i386-tbl.h: Re-generate.
149
31184569
JB		 1502021-03-24 Jan Beulich <jbeulich@suse.com>
151
152 * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
153 check.
154 * i386-opc.h (Prefix_*): Move #define-s.
155 * i386-opc.tbl: Move pseudo prefix enumerator values to
156 extension opcode field. Introduce pseudopfx template.
157 * i386-tbl.h: Re-generate.
158
b933fa4b
JB		 1592021-03-23 Jan Beulich <jbeulich@suse.com>
160
161 * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
162 comment.
163 * i386-tbl.h: Re-generate.
164
dac10fb0
JB		 1652021-03-23 Jan Beulich <jbeulich@suse.com>
166
167 * i386-opc.h (struct insn_template): Move cpu_flags field past
168 opcode_modifier one.
169 * i386-tbl.h: Re-generate.
170
441f6aca
JB		 1712021-03-23 Jan Beulich <jbeulich@suse.com>
172
173 * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
174 * i386-opc.h (OpcodeSpace): New enumerator.
175 (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
176 (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
177 SPACE_XOP09, SPACE_XOP0A): ... respectively.
178 (struct i386_opcode_modifier): New field opcodespace. Shrink
179 opcodeprefix field.
180 i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
181 SpaceXOP09, SpaceXOP0A): Define. Use them to replace
182 OpcodePrefix uses.
183 * i386-tbl.h: Re-generate.
184
08dedd66
ML		 1852021-03-22 Martin Liska <mliska@suse.cz>
186
187 * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
188 * arc-dis.c (parse_option): Likewise.
189 * arm-dis.c (parse_arm_disassembler_options): Likewise.
190 * cris-dis.c (print_with_operands): Likewise.
191 * h8300-dis.c (bfd_h8_disassemble): Likewise.
192 * i386-dis.c (print_insn): Likewise.
193 * ia64-gen.c (fetch_insn_class): Likewise.
194 (parse_resource_users): Likewise.
195 (in_iclass): Likewise.
196 (lookup_specifier): Likewise.
197 (insert_opcode_dependencies): Likewise.
198 * mips-dis.c (parse_mips_ase_option): Likewise.
199 (parse_mips_dis_option): Likewise.
200 * s390-dis.c (disassemble_init_s390): Likewise.
201 * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
202
80d49d6a
KLC		 2032021-03-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
204
205 * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
206
7fce7ea9
PW		 2072021-03-12 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
208
209 * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
210 icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
211
78c84bf9
AM		 2122021-03-12 Alan Modra <amodra@gmail.com>
213
214 * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
215
fd1fd061
JB		 2162021-03-11 Jan Beulich <jbeulich@suse.com>
217
218 * i386-dis.c (OP_XMM): Re-order checks.
219
ac7a2311
JB		 2202021-03-11 Jan Beulich <jbeulich@suse.com>
221
222 * i386-dis.c (putop): Drop need_vex check when also checking
223 vex.evex.
224 (intel_operand_size, OP_E_memory): Drop vex.evex check when also
225 checking vex.b.
226
da944c8a
JB		 2272021-03-11 Jan Beulich <jbeulich@suse.com>
228
229 * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
230 checks. Move case label past broadcast check.
231
b763d508
JB		 2322021-03-10 Jan Beulich <jbeulich@suse.com>
233
234 * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
235 vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
236 REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
237 EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
238 EVEX_W_0F38C7_M_0_L_2): Delete.
239 (REG_EVEX_0F38C7_M_0_L_2): New.
240 (intel_operand_size): Handle VEX and EVEX the same for
241 vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
242 vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
243 (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
244 vex_vsib_q_w_d_mode uses.
245 * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
246 0F38A1, and 0F38A3 entries.
247 * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
248 entry.
249 * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
250 * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
251 0F38A3 entries.
252
32e31ad7
JB		 2532021-03-10 Jan Beulich <jbeulich@suse.com>
254
255 * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
256 REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
257 MOD_VEX_0FXOP_09_12): Rename to ...
258 (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
259 REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
260 (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
261 RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
262 X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
263 X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
264 (reg_table): Adjust comments.
265 (x86_64_table): Move X86_64_0F24, X86_64_0F26,
266 X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
267 X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
268 (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
269 (vex_len_table): Adjust opcode 0A_12 entry.
270 (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
271 MOD_C5_32BIT, and MOD_XOP_09_12 entries.
272 (rm_table): Move hreset entry.
273
85ba7507
JB		 2742021-03-10 Jan Beulich <jbeulich@suse.com>
275
276 * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
277 EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
278 EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
279 EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
280 EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
281 (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
282 (get_valid_dis386): Also handle 512-bit vector length when
283 vectoring into vex_len_table[].
284 * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
285 0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
286 entries.
287 * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
288 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
289 * i386-dis-evex-prefix.h: Adjust 0F7E entry.
290 * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
291 entries.
292
066f82b9
JB		 2932021-03-10 Jan Beulich <jbeulich@suse.com>
294
295 * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
296 Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
297 EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
298 * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
299 entries.
300 * i386-dis-evex-len.h (evex_len_table): Likewise.
301 * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
302
fc681dd6
JB		 3032021-03-10 Jan Beulich <jbeulich@suse.com>
304
305 * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
306 MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
307 MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
308 MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
309 MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
310 MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
311 MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
312 MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
313 EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
314 EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
315 EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
316 EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
317 EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
318 EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
319 EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
320 EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
321 EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
322 EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
323 EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
324 EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
325 EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
326 EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
327 EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
328 EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
329 EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
330 EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
331 EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
332 EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
333 EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
334 EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
335 EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
336 EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
337 REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
338 REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
339 MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
340 MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
341 EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
342 EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
343 EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
344 EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
345 EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
346 EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
347 EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
348 EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
349 EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
350 EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
351 EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
352 EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
353 EVEX_W_0F3A43_L_n): New.
354 * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
355 0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
356 0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
357 * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
358 for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
359 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
360 0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
361 * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
362 0F385B, 0F38C6, and 0F38C7 entries.
363 * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
364 0F38C6 and 0F38C7.
365 * i386-dis-evex-w.h: No longer link to evex_len_table[] for
366 opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
367 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
368 evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
369
13954a31
JB		 3702021-03-10 Jan Beulich <jbeulich@suse.com>
371
372 * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
373 MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
374 MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
375 MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
376 MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
377 MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
378 MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
379 MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
380 MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
381 MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
382 MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
383 MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
384 MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
385 MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
386 MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
387 MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
388 MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
389 MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
390 MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
391 MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
392 MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
393 MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
394 MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
395 MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
396 MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
397 PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
398 PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
399 PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
400 PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
401 PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
402 VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
403 VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
404 VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
405 VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
406 VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
407 VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
408 VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
409 VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
410 VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
411 VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
412 VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
413 VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
414 VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
415 VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
416 VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
417 VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
418 VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
419 VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
420 VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
421 VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
422 VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
423 VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
424 VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
425 VEX_W_0F99_P_2_LEN_0): Delete.
426 MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
427 MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
428 MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
429 MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
430 MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
431 PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
432 PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
433 PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
434 PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
435 PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
436 PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
437 PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
438 PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
439 PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
440 PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
441 PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
442 PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
443 PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
444 PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
445 VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
446 VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
447 VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
448 VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
449 VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
450 VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
451 VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
452 VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
453 (prefix_table): No longer link to vex_len_table[] for opcodes
454 0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
455 0F92, 0F93, 0F98, and 0F99.
456 (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
457 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
458 0F98, and 0F99.
459 (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
460 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
461 0F98, and 0F99.
462 (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
463 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
464 0F98, and 0F99.
465 (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
466 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
467 0F98, and 0F99.
468
14d10c6c
JB		 4692021-03-10 Jan Beulich <jbeulich@suse.com>
470
471 * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
472 Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
473 REG_VEX_0F73_M_0 respectively.
474 (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
475 MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
476 MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
477 MOD_VEX_0F73_REG_7): Delete.
478 (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
479 (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
480 PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
481 PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
482 PREFIX_VEX_0F3AF0_L_0 respectively.
483 (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
484 VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
485 VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
486 VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
487 (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
488 VEX_LEN_0F38F7): New.
489 (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
490 (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
491 0F72, and 0F73. No longer link to vex_len_table[] for opcode
492 0F38F3.
493 (prefix_table): No longer link to vex_len_table[] for opcodes
494 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
495 (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
496 0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
497 0F38F6, 0F38F7, and 0F3AF0.
498 (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
499 prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
500 (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
501 0F73.
502
00ec1875
JB		 5032021-03-10 Jan Beulich <jbeulich@suse.com>
504
505 * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
506 REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
507 (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
508 MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
509 MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
510 (MOD_0F71, MOD_0F72, MOD_0F73): New.
511 (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
512 73.
513 (reg_table): No longer link to mod_table[] for opcodes 0F71,
514 0F72, and 0F73.
515 (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
516 0F73.
517
31941983
JB		 5182021-03-10 Jan Beulich <jbeulich@suse.com>
519
520 * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
521 MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
522 (reg_table): Don't link to mod_table[] where not needed. Add
523 PREFIX_IGNORED to nop entries.
524 (prefix_table): Replace PREFIX_OPCODE in nop entries.
525 (mod_table): Add nop entries next to prefetch ones. Drop
526 MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
527 MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
528 (rm_table): Add PREFIX_IGNORED to nop entries. Drop
529 PREFIX_OPCODE from endbr* entries.
530 (get_valid_dis386): Also consider entry's name when zapping
531 vindex.
532 (print_insn): Handle PREFIX_IGNORED.
533
742732c7
JB		 5342021-03-09 Jan Beulich <jbeulich@suse.com>
535
536 * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
537 IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
538 element.
539 * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
540 HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
541 (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
542 PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
543 (struct i386_opcode_modifier): Delete notrackprefixok,
544 islockable, hleprefixok, and repprefixok fields. Add prefixok
545 field.
546 * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
547 HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
548 (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
549 not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
550 Replace HLEPrefixOk.
551 * opcodes/i386-tbl.h: Re-generate.
552
e93a3b27
JB		 5532021-03-09 Jan Beulich <jbeulich@suse.com>
554
555 * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
556 * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
557 64-bit form.
558 * opcodes/i386-tbl.h: Re-generate.
559
75363b6d
JB		 5602021-03-03 Jan Beulich <jbeulich@suse.com>
561
562 * i386-gen.c (output_i386_opcode): Don't get operand count. Look
563 for {} instead of {0}. Don't look for '0'.
564 * i386-opc.tbl: Drop operand count field. Drop redundant operand
565 size specifiers.
566
5a9f5403
NC		 5672021-02-19 Nelson Chu <nelson.chu@sifive.com>
568
569 PR 27158
570 * riscv-dis.c (print_insn_args): Updated encoding macros.
571 * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
572 (match_c_addi16sp): Updated encoding macros.
573 (match_c_lui): Likewise.
574 (match_c_lui_with_hint): Likewise.
575 (match_c_addi4spn): Likewise.
576 (match_c_slli): Likewise.
577 (match_slli_as_c_slli): Likewise.
578 (match_c_slli64): Likewise.
579 (match_srxi_as_c_srxi): Likewise.
580 (riscv_insn_types): Added .insn css/cl/cs.
581
3d73d29e
NC		 5822021-02-18 Nelson Chu <nelson.chu@sifive.com>
583
584 * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
585 (default_priv_spec): Updated type to riscv_spec_class.
586 (parse_riscv_dis_option): Updated.
587 * riscv-opc.c: Moved stuff and make the file tidy.
588
b9b204b3
AM		 5892021-02-17 Alan Modra <amodra@gmail.com>
590
591 * wasm32-dis.c: Include limits.h.
592 (CHAR_BIT): Provide backup define.
593 (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
594 Correct signed overflow checking.
595
394ae71f
JB		 5962021-02-16 Jan Beulich <jbeulich@suse.com>
597
598 * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
599 * i386-tbl.h: Re-generate.
600
b818b220
JB		 6012021-02-16 Jan Beulich <jbeulich@suse.com>
602
603 * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
604 Oword.
605 * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
606
ba2b480f
AK		 6072021-02-15 Andreas Krebbel <krebbel@linux.ibm.com>
608
609 * s390-mkopc.c (main): Accept arch14 as cpu string.
610 * s390-opc.txt: Add new arch14 instructions.
611
95148614
NA		 6122021-02-04 Nick Alcock <nick.alcock@oracle.com>
613
614 * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
615 favour of LIBINTL.
616 * configure: Regenerated.
617
bfd428bc
MF		 6182021-02-08 Mike Frysinger <vapier@gentoo.org>
619
620 * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
621 * tic54x-opc.c (regs): Rename to ...
622 (tic54x_regs): ... this.
623 (mmregs): Rename to ...
624 (tic54x_mmregs): ... this.
625 (condition_codes): Rename to ...
626 (tic54x_condition_codes): ... this.
627 (cc2_codes): Rename to ...
628 (tic54x_cc2_codes): ... this.
629 (cc3_codes): Rename to ...
630 (tic54x_cc3_codes): ... this.
631 (status_bits): Rename to ...
632 (tic54x_status_bits): ... this.
633 (misc_symbols): Rename to ...
634 (tic54x_misc_symbols): ... this.
635
24075dcc
NC		 6362021-02-04 Nelson Chu <nelson.chu@sifive.com>
637
638 * riscv-opc.c (MASK_RVB_IMM): Removed.
639 (riscv_opcodes): Removed zb* instructions.
640 (riscv_ext_version_table): Removed versions for zb*.
641
c3ffb8f3
AM		 6422021-01-26 Alan Modra <amodra@gmail.com>
643
644 * i386-gen.c (parse_template): Ensure entire template_instance
645 is initialised.
646
1942a048
NC		 6472021-01-15 Nelson Chu <nelson.chu@sifive.com>
648
649 * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
650 (riscv_fpr_names_abi): Likewise.
651 (riscv_opcodes): Likewise.
652 (riscv_insn_types): Likewise.
653
b800637e
NC		 6542021-01-15 Nelson Chu <nelson.chu@sifive.com>
655
656 * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
657
dcd709e0
NC		 6582021-01-15 Nelson Chu <nelson.chu@sifive.com>
659
660 * riscv-dis.c: Comments tidy and improvement.
661 * riscv-opc.c: Likewise.
662
5347ed60
AM		 6632021-01-13 Alan Modra <amodra@gmail.com>
664
665 * Makefile.in: Regenerate.
666
d546b610
L		 6672021-01-12 H.J. Lu <hongjiu.lu@intel.com>
668
669 PR binutils/26792
670 * configure.ac: Use GNU_MAKE_JOBSERVER.
671 * aclocal.m4: Regenerated.
672 * configure: Likewise.
673
6d104cac
NC		 6742021-01-12 Nick Clifton <nickc@redhat.com>
675
676 * po/sr.po: Updated Serbian translation.
677
83b33c6c
L		 6782021-01-11 H.J. Lu <hongjiu.lu@intel.com>
679
680 PR ld/27173
681 * configure: Regenerated.
682
82c70b08
KT		 6832021-01-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
684
685 * aarch64-asm-2.c: Regenerate.
686 * aarch64-dis-2.c: Likewise.
687 * aarch64-opc-2.c: Likewise.
688 * aarch64-opc.c (aarch64_print_operand):
689 Delete handling of AARCH64_OPND_CSRE_CSR.
690 * aarch64-tbl.h (aarch64_feature_csre): Delete.
691 (CSRE): Likewise.
692 (_CSRE_INSN): Likewise.
693 (aarch64_opcode_table): Delete csr.
694
a8aa72b9
NC		 6952021-01-11 Nick Clifton <nickc@redhat.com>
696
697 * po/de.po: Updated German translation.
698 * po/fr.po: Updated French translation.
699 * po/pt_BR.po: Updated Brazilian Portuguese translation.
700 * po/sv.po: Updated Swedish translation.
701 * po/uk.po: Updated Ukranian translation.
702
a4966cd9
L		 7032021-01-09 H.J. Lu <hongjiu.lu@intel.com>
704
705 * configure: Regenerated.
706
573fe3fb
NC		 7072021-01-09 Nick Clifton <nickc@redhat.com>
708
709 * configure: Regenerate.
710 * po/opcodes.pot: Regenerate.
711
055bc77a
NC		 7122021-01-09 Nick Clifton <nickc@redhat.com>
713
714 * 2.36 release branch crated.
715
aae7fcb8
PB		 7162021-01-08 Peter Bergner <bergner@linux.ibm.com>
717
718 * ppc-opc.c (insert_dw, (extract_dw): New functions.
719 (DW, (XRC_MASK): Define.
720 (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
721
64307045
AM		 7222021-01-09 Alan Modra <amodra@gmail.com>
723
724 * configure: Regenerate.
725
ed205222
NC		 7262021-01-08 Nick Clifton <nickc@redhat.com>
727
728 * po/sv.po: Updated Swedish translation.
729
fb932b57
NC		 7302021-01-08 Nick Clifton <nickc@redhat.com>
731
e84c8716
NC		 732 PR 27129
733 * aarch64-dis.c (determine_disassembling_preference): Move call to
734 aarch64_match_operands_constraint outside of the assertion.
735 * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
736 Replace with a return of FALSE.
737
fb932b57
NC		 738 PR 27139
739 * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
740 core system register.
741
f4782128
ST		 7422021-01-07 Samuel Thibault <samuel.thibault@gnu.org>
743
744 * configure: Regenerate.
745
1b0927db
NC		 7462021-01-07 Nick Clifton <nickc@redhat.com>
747
748 * po/fr.po: Updated French translation.
749
3b288c8e
FN		 7502021-01-07 Fredrik Noring <noring@nocrew.org>
751
752 * m68k-opc.c (chkl): Change minimum architecture requirement to
753 m68020.
754
aa881ecd
PT		 7552021-01-07 Philipp Tomsich <prt@gnu.org>
756
757 * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
758
2652cfad
CXW		 7592021-01-07 Claire Xenia Wolf <claire@symbioticeda.com>
760 Jim Wilson <jimw@sifive.com>
761 Andrew Waterman <andrew@sifive.com>
762 Maxim Blinov <maxim.blinov@embecosm.com>
763 Kito Cheng <kito.cheng@sifive.com>
764 Nelson Chu <nelson.chu@sifive.com>
765
766 * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
767 (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
768
250d07de
AM		 7692021-01-01 Alan Modra <amodra@gmail.com>
770
771 Update year range in copyright notice of all files.
772
c2795844 773For older changes see ChangeLog-2020
3499769a 774\f
c2795844 775Copyright (C) 2021 Free Software Foundation, Inc.
3499769a
AM		 776
777Copying and distribution of this file, with or without modification,
778are permitted in any medium without royalty provided the copyright
779notice and this notice are preserved.
780
781Local Variables:
782mode: change-log
783left-margin: 8
784fill-column: 74
785version-control: never
786End:
GDB Binutils - Deliverables
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