projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Fix address violation parsing a corrupt ieee binary.
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
63323b5b
NC		 12017-06-15 Nick Clifton <nickc@redhat.com>
2
3 PR binutils/21588
4 * rl78-decode.opc (OP_BUF_LEN): Define.
5 (GETBYTE): Check for the index exceeding OP_BUF_LEN.
6 (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
7 array.
8 * rl78-decode.c: Regenerate.
9
08c7881b
NC		 102017-06-15 Nick Clifton <nickc@redhat.com>
11
12 PR binutils/21586
13 * bfin-dis.c (gregs): Clip index to prevent overflow.
14 (regs): Likewise.
15 (regs_lo): Likewise.
16 (regs_hi): Likewise.
17
e64519d1
NC		 182017-06-14 Nick Clifton <nickc@redhat.com>
19
20 PR binutils/21576
21 * score7-dis.c (score_opcodes): Add sentinel.
22
6394c606
YQ		 232017-06-14 Yao Qi <yao.qi@linaro.org>
24
25 * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
26 * arm-dis.c: Likewise.
27 * ia64-dis.c: Likewise.
28 * mips-dis.c: Likewise.
29 * spu-dis.c: Likewise.
30 * disassemble.h (print_insn_aarch64): New declaration, moved from
31 include/dis-asm.h.
32 (print_insn_big_arm, print_insn_big_mips): Likewise.
33 (print_insn_i386, print_insn_ia64): Likewise.
34 (print_insn_little_arm, print_insn_little_mips): Likewise.
35
db5fa770
NC		 362017-06-14 Nick Clifton <nickc@redhat.com>
37
38 PR binutils/21587
39 * rx-decode.opc: Include libiberty.h
40 (GET_SCALE): New macro - validates access to SCALE array.
41 (GET_PSCALE): New macro - validates access to PSCALE array.
42 (DIs, SIs, S2Is, rx_disp): Use new macros.
43 * rx-decode.c: Regenerate.
44
05c966f3
AV		 452017-07-14 Andre Vieira <andre.simoesdiasvieira@arm.com>
46
47 * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
48
10045478
AK		 492017-05-30 Anton Kolesov <anton.kolesov@synopsys.com>
50
51 * arc-dis.c (enforced_isa_mask): Declare.
52 (cpu_types): Likewise.
53 (parse_cpu_option): New function.
54 (parse_disassembler_options): Use it.
55 (print_insn_arc): Use enforced_isa_mask.
56 (print_arc_disassembler_options): Document new options.
57
88c1242d
YQ		 582017-05-24 Yao Qi <yao.qi@linaro.org>
59
60 * alpha-dis.c: Include disassemble.h, don't include
61 dis-asm.h.
62 * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
63 * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
64 * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
65 * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
66 * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
67 * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
68 * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
69 * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
70 * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
71 * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
72 * moxie-dis.c, msp430-dis.c, mt-dis.c:
73 * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
74 * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
75 * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
76 * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
77 * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
78 * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
79 * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
80 * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
81 * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
82 * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
83 * z80-dis.c, z8k-dis.c: Likewise.
84 * disassemble.h: New file.
85
ab20fa4a
YQ		 862017-05-24 Yao Qi <yao.qi@linaro.org>
87
88 * rl78-dis.c (rl78_get_disassembler): If parameter abfd
89 is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
90
003ca0fd
YQ		 912017-05-24 Yao Qi <yao.qi@linaro.org>
92
93 * disassemble.c (disassembler): Add arguments a, big and mach.
94 Use them.
95
04ef582a
L		 962017-05-22 H.J. Lu <hongjiu.lu@intel.com>
97
98 * i386-dis.c (NOTRACK_Fixup): New.
99 (NOTRACK): Likewise.
100 (NOTRACK_PREFIX): Likewise.
101 (last_active_prefix): Likewise.
102 (reg_table): Use NOTRACK on indirect call and jmp.
103 (ckprefix): Set last_active_prefix.
104 (prefix_name): Return "notrack" for NOTRACK_PREFIX.
105 * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
106 * i386-opc.h (NoTrackPrefixOk): New.
107 (i386_opcode_modifier): Add notrackprefixok.
108 * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
109 Add notrack.
110 * i386-tbl.h: Regenerated.
111
64517994
JM		 1122017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
113
114 * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
115 (X_IMM2): Define.
116 (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
117 bfd_mach_sparc_v9m8.
118 (print_insn_sparc): Handle new operand types.
119 * sparc-opc.c (MASK_M8): Define.
120 (v6): Add MASK_M8.
121 (v6notlet): Likewise.
122 (v7): Likewise.
123 (v8): Likewise.
124 (v9): Likewise.
125 (v9a): Likewise.
126 (v9b): Likewise.
127 (v9c): Likewise.
128 (v9d): Likewise.
129 (v9e): Likewise.
130 (v9v): Likewise.
131 (v9m): Likewise.
132 (v9andleon): Likewise.
133 (m8): Define.
134 (HWS_VM8): Define.
135 (HWS2_VM8): Likewise.
136 (sparc_opcode_archs): Add entry for "m8".
137 (sparc_opcodes): Add OSA2017 and M8 instructions
138 dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
139 fpx{ll,ra,rl}64x,
140 ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
141 ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
142 revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
143 stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
144 (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
145 ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
146 ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
147 ASI_CORE_SELECT_COMMIT_NHT.
148
535b785f
AM		 1492017-05-18 Alan Modra <amodra@gmail.com>
150
151 * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
152 * aarch64-dis.c: Likewise.
153 * aarch64-gen.c: Likewise.
154 * aarch64-opc.c: Likewise.
155
25499ac7
MR		 1562017-05-15 Maciej W. Rozycki <macro@imgtec.com>
157 Matthew Fortune <matthew.fortune@imgtec.com>
158
159 * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
160 ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
161 (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
162 (print_insn_arg) <OP_REG28>: Add handler.
163 (validate_insn_args) <OP_REG28>: Handle.
164 (print_mips16_insn_arg): Handle MIPS16 instructions that require
165 32-bit encoding and 9-bit immediates.
166 (print_insn_mips16): Handle MIPS16 instructions that require
167 32-bit encoding and MFC0/MTC0 operand decoding.
168 * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
169 <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
170 (RD_C0, WR_C0, E2, E2MT): New macros.
171 (mips16_opcodes): Add entries for MIPS16e2 instructions:
172 GP-relative "addiu" and its "addu" spelling, "andi", "cache",
173 "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
174 "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
175 "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
176 "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
177 instructions, "swl", "swr", "sync" and its "sync_acquire",
178 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
179 "xori", "dmt", "dvpe", "emt" and "evpe". Add split
180 regular/extended entries for original MIPS16 ISA revision
181 instructions whose extended forms are subdecoded in the MIPS16e2
182 ISA revision: "li", "sll" and "srl".
183
fdfb4752
MR		 1842017-05-15 Maciej W. Rozycki <macro@imgtec.com>
185
186 * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
187 reference in CP0 move operand decoding.
188
a4f89915
MR		 1892017-05-12 Maciej W. Rozycki <macro@imgtec.com>
190
191 * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
192 type to hexadecimal.
193 (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
194
99e2d67a
MR		 1952017-05-11 Maciej W. Rozycki <macro@imgtec.com>
196
197 * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
198 "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
199 "sync_rmb" and "sync_wmb" as aliases.
200 * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
201 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
202
53a346d8
CZ		 2032017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
204
205 * arc-dis.c (parse_option): Update quarkse_em option..
206 * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
207 QUARKSE1.
208 (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
209
f91d48de
KC		 2102017-05-03 Kito Cheng <kito.cheng@gmail.com>
211
212 * riscv-dis.c (print_insn_args): Handle 'Co' operands.
213
43e379d7
MC		 2142017-05-01 Michael Clark <michaeljclark@mac.com>
215
216 * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
217 register.
218
a4ddc54e
MR		 2192017-05-02 Maciej W. Rozycki <macro@imgtec.com>
220
221 * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
222 and branches and not synthetic data instructions.
223
fe50e98c
BE		 2242017-05-02 Bernd Edlinger <bernd.edlinger@hotmail.de>
225
226 * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
227
126124cc
CZ		 2282017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
229
230 * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
231 * arc-opc.c (insert_r13el): New function.
232 (R13_EL): Define.
233 * arc-tbl.h: Add new enter/leave variants.
234
be6a24d8
CZ		 2352017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
236
237 * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
238
0348fd79
MR		 2392017-04-25 Maciej W. Rozycki <macro@imgtec.com>
240
241 * mips-dis.c (print_mips_disassembler_options): Add
242 `no-aliases'.
243
6e3d1f07
MR		 2442017-04-25 Maciej W. Rozycki <macro@imgtec.com>
245
246 * mips16-opc.c (AL): New macro.
247 (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
248 of "ld" and "lw" as aliases.
249
957f6b39
TC		 2502017-04-24 Tamar Christina <tamar.christina@arm.com>
251
252 * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
253 arguments.
254
a8cc8a54
AM		 2552017-04-22 Alexander Fedotov <alfedotov@gmail.com>
256 Alan Modra <amodra@gmail.com>
257
258 * ppc-opc.c (ELEV): Define.
259 (vle_opcodes): Add se_rfgi and e_sc.
260 (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
261 for E200Z4.
262
3ab87b68
JM		 2632017-04-21 Jose E. Marchesi <jose.marchesi@oracle.com>
264
265 * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
266
792f174f
NC		 2672017-04-21 Nick Clifton <nickc@redhat.com>
268
269 PR binutils/21380
270 * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
271 LD3R and LD4R.
272
42742084
AM		 2732017-04-13 Alan Modra <amodra@gmail.com>
274
275 * epiphany-desc.c: Regenerate.
276 * fr30-desc.c: Regenerate.
277 * frv-desc.c: Regenerate.
278 * ip2k-desc.c: Regenerate.
279 * iq2000-desc.c: Regenerate.
280 * lm32-desc.c: Regenerate.
281 * m32c-desc.c: Regenerate.
282 * m32r-desc.c: Regenerate.
283 * mep-desc.c: Regenerate.
284 * mt-desc.c: Regenerate.
285 * or1k-desc.c: Regenerate.
286 * xc16x-desc.c: Regenerate.
287 * xstormy16-desc.c: Regenerate.
288
9a85b496
AM		 2892017-04-11 Alan Modra <amodra@gmail.com>
290
ef85eab0 291 * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
c03dc33b
AM		 292 PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm". Formatting. Set
293 PPC_OPCODE_TMR for e6500.
9a85b496
AM		 294 * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
295 (PPCVEC3): Define as PPC_OPCODE_POWER9.
9570835e
AM		 296 (PPCVSX2): Define as PPC_OPCODE_POWER8.
297 (PPCVSX3): Define as PPC_OPCODE_POWER9.
ef85eab0 298 (PPCHTM): Define as PPC_OPCODE_POWER8.
c03dc33b 299 (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
9a85b496 300
62adc510
AM		 3012017-04-10 Alan Modra <amodra@gmail.com>
302
303 * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
304 * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
305 (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
306 removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
307
aa808707
PC		 3082017-04-09 Pip Cet <pipcet@gmail.com>
309
310 * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
311 appropriate floating-point precision directly.
312
ac8f0f72
AM		 3132017-04-07 Alan Modra <amodra@gmail.com>
314
315 * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
316 lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
317 lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
318 lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
319 vector instructions with E6500 not PPCVEC2.
320
62ecb94c
PC		 3212017-04-06 Pip Cet <pipcet@gmail.com>
322
323 * Makefile.am: Add wasm32-dis.c.
324 * configure.ac: Add wasm32-dis.c to wasm32 target.
325 * disassemble.c: Add wasm32 disassembler code.
326 * wasm32-dis.c: New file.
327 * Makefile.in: Regenerate.
328 * configure: Regenerate.
329 * po/POTFILES.in: Regenerate.
330 * po/opcodes.pot: Regenerate.
331
f995bbe8
PA		 3322017-04-05 Pedro Alves <palves@redhat.com>
333
334 * arc-dis.c (parse_option, parse_disassembler_options): Constify.
335 * arm-dis.c (parse_arm_disassembler_options): Constify.
336 * ppc-dis.c (powerpc_init_dialect): Constify local.
337 * vax-dis.c (parse_disassembler_options): Constify.
338
b5292032
PD		 3392017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
340
341 * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
342 RISCV_GP_SYMBOL.
343
f96bd6c2
PC		 3442017-03-30 Pip Cet <pipcet@gmail.com>
345
346 * configure.ac: Add (empty) bfd_wasm32_arch target.
347 * configure: Regenerate
348 * po/opcodes.pot: Regenerate.
349
f7c514a3
JM		 3502017-03-29 Sheldon Lobo <sheldon.lobo@oracle.com>
351
352 Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
353 OSA2015.
354 * opcodes/sparc-opc.c (asi_table): New ASIs.
355
52be03fd
AM		 3562017-03-29 Alan Modra <amodra@gmail.com>
357
358 * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add
359 "raw" option.
360 (lookup_powerpc): Don't special case -1 dialect. Handle
361 PPC_OPCODE_RAW.
362 (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
363 lookup_powerpc call, pass it on second.
364
9b753937
AM		 3652017-03-27 Alan Modra <amodra@gmail.com>
366
367 PR 21303
368 * ppc-dis.c (struct ppc_mopt): Comment.
369 (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
370
c0c31e91
RZ		 3712017-03-27 Rinat Zelig <rinat@mellanox.com>
372
373 * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
374 * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
375 F_NPS_M, F_NPS_CORE, F_NPS_ALL.
376 (insert_nps_misc_imm_offset): New function.
377 (extract_nps_misc imm_offset): New function.
378 (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
379 (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
380
2253c8f0
AK		 3812017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
382
383 * s390-mkopc.c (main): Remove vx2 check.
384 * s390-opc.txt: Remove vx2 instruction flags.
385
645d3342
RZ		 3862017-03-21 Rinat Zelig <rinat@mellanox.com>
387
388 * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
389 * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
390 (insert_nps_imm_offset): New function.
391 (extract_nps_imm_offset): New function.
392 (insert_nps_imm_entry): New function.
393 (extract_nps_imm_entry): New function.
394
4b94dd2d
AM		 3952017-03-17 Alan Modra <amodra@gmail.com>
396
397 PR 21248
398 * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
399 mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after
400 those spr mnemonics they alias. Similarly for mtibatl, mtibatu.
401
b416fe87
KC		 4022017-03-14 Kito Cheng <kito.cheng@gmail.com>
403
404 * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
405 <c.andi>: Likewise.
406 <c.addiw> Likewise.
407
03b039a5
KC		 4082017-03-14 Kito Cheng <kito.cheng@gmail.com>
409
410 * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
411
2c232b83
AW		 4122017-03-13 Andrew Waterman <andrew@sifive.com>
413
414 * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
415 <srl> Likewise.
416 <srai> Likewise.
417 <sra> Likewise.
418
86fa6981
L		 4192017-03-09 H.J. Lu <hongjiu.lu@intel.com>
420
421 * i386-gen.c (opcode_modifiers): Replace S with Load.
422 * i386-opc.h (S): Removed.
423 (Load): New.
424 (i386_opcode_modifier): Replace s with load.
425 * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
426 and {evex}. Replace S with Load.
427 * i386-tbl.h: Regenerated.
428
c1fe188b
L		 4292017-03-09 H.J. Lu <hongjiu.lu@intel.com>
430
431 * i386-opc.tbl: Use CpuCET on rdsspq.
432 * i386-tbl.h: Regenerated.
433
4b8b687e
PB		 4342017-03-08 Peter Bergner <bergner@vnet.ibm.com>
435
436 * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
437 <vsx>: Do not use PPC_OPCODE_VSX3;
438
1437d063
PB		 4392017-03-08 Peter Bergner <bergner@vnet.ibm.com>
440
441 * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
442
603555e5
L		 4432017-03-06 H.J. Lu <hongjiu.lu@intel.com>
444
445 * i386-dis.c (REG_0F1E_MOD_3): New enum.
446 (MOD_0F1E_PREFIX_1): Likewise.
447 (MOD_0F38F5_PREFIX_2): Likewise.
448 (MOD_0F38F6_PREFIX_0): Likewise.
449 (RM_0F1E_MOD_3_REG_7): Likewise.
450 (PREFIX_MOD_0_0F01_REG_5): Likewise.
451 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
452 (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
453 (PREFIX_0F1E): Likewise.
454 (PREFIX_MOD_0_0FAE_REG_5): Likewise.
455 (PREFIX_0F38F5): Likewise.
456 (dis386_twobyte): Use PREFIX_0F1E.
457 (reg_table): Add REG_0F1E_MOD_3.
458 (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
459 PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
460 PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
461 PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
462 (three_byte_table): Use PREFIX_0F38F5.
463 (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
464 Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
465 (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
466 RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
467 PREFIX_MOD_3_0F01_REG_5_RM_2.
468 * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
469 (cpu_flags): Add CpuCET.
470 * i386-opc.h (CpuCET): New enum.
471 (CpuUnused): Commented out.
472 (i386_cpu_flags): Add cpucet.
473 * i386-opc.tbl: Add Intel CET instructions.
474 * i386-init.h: Regenerated.
475 * i386-tbl.h: Likewise.
476
73f07bff
AM		 4772017-03-06 Alan Modra <amodra@gmail.com>
478
479 PR 21124
480 * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
481 (extract_raq, extract_ras, extract_rbx): New functions.
482 (powerpc_operands): Use opposite corresponding insert function.
483 (Q_MASK): Define.
484 (powerpc_opcodes): Apply Q_MASK to all quad insns with even
485 register restriction.
486
65b48a81
PB		 4872017-02-28 Peter Bergner <bergner@vnet.ibm.com>
488
489 * disassemble.c Include "safe-ctype.h".
490 (disassemble_init_for_target): Handle s390 init.
491 (remove_whitespace_and_extra_commas): New function.
492 (disassembler_options_cmp): Likewise.
493 * arm-dis.c: Include "libiberty.h".
494 (NUM_ELEM): Delete.
495 (regnames): Use long disassembler style names.
496 Add force-thumb and no-force-thumb options.
497 (NUM_ARM_REGNAMES): Rename from this...
498 (NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE.
499 (get_arm_regname_num_options): Delete.
500 (set_arm_regname_option): Likewise.
501 (get_arm_regnames): Likewise.
502 (parse_disassembler_options): Likewise.
503 (parse_arm_disassembler_option): Rename from this...
504 (parse_arm_disassembler_options): ...to this. Make static.
505 Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
506 (print_insn): Use parse_arm_disassembler_options.
507 (disassembler_options_arm): New function.
508 (print_arm_disassembler_options): Handle updated regnames.
509 * ppc-dis.c: Include "libiberty.h".
510 (ppc_opts): Add "32" and "64" entries.
511 (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
512 (powerpc_init_dialect): Add break to switch statement.
513 Use new FOR_EACH_DISASSEMBLER_OPTION macro.
514 (disassembler_options_powerpc): New function.
515 (print_ppc_disassembler_options): Use ARRAY_SIZE.
516 Remove printing of "32" and "64".
517 * s390-dis.c: Include "libiberty.h".
518 (init_flag): Remove unneeded variable.
519 (struct s390_options_t): New structure type.
520 (options): New structure.
521 (init_disasm): Rename from this...
522 (disassemble_init_s390): ...to this. Add initializations for
523 current_arch_mask and option_use_insn_len_bits_p. Remove init_flag.
524 (print_insn_s390): Delete call to init_disasm.
525 (disassembler_options_s390): New function.
526 (print_s390_disassembler_options): Print using information from
527 struct 'options'.
528 * po/opcodes.pot: Regenerate.
529
15c7c1d8
JB		 5302017-02-28 Jan Beulich <jbeulich@suse.com>
531
532 * i386-dis.c (PCMPESTR_Fixup): New.
533 (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
534 (prefix_table): Use PCMPESTR_Fixup.
535 (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
536 PCMPESTR_Fixup.
537 (vex_w_table): Delete VPCMPESTR{I,M} entries.
538 * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
539 Split 64-bit and non-64-bit variants.
540 * opcodes/i386-tbl.h: Re-generate.
541
582e12bf
RS		 5422017-02-24 Richard Sandiford <richard.sandiford@arm.com>
543
544 * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
545 (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
546 (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
547 (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
548 (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
549 (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
550 (OP_SVE_V_HSD): New macros.
551 (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
552 (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
553 (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
554 (aarch64_opcode_table): Add new SVE instructions.
555 (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
556 for rotation operands. Add new SVE operands.
557 * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
558 (ins_sve_quad_index): Likewise.
559 (ins_imm_rotate): Split into...
560 (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
561 * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
562 (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
563 functions.
564 (aarch64_ins_sve_addr_ri_s4): New function.
565 (aarch64_ins_sve_quad_index): Likewise.
566 (do_misc_encoding): Handle "MOV Zn.Q, Qm".
567 * aarch64-asm-2.c: Regenerate.
568 * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
569 (ext_sve_quad_index): Likewise.
570 (ext_imm_rotate): Split into...
571 (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
572 * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
573 (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
574 functions.
575 (aarch64_ext_sve_addr_ri_s4): New function.
576 (aarch64_ext_sve_quad_index): Likewise.
577 (aarch64_ext_sve_index): Allow quad indices.
578 (do_misc_decoding): Likewise.
579 * aarch64-dis-2.c: Regenerate.
580 * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
581 aarch64_field_kinds.
582 (OPD_F_OD_MASK): Widen by one bit.
583 (OPD_F_NO_ZR): Bump accordingly.
584 (get_operand_field_width): New function.
585 * aarch64-opc.c (fields): Add new SVE fields.
586 (operand_general_constraint_met_p): Handle new SVE operands.
587 (aarch64_print_operand): Likewise.
588 * aarch64-opc-2.c: Regenerate.
589
f482d304
RS		 5902017-02-24 Richard Sandiford <richard.sandiford@arm.com>
591
592 * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
593 (aarch64_feature_compnum): ...this.
594 (SIMD_V8_3): Replace with...
595 (COMPNUM): ...this.
596 (CNUM_INSN): New macro.
597 (aarch64_opcode_table): Use it for the complex number instructions.
598
7db2c588
JB		 5992017-02-24 Jan Beulich <jbeulich@suse.com>
600
601 * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
602
1e9d41d4
SL		 6032017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
604
605 Add support for associating SPARC ASIs with an architecture level.
606 * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
607 * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
608 decoding of SPARC ASIs.
609
53c4d625
JB		 6102017-02-23 Jan Beulich <jbeulich@suse.com>
611
612 * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
613 82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
614
11648de5
JB		 6152017-02-21 Jan Beulich <jbeulich@suse.com>
616
617 * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
618 1 (instead of to itself). Correct typo.
619
f98d33be
AW		 6202017-02-14 Andrew Waterman <andrew@sifive.com>
621
622 * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
623 pseudoinstructions.
624
773fb663
RS		 6252017-02-15 Richard Sandiford <richard.sandiford@arm.com>
626
627 * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
628 (aarch64_sys_reg_supported_p): Handle them.
629
cc07cda6
CZ		 6302017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
631
632 * arc-opc.c (UIMM6_20R): Define.
633 (SIMM12_20): Use above.
634 (SIMM12_20R): Define.
635 (SIMM3_5_S): Use above.
636 (UIMM7_A32_11R_S): Define.
637 (UIMM7_9_S): Use above.
638 (UIMM3_13R_S): Define.
639 (SIMM11_A32_7_S): Use above.
640 (SIMM9_8R): Define.
641 (UIMM10_A32_8_S): Use above.
642 (UIMM8_8R_S): Define.
643 (W6): Use above.
644 (arc_relax_opcodes): Use all above defines.
645
66a5a740
VG		 6462017-02-15 Vineet Gupta <vgupta@synopsys.com>
647
648 * arc-regs.h: Distinguish some of the registers different on
649 ARC700 and HS38 cpus.
650
7e0de605
AM		 6512017-02-14 Alan Modra <amodra@gmail.com>
652
653 PR 21118
654 * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
655 with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
656
54064fdb
AM		 6572017-02-11 Stafford Horne <shorne@gmail.com>
658 Alan Modra <amodra@gmail.com>
659
660 * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
661 Use insn_bytes_value and insn_int_value directly instead. Don't
662 free allocated memory until function exit.
663
dce75bf9
NP		 6642017-02-10 Nicholas Piggin <npiggin@gmail.com>
665
666 * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
667
1b7e3d2f
NC		 6682017-02-03 Nick Clifton <nickc@redhat.com>
669
670 PR 21096
671 * aarch64-opc.c (print_register_list): Ensure that the register
672 list index will fir into the tb buffer.
673 (print_register_offset_address): Likewise.
674 * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
675
8ec5cf65
AD		 6762017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
677
678 PR 21056
679 * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
680 instructions when the previous fetch packet ends with a 32-bit
681 instruction.
682
a1aa5e81
DD		 6832017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
684
685 * pru-opc.c: Remove vague reference to a future GDB port.
686
add3afb2
NC		 6872017-01-20 Nick Clifton <nickc@redhat.com>
688
689 * po/ga.po: Updated Irish translation.
690
c13a63b0
SN		 6912017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
692
693 * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
694
9608051a
YQ		 6952017-01-13 Yao Qi <yao.qi@linaro.org>
696
697 * m68k-dis.c (match_insn_m68k): Extend comments. Return -1
698 if FETCH_DATA returns 0.
699 (m68k_scan_mask): Likewise.
700 (print_insn_m68k): Update code to handle -1 return value.
701
f622ea96
YQ		 7022017-01-13 Yao Qi <yao.qi@linaro.org>
703
704 * m68k-dis.c (enum print_insn_arg_error): New.
705 (NEXTBYTE): Replace -3 with
706 PRINT_INSN_ARG_MEMORY_ERROR.
707 (NEXTULONG): Likewise.
708 (NEXTSINGLE): Likewise.
709 (NEXTDOUBLE): Likewise.
710 (NEXTDOUBLE): Likewise.
711 (NEXTPACKED): Likewise.
712 (FETCH_ARG): Likewise.
713 (FETCH_DATA): Update comments.
714 (print_insn_arg): Update comments. Replace magic numbers with
715 enum.
716 (match_insn_m68k): Likewise.
717
620214f7
IT		 7182017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
719
720 * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
721 * i386-dis-evex.h (evex_table): Updated.
722 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
723 CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
724 (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
725 * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
726 (i386_cpu_flags): Add cpuavx512_vpopcntdq.
727 * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
728 * i386-init.h: Regenerate.
729 * i386-tbl.h: Ditto.
730
d95014a2
YQ		 7312017-01-12 Yao Qi <yao.qi@linaro.org>
732
733 * msp430-dis.c (msp430_singleoperand): Return -1 if
734 msp430dis_opcode_signed returns false.
735 (msp430_doubleoperand): Likewise.
736 (msp430_branchinstr): Return -1 if
737 msp430dis_opcode_unsigned returns false.
738 (msp430x_calla_instr): Likewise.
739 (print_insn_msp430): Likewise.
740
0ae60c3e
NC		 7412017-01-05 Nick Clifton <nickc@redhat.com>
742
743 PR 20946
744 * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
745 could not be matched.
746 (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
747 NULL.
748
d74d4880
SN		 7492017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
750
751 * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
752 (aarch64_opcode_table): Use RCPC_INSN.
753
cc917fd9
KC		 7542017-01-03 Kito Cheng <kito.cheng@gmail.com>
755
756 * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
757 extension.
758 * riscv-opcodes/all-opcodes: Likewise.
759
b52d3cfc
DP		 7602017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
761
762 * riscv-dis.c (print_insn_args): Add fall through comment.
763
f90c58d5
NC		 7642017-01-03 Nick Clifton <nickc@redhat.com>
765
766 * po/sr.po: New Serbian translation.
767 * configure.ac (ALL_LINGUAS): Add sr.
768 * configure: Regenerate.
769
f47b0d4a
AM		 7702017-01-02 Alan Modra <amodra@gmail.com>
771
772 * epiphany-desc.h: Regenerate.
773 * epiphany-opc.h: Regenerate.
774 * fr30-desc.h: Regenerate.
775 * fr30-opc.h: Regenerate.
776 * frv-desc.h: Regenerate.
777 * frv-opc.h: Regenerate.
778 * ip2k-desc.h: Regenerate.
779 * ip2k-opc.h: Regenerate.
780 * iq2000-desc.h: Regenerate.
781 * iq2000-opc.h: Regenerate.
782 * lm32-desc.h: Regenerate.
783 * lm32-opc.h: Regenerate.
784 * m32c-desc.h: Regenerate.
785 * m32c-opc.h: Regenerate.
786 * m32r-desc.h: Regenerate.
787 * m32r-opc.h: Regenerate.
788 * mep-desc.h: Regenerate.
789 * mep-opc.h: Regenerate.
790 * mt-desc.h: Regenerate.
791 * mt-opc.h: Regenerate.
792 * or1k-desc.h: Regenerate.
793 * or1k-opc.h: Regenerate.
794 * xc16x-desc.h: Regenerate.
795 * xc16x-opc.h: Regenerate.
796 * xstormy16-desc.h: Regenerate.
797 * xstormy16-opc.h: Regenerate.
798
2571583a
AM		 7992017-01-02 Alan Modra <amodra@gmail.com>
800
801 Update year range in copyright notice of all files.
802
5c1ad6b5 803For older changes see ChangeLog-2016
3499769a 804\f
5c1ad6b5 805Copyright (C) 2017 Free Software Foundation, Inc.
3499769a
AM		 806
807Copying and distribution of this file, with or without modification,
808are permitted in any medium without royalty provided the copyright
809notice and this notice are preserved.
810
811Local Variables:
812mode: change-log
813left-margin: 8
814fill-column: 74
815version-control: never
816End:
GDB Binutils - Deliverables
This page took 0.133891 seconds and 4 git commands to generate.