[deliverable/binutils-gdb.git] / opcodes / ChangeLog

2017-03-29  Sheldon Lobo  <sheldon.lobo@oracle.com>

	Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
	OSA2015.
	* opcodes/sparc-opc.c (asi_table): New ASIs.

2017-03-29  Alan Modra  <amodra@gmail.com>

	* ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags.  Add
	"raw" option.
	(lookup_powerpc): Don't special case -1 dialect.  Handle
	PPC_OPCODE_RAW.
	(print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
	lookup_powerpc call, pass it on second.

2017-03-27  Alan Modra  <amodra@gmail.com>

	PR 21303
	* ppc-dis.c (struct ppc_mopt): Comment.
	(ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.

2017-03-27  Rinat Zelig  <rinat@mellanox.com>

	* arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
	* arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
	F_NPS_M, F_NPS_CORE, F_NPS_ALL.
	(insert_nps_misc_imm_offset): New function.
	(extract_nps_misc imm_offset): New function.
	(arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
	(arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.

2017-03-21  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* s390-mkopc.c (main): Remove vx2 check.
	* s390-opc.txt: Remove vx2 instruction flags.

2017-03-21  Rinat Zelig  <rinat@mellanox.com>

	* arc-nps400-tbl.h: Add cp32/cp16 instructions format.
	* arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
	(insert_nps_imm_offset): New function.
	(extract_nps_imm_offset): New function.
	(insert_nps_imm_entry): New function.
	(extract_nps_imm_entry): New function.

2017-03-17  Alan Modra  <amodra@gmail.com>

	PR 21248
	* ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
	mtivor32, and mtivor33 for e6500.  Move mfibatl and mfibatu after
	those spr mnemonics they alias.  Similarly for mtibatl, mtibatu.

2017-03-14  Kito Cheng  <kito.cheng@gmail.com>

	* riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
	<c.andi>: Likewise.
	<c.addiw> Likewise.

2017-03-14  Kito Cheng  <kito.cheng@gmail.com>

	* riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.

2017-03-13  Andrew Waterman  <andrew@sifive.com>

	* riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
	<srl> Likewise.
	<srai> Likewise.
	<sra> Likewise.

2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (opcode_modifiers): Replace S with Load.
	* i386-opc.h (S): Removed.
	(Load): New.
	(i386_opcode_modifier): Replace s with load.
	* i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
	and {evex}.  Replace S with Load.
	* i386-tbl.h: Regenerated.

2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.tbl: Use CpuCET on rdsspq.
	* i386-tbl.h: Regenerated.

2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>

	* ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
	<vsx>: Do not use PPC_OPCODE_VSX3;

2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>

	* ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.

2017-03-06  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (REG_0F1E_MOD_3): New enum.
	(MOD_0F1E_PREFIX_1): Likewise.
	(MOD_0F38F5_PREFIX_2): Likewise.
	(MOD_0F38F6_PREFIX_0): Likewise.
	(RM_0F1E_MOD_3_REG_7): Likewise.
	(PREFIX_MOD_0_0F01_REG_5): Likewise.
	(PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
	(PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
	(PREFIX_0F1E): Likewise.
	(PREFIX_MOD_0_0FAE_REG_5): Likewise.
	(PREFIX_0F38F5): Likewise.
	(dis386_twobyte): Use PREFIX_0F1E.
	(reg_table): Add REG_0F1E_MOD_3.
	(prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
	PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
	PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5.  Update
	PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
	(three_byte_table): Use PREFIX_0F38F5.
	(mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
	Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
	(rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
	RM_0F1E_MOD_3_REG_7.  Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
	PREFIX_MOD_3_0F01_REG_5_RM_2.
	* i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
	(cpu_flags): Add CpuCET.
	* i386-opc.h (CpuCET): New enum.
	(CpuUnused): Commented out.
	(i386_cpu_flags): Add cpucet.
	* i386-opc.tbl: Add Intel CET instructions.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2017-03-06  Alan Modra  <amodra@gmail.com>

	PR 21124
	* ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
	(extract_raq, extract_ras, extract_rbx): New functions.
	(powerpc_operands): Use opposite corresponding insert function.
	(Q_MASK): Define.
	(powerpc_opcodes): Apply Q_MASK to all quad insns with even
	register restriction.

2017-02-28  Peter Bergner  <bergner@vnet.ibm.com>

	* disassemble.c Include "safe-ctype.h".
	(disassemble_init_for_target): Handle s390 init.
	(remove_whitespace_and_extra_commas): New function.
	(disassembler_options_cmp): Likewise.
	* arm-dis.c: Include "libiberty.h".
	(NUM_ELEM): Delete.
	(regnames): Use long disassembler style names.
	Add force-thumb and no-force-thumb options.
	(NUM_ARM_REGNAMES): Rename from this...
	(NUM_ARM_OPTIONS): ...to this.  Use ARRAY_SIZE.
	(get_arm_regname_num_options): Delete.
	(set_arm_regname_option): Likewise.
	(get_arm_regnames): Likewise.
	(parse_disassembler_options): Likewise.
	(parse_arm_disassembler_option): Rename from this...
	(parse_arm_disassembler_options): ...to this.  Make static.
	Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
	(print_insn): Use parse_arm_disassembler_options.
	(disassembler_options_arm): New function.
	(print_arm_disassembler_options): Handle updated regnames.
	* ppc-dis.c: Include "libiberty.h".
	(ppc_opts): Add "32" and "64" entries.
	(ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
	(powerpc_init_dialect): Add break to switch statement.
	Use new FOR_EACH_DISASSEMBLER_OPTION macro.
	(disassembler_options_powerpc): New function.
	(print_ppc_disassembler_options): Use ARRAY_SIZE.
	Remove printing of "32" and "64".
	* s390-dis.c: Include "libiberty.h".
	(init_flag): Remove unneeded variable.
	(struct s390_options_t): New structure type.
	(options): New structure.
	(init_disasm): Rename from this...
	(disassemble_init_s390): ...to this.  Add initializations for
	current_arch_mask and option_use_insn_len_bits_p.  Remove init_flag.
	(print_insn_s390): Delete call to init_disasm.
	(disassembler_options_s390): New function.
	(print_s390_disassembler_options): Print using information from
	struct 'options'.
	* po/opcodes.pot: Regenerate.

2017-02-28  Jan Beulich  <jbeulich@suse.com>

	* i386-dis.c (PCMPESTR_Fixup): New.
	(VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
	(prefix_table): Use PCMPESTR_Fixup.
	(vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
	PCMPESTR_Fixup.
	(vex_w_table): Delete VPCMPESTR{I,M} entries.
	* i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
	Split 64-bit and non-64-bit variants.
	* opcodes/i386-tbl.h: Re-generate.

2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>

	* aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
	(OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
	(OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
	(OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
	(OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
	(OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
	(OP_SVE_V_HSD): New macros.
	(OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
	(OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
	(OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
	(aarch64_opcode_table): Add new SVE instructions.
	(aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
	for rotation operands.  Add new SVE operands.
	* aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
	(ins_sve_quad_index): Likewise.
	(ins_imm_rotate): Split into...
	(ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
	* aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
	(aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
	functions.
	(aarch64_ins_sve_addr_ri_s4): New function.
	(aarch64_ins_sve_quad_index): Likewise.
	(do_misc_encoding): Handle "MOV Zn.Q, Qm".
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
	(ext_sve_quad_index): Likewise.
	(ext_imm_rotate): Split into...
	(ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
	* aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
	(aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
	functions.
	(aarch64_ext_sve_addr_ri_s4): New function.
	(aarch64_ext_sve_quad_index): Likewise.
	(aarch64_ext_sve_index): Allow quad indices.
	(do_misc_decoding): Likewise.
	* aarch64-dis-2.c: Regenerate.
	* aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
	aarch64_field_kinds.
	(OPD_F_OD_MASK): Widen by one bit.
	(OPD_F_NO_ZR): Bump accordingly.
	(get_operand_field_width): New function.
	* aarch64-opc.c (fields): Add new SVE fields.
	(operand_general_constraint_met_p): Handle new SVE operands.
	(aarch64_print_operand): Likewise.
	* aarch64-opc-2.c: Regenerate.

2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>

	* aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
	(aarch64_feature_compnum): ...this.
	(SIMD_V8_3): Replace with...
	(COMPNUM): ...this.
	(CNUM_INSN): New macro.
	(aarch64_opcode_table): Use it for the complex number instructions.

2017-02-24  Jan Beulich  <jbeulich@suse.com>

	* i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.

2017-02-23  Sheldon Lobo <sheldon.lobo@oracle.com>

	Add support for associating SPARC ASIs with an architecture level.
	* include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
	* opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
	decoding of SPARC ASIs.

2017-02-23  Jan Beulich  <jbeulich@suse.com>

	* i386-dis.c (get_valid_dis386): Don't special case VEX opcode
	82. For 3-byte VEX only special case opcode 77 in VEX_0F space.

2017-02-21  Jan Beulich  <jbeulich@suse.com>

	* aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
	1 (instead of to itself). Correct typo.

2017-02-14  Andrew Waterman  <andrew@sifive.com>

	* riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
	pseudoinstructions.

2017-02-15  Richard Sandiford  <richard.sandiford@arm.com>

	* aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
	(aarch64_sys_reg_supported_p): Handle them.

2017-02-15  Claudiu Zissulescu  <claziss@synopsys.com>

	* arc-opc.c (UIMM6_20R): Define.
	(SIMM12_20): Use above.
	(SIMM12_20R): Define.
	(SIMM3_5_S): Use above.
	(UIMM7_A32_11R_S): Define.
	(UIMM7_9_S): Use above.
	(UIMM3_13R_S): Define.
	(SIMM11_A32_7_S): Use above.
	(SIMM9_8R): Define.
	(UIMM10_A32_8_S): Use above.
	(UIMM8_8R_S): Define.
	(W6): Use above.
	(arc_relax_opcodes): Use all above defines.

2017-02-15  Vineet Gupta <vgupta@synopsys.com>

	* arc-regs.h: Distinguish some of the registers different on
	ARC700 and HS38 cpus.

2017-02-14  Alan Modra  <amodra@gmail.com>

	PR 21118
	* ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
	with PPC_OPERAND_SPR.  Flag PSQ and PSQM with PPC_OPERAND_GQR.

2017-02-11  Stafford Horne  <shorne@gmail.com>
	    Alan Modra  <amodra@gmail.com>

	* cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
	Use insn_bytes_value and insn_int_value directly instead.  Don't
	free allocated memory until function exit.

2017-02-10  Nicholas Piggin  <npiggin@gmail.com>

	* ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.

2017-02-03  Nick Clifton  <nickc@redhat.com>

	PR 21096
	* aarch64-opc.c (print_register_list): Ensure that the register
	list index will fir into the tb buffer.
	(print_register_offset_address): Likewise.
	* tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.

2017-01-27  Alexis Deruell  <alexis.deruelle@gmail.com>

	PR 21056
	* tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
	instructions when the previous fetch packet ends with a 32-bit
	instruction.

2017-01-24  Dimitar Dimitrov  <dimitar@dinux.eu>

        * pru-opc.c: Remove vague reference to a future GDB port.

2017-01-20  Nick Clifton  <nickc@redhat.com>

	* po/ga.po: Updated Irish translation.

2017-01-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>

	* arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.

2017-01-13  Yao Qi  <yao.qi@linaro.org>

	* m68k-dis.c (match_insn_m68k): Extend comments.  Return -1
	if FETCH_DATA returns 0.
	(m68k_scan_mask): Likewise.
	(print_insn_m68k): Update code to handle -1 return value.

2017-01-13  Yao Qi  <yao.qi@linaro.org>

	* m68k-dis.c (enum print_insn_arg_error): New.
	(NEXTBYTE): Replace -3 with
	PRINT_INSN_ARG_MEMORY_ERROR.
	(NEXTULONG): Likewise.
	(NEXTSINGLE): Likewise.
	(NEXTDOUBLE): Likewise.
	(NEXTDOUBLE): Likewise.
	(NEXTPACKED): Likewise.
	(FETCH_ARG): Likewise.
	(FETCH_DATA): Update comments.
	(print_insn_arg): Update comments. Replace magic numbers with
	enum.
	(match_insn_m68k): Likewise.

2017-01-12  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>

	* i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
	* i386-dis-evex.h (evex_table): Updated.
	* i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
	CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
	(cpu_flags): Add CpuAVX512_VPOPCNTDQ.
	* i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
	(i386_cpu_flags): Add cpuavx512_vpopcntdq.
	* i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
	* i386-init.h: Regenerate.
	* i386-tbl.h: Ditto.

2017-01-12  Yao Qi  <yao.qi@linaro.org>

	* msp430-dis.c (msp430_singleoperand): Return -1 if
	msp430dis_opcode_signed returns false.
	(msp430_doubleoperand): Likewise.
	(msp430_branchinstr): Return -1 if
	msp430dis_opcode_unsigned returns false.
	(msp430x_calla_instr): Likewise.
	(print_insn_msp430): Likewise.

2017-01-05  Nick Clifton  <nickc@redhat.com>

	PR 20946
	* frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
	could not be matched.
	(frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
	NULL.

2017-01-04  Szabolcs Nagy  <szabolcs.nagy@arm.com>

	* aarch64-tbl.h (RCPC, RCPC_INSN): Define.
	(aarch64_opcode_table): Use RCPC_INSN.

2017-01-03  Kito Cheng  <kito.cheng@gmail.com>

	* riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
	extension.
	* riscv-opcodes/all-opcodes: Likewise.

2017-01-03  Dilyan Palauzov  <dilyan.palauzov@aegee.org>

	* riscv-dis.c (print_insn_args): Add fall through comment.

2017-01-03  Nick Clifton  <nickc@redhat.com>

	* po/sr.po: New Serbian translation.
	* configure.ac (ALL_LINGUAS): Add sr.
	* configure: Regenerate.

2017-01-02  Alan Modra  <amodra@gmail.com>

	* epiphany-desc.h: Regenerate.
	* epiphany-opc.h: Regenerate.
	* fr30-desc.h: Regenerate.
	* fr30-opc.h: Regenerate.
	* frv-desc.h: Regenerate.
	* frv-opc.h: Regenerate.
	* ip2k-desc.h: Regenerate.
	* ip2k-opc.h: Regenerate.
	* iq2000-desc.h: Regenerate.
	* iq2000-opc.h: Regenerate.
	* lm32-desc.h: Regenerate.
	* lm32-opc.h: Regenerate.
	* m32c-desc.h: Regenerate.
	* m32c-opc.h: Regenerate.
	* m32r-desc.h: Regenerate.
	* m32r-opc.h: Regenerate.
	* mep-desc.h: Regenerate.
	* mep-opc.h: Regenerate.
	* mt-desc.h: Regenerate.
	* mt-opc.h: Regenerate.
	* or1k-desc.h: Regenerate.
	* or1k-opc.h: Regenerate.
	* xc16x-desc.h: Regenerate.
	* xc16x-opc.h: Regenerate.
	* xstormy16-desc.h: Regenerate.
	* xstormy16-opc.h: Regenerate.

2017-01-02  Alan Modra  <amodra@gmail.com>

	Update year range in copyright notice of all files.

For older changes see ChangeLog-2016
\f
Copyright (C) 2017 Free Software Foundation, Inc.

Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved.

Local Variables:
mode: change-log
left-margin: 8
fill-column: 74
version-control: never
End:
Commit	Line	Data
f7c514a3 JM	1	2017-03-29 Sheldon Lobo <sheldon.lobo@oracle.com>
	2
	3	Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
	4	OSA2015.
	5	* opcodes/sparc-opc.c (asi_table): New ASIs.
	6
52be03fd AM	7	2017-03-29 Alan Modra <amodra@gmail.com>
	8
	9	* ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add
	10	"raw" option.
	11	(lookup_powerpc): Don't special case -1 dialect. Handle
	12	PPC_OPCODE_RAW.
	13	(print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
	14	lookup_powerpc call, pass it on second.
	15
9b753937 AM	16	2017-03-27 Alan Modra <amodra@gmail.com>
	17
	18	PR 21303
	19	* ppc-dis.c (struct ppc_mopt): Comment.
	20	(ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
	21
c0c31e91 RZ	22	2017-03-27 Rinat Zelig <rinat@mellanox.com>
	23
	24	* arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
	25	* arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
	26	F_NPS_M, F_NPS_CORE, F_NPS_ALL.
	27	(insert_nps_misc_imm_offset): New function.
	28	(extract_nps_misc imm_offset): New function.
	29	(arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
	30	(arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
	31
2253c8f0 AK	32	2017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
	33
	34	* s390-mkopc.c (main): Remove vx2 check.
	35	* s390-opc.txt: Remove vx2 instruction flags.
	36
645d3342 RZ	37	2017-03-21 Rinat Zelig <rinat@mellanox.com>
	38
	39	* arc-nps400-tbl.h: Add cp32/cp16 instructions format.
	40	* arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
	41	(insert_nps_imm_offset): New function.
	42	(extract_nps_imm_offset): New function.
	43	(insert_nps_imm_entry): New function.
	44	(extract_nps_imm_entry): New function.
	45
4b94dd2d AM	46	2017-03-17 Alan Modra <amodra@gmail.com>
	47
	48	PR 21248
	49	* ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
	50	mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after
	51	those spr mnemonics they alias. Similarly for mtibatl, mtibatu.
	52
b416fe87 KC	53	2017-03-14 Kito Cheng <kito.cheng@gmail.com>
	54
	55	* riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
	56	<c.andi>: Likewise.
	57	<c.addiw> Likewise.
	58
03b039a5 KC	59	2017-03-14 Kito Cheng <kito.cheng@gmail.com>
	60
	61	* riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
	62
2c232b83 AW	63	2017-03-13 Andrew Waterman <andrew@sifive.com>
	64
	65	* riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
	66	<srl> Likewise.
	67	<srai> Likewise.
	68	<sra> Likewise.
	69
86fa6981 L	70	2017-03-09 H.J. Lu <hongjiu.lu@intel.com>
	71
	72	* i386-gen.c (opcode_modifiers): Replace S with Load.
	73	* i386-opc.h (S): Removed.
	74	(Load): New.
	75	(i386_opcode_modifier): Replace s with load.
	76	* i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
	77	and {evex}. Replace S with Load.
	78	* i386-tbl.h: Regenerated.
	79
c1fe188b L	80	2017-03-09 H.J. Lu <hongjiu.lu@intel.com>
	81
	82	* i386-opc.tbl: Use CpuCET on rdsspq.
	83	* i386-tbl.h: Regenerated.
	84
4b8b687e PB	85	2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
	86
	87	* ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
	88	<vsx>: Do not use PPC_OPCODE_VSX3;
	89
1437d063 PB	90	2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
	91
	92	* ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
	93
603555e5 L	94	2017-03-06 H.J. Lu <hongjiu.lu@intel.com>
	95
	96	* i386-dis.c (REG_0F1E_MOD_3): New enum.
	97	(MOD_0F1E_PREFIX_1): Likewise.
	98	(MOD_0F38F5_PREFIX_2): Likewise.
	99	(MOD_0F38F6_PREFIX_0): Likewise.
	100	(RM_0F1E_MOD_3_REG_7): Likewise.
	101	(PREFIX_MOD_0_0F01_REG_5): Likewise.
	102	(PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
	103	(PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
	104	(PREFIX_0F1E): Likewise.
	105	(PREFIX_MOD_0_0FAE_REG_5): Likewise.
	106	(PREFIX_0F38F5): Likewise.
	107	(dis386_twobyte): Use PREFIX_0F1E.
	108	(reg_table): Add REG_0F1E_MOD_3.
	109	(prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
	110	PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
	111	PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
	112	PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
	113	(three_byte_table): Use PREFIX_0F38F5.
	114	(mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
	115	Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
	116	(rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
	117	RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
	118	PREFIX_MOD_3_0F01_REG_5_RM_2.
	119	* i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
	120	(cpu_flags): Add CpuCET.
	121	* i386-opc.h (CpuCET): New enum.
	122	(CpuUnused): Commented out.
	123	(i386_cpu_flags): Add cpucet.
	124	* i386-opc.tbl: Add Intel CET instructions.
	125	* i386-init.h: Regenerated.
	126	* i386-tbl.h: Likewise.
	127
73f07bff AM	128	2017-03-06 Alan Modra <amodra@gmail.com>
	129
	130	PR 21124
	131	* ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
	132	(extract_raq, extract_ras, extract_rbx): New functions.
	133	(powerpc_operands): Use opposite corresponding insert function.
	134	(Q_MASK): Define.
	135	(powerpc_opcodes): Apply Q_MASK to all quad insns with even
	136	register restriction.
	137
65b48a81 PB	138	2017-02-28 Peter Bergner <bergner@vnet.ibm.com>
	139
	140	* disassemble.c Include "safe-ctype.h".
	141	(disassemble_init_for_target): Handle s390 init.
	142	(remove_whitespace_and_extra_commas): New function.
	143	(disassembler_options_cmp): Likewise.
	144	* arm-dis.c: Include "libiberty.h".
	145	(NUM_ELEM): Delete.
	146	(regnames): Use long disassembler style names.
	147	Add force-thumb and no-force-thumb options.
	148	(NUM_ARM_REGNAMES): Rename from this...
	149	(NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE.
	150	(get_arm_regname_num_options): Delete.
	151	(set_arm_regname_option): Likewise.
	152	(get_arm_regnames): Likewise.
	153	(parse_disassembler_options): Likewise.
	154	(parse_arm_disassembler_option): Rename from this...
	155	(parse_arm_disassembler_options): ...to this. Make static.
	156	Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
	157	(print_insn): Use parse_arm_disassembler_options.
	158	(disassembler_options_arm): New function.
	159	(print_arm_disassembler_options): Handle updated regnames.
	160	* ppc-dis.c: Include "libiberty.h".
	161	(ppc_opts): Add "32" and "64" entries.
	162	(ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
	163	(powerpc_init_dialect): Add break to switch statement.
	164	Use new FOR_EACH_DISASSEMBLER_OPTION macro.
	165	(disassembler_options_powerpc): New function.
	166	(print_ppc_disassembler_options): Use ARRAY_SIZE.
	167	Remove printing of "32" and "64".
	168	* s390-dis.c: Include "libiberty.h".
	169	(init_flag): Remove unneeded variable.
	170	(struct s390_options_t): New structure type.
	171	(options): New structure.
	172	(init_disasm): Rename from this...
	173	(disassemble_init_s390): ...to this. Add initializations for
	174	current_arch_mask and option_use_insn_len_bits_p. Remove init_flag.
	175	(print_insn_s390): Delete call to init_disasm.
	176	(disassembler_options_s390): New function.
	177	(print_s390_disassembler_options): Print using information from
	178	struct 'options'.
	179	* po/opcodes.pot: Regenerate.
	180
15c7c1d8 JB	181	2017-02-28 Jan Beulich <jbeulich@suse.com>
	182
	183	* i386-dis.c (PCMPESTR_Fixup): New.
	184	(VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
	185	(prefix_table): Use PCMPESTR_Fixup.
	186	(vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
	187	PCMPESTR_Fixup.
	188	(vex_w_table): Delete VPCMPESTR{I,M} entries.
	189	* i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
	190	Split 64-bit and non-64-bit variants.
	191	* opcodes/i386-tbl.h: Re-generate.
	192
582e12bf RS	193	2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
	194
	195	* aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
	196	(OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
	197	(OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
	198	(OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
	199	(OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
	200	(OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
	201	(OP_SVE_V_HSD): New macros.
	202	(OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
	203	(OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
	204	(OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
	205	(aarch64_opcode_table): Add new SVE instructions.
	206	(aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
	207	for rotation operands. Add new SVE operands.
	208	* aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
	209	(ins_sve_quad_index): Likewise.
	210	(ins_imm_rotate): Split into...
	211	(ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
	212	* aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
	213	(aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
	214	functions.
	215	(aarch64_ins_sve_addr_ri_s4): New function.
	216	(aarch64_ins_sve_quad_index): Likewise.
	217	(do_misc_encoding): Handle "MOV Zn.Q, Qm".
	218	* aarch64-asm-2.c: Regenerate.
	219	* aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
	220	(ext_sve_quad_index): Likewise.
	221	(ext_imm_rotate): Split into...
	222	(ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
	223	* aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
	224	(aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
	225	functions.
	226	(aarch64_ext_sve_addr_ri_s4): New function.
	227	(aarch64_ext_sve_quad_index): Likewise.
	228	(aarch64_ext_sve_index): Allow quad indices.
	229	(do_misc_decoding): Likewise.
	230	* aarch64-dis-2.c: Regenerate.
	231	* aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
	232	aarch64_field_kinds.
	233	(OPD_F_OD_MASK): Widen by one bit.
	234	(OPD_F_NO_ZR): Bump accordingly.
	235	(get_operand_field_width): New function.
	236	* aarch64-opc.c (fields): Add new SVE fields.
	237	(operand_general_constraint_met_p): Handle new SVE operands.
	238	(aarch64_print_operand): Likewise.
	239	* aarch64-opc-2.c: Regenerate.
	240
f482d304 RS	241	2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
	242
	243	* aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
	244	(aarch64_feature_compnum): ...this.
	245	(SIMD_V8_3): Replace with...
	246	(COMPNUM): ...this.
	247	(CNUM_INSN): New macro.
	248	(aarch64_opcode_table): Use it for the complex number instructions.
	249
7db2c588 JB	250	2017-02-24 Jan Beulich <jbeulich@suse.com>
	251
	252	* i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
	253
1e9d41d4 SL	254	2017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
	255
	256	Add support for associating SPARC ASIs with an architecture level.
	257	* include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
	258	* opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
	259	decoding of SPARC ASIs.
	260
53c4d625 JB	261	2017-02-23 Jan Beulich <jbeulich@suse.com>
	262
	263	* i386-dis.c (get_valid_dis386): Don't special case VEX opcode
	264	82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
	265
11648de5 JB	266	2017-02-21 Jan Beulich <jbeulich@suse.com>
	267
	268	* aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
	269	1 (instead of to itself). Correct typo.
	270
f98d33be AW	271	2017-02-14 Andrew Waterman <andrew@sifive.com>
	272
	273	* riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
	274	pseudoinstructions.
	275
773fb663 RS	276	2017-02-15 Richard Sandiford <richard.sandiford@arm.com>
	277
	278	* aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
	279	(aarch64_sys_reg_supported_p): Handle them.
	280
cc07cda6 CZ	281	2017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
	282
	283	* arc-opc.c (UIMM6_20R): Define.
	284	(SIMM12_20): Use above.
	285	(SIMM12_20R): Define.
	286	(SIMM3_5_S): Use above.
	287	(UIMM7_A32_11R_S): Define.
	288	(UIMM7_9_S): Use above.
	289	(UIMM3_13R_S): Define.
	290	(SIMM11_A32_7_S): Use above.
	291	(SIMM9_8R): Define.
	292	(UIMM10_A32_8_S): Use above.
	293	(UIMM8_8R_S): Define.
	294	(W6): Use above.
	295	(arc_relax_opcodes): Use all above defines.
	296
66a5a740 VG	297	2017-02-15 Vineet Gupta <vgupta@synopsys.com>
	298
	299	* arc-regs.h: Distinguish some of the registers different on
	300	ARC700 and HS38 cpus.
	301
7e0de605 AM	302	2017-02-14 Alan Modra <amodra@gmail.com>
	303
	304	PR 21118
	305	* ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
	306	with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
	307
54064fdb AM	308	2017-02-11 Stafford Horne <shorne@gmail.com>
	309	Alan Modra <amodra@gmail.com>
	310
	311	* cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
	312	Use insn_bytes_value and insn_int_value directly instead. Don't
	313	free allocated memory until function exit.
	314
dce75bf9 NP	315	2017-02-10 Nicholas Piggin <npiggin@gmail.com>
	316
	317	* ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
	318
1b7e3d2f NC	319	2017-02-03 Nick Clifton <nickc@redhat.com>
	320
	321	PR 21096
	322	* aarch64-opc.c (print_register_list): Ensure that the register
	323	list index will fir into the tb buffer.
	324	(print_register_offset_address): Likewise.
	325	* tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
	326
8ec5cf65 AD	327	2017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
	328
	329	PR 21056
	330	* tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
	331	instructions when the previous fetch packet ends with a 32-bit
	332	instruction.
	333
a1aa5e81 DD	334	2017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
	335
	336	* pru-opc.c: Remove vague reference to a future GDB port.
	337
add3afb2 NC	338	2017-01-20 Nick Clifton <nickc@redhat.com>
	339
	340	* po/ga.po: Updated Irish translation.
	341
c13a63b0 SN	342	2017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
	343
	344	* arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
	345
9608051a YQ	346	2017-01-13 Yao Qi <yao.qi@linaro.org>
	347
	348	* m68k-dis.c (match_insn_m68k): Extend comments. Return -1
	349	if FETCH_DATA returns 0.
	350	(m68k_scan_mask): Likewise.
	351	(print_insn_m68k): Update code to handle -1 return value.
	352
f622ea96 YQ	353	2017-01-13 Yao Qi <yao.qi@linaro.org>
	354
	355	* m68k-dis.c (enum print_insn_arg_error): New.
	356	(NEXTBYTE): Replace -3 with
	357	PRINT_INSN_ARG_MEMORY_ERROR.
	358	(NEXTULONG): Likewise.
	359	(NEXTSINGLE): Likewise.
	360	(NEXTDOUBLE): Likewise.
	361	(NEXTDOUBLE): Likewise.
	362	(NEXTPACKED): Likewise.
	363	(FETCH_ARG): Likewise.
	364	(FETCH_DATA): Update comments.
	365	(print_insn_arg): Update comments. Replace magic numbers with
	366	enum.
	367	(match_insn_m68k): Likewise.
	368
620214f7 IT	369	2017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
	370
	371	* i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
	372	* i386-dis-evex.h (evex_table): Updated.
	373	* i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
	374	CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
	375	(cpu_flags): Add CpuAVX512_VPOPCNTDQ.
	376	* i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
	377	(i386_cpu_flags): Add cpuavx512_vpopcntdq.
	378	* i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
	379	* i386-init.h: Regenerate.
	380	* i386-tbl.h: Ditto.
	381
d95014a2 YQ	382	2017-01-12 Yao Qi <yao.qi@linaro.org>
	383
	384	* msp430-dis.c (msp430_singleoperand): Return -1 if
	385	msp430dis_opcode_signed returns false.
	386	(msp430_doubleoperand): Likewise.
	387	(msp430_branchinstr): Return -1 if
	388	msp430dis_opcode_unsigned returns false.
	389	(msp430x_calla_instr): Likewise.
	390	(print_insn_msp430): Likewise.
	391
0ae60c3e NC	392	2017-01-05 Nick Clifton <nickc@redhat.com>
	393
	394	PR 20946
	395	* frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
	396	could not be matched.
	397	(frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
	398	NULL.
	399
d74d4880 SN	400	2017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
	401
	402	* aarch64-tbl.h (RCPC, RCPC_INSN): Define.
	403	(aarch64_opcode_table): Use RCPC_INSN.
	404
cc917fd9 KC	405	2017-01-03 Kito Cheng <kito.cheng@gmail.com>
	406
	407	* riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
	408	extension.
	409	* riscv-opcodes/all-opcodes: Likewise.
	410
b52d3cfc DP	411	2017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
	412
	413	* riscv-dis.c (print_insn_args): Add fall through comment.
	414
f90c58d5 NC	415	2017-01-03 Nick Clifton <nickc@redhat.com>
	416
	417	* po/sr.po: New Serbian translation.
	418	* configure.ac (ALL_LINGUAS): Add sr.
	419	* configure: Regenerate.
	420
f47b0d4a AM	421	2017-01-02 Alan Modra <amodra@gmail.com>
	422
	423	* epiphany-desc.h: Regenerate.
	424	* epiphany-opc.h: Regenerate.
	425	* fr30-desc.h: Regenerate.
	426	* fr30-opc.h: Regenerate.
	427	* frv-desc.h: Regenerate.
	428	* frv-opc.h: Regenerate.
	429	* ip2k-desc.h: Regenerate.
	430	* ip2k-opc.h: Regenerate.
	431	* iq2000-desc.h: Regenerate.
	432	* iq2000-opc.h: Regenerate.
	433	* lm32-desc.h: Regenerate.
	434	* lm32-opc.h: Regenerate.
	435	* m32c-desc.h: Regenerate.
	436	* m32c-opc.h: Regenerate.
	437	* m32r-desc.h: Regenerate.
	438	* m32r-opc.h: Regenerate.
	439	* mep-desc.h: Regenerate.
	440	* mep-opc.h: Regenerate.
	441	* mt-desc.h: Regenerate.
	442	* mt-opc.h: Regenerate.
	443	* or1k-desc.h: Regenerate.
	444	* or1k-opc.h: Regenerate.
	445	* xc16x-desc.h: Regenerate.
	446	* xc16x-opc.h: Regenerate.
	447	* xstormy16-desc.h: Regenerate.
	448	* xstormy16-opc.h: Regenerate.
	449
2571583a AM	450	2017-01-02 Alan Modra <amodra@gmail.com>
	451
	452	Update year range in copyright notice of all files.
	453
5c1ad6b5	454	For older changes see ChangeLog-2016
3499769a	455	\f
5c1ad6b5	456	Copyright (C) 2017 Free Software Foundation, Inc.
3499769a AM	457
	458	Copying and distribution of this file, with or without modification,
	459	are permitted in any medium without royalty provided the copyright
	460	notice and this notice are preserved.
	461
	462	Local Variables:
	463	mode: change-log
	464	left-margin: 8
	465	fill-column: 74
	466	version-control: never
	467	End: