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x86: correct UDn
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
66f1eba0
JB		 12017-11-23 Jan Beulich <jbeulich@suse.com>
2
3 * i386-dis.c (dis386_twobyte): Correct ud1. Add ud0.
4 (twobyte_has_modrm): Set flag for index 0xb9 and 0xff.
5 * i386-opc.tbl (ud1, ud2b): Add operands.
6 (ud0): New.
7 * i386-tbl.h: Re-generate.
8
94b98370
IT		 92017-11-22 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
10
11 * i386-opc.tbl: Remove Vec_Disp8 from vgf2p8mulb.
12 * i386-tbl.h: Regenerate.
13
6f19e86d
IT		 142017-11-22 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
15
16 * i386-opc.tbl: Remove Vec_Disp8 from vpcompressb and vpexpandb.
17 * i386-tbl.h: Regenerate.
18
dc958481 192017-11-22 Claudiu Zissulescu <claziss@synopsys.com>
20
21 *arc-opc (insert_rhv2): Check h-regs range.
22
50d2740d 232017-11-21 Claudiu Zissulescu <claziss@synopsys.com>
24
25 * arc-dis.c (print_insn_arc): Pretty print pc-relative offsets.
26 * arc-opc.c (SIMM21_A16_5): Make it pc-relative.
27
d0f7791c
TC		 282017-11-16 Tamar Christina <tamar.christina@arm.com>
29
30 * aarch64-tbl.h (aarch64_feature_fp_16_v8_2): Require AARCH64_FEATURE_F16_FML
31 and AARCH64_FEATURE_F16.
32
e9dbdd80
TC		 332017-11-16 Tamar Christina <tamar.christina@arm.com>
34
35 * aarch64-tbl.h (sha512h, sha512h2, sha512su0, sha512su1, eor3): New.
36 (rax1, xar, bcax, sm3ss1, sm3tt1a, sm3tt1b, sm3tt2a, sm3tt2b): New.
37 (sm3partw1, sm3partw2, sm4e, sm4ekey, fmlal, fmlsl): New.
38 (fmlal2, fmlsl2, cfinv, rmif, setf8, setf16, stlurb): New.
39 (ldapurb, ldapursb, stlurh, ldapurh, ldapursh, stlur): New.
40 (ldapur, ldapursw, stlur): New.
41 * aarch64-dis-2.c: Regenerate.
42
5f847646
JB		 432017-11-16 Jan Beulich <jbeulich@suse.com>
44
45 (get_valid_dis386): Never flag bad opcode when
46 vex.register_specifier is beyond 7. Always store all four
47 bits of it. Move 16-/32-bit override in EVEX handling after
48 all to be overridden bits have been set.
49 (OP_VEX): Mask vex.register_specifier outside of 64-bit mode.
50 Use rex to determine GPR register set.
51 (OP_EX_VexReg, OP_Vex_2src_1, OP_Vex_2src_2, OP_REG_VexI4,
52 OP_LWP_E): Mask vex.register_specifier outside of 64-bit mode.
53
390a6789
JB		 542017-11-15 Jan Beulich <jbeulich@suse.com>
55
56 * i386-dis.c (OP_VEX, OP_LWPCB_E, OP_LWP_E): Use rex to
57 determine GPR register set.
58
3a2430e0
JB		 592017-11-15 Jan Beulich <jbeulich@suse.com>
60
61 * i386-dis.c (VEXI4_Fixup, VexI4): Delete.
62 (prefix_table, xop_table, vex_len_table): Remove VexI4 uses.
63 (OP_EX_VexW): Move setting of vex_w_done. Update codep on 2nd
64 pass.
65 (OP_REG_VexI4): Drop low 4 bits check.
66
0645f0a2
JB		 672017-11-15 Jan Beulich <jbeulich@suse.com>
68
69 * i386-reg.tbl (axl): Remove Acc and Byte.
70 * i386-tbl.h: Re-generate.
71
be92cb14
JB		 722017-11-14 Jan Beulich <jbeulich@suse.com>
73
74 * i386-dis.c (VPCOM_Fixup, VPCOM, xop_cmp_op): New.
75 (vex_len_table): Use VPCOM.
76
2645e1d0
JB		 772017-11-14 Jan Beulich <jbeulich@suse.com>
78
79 * i386-dis-evex.h (evex_table[EVEX_W_0F3A3E_P_2]): Use VPCMP.
80 (evex_table[EVEX_W_0F3A3F_P_2]): Likewise.
81 * i386-opc.tbl (vpcmpeqb, vpcmpgtb, vpcmpeqw, vpcmpgtw, vpcmpuw,
82 vpcmpw): Move up.
83 (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb, vpcmpnleb, vpcmpnltb,
84 vpcmpequb, vpcmpleub, vpcmpltub, vpcmpnequb, vpcmpnleub,
85 vpcmpnltub, vpcmpeqw, vpcmplew, vpcmpltw, vpcmpneqw, vpcmpnlew,
86 vpcmpnltw, vpcmpequw, vpcmpleuw, vpcmpltuw, vpcmpnequw, vpcmpnleuw,
87 vpcmpnltuw): New.
88 * i386-tbl.h: Re-generate.
89
df145ef6
JB		 902017-11-14 Jan Beulich <jbeulich@suse.com>
91
92 * i386-opc.tbl (cmps, ins, lods, movs, outs, scas, scmp, slod,
93 smov, ssca, stos, ssto, xlat): Drop Disp*.
94 * i386-tbl.h: Re-generate.
95
897e603c
JB		 962017-11-13 Jan Beulich <jbeulich@suse.com>
97
98 * i386-opc.tbl (fxsave64, fxrstor64, xsave64, xrstor64,
99 xsaveopt64): Add No_qSuf.
100 * i386-tbl.h: Re-generate.
101
793a1948
TC		 1022017-11-09 Tamar Christina <tamar.christina@arm.com>
103
104 * aarch64-opc.c (aarch64_sys_regs): Add ARMv8.4-a registers;
105 dit, vstcr_el2, vsttbr_el2, cnthvs_tval_el2, cnthvs_cval_el2,
106 cnthvs_ctl_el2, cnthps_tval_el2, cnthps_cval_el2, cnthps_ctl_el2,
107 sder32_el2, vncr_el2.
108 (aarch64_sys_reg_supported_p): Likewise.
109 (aarch64_pstatefields): Add dit register.
110 (aarch64_pstatefield_supported_p): Likewise.
111 (aarch64_sys_regs_tlbi): Add vmalle1os, vae1os, aside1os, vaae1os,
112 vale1os, vaale1os, ipas2e1os, ipas2le1os, vae2os, vale2os, vmalls12e1os,
113 vae3os, vale3os, alle2os, alle1os, alle3os, rvae1, rvaae1, rvale1,
114 rvaale1, rvae1is, rvaae1is, rvale1is, rvaale1is, rvae1os, rvaae1os,
115 rvale1os, rvaale1os, ripas2e1is, ripas2le1is, ripas2e1, ripas2le1,
116 ripas2e1os, ripas2le1os, rvae2, rvale2, rvae2is, rvale2is, rvae2os,
117 rvale2os, rvae3, rvale3, rvae3is, rvale3is, rvae3os, rvale3os.
118
1a7ed57c
TC		 1192017-11-09 Tamar Christina <tamar.christina@arm.com>
120
121 * aarch64-tbl.h (QL_SHA512UPT, QL_V2SAME2D, QL_V3SAME2D): New.
122 (QL_V4SAME16B, QL_V4SAME4S, QL_XAR, QL_SM3TT, QL_V3FML2S): New.
123 (QL_V3FML4S, QL_V2FML2S, QL_V2FML4S, QL_RMIF, QL_SETF): New.
124 (QL_STLW, QL_STLX): New.
125
f42f1a1d
TC		 1262017-11-09 Tamar Christina <tamar.christina@arm.com>
127
128 * aarch64-asm.h (ins_addr_offset): New.
129 * aarch64-asm.c (aarch64_ins_reglane): Add cryptosm3.
130 (aarch64_ins_addr_offset): New.
131 * aarch64-asm-2.c: Regenerate.
132 * aarch64-dis.h (ext_addr_offset): New.
133 * aarch64-dis.c (aarch64_ext_reglane): Add cryptosm3.
134 (aarch64_ext_addr_offset): New.
135 * aarch64-dis-2.c: Regenerate.
136 * aarch64-opc.h (aarch64_field_kind): Add FLD_imm6_2,
137 FLD_imm4_2 and FLD_SM3_imm2.
138 * aarch64-opc.c (fields): Add FLD_imm6_2,
139 FLD_imm4_2 and FLD_SM3_imm2.
140 (operand_general_constraint_met_p): Add AARCH64_OPND_ADDR_OFFSET.
141 (aarch64_print_operand): Add AARCH64_OPND_Va, AARCH64_OPND_SM3_IMM2,
142 AARCH64_OPND_MASK, AARCH64_OPND_IMM_2 and AARCH64_OPND_ADDR_OFFSET.
143 * aarch64-opc-2.c (Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2): New.
144 * aarch64-tbl.h
145 (aarch64_opcode_table): Add Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2.
146
b6b9ca0c
TC		 1472017-11-09 Tamar Christina <tamar.christina@arm.com>
148
149 * aarch64-tbl.h
150 (aarch64_feature_v8_4, aarch64_feature_crypto_v8_2): New.
151 (aarch64_feature_sm4, aarch64_feature_sha3): New.
152 (aarch64_feature_fp_16_v8_2): New.
153 (ARMV8_4, SHA3, SM4, CRYPTO_V8_2, FP_F16_V8_2): New.
154 (V8_4_INSN, CRYPTO_V8_2_INSN): New.
155 (SHA3_INSN, SM4_INSN, FP16_V8_2_INSN): New.
156
c0e7cef7
NC		 1572017-11-08 Tamar Christina <tamar.christina@arm.com>
158
159 * aarch64-tbl.h (aarch64_feature_crypto): Add AES and SHA2.
160 (aarch64_feature_sha2, aarch64_feature_aes): New.
161 (SHA2, AES): New.
162 (AES_INSN, SHA2_INSN): New.
163 (pmull, pmull2, aese, aesd, aesmc, aesimc): Change to AES_INS.
164 (sha1h, sha1su1, sha256su0, sha1c, sha1p,
165 sha1m, sha1su0, sha256h, sha256h2, sha256su1):
166 Change to SHA2_INS.
167
dec41383
JW		 1682017-11-08 Jiong Wang <jiong.wang@arm.com>
169 Tamar Christina <tamar.christina@arm.com>
170
171 * arm-dis.c (coprocessor_opcodes): New entries for ARMv8.2-A new
172 FP16 instructions, including vfmal.f16 and vfmsl.f16.
173
52eab766
AB		 1742017-11-07 Andrew Burgess <andrew.burgess@embecosm.com>
175
176 * arc-nps400-tbl.h: Change incorrect use of NONE to MISC.
177
6003e27e
AM		 1782017-11-07 Alan Modra <amodra@gmail.com>
179
180 * opintl.h: Formatting, comment fixes.
181 (gettext, ngettext): Redefine when ENABLE_NLS.
182 (ngettext, dngettext, dcngettext): Define when !ENABLE_NLS.
183 (_): Define using gettext.
184 (textdomain, bindtextdomain): Use safer "do nothing".
185
fdddd290 1862017-11-03 Claudiu Zissulescu <claziss@synopsys.com>
187
188 * arc-dis.c (print_hex): New variable.
189 (parse_option): Check for hex option.
190 (print_insn_arc): Use hexadecimal representation for short
191 immediate values when requested.
192 (print_arc_disassembler_options): Add hex option to the list.
193
3334eba7 1942017-11-03 Claudiu Zissulescu <claziss@synopsys.com>
195
196 * arc-tbl.h (abss, abssh, adc, adcs, adds, aslacc, asls, aslsacc)
197 (asrs, asrsr, cbflyhf0r, cbflyhf1r, cmacchfr, cmacchnfr, cmachfr)
198 (cmachnfr, cmpychfr, cmpychnfr, cmpyhfmr, cmpyhfr, cmpyhnfr, divf)
199 (dmachbl, dmachbm, dmachf, dmachfr, dmacwhf, dmpyhbl, dmpyhbm)
200 (dmpyhf, dmpyhfr, dmpyhwf, dmpywhf, dsync, flagacc, getacc, macdf)
201 (macf, macfr, macwhfl, macwhflr, macwhfm, macwhfmr, macwhkl)
202 (macwhkul, macwhl, macwhul, mpydf, mpyf, mpyfr, mpywhfl, mpywhflr)
203 (mpywhfm, mpywhfmr, mpywhkl, mpywhkul, mpywhl, mpywhul, msubdf)
204 (msubf, msubfr, msubwhfl, msubwhflr, msubwhfm, msubwhfmr, mul64)
205 (negs, negsh, normacc, qmachf, qmpyh, qmpyhf, rndh, satf, sath)
206 (sbcs, setacc, sflag, sqrt, sqrtf, subs, swi_s, vabs2h, vabss2h)
207 (vadd4b, vadds2, vadds2h, vadds4h, vaddsubs, vaddsubs2h)
208 (vaddsubs4h, valgn2h, vasl2h, vasls2h, vasr2h, vasrs2h, vasrsr2h)
209 (vext2bhl, vext2bhlf, vext2bhm, vext2bhmf, vlsr2h, vmac2hf)
210 (vmac2hfr, vmac2hnfr, vmax2h, vmin2h, vmpy2h, vmpy2hf, vmpy2hfr)
211 (vmpy2hwf, vmsub2hf, vmsub2hfr, vmsub2hnfr, vneg2h, vnegs2h)
212 (vnorm2h, vpack2hbl, vpack2hblf, vpack2hbm, vpack2hbmf, vpack2hl)
213 (vpack2hm, vperm, vrep2hl, vrep2hm, vsext2bhl, vsext2bhm, vsub4b)
214 (vsubadds, vsubadds2h, vsubadds4h, vsubs2, vsubs2h, vsubs4h):
215 Changed opcodes.
216 (prealloc, prefetch*): Place them before ld instruction.
217 * arc-opc.c (skip_this_opcode): Add ARITH class.
218
e5d70d6b
AM		 2192017-10-25 Alan Modra <amodra@gmail.com>
220
221 PR 22348
222 * cr16-dis.c (cr16_cinvs, instruction, cr16_currInsn): Make static.
223 (cr16_words, cr16_allWords, processing_argument_number): Likewise.
224 (imm4flag, size_changed): Likewise.
225 * crx-dis.c (crx_cinvs, NUMCINVS, instruction, currInsn): Likewise.
226 (words, allWords, processing_argument_number): Likewise.
227 (cst4flag, size_changed): Likewise.
228 * crx-opc.c (crx_cst4_map): Rename from cst4_map.
229 (crx_cst4_maps): Rename from cst4_maps.
230 (crx_no_op_insn): Rename from no_op_insn.
231
63a25ea0
AW		 2322017-10-24 Andrew Waterman <andrew@sifive.com>
233
234 * riscv-opc.c (match_c_addi16sp) : New function.
235 (match_c_addi4spn): New function.
236 (match_c_lui): Don't allow 0-immediate encodings.
237 (riscv_opcodes) <addi>: Use the above functions.
238 <add>: Likewise.
239 <c.addi4spn>: Likewise.
240 <c.addi16sp>: Likewise.
241
fe4e2a3c
IT		 2422017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
243
244 * i386-init.h: Regenerate
245 * i386-tbl.h: Likewise
246
2739ef6d
IT		 2472017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
248
249 * i386-dis.c (enum): Add PREFIX_EVEX_0F3854, PREFIX_EVEX_0F388F.
250 (enum): Add EVEX_W_0F3854_P_2.
251 * i386-dis-evex.h (evex_table): Updated.
252 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BITALG,
253 CPU_ANY_AVX512_BITALG_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
254 (cpu_flags): Add CpuAVX512_BITALG.
255 * i386-opc.h (enum): Add CpuAVX512_BITALG.
256 (i386_cpu_flags): Add cpuavx512_bitalg..
257 * i386-opc.tbl: Add Intel AVX512_BITALG instructions.
258 * i386-init.h: Regenerate.
259 * i386-tbl.h: Likewise.
260
2612017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
262
263 * i386-dis.c (enum): Add PREFIX_EVEX_0F3850, PREFIX_EVEX_0F3851.
264 * i386-dis-evex.h (evex_table): Updated.
265 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VNNI,
266 CPU_ANY_AVX512_VNNI_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
267 (cpu_flags): Add CpuAVX512_VNNI.
268 * i386-opc.h (enum): Add CpuAVX512_VNNI.
269 (i386_cpu_flags): Add cpuavx512_vnni.
270 * i386-opc.tbl Add Intel AVX512_VNNI instructions.
271 * i386-init.h: Regenerate.
272 * i386-tbl.h: Likewise.
273
2742017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
275
276 * i386-dis.c (enum): Add PREFIX_EVEX_0F3A44.
277 (enum): Remove VEX_LEN_0F3A44_P_2.
278 (vex_len_table): Ditto.
279 (enum): Remove VEX_W_0F3A44_P_2.
280 (vew_w_table): Ditto.
281 (prefix_table): Adjust instructions (see prefixes above).
282 * i386-dis-evex.h (evex_table):
283 Add new instructions (see prefixes above).
284 * i386-gen.c (cpu_flag_init): Add VPCLMULQDQ.
285 (bitfield_cpu_flags): Ditto.
286 * i386-opc.h (enum): Ditto.
287 (i386_cpu_flags): Ditto.
288 (CpuUnused): Comment out to avoid zero-width field problem.
289 * i386-opc.tbl (vpclmulqdq): New instruction.
290 * i386-init.h: Regenerate.
291 * i386-tbl.h: Ditto.
292
2932017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
294
295 * i386-dis.c (enum): Add PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD,
296 PREFIX_EVEX_0F38DE, PREFIX_EVEX_0F38DF.
297 (enum): Remove VEX_LEN_0F38DC_P_2, VEX_LEN_0F38DD_P_2,
298 VEX_LEN_0F38DE_P_2, VEX_LEN_0F38DF_P_2.
299 (vex_len_table): Ditto.
300 (enum): Remove VEX_W_0F38DC_P_2, VEX_W_0F38DD_P_2,
301 VEX_W_0F38DE_P_2, VEX_W_0F38DF_P_2.
302 (vew_w_table): Ditto.
303 (prefix_table): Adjust instructions (see prefixes above).
304 * i386-dis-evex.h (evex_table):
305 Add new instructions (see prefixes above).
306 * i386-gen.c (cpu_flag_init): Add VAES.
307 (bitfield_cpu_flags): Ditto.
308 * i386-opc.h (enum): Ditto.
309 (i386_cpu_flags): Ditto.
310 * i386-opc.tbl (vaes{enc,dec}{last,}): New instructions.
311 * i386-init.h: Regenerate.
312 * i386-tbl.h: Ditto.
313
3142017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
315
316 * i386-dis.c (enum): Add PREFIX_0F38CF, PREFIX_0F3ACE, PREFIX_0F3ACF,
317 PREFIX_VEX_0F38CF, PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF,
318 PREFIX_EVEX_0F38CF, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF.
319 (enum): Add VEX_W_0F38CF_P_2, VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2,
320 EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2.
321 (prefix_table): Updated (see prefixes above).
322 (three_byte_table): Likewise.
323 (vex_w_table): Likewise.
324 * i386-dis-evex.h: Likewise.
325 * i386-gen.c (cpu_flag_init): Add CPU_GFNI_FLAGS, CpuGFNI.
326 (cpu_flags): Add CpuGFNI.
327 * i386-opc.h (enum): Add CpuGFNI.
328 (i386_cpu_flags): Add cpugfni.
329 * i386-opc.tbl: Add Intel GFNI instructions.
330 * i386-init.h: Regenerate.
331 * i386-tbl.h: Likewise.
332
3332017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
334
335 * i386-dis.c (enum): Add b_scalar_mode, w_scalar_mode.
336 Define EXbScalar and EXwScalar for OP_EX.
337 (enum): Add PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863,
338 PREFIX_EVEX_0F3870, PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3872,
339 PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
340 PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73.
341 (enum): Add EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2,
342 EVEX_W_0F3870_P_2, EVEX_W_0F3871_P_2, EVEX_W_0F3872_P_2,
343 EVEX_W_0F3873_P_2, EVEX_W_0F3A70_P_2, EVEX_W_0F3A71_P_2,
344 EVEX_W_0F3A72_P_2, EVEX_W_0F3A73_P_2.
345 (intel_operand_size): Handle b_scalar_mode and w_scalar_mode.
346 (OP_E_memory): Likewise.
347 * i386-dis-evex.h: Updated.
348 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VBMI2,
349 CPU_ANY_AVX512_VBMI2_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
350 (cpu_flags): Add CpuAVX512_VBMI2.
351 * i386-opc.h (enum): Add CpuAVX512_VBMI2.
352 (i386_cpu_flags): Add cpuavx512_vbmi2.
353 * i386-opc.tbl: Add Intel AVX512_VBMI2 instructions.
354 * i386-init.h: Regenerate.
355 * i386-tbl.h: Likewise.
356
2a6969e1
EB		 3572017-10-18 Eric Botcazou <ebotcazou@adacore.com>
358
359 * visium-dis.c (disassem_class1) <case 0>: Print the operands.
360
3b4b0a62
JB		 3612017-10-12 James Bowman <james.bowman@ftdichip.com>
362
363 * ft32-dis.c (print_insn_ft32): Replace FT32_FLD_K8 with K15.
364 * ft32-opc.c (ft32_opc_info): Replace FT32_FLD_K8 with
365 K15. Add jmpix pattern.
366
8e464506
AK		 3672017-10-09 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
368
369 * s390-opc.txt (prno, tpei, irbm): New instructions added.
370
ee6767da
AK		 3712017-10-09 Heiko Carstens <heiko.carstens@de.ibm.com>
372
373 * s390-opc.c (INSTR_SI_RD): New macro.
374 (INSTR_S_RD): Adjust example instruction.
375 * s390-opc.txt (lpsw, ssm, ts): Change S_RD instruction format to
376 SI_RD.
377
d2e6c9a3
AF		 3782017-10-01 Alexander Fedotov <alfedotov@gmail.com>
379
380 * ppc-opc.c (vle_opcodes): Add e_lmvsprw, e_lmvgprw,
381 e_lmvsrrw, e_lmvcsrrw and e_lmvcsrrw as official mnemonics for
382 VLE multimple load/store instructions. Old e_ldm* variants are
383 kept as aliases.
384 Add missing e_lmvmcsrrw and e_stmvmcsrrw.
385
8e43602e
NC		 3862017-09-27 Nick Clifton <nickc@redhat.com>
387
388 PR 22179
389 * riscv-opc.c (riscv_opcodes): Add fmv.x.w and fmv.w.x as the new
390 names for the fmv.x.s and fmv.s.x instructions respectively.
391
58a0b827
NC		 3922017-09-26 do <do@nerilex.org>
393
394 PR 22123
395 * m68k-opc.c (m68k_opcodes): Allow macw and macl instructions to
396 be used on CPUs that have emacs support.
397
57a024f4
SDJ		 3982017-09-21 Sergio Durigan Junior <sergiodj@redhat.com>
399
400 * aarch64-opc.c (expand_fp_imm): Initialize 'imm'.
401
4ec521f2
KLC		 4022017-09-09 Kamil Rytarowski <n54@gmx.com>
403
404 * nds32-asm.c: Rename __BIT() to N32_BIT().
405 * nds32-asm.h: Likewise.
406 * nds32-dis.c: Likewise.
407
4e9ac44a
L		 4082017-09-09 H.J. Lu <hongjiu.lu@intel.com>
409
410 * i386-dis.c (last_active_prefix): Removed.
411 (ckprefix): Don't set last_active_prefix.
412 (NOTRACK_Fixup): Don't check last_active_prefix.
413
b55f3386
NC		 4142017-08-31 Nick Clifton <nickc@redhat.com>
415
416 * po/fr.po: Updated French translation.
417
59e8523b
JB		 4182017-08-31 James Bowman <james.bowman@ftdichip.com>
419
420 * ft32-dis.c (print_insn_ft32): Correct display of non-address
421 fields.
422
74081948
AF		 4232017-08-23 Alexander Fedotov <alexander.fedotov@nxp.com>
424 Edmar Wienskoski <edmar.wienskoski@nxp.com>
425
426 * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_SPE2 and
427 PPC_OPCODE_EFS2 flag to "e200z4" entry.
428 New entries efs2 and spe2.
429 Add PPC_OPCODE_SPE2 and PPC_OPCODE_EFS2 flag to "vle" entry.
430 (SPE2_OPCD_SEGS): New macro.
431 (spe2_opcd_indices): New.
432 (disassemble_init_powerpc): Handle SPE2 opcodes.
433 (lookup_spe2): New function.
434 (print_insn_powerpc): call lookup_spe2.
435 * ppc-opc.c (insert_evuimm1_ex0): New function.
436 (extract_evuimm1_ex0): Likewise.
437 (insert_evuimm_lt8): Likewise.
438 (extract_evuimm_lt8): Likewise.
439 (insert_off_spe2): Likewise.
440 (extract_off_spe2): Likewise.
441 (insert_Ddd): Likewise.
442 (extract_Ddd): Likewise.
443 (DD): New operand.
444 (EVUIMM_LT8): Likewise.
445 (EVUIMM_LT16): Adjust.
446 (MMMM): New operand.
447 (EVUIMM_1): Likewise.
448 (EVUIMM_1_EX0): Likewise.
449 (EVUIMM_2): Adjust.
450 (NNN): New operand.
451 (VX_OFF_SPE2): Likewise.
452 (BBB): Likewise.
453 (DDD): Likewise.
454 (VX_MASK_DDD): New mask.
455 (HH): New operand.
456 (VX_RA_CONST): New macro.
457 (VX_RA_CONST_MASK): Likewise.
458 (VX_RB_CONST): Likewise.
459 (VX_RB_CONST_MASK): Likewise.
460 (VX_OFF_SPE2_MASK): Likewise.
461 (VX_SPE_CRFD): Likewise.
462 (VX_SPE_CRFD_MASK VX): Likewise.
463 (VX_SPE2_CLR): Likewise.
464 (VX_SPE2_CLR_MASK): Likewise.
465 (VX_SPE2_SPLATB): Likewise.
466 (VX_SPE2_SPLATB_MASK): Likewise.
467 (VX_SPE2_OCTET): Likewise.
468 (VX_SPE2_OCTET_MASK): Likewise.
469 (VX_SPE2_DDHH): Likewise.
470 (VX_SPE2_DDHH_MASK): Likewise.
471 (VX_SPE2_HH): Likewise.
472 (VX_SPE2_HH_MASK): Likewise.
473 (VX_SPE2_EVMAR): Likewise.
474 (VX_SPE2_EVMAR_MASK): Likewise.
475 (PPCSPE2): Likewise.
476 (PPCEFS2): Likewise.
477 (vle_opcodes): Add EFS2 and some missing SPE opcodes.
478 (powerpc_macros): Map old SPE instructions have new names
479 with the same opcodes. Add SPE2 instructions which just are
480 mapped to SPE2.
481 (spe2_opcodes): Add SPE2 opcodes.
482
b80c7270
AM		 4832017-08-23 Alan Modra <amodra@gmail.com>
484
485 * ppc-opc.c: Formatting and comment fixes. Move insert and
486 extract functions earlier, deleting forward declarations.
487 (insert_nbi, insert_raq, insert_rbx): Expand use of RT_MASK and
488 RA_MASK.
489
67d888f5
PD		 4902017-08-22 Palmer Dabbelt <palmer@dabbelt.com>
491
492 * riscv-opc.c (riscv_opcodes): Mark "c.nop" as an alias.
493
e3c2f928
AF		 4942017-08-21 Alexander Fedotov <alexander.fedotov@nxp.com>
495 Edmar Wienskoski <edmar.wienskoski@nxp.com>
496
497 * ppc-opc.c (insert_evuimm2_ex0): New function.
498 (extract_evuimm2_ex0): Likewise.
499 (insert_evuimm4_ex0): Likewise.
500 (extract_evuimm4_ex0): Likewise.
501 (insert_evuimm8_ex0): Likewise.
502 (extract_evuimm8_ex0): Likewise.
503 (insert_evuimm_lt16): Likewise.
504 (extract_evuimm_lt16): Likewise.
505 (insert_rD_rS_even): Likewise.
506 (extract_rD_rS_even): Likewise.
507 (insert_off_lsp): Likewise.
508 (extract_off_lsp): Likewise.
509 (RD_EVEN): New operand.
510 (RS_EVEN): Likewise.
511 (RSQ): Adjust.
512 (EVUIMM_LT16): New operand.
513 (HTM_SI): Adjust.
514 (EVUIMM_2_EX0): New operand.
515 (EVUIMM_4): Adjust.
516 (EVUIMM_4_EX0): New operand.
517 (EVUIMM_8): Adjust.
518 (EVUIMM_8_EX0): New operand.
519 (WS): Adjust.
520 (VX_OFF): New operand.
521 (VX_LSP): New macro.
522 (VX_LSP_MASK): Likewise.
523 (VX_LSP_OFF_MASK): Likewise.
524 (PPC_OPCODE_LSP): Likewise.
525 (vle_opcodes): Add LSP opcodes.
526 * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_LSP flag to "vle" entry.
527
cc4a945a
JW		 5282017-08-09 Jiong Wang <jiong.wang@arm.com>
529
530 * arm-dis.c (thumb32_opcodes): Use format 'R' instead of 'S' for
531 register operands in CRC instructions.
532 (print_insn_thumb32): Remove "<bitfield>S" support. Updated the
533 comments.
534
b28b8b5e
L		 5352017-08-07 H.J. Lu <hongjiu.lu@intel.com>
536
537 * disassemble.c (disassembler): Mark big and mach with
538 ATTRIBUTE_UNUSED.
539
e347efc3
MR		 5402017-08-07 Maciej W. Rozycki <macro@imgtec.com>
541
542 * disassemble.c (disassembler): Remove arch/mach/endian
543 assertions.
544
7cbc739c
NC		 5452017-07-25 Nick Clifton <nickc@redhat.com>
546
547 PR 21739
548 * arc-opc.c (insert_rhv2): Use lower case first letter in error
549 message.
550 (insert_r0): Likewise.
551 (insert_r1): Likewise.
552 (insert_r2): Likewise.
553 (insert_r3): Likewise.
554 (insert_sp): Likewise.
555 (insert_gp): Likewise.
556 (insert_pcl): Likewise.
557 (insert_blink): Likewise.
558 (insert_ilink1): Likewise.
559 (insert_ilink2): Likewise.
560 (insert_ras): Likewise.
561 (insert_rbs): Likewise.
562 (insert_rcs): Likewise.
563 (insert_simm3s): Likewise.
564 (insert_rrange): Likewise.
565 (insert_r13el): Likewise.
566 (insert_fpel): Likewise.
567 (insert_blinkel): Likewise.
568 (insert_pclel): Likewise.
569 (insert_nps_bitop_size_2b): Likewise.
570 (insert_nps_imm_offset): Likewise.
571 (insert_nps_imm_entry): Likewise.
572 (insert_nps_size_16bit): Likewise.
573 (insert_nps_##NAME##_pos): Likewise.
574 (insert_nps_##NAME): Likewise.
575 (insert_nps_bitop_ins_ext): Likewise.
576 (insert_nps_##NAME): Likewise.
577 (insert_nps_min_hofs): Likewise.
578 (insert_nps_##NAME): Likewise.
579 (insert_nps_rbdouble_64): Likewise.
580 (insert_nps_misc_imm_offset): Likewise.
581 * riscv-dis.c (print_riscv_disassembler_options): Fix typo in
582 option description.
583
7684e580
JW		 5842017-07-24 Laurent Desnogues <laurent.desnogues@arm.com>
585 Jiong Wang <jiong.wang@arm.com>
586
587 * aarch64-gen.c (print_decision_tree_1): Reverse the index of PATTERN to
588 correct the print.
589 * aarch64-dis-2.c: Regenerated.
590
47826cdb
AK		 5912017-07-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
592
593 * s390-mkopc.c (main): Enable z14 as CPU string in the opcode
594 table.
595
2d2dbad0
NC		 5962017-07-20 Nick Clifton <nickc@redhat.com>
597
598 * po/de.po: Updated German translation.
599
70b448ba 6002017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
601
602 * arc-regs.h (sec_stat): New aux register.
603 (aux_kernel_sp): Likewise.
604 (aux_sec_u_sp): Likewise.
605 (aux_sec_k_sp): Likewise.
606 (sec_vecbase_build): Likewise.
607 (nsc_table_top): Likewise.
608 (nsc_table_base): Likewise.
609 (ersec_stat): Likewise.
610 (aux_sec_except): Likewise.
611
7179e0e6
CZ		 6122017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
613
614 * arc-opc.c (extract_uimm12_20): New function.
615 (UIMM12_20): New operand.
616 (SIMM3_5_S): Adjust.
617 * arc-tbl.h (sjli): Add new instruction.
618
684d5a10
JEM		 6192017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
620 John Eric Martin <John.Martin@emmicro-us.com>
621
622 * arc-opc.c (UIMM10_6_S_JLIOFF): Define.
623 (UIMM3_23): Adjust accordingly.
624 * arc-regs.h: Add/correct jli_base register.
625 * arc-tbl.h (jli_s): Likewise.
626
de194d85
YC		 6272017-07-18 Nick Clifton <nickc@redhat.com>
628
629 PR 21775
630 * aarch64-opc.c: Fix spelling typos.
631 * i386-dis.c: Likewise.
632
0f6329bd
RB		 6332017-07-14 Ravi Bangoria <ravi.bangoria@linux.vnet.ibm.com>
634
635 * dis-buf.c (buffer_read_memory): Change type of end_addr_offset,
636 max_addr_offset and octets variables to size_t.
637
429d795d
AM		 6382017-07-12 Alan Modra <amodra@gmail.com>
639
640 * po/da.po: Update from translationproject.org/latest/opcodes/.
641 * po/de.po: Likewise.
642 * po/es.po: Likewise.
643 * po/fi.po: Likewise.
644 * po/fr.po: Likewise.
645 * po/id.po: Likewise.
646 * po/it.po: Likewise.
647 * po/nl.po: Likewise.
648 * po/pt_BR.po: Likewise.
649 * po/ro.po: Likewise.
650 * po/sv.po: Likewise.
651 * po/tr.po: Likewise.
652 * po/uk.po: Likewise.
653 * po/vi.po: Likewise.
654 * po/zh_CN.po: Likewise.
655
4162bb66
AM		 6562017-07-11 Yao Qi <yao.qi@linaro.org>
657 Alan Modra <amodra@gmail.com>
658
659 * cgen.sh: Mark generated files read-only.
660 * epiphany-asm.c: Regenerate.
661 * epiphany-desc.c: Regenerate.
662 * epiphany-desc.h: Regenerate.
663 * epiphany-dis.c: Regenerate.
664 * epiphany-ibld.c: Regenerate.
665 * epiphany-opc.c: Regenerate.
666 * epiphany-opc.h: Regenerate.
667 * fr30-asm.c: Regenerate.
668 * fr30-desc.c: Regenerate.
669 * fr30-desc.h: Regenerate.
670 * fr30-dis.c: Regenerate.
671 * fr30-ibld.c: Regenerate.
672 * fr30-opc.c: Regenerate.
673 * fr30-opc.h: Regenerate.
674 * frv-asm.c: Regenerate.
675 * frv-desc.c: Regenerate.
676 * frv-desc.h: Regenerate.
677 * frv-dis.c: Regenerate.
678 * frv-ibld.c: Regenerate.
679 * frv-opc.c: Regenerate.
680 * frv-opc.h: Regenerate.
681 * ip2k-asm.c: Regenerate.
682 * ip2k-desc.c: Regenerate.
683 * ip2k-desc.h: Regenerate.
684 * ip2k-dis.c: Regenerate.
685 * ip2k-ibld.c: Regenerate.
686 * ip2k-opc.c: Regenerate.
687 * ip2k-opc.h: Regenerate.
688 * iq2000-asm.c: Regenerate.
689 * iq2000-desc.c: Regenerate.
690 * iq2000-desc.h: Regenerate.
691 * iq2000-dis.c: Regenerate.
692 * iq2000-ibld.c: Regenerate.
693 * iq2000-opc.c: Regenerate.
694 * iq2000-opc.h: Regenerate.
695 * lm32-asm.c: Regenerate.
696 * lm32-desc.c: Regenerate.
697 * lm32-desc.h: Regenerate.
698 * lm32-dis.c: Regenerate.
699 * lm32-ibld.c: Regenerate.
700 * lm32-opc.c: Regenerate.
701 * lm32-opc.h: Regenerate.
702 * lm32-opinst.c: Regenerate.
703 * m32c-asm.c: Regenerate.
704 * m32c-desc.c: Regenerate.
705 * m32c-desc.h: Regenerate.
706 * m32c-dis.c: Regenerate.
707 * m32c-ibld.c: Regenerate.
708 * m32c-opc.c: Regenerate.
709 * m32c-opc.h: Regenerate.
710 * m32r-asm.c: Regenerate.
711 * m32r-desc.c: Regenerate.
712 * m32r-desc.h: Regenerate.
713 * m32r-dis.c: Regenerate.
714 * m32r-ibld.c: Regenerate.
715 * m32r-opc.c: Regenerate.
716 * m32r-opc.h: Regenerate.
717 * m32r-opinst.c: Regenerate.
718 * mep-asm.c: Regenerate.
719 * mep-desc.c: Regenerate.
720 * mep-desc.h: Regenerate.
721 * mep-dis.c: Regenerate.
722 * mep-ibld.c: Regenerate.
723 * mep-opc.c: Regenerate.
724 * mep-opc.h: Regenerate.
725 * mt-asm.c: Regenerate.
726 * mt-desc.c: Regenerate.
727 * mt-desc.h: Regenerate.
728 * mt-dis.c: Regenerate.
729 * mt-ibld.c: Regenerate.
730 * mt-opc.c: Regenerate.
731 * mt-opc.h: Regenerate.
732 * or1k-asm.c: Regenerate.
733 * or1k-desc.c: Regenerate.
734 * or1k-desc.h: Regenerate.
735 * or1k-dis.c: Regenerate.
736 * or1k-ibld.c: Regenerate.
737 * or1k-opc.c: Regenerate.
738 * or1k-opc.h: Regenerate.
739 * or1k-opinst.c: Regenerate.
740 * xc16x-asm.c: Regenerate.
741 * xc16x-desc.c: Regenerate.
742 * xc16x-desc.h: Regenerate.
743 * xc16x-dis.c: Regenerate.
744 * xc16x-ibld.c: Regenerate.
745 * xc16x-opc.c: Regenerate.
746 * xc16x-opc.h: Regenerate.
747 * xstormy16-asm.c: Regenerate.
748 * xstormy16-desc.c: Regenerate.
749 * xstormy16-desc.h: Regenerate.
750 * xstormy16-dis.c: Regenerate.
751 * xstormy16-ibld.c: Regenerate.
752 * xstormy16-opc.c: Regenerate.
753 * xstormy16-opc.h: Regenerate.
754
7639175c
AM		 7552017-07-07 Alan Modra <amodra@gmail.com>
756
757 * cgen-dis.in: Include disassemble.h, not dis-asm.h.
758 * m32c-dis.c: Regenerate.
759 * mep-dis.c: Regenerate.
760
e4bdd679
BP		 7612017-07-05 Borislav Petkov <bp@suse.de>
762
763 * i386-dis.c: Enable ModRM.reg /6 aliases.
764
60c96dbf
RR		 7652017-07-04 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
766
767 * opcodes/arm-dis.c: Support MVFR2 in disassembly
768 with vmrs and vmsr.
769
0d702cfe
TG		 7702017-07-04 Tristan Gingold <gingold@adacore.com>
771
772 * configure: Regenerate.
773
15e6ed8c
TG		 7742017-07-03 Tristan Gingold <gingold@adacore.com>
775
776 * po/opcodes.pot: Regenerate.
777
b1d3c886
MR		 7782017-06-30 Maciej W. Rozycki <macro@imgtec.com>
779
780 * mips-opc.c (mips_builtin_opcodes): Move "lsa" and "dlsa"
781 entries to the MSA ASE instruction block.
782
909b4e3d
MR		 7832017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
784 Maciej W. Rozycki <macro@imgtec.com>
785
786 * micromips-opc.c (XPA, XPAVZ): New macros.
787 (micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and
788 "mthgc0".
789
f5b2fd52
MR		 7902017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
791 Maciej W. Rozycki <macro@imgtec.com>
792
793 * micromips-opc.c (I36): New macro.
794 (micromips_opcodes): Add "eretnc".
795
9785fc2a
MR		 7962017-06-30 Maciej W. Rozycki <macro@imgtec.com>
797 Andrew Bennett <andrew.bennett@imgtec.com>
798
799 * mips-dis.c (mips_calculate_combination_ases): Handle the
800 ASE_XPA_VIRT flag.
801 (parse_mips_ase_option): New function.
802 (parse_mips_dis_option): Factor out ASE option handling to the
803 new function. Call `mips_calculate_combination_ases'.
804 * mips-opc.c (XPAVZ): New macro.
805 (mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0",
806 "mfhgc0", "mthc0" and "mthgc0".
807
60804c53
MR		 8082017-06-29 Maciej W. Rozycki <macro@imgtec.com>
809
810 * mips-dis.c (mips_calculate_combination_ases): New function.
811 (mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT
812 calculation to the new function.
813 (set_default_mips_dis_options): Call the new function.
814
2e74f9dd
AK		 8152017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
816
817 * arc-dis.c (parse_disassembler_options): Use
818 FOR_EACH_DISASSEMBLER_OPTION.
819
e1e94c49
AK		 8202017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
821
822 * arc-dis.c (parse_option): Use disassembler_options_cmp to compare
823 disassembler option strings.
824 (parse_cpu_option): Likewise.
825
65a55fbb
TC		 8262017-06-28 Tamar Christina <tamar.christina@arm.com>
827
828 * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod.
829 * aarch64-dis.c (aarch64_ext_reglane): Likewise.
830 * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New.
831 (aarch64_feature_dotprod, DOT_INSN): New.
832 (udot, sdot): New.
833 * aarch64-dis-2.c: Regenerated.
834
c604a79a
JW		 8352017-06-28 Jiong Wang <jiong.wang@arm.com>
836
837 * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
838
38bf472a
MR		 8392017-06-28 Maciej W. Rozycki <macro@imgtec.com>
840 Matthew Fortune <matthew.fortune@imgtec.com>
4151f684 841 Andrew Bennett <andrew.bennett@imgtec.com>
38bf472a
MR		 842
843 * mips-formats.h (INT_BIAS): New macro.
844 (INT_ADJ): Redefine in INT_BIAS terms.
845 * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
846 (mips_print_save_restore): New function.
847 (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
848 (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
849 call.
850 (print_insn_args): Handle OP_SAVE_RESTORE_LIST.
851 (print_mips16_insn_arg): Call `mips_print_save_restore' for
852 OP_SAVE_RESTORE_LIST handling, factored out from here.
853 * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
854 (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
855 (mips_builtin_opcodes): Add "restore" and "save" entries.
856 * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
857 (IAMR2): New macro.
858 (mips16_opcodes): Add "copyw" and "ucopyw" entries.
859
9bdfdbf9
AW		 8602017-06-23 Andrew Waterman <andrew@sifive.com>
861
862 * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
863 alias; do not mark SLTI instruction as an alias.
864
2234eee6
L		 8652017-06-21 H.J. Lu <hongjiu.lu@intel.com>
866
867 * i386-dis.c (RM_0FAE_REG_5): Removed.
868 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
869 (PREFIX_MOD_3_0F01_REG_5_RM_0): New.
870 (PREFIX_MOD_3_0FAE_REG_5): Likewise.
871 (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1. Add
872 PREFIX_MOD_3_0F01_REG_5_RM_0.
873 (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5. Add
874 PREFIX_MOD_3_0FAE_REG_5.
875 (mod_table): Update MOD_0FAE_REG_5.
876 (rm_table): Update RM_0F01_REG_5. Remove RM_0FAE_REG_5.
877 * i386-opc.tbl: Update incsspd, incsspq and setssbsy.
878 * i386-tbl.h: Regenerated.
879
c2f76402
L		 8802017-06-21 H.J. Lu <hongjiu.lu@intel.com>
881
882 * i386-dis.c (prefix_table): Replace savessp with saveprevssp.
883 * i386-opc.tbl: Likewise.
884 * i386-tbl.h: Regenerated.
885
9fef80d6
L		 8862017-06-21 H.J. Lu <hongjiu.lu@intel.com>
887
888 * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"
889 and "jmp{&|}".
890 (NOTRACK_Fixup): Support memory indirect branch with NOTRACK
891 prefix.
892
0f6d864d
NC		 8932017-06-19 Nick Clifton <nickc@redhat.com>
894
895 PR binutils/21614
896 * score-dis.c (score_opcodes): Add sentinel.
897
e197589b
AM		 8982017-06-16 Alan Modra <amodra@gmail.com>
899
900 * rx-decode.c: Regenerate.
901
0d96e4df
L		 9022017-06-15 H.J. Lu <hongjiu.lu@intel.com>
903
904 PR binutils/21594
905 * i386-dis.c (OP_E_register): Check valid bnd register.
906 (OP_G): Likewise.
907
cd3ea7c6
NC		 9082017-06-15 Nick Clifton <nickc@redhat.com>
909
910 PR binutils/21595
911 * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
912 range value.
913
63323b5b
NC		 9142017-06-15 Nick Clifton <nickc@redhat.com>
915
916 PR binutils/21588
917 * rl78-decode.opc (OP_BUF_LEN): Define.
918 (GETBYTE): Check for the index exceeding OP_BUF_LEN.
919 (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
920 array.
921 * rl78-decode.c: Regenerate.
922
08c7881b
NC		 9232017-06-15 Nick Clifton <nickc@redhat.com>
924
925 PR binutils/21586
926 * bfin-dis.c (gregs): Clip index to prevent overflow.
927 (regs): Likewise.
928 (regs_lo): Likewise.
929 (regs_hi): Likewise.
930
e64519d1
NC		 9312017-06-14 Nick Clifton <nickc@redhat.com>
932
933 PR binutils/21576
934 * score7-dis.c (score_opcodes): Add sentinel.
935
6394c606
YQ		 9362017-06-14 Yao Qi <yao.qi@linaro.org>
937
938 * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
939 * arm-dis.c: Likewise.
940 * ia64-dis.c: Likewise.
941 * mips-dis.c: Likewise.
942 * spu-dis.c: Likewise.
943 * disassemble.h (print_insn_aarch64): New declaration, moved from
944 include/dis-asm.h.
945 (print_insn_big_arm, print_insn_big_mips): Likewise.
946 (print_insn_i386, print_insn_ia64): Likewise.
947 (print_insn_little_arm, print_insn_little_mips): Likewise.
948
db5fa770
NC		 9492017-06-14 Nick Clifton <nickc@redhat.com>
950
951 PR binutils/21587
952 * rx-decode.opc: Include libiberty.h
953 (GET_SCALE): New macro - validates access to SCALE array.
954 (GET_PSCALE): New macro - validates access to PSCALE array.
955 (DIs, SIs, S2Is, rx_disp): Use new macros.
956 * rx-decode.c: Regenerate.
957
05c966f3
AV		 9582017-07-14 Andre Vieira <andre.simoesdiasvieira@arm.com>
959
960 * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
961
10045478
AK		 9622017-05-30 Anton Kolesov <anton.kolesov@synopsys.com>
963
964 * arc-dis.c (enforced_isa_mask): Declare.
965 (cpu_types): Likewise.
966 (parse_cpu_option): New function.
967 (parse_disassembler_options): Use it.
968 (print_insn_arc): Use enforced_isa_mask.
969 (print_arc_disassembler_options): Document new options.
970
88c1242d
YQ		 9712017-05-24 Yao Qi <yao.qi@linaro.org>
972
973 * alpha-dis.c: Include disassemble.h, don't include
974 dis-asm.h.
975 * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
976 * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
977 * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
978 * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
979 * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
980 * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
981 * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
982 * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
983 * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
984 * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
985 * moxie-dis.c, msp430-dis.c, mt-dis.c:
986 * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
987 * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
988 * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
989 * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
990 * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
991 * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
992 * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
993 * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
994 * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
995 * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
996 * z80-dis.c, z8k-dis.c: Likewise.
997 * disassemble.h: New file.
998
ab20fa4a
YQ		 9992017-05-24 Yao Qi <yao.qi@linaro.org>
1000
1001 * rl78-dis.c (rl78_get_disassembler): If parameter abfd
1002 is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
1003
003ca0fd
YQ		 10042017-05-24 Yao Qi <yao.qi@linaro.org>
1005
1006 * disassemble.c (disassembler): Add arguments a, big and mach.
1007 Use them.
1008
04ef582a
L		 10092017-05-22 H.J. Lu <hongjiu.lu@intel.com>
1010
1011 * i386-dis.c (NOTRACK_Fixup): New.
1012 (NOTRACK): Likewise.
1013 (NOTRACK_PREFIX): Likewise.
1014 (last_active_prefix): Likewise.
1015 (reg_table): Use NOTRACK on indirect call and jmp.
1016 (ckprefix): Set last_active_prefix.
1017 (prefix_name): Return "notrack" for NOTRACK_PREFIX.
1018 * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
1019 * i386-opc.h (NoTrackPrefixOk): New.
1020 (i386_opcode_modifier): Add notrackprefixok.
1021 * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
1022 Add notrack.
1023 * i386-tbl.h: Regenerated.
1024
64517994
JM		 10252017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
1026
1027 * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
1028 (X_IMM2): Define.
1029 (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
1030 bfd_mach_sparc_v9m8.
1031 (print_insn_sparc): Handle new operand types.
1032 * sparc-opc.c (MASK_M8): Define.
1033 (v6): Add MASK_M8.
1034 (v6notlet): Likewise.
1035 (v7): Likewise.
1036 (v8): Likewise.
1037 (v9): Likewise.
1038 (v9a): Likewise.
1039 (v9b): Likewise.
1040 (v9c): Likewise.
1041 (v9d): Likewise.
1042 (v9e): Likewise.
1043 (v9v): Likewise.
1044 (v9m): Likewise.
1045 (v9andleon): Likewise.
1046 (m8): Define.
1047 (HWS_VM8): Define.
1048 (HWS2_VM8): Likewise.
1049 (sparc_opcode_archs): Add entry for "m8".
1050 (sparc_opcodes): Add OSA2017 and M8 instructions
1051 dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
1052 fpx{ll,ra,rl}64x,
1053 ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
1054 ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
1055 revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
1056 stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
1057 (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
1058 ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
1059 ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
1060 ASI_CORE_SELECT_COMMIT_NHT.
1061
535b785f
AM		 10622017-05-18 Alan Modra <amodra@gmail.com>
1063
1064 * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
1065 * aarch64-dis.c: Likewise.
1066 * aarch64-gen.c: Likewise.
1067 * aarch64-opc.c: Likewise.
1068
25499ac7
MR		 10692017-05-15 Maciej W. Rozycki <macro@imgtec.com>
1070 Matthew Fortune <matthew.fortune@imgtec.com>
1071
1072 * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
1073 ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
1074 (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
1075 (print_insn_arg) <OP_REG28>: Add handler.
1076 (validate_insn_args) <OP_REG28>: Handle.
1077 (print_mips16_insn_arg): Handle MIPS16 instructions that require
1078 32-bit encoding and 9-bit immediates.
1079 (print_insn_mips16): Handle MIPS16 instructions that require
1080 32-bit encoding and MFC0/MTC0 operand decoding.
1081 * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
1082 <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
1083 (RD_C0, WR_C0, E2, E2MT): New macros.
1084 (mips16_opcodes): Add entries for MIPS16e2 instructions:
1085 GP-relative "addiu" and its "addu" spelling, "andi", "cache",
1086 "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
1087 "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
1088 "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
1089 "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
1090 instructions, "swl", "swr", "sync" and its "sync_acquire",
1091 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
1092 "xori", "dmt", "dvpe", "emt" and "evpe". Add split
1093 regular/extended entries for original MIPS16 ISA revision
1094 instructions whose extended forms are subdecoded in the MIPS16e2
1095 ISA revision: "li", "sll" and "srl".
1096
fdfb4752
MR		 10972017-05-15 Maciej W. Rozycki <macro@imgtec.com>
1098
1099 * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
1100 reference in CP0 move operand decoding.
1101
a4f89915
MR		 11022017-05-12 Maciej W. Rozycki <macro@imgtec.com>
1103
1104 * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
1105 type to hexadecimal.
1106 (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
1107
99e2d67a
MR		 11082017-05-11 Maciej W. Rozycki <macro@imgtec.com>
1109
1110 * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
1111 "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
1112 "sync_rmb" and "sync_wmb" as aliases.
1113 * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
1114 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
1115
53a346d8
CZ		 11162017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
1117
1118 * arc-dis.c (parse_option): Update quarkse_em option..
1119 * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
1120 QUARKSE1.
1121 (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
1122
f91d48de
KC		 11232017-05-03 Kito Cheng <kito.cheng@gmail.com>
1124
1125 * riscv-dis.c (print_insn_args): Handle 'Co' operands.
1126
43e379d7
MC		 11272017-05-01 Michael Clark <michaeljclark@mac.com>
1128
1129 * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
1130 register.
1131
a4ddc54e
MR		 11322017-05-02 Maciej W. Rozycki <macro@imgtec.com>
1133
1134 * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
1135 and branches and not synthetic data instructions.
1136
fe50e98c
BE		 11372017-05-02 Bernd Edlinger <bernd.edlinger@hotmail.de>
1138
1139 * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
1140
126124cc
CZ		 11412017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
1142
1143 * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
1144 * arc-opc.c (insert_r13el): New function.
1145 (R13_EL): Define.
1146 * arc-tbl.h: Add new enter/leave variants.
1147
be6a24d8
CZ		 11482017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
1149
1150 * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
1151
0348fd79
MR		 11522017-04-25 Maciej W. Rozycki <macro@imgtec.com>
1153
1154 * mips-dis.c (print_mips_disassembler_options): Add
1155 `no-aliases'.
1156
6e3d1f07
MR		 11572017-04-25 Maciej W. Rozycki <macro@imgtec.com>
1158
1159 * mips16-opc.c (AL): New macro.
1160 (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
1161 of "ld" and "lw" as aliases.
1162
957f6b39
TC		 11632017-04-24 Tamar Christina <tamar.christina@arm.com>
1164
1165 * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
1166 arguments.
1167
a8cc8a54
AM		 11682017-04-22 Alexander Fedotov <alfedotov@gmail.com>
1169 Alan Modra <amodra@gmail.com>
1170
1171 * ppc-opc.c (ELEV): Define.
1172 (vle_opcodes): Add se_rfgi and e_sc.
1173 (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
1174 for E200Z4.
1175
3ab87b68
JM		 11762017-04-21 Jose E. Marchesi <jose.marchesi@oracle.com>
1177
1178 * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
1179
792f174f
NC		 11802017-04-21 Nick Clifton <nickc@redhat.com>
1181
1182 PR binutils/21380
1183 * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
1184 LD3R and LD4R.
1185
42742084
AM		 11862017-04-13 Alan Modra <amodra@gmail.com>
1187
1188 * epiphany-desc.c: Regenerate.
1189 * fr30-desc.c: Regenerate.
1190 * frv-desc.c: Regenerate.
1191 * ip2k-desc.c: Regenerate.
1192 * iq2000-desc.c: Regenerate.
1193 * lm32-desc.c: Regenerate.
1194 * m32c-desc.c: Regenerate.
1195 * m32r-desc.c: Regenerate.
1196 * mep-desc.c: Regenerate.
1197 * mt-desc.c: Regenerate.
1198 * or1k-desc.c: Regenerate.
1199 * xc16x-desc.c: Regenerate.
1200 * xstormy16-desc.c: Regenerate.
1201
9a85b496
AM		 12022017-04-11 Alan Modra <amodra@gmail.com>
1203
ef85eab0 1204 * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
c03dc33b
AM		 1205 PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm". Formatting. Set
1206 PPC_OPCODE_TMR for e6500.
9a85b496
AM		 1207 * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
1208 (PPCVEC3): Define as PPC_OPCODE_POWER9.
9570835e
AM		 1209 (PPCVSX2): Define as PPC_OPCODE_POWER8.
1210 (PPCVSX3): Define as PPC_OPCODE_POWER9.
ef85eab0 1211 (PPCHTM): Define as PPC_OPCODE_POWER8.
c03dc33b 1212 (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
9a85b496 1213
62adc510
AM		 12142017-04-10 Alan Modra <amodra@gmail.com>
1215
1216 * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
1217 * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
1218 (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
1219 removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
1220
aa808707
PC		 12212017-04-09 Pip Cet <pipcet@gmail.com>
1222
1223 * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
1224 appropriate floating-point precision directly.
1225
ac8f0f72
AM		 12262017-04-07 Alan Modra <amodra@gmail.com>
1227
1228 * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
1229 lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
1230 lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
1231 lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
1232 vector instructions with E6500 not PPCVEC2.
1233
62ecb94c
PC		 12342017-04-06 Pip Cet <pipcet@gmail.com>
1235
1236 * Makefile.am: Add wasm32-dis.c.
1237 * configure.ac: Add wasm32-dis.c to wasm32 target.
1238 * disassemble.c: Add wasm32 disassembler code.
1239 * wasm32-dis.c: New file.
1240 * Makefile.in: Regenerate.
1241 * configure: Regenerate.
1242 * po/POTFILES.in: Regenerate.
1243 * po/opcodes.pot: Regenerate.
1244
f995bbe8
PA		 12452017-04-05 Pedro Alves <palves@redhat.com>
1246
1247 * arc-dis.c (parse_option, parse_disassembler_options): Constify.
1248 * arm-dis.c (parse_arm_disassembler_options): Constify.
1249 * ppc-dis.c (powerpc_init_dialect): Constify local.
1250 * vax-dis.c (parse_disassembler_options): Constify.
1251
b5292032
PD		 12522017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
1253
1254 * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
1255 RISCV_GP_SYMBOL.
1256
f96bd6c2
PC		 12572017-03-30 Pip Cet <pipcet@gmail.com>
1258
1259 * configure.ac: Add (empty) bfd_wasm32_arch target.
1260 * configure: Regenerate
1261 * po/opcodes.pot: Regenerate.
1262
f7c514a3
JM		 12632017-03-29 Sheldon Lobo <sheldon.lobo@oracle.com>
1264
1265 Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
1266 OSA2015.
1267 * opcodes/sparc-opc.c (asi_table): New ASIs.
1268
52be03fd
AM		 12692017-03-29 Alan Modra <amodra@gmail.com>
1270
1271 * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add
1272 "raw" option.
1273 (lookup_powerpc): Don't special case -1 dialect. Handle
1274 PPC_OPCODE_RAW.
1275 (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
1276 lookup_powerpc call, pass it on second.
1277
9b753937
AM		 12782017-03-27 Alan Modra <amodra@gmail.com>
1279
1280 PR 21303
1281 * ppc-dis.c (struct ppc_mopt): Comment.
1282 (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
1283
c0c31e91
RZ		 12842017-03-27 Rinat Zelig <rinat@mellanox.com>
1285
1286 * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
1287 * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
1288 F_NPS_M, F_NPS_CORE, F_NPS_ALL.
1289 (insert_nps_misc_imm_offset): New function.
1290 (extract_nps_misc imm_offset): New function.
1291 (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
1292 (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
1293
2253c8f0
AK		 12942017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1295
1296 * s390-mkopc.c (main): Remove vx2 check.
1297 * s390-opc.txt: Remove vx2 instruction flags.
1298
645d3342
RZ		 12992017-03-21 Rinat Zelig <rinat@mellanox.com>
1300
1301 * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
1302 * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
1303 (insert_nps_imm_offset): New function.
1304 (extract_nps_imm_offset): New function.
1305 (insert_nps_imm_entry): New function.
1306 (extract_nps_imm_entry): New function.
1307
4b94dd2d
AM		 13082017-03-17 Alan Modra <amodra@gmail.com>
1309
1310 PR 21248
1311 * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
1312 mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after
1313 those spr mnemonics they alias. Similarly for mtibatl, mtibatu.
1314
b416fe87
KC		 13152017-03-14 Kito Cheng <kito.cheng@gmail.com>
1316
1317 * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
1318 <c.andi>: Likewise.
1319 <c.addiw> Likewise.
1320
03b039a5
KC		 13212017-03-14 Kito Cheng <kito.cheng@gmail.com>
1322
1323 * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
1324
2c232b83
AW		 13252017-03-13 Andrew Waterman <andrew@sifive.com>
1326
1327 * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
1328 <srl> Likewise.
1329 <srai> Likewise.
1330 <sra> Likewise.
1331
86fa6981
L		 13322017-03-09 H.J. Lu <hongjiu.lu@intel.com>
1333
1334 * i386-gen.c (opcode_modifiers): Replace S with Load.
1335 * i386-opc.h (S): Removed.
1336 (Load): New.
1337 (i386_opcode_modifier): Replace s with load.
1338 * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
1339 and {evex}. Replace S with Load.
1340 * i386-tbl.h: Regenerated.
1341
c1fe188b
L		 13422017-03-09 H.J. Lu <hongjiu.lu@intel.com>
1343
1344 * i386-opc.tbl: Use CpuCET on rdsspq.
1345 * i386-tbl.h: Regenerated.
1346
4b8b687e
PB		 13472017-03-08 Peter Bergner <bergner@vnet.ibm.com>
1348
1349 * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
1350 <vsx>: Do not use PPC_OPCODE_VSX3;
1351
1437d063
PB		 13522017-03-08 Peter Bergner <bergner@vnet.ibm.com>
1353
1354 * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
1355
603555e5
L		 13562017-03-06 H.J. Lu <hongjiu.lu@intel.com>
1357
1358 * i386-dis.c (REG_0F1E_MOD_3): New enum.
1359 (MOD_0F1E_PREFIX_1): Likewise.
1360 (MOD_0F38F5_PREFIX_2): Likewise.
1361 (MOD_0F38F6_PREFIX_0): Likewise.
1362 (RM_0F1E_MOD_3_REG_7): Likewise.
1363 (PREFIX_MOD_0_0F01_REG_5): Likewise.
1364 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
1365 (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
1366 (PREFIX_0F1E): Likewise.
1367 (PREFIX_MOD_0_0FAE_REG_5): Likewise.
1368 (PREFIX_0F38F5): Likewise.
1369 (dis386_twobyte): Use PREFIX_0F1E.
1370 (reg_table): Add REG_0F1E_MOD_3.
1371 (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
1372 PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
1373 PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
1374 PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
1375 (three_byte_table): Use PREFIX_0F38F5.
1376 (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
1377 Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
1378 (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
1379 RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
1380 PREFIX_MOD_3_0F01_REG_5_RM_2.
1381 * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
1382 (cpu_flags): Add CpuCET.
1383 * i386-opc.h (CpuCET): New enum.
1384 (CpuUnused): Commented out.
1385 (i386_cpu_flags): Add cpucet.
1386 * i386-opc.tbl: Add Intel CET instructions.
1387 * i386-init.h: Regenerated.
1388 * i386-tbl.h: Likewise.
1389
73f07bff
AM		 13902017-03-06 Alan Modra <amodra@gmail.com>
1391
1392 PR 21124
1393 * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
1394 (extract_raq, extract_ras, extract_rbx): New functions.
1395 (powerpc_operands): Use opposite corresponding insert function.
1396 (Q_MASK): Define.
1397 (powerpc_opcodes): Apply Q_MASK to all quad insns with even
1398 register restriction.
1399
65b48a81
PB		 14002017-02-28 Peter Bergner <bergner@vnet.ibm.com>
1401
1402 * disassemble.c Include "safe-ctype.h".
1403 (disassemble_init_for_target): Handle s390 init.
1404 (remove_whitespace_and_extra_commas): New function.
1405 (disassembler_options_cmp): Likewise.
1406 * arm-dis.c: Include "libiberty.h".
1407 (NUM_ELEM): Delete.
1408 (regnames): Use long disassembler style names.
1409 Add force-thumb and no-force-thumb options.
1410 (NUM_ARM_REGNAMES): Rename from this...
1411 (NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE.
1412 (get_arm_regname_num_options): Delete.
1413 (set_arm_regname_option): Likewise.
1414 (get_arm_regnames): Likewise.
1415 (parse_disassembler_options): Likewise.
1416 (parse_arm_disassembler_option): Rename from this...
1417 (parse_arm_disassembler_options): ...to this. Make static.
1418 Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
1419 (print_insn): Use parse_arm_disassembler_options.
1420 (disassembler_options_arm): New function.
1421 (print_arm_disassembler_options): Handle updated regnames.
1422 * ppc-dis.c: Include "libiberty.h".
1423 (ppc_opts): Add "32" and "64" entries.
1424 (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
1425 (powerpc_init_dialect): Add break to switch statement.
1426 Use new FOR_EACH_DISASSEMBLER_OPTION macro.
1427 (disassembler_options_powerpc): New function.
1428 (print_ppc_disassembler_options): Use ARRAY_SIZE.
1429 Remove printing of "32" and "64".
1430 * s390-dis.c: Include "libiberty.h".
1431 (init_flag): Remove unneeded variable.
1432 (struct s390_options_t): New structure type.
1433 (options): New structure.
1434 (init_disasm): Rename from this...
1435 (disassemble_init_s390): ...to this. Add initializations for
1436 current_arch_mask and option_use_insn_len_bits_p. Remove init_flag.
1437 (print_insn_s390): Delete call to init_disasm.
1438 (disassembler_options_s390): New function.
1439 (print_s390_disassembler_options): Print using information from
1440 struct 'options'.
1441 * po/opcodes.pot: Regenerate.
1442
15c7c1d8
JB		 14432017-02-28 Jan Beulich <jbeulich@suse.com>
1444
1445 * i386-dis.c (PCMPESTR_Fixup): New.
1446 (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
1447 (prefix_table): Use PCMPESTR_Fixup.
1448 (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
1449 PCMPESTR_Fixup.
1450 (vex_w_table): Delete VPCMPESTR{I,M} entries.
1451 * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
1452 Split 64-bit and non-64-bit variants.
1453 * opcodes/i386-tbl.h: Re-generate.
1454
582e12bf
RS		 14552017-02-24 Richard Sandiford <richard.sandiford@arm.com>
1456
1457 * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
1458 (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
1459 (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
1460 (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
1461 (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
1462 (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
1463 (OP_SVE_V_HSD): New macros.
1464 (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
1465 (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
1466 (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
1467 (aarch64_opcode_table): Add new SVE instructions.
1468 (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
1469 for rotation operands. Add new SVE operands.
1470 * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
1471 (ins_sve_quad_index): Likewise.
1472 (ins_imm_rotate): Split into...
1473 (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
1474 * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
1475 (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
1476 functions.
1477 (aarch64_ins_sve_addr_ri_s4): New function.
1478 (aarch64_ins_sve_quad_index): Likewise.
1479 (do_misc_encoding): Handle "MOV Zn.Q, Qm".
1480 * aarch64-asm-2.c: Regenerate.
1481 * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
1482 (ext_sve_quad_index): Likewise.
1483 (ext_imm_rotate): Split into...
1484 (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
1485 * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
1486 (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
1487 functions.
1488 (aarch64_ext_sve_addr_ri_s4): New function.
1489 (aarch64_ext_sve_quad_index): Likewise.
1490 (aarch64_ext_sve_index): Allow quad indices.
1491 (do_misc_decoding): Likewise.
1492 * aarch64-dis-2.c: Regenerate.
1493 * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
1494 aarch64_field_kinds.
1495 (OPD_F_OD_MASK): Widen by one bit.
1496 (OPD_F_NO_ZR): Bump accordingly.
1497 (get_operand_field_width): New function.
1498 * aarch64-opc.c (fields): Add new SVE fields.
1499 (operand_general_constraint_met_p): Handle new SVE operands.
1500 (aarch64_print_operand): Likewise.
1501 * aarch64-opc-2.c: Regenerate.
1502
f482d304
RS		 15032017-02-24 Richard Sandiford <richard.sandiford@arm.com>
1504
1505 * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
1506 (aarch64_feature_compnum): ...this.
1507 (SIMD_V8_3): Replace with...
1508 (COMPNUM): ...this.
1509 (CNUM_INSN): New macro.
1510 (aarch64_opcode_table): Use it for the complex number instructions.
1511
7db2c588
JB		 15122017-02-24 Jan Beulich <jbeulich@suse.com>
1513
1514 * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
1515
1e9d41d4
SL		 15162017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
1517
1518 Add support for associating SPARC ASIs with an architecture level.
1519 * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
1520 * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
1521 decoding of SPARC ASIs.
1522
53c4d625
JB		 15232017-02-23 Jan Beulich <jbeulich@suse.com>
1524
1525 * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
1526 82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
1527
11648de5
JB		 15282017-02-21 Jan Beulich <jbeulich@suse.com>
1529
1530 * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
1531 1 (instead of to itself). Correct typo.
1532
f98d33be
AW		 15332017-02-14 Andrew Waterman <andrew@sifive.com>
1534
1535 * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
1536 pseudoinstructions.
1537
773fb663
RS		 15382017-02-15 Richard Sandiford <richard.sandiford@arm.com>
1539
1540 * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
1541 (aarch64_sys_reg_supported_p): Handle them.
1542
cc07cda6
CZ		 15432017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
1544
1545 * arc-opc.c (UIMM6_20R): Define.
1546 (SIMM12_20): Use above.
1547 (SIMM12_20R): Define.
1548 (SIMM3_5_S): Use above.
1549 (UIMM7_A32_11R_S): Define.
1550 (UIMM7_9_S): Use above.
1551 (UIMM3_13R_S): Define.
1552 (SIMM11_A32_7_S): Use above.
1553 (SIMM9_8R): Define.
1554 (UIMM10_A32_8_S): Use above.
1555 (UIMM8_8R_S): Define.
1556 (W6): Use above.
1557 (arc_relax_opcodes): Use all above defines.
1558
66a5a740
VG		 15592017-02-15 Vineet Gupta <vgupta@synopsys.com>
1560
1561 * arc-regs.h: Distinguish some of the registers different on
1562 ARC700 and HS38 cpus.
1563
7e0de605
AM		 15642017-02-14 Alan Modra <amodra@gmail.com>
1565
1566 PR 21118
1567 * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
1568 with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
1569
54064fdb
AM		 15702017-02-11 Stafford Horne <shorne@gmail.com>
1571 Alan Modra <amodra@gmail.com>
1572
1573 * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
1574 Use insn_bytes_value and insn_int_value directly instead. Don't
1575 free allocated memory until function exit.
1576
dce75bf9
NP		 15772017-02-10 Nicholas Piggin <npiggin@gmail.com>
1578
1579 * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
1580
1b7e3d2f
NC		 15812017-02-03 Nick Clifton <nickc@redhat.com>
1582
1583 PR 21096
1584 * aarch64-opc.c (print_register_list): Ensure that the register
1585 list index will fir into the tb buffer.
1586 (print_register_offset_address): Likewise.
1587 * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
1588
8ec5cf65
AD		 15892017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
1590
1591 PR 21056
1592 * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
1593 instructions when the previous fetch packet ends with a 32-bit
1594 instruction.
1595
a1aa5e81
DD		 15962017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
1597
1598 * pru-opc.c: Remove vague reference to a future GDB port.
1599
add3afb2
NC		 16002017-01-20 Nick Clifton <nickc@redhat.com>
1601
1602 * po/ga.po: Updated Irish translation.
1603
c13a63b0
SN		 16042017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
1605
1606 * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
1607
9608051a
YQ		 16082017-01-13 Yao Qi <yao.qi@linaro.org>
1609
1610 * m68k-dis.c (match_insn_m68k): Extend comments. Return -1
1611 if FETCH_DATA returns 0.
1612 (m68k_scan_mask): Likewise.
1613 (print_insn_m68k): Update code to handle -1 return value.
1614
f622ea96
YQ		 16152017-01-13 Yao Qi <yao.qi@linaro.org>
1616
1617 * m68k-dis.c (enum print_insn_arg_error): New.
1618 (NEXTBYTE): Replace -3 with
1619 PRINT_INSN_ARG_MEMORY_ERROR.
1620 (NEXTULONG): Likewise.
1621 (NEXTSINGLE): Likewise.
1622 (NEXTDOUBLE): Likewise.
1623 (NEXTDOUBLE): Likewise.
1624 (NEXTPACKED): Likewise.
1625 (FETCH_ARG): Likewise.
1626 (FETCH_DATA): Update comments.
1627 (print_insn_arg): Update comments. Replace magic numbers with
1628 enum.
1629 (match_insn_m68k): Likewise.
1630
620214f7
IT		 16312017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1632
1633 * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
1634 * i386-dis-evex.h (evex_table): Updated.
1635 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
1636 CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
1637 (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
1638 * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
1639 (i386_cpu_flags): Add cpuavx512_vpopcntdq.
1640 * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
1641 * i386-init.h: Regenerate.
1642 * i386-tbl.h: Ditto.
1643
d95014a2
YQ		 16442017-01-12 Yao Qi <yao.qi@linaro.org>
1645
1646 * msp430-dis.c (msp430_singleoperand): Return -1 if
1647 msp430dis_opcode_signed returns false.
1648 (msp430_doubleoperand): Likewise.
1649 (msp430_branchinstr): Return -1 if
1650 msp430dis_opcode_unsigned returns false.
1651 (msp430x_calla_instr): Likewise.
1652 (print_insn_msp430): Likewise.
1653
0ae60c3e
NC		 16542017-01-05 Nick Clifton <nickc@redhat.com>
1655
1656 PR 20946
1657 * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
1658 could not be matched.
1659 (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
1660 NULL.
1661
d74d4880
SN		 16622017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
1663
1664 * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
1665 (aarch64_opcode_table): Use RCPC_INSN.
1666
cc917fd9
KC		 16672017-01-03 Kito Cheng <kito.cheng@gmail.com>
1668
1669 * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
1670 extension.
1671 * riscv-opcodes/all-opcodes: Likewise.
1672
b52d3cfc
DP		 16732017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
1674
1675 * riscv-dis.c (print_insn_args): Add fall through comment.
1676
f90c58d5
NC		 16772017-01-03 Nick Clifton <nickc@redhat.com>
1678
1679 * po/sr.po: New Serbian translation.
1680 * configure.ac (ALL_LINGUAS): Add sr.
1681 * configure: Regenerate.
1682
f47b0d4a
AM		 16832017-01-02 Alan Modra <amodra@gmail.com>
1684
1685 * epiphany-desc.h: Regenerate.
1686 * epiphany-opc.h: Regenerate.
1687 * fr30-desc.h: Regenerate.
1688 * fr30-opc.h: Regenerate.
1689 * frv-desc.h: Regenerate.
1690 * frv-opc.h: Regenerate.
1691 * ip2k-desc.h: Regenerate.
1692 * ip2k-opc.h: Regenerate.
1693 * iq2000-desc.h: Regenerate.
1694 * iq2000-opc.h: Regenerate.
1695 * lm32-desc.h: Regenerate.
1696 * lm32-opc.h: Regenerate.
1697 * m32c-desc.h: Regenerate.
1698 * m32c-opc.h: Regenerate.
1699 * m32r-desc.h: Regenerate.
1700 * m32r-opc.h: Regenerate.
1701 * mep-desc.h: Regenerate.
1702 * mep-opc.h: Regenerate.
1703 * mt-desc.h: Regenerate.
1704 * mt-opc.h: Regenerate.
1705 * or1k-desc.h: Regenerate.
1706 * or1k-opc.h: Regenerate.
1707 * xc16x-desc.h: Regenerate.
1708 * xc16x-opc.h: Regenerate.
1709 * xstormy16-desc.h: Regenerate.
1710 * xstormy16-opc.h: Regenerate.
1711
2571583a
AM		 17122017-01-02 Alan Modra <amodra@gmail.com>
1713
1714 Update year range in copyright notice of all files.
1715
5c1ad6b5 1716For older changes see ChangeLog-2016
3499769a 1717\f
5c1ad6b5 1718Copyright (C) 2017 Free Software Foundation, Inc.
3499769a
AM		 1719
1720Copying and distribution of this file, with or without modification,
1721are permitted in any medium without royalty provided the copyright
1722notice and this notice are preserved.
1723
1724Local Variables:
1725mode: change-log
1726left-margin: 8
1727fill-column: 74
1728version-control: never
1729End:
GDB Binutils - Deliverables
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