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Fix a small set of Z80 problems.
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
1673df32
JB		 12020-03-13 Jan Beulich <jbeulich@suse.com>
2
3 * i386-dis.c (X86_64_0D): Rename to ...
4 (X86_64_0E): ... this.
5
384f3689
L		 62020-03-09 H.J. Lu <hongjiu.lu@intel.com>
7
8 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
9 * Makefile.in: Regenerated.
10
865e2027
JB		 112020-03-09 Jan Beulich <jbeulich@suse.com>
12
13 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
14 3-operand pseudos.
15 * i386-tbl.h: Re-generate.
16
2f13234b
JB		 172020-03-09 Jan Beulich <jbeulich@suse.com>
18
19 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
20 vprot*, vpsha*, and vpshl*.
21 * i386-tbl.h: Re-generate.
22
3fabc179
JB		 232020-03-09 Jan Beulich <jbeulich@suse.com>
24
25 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
26 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
27 * i386-tbl.h: Re-generate.
28
3677e4c1
JB		 292020-03-09 Jan Beulich <jbeulich@suse.com>
30
31 * i386-gen.c (set_bitfield): Ignore zero-length field names.
32 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
33 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
34 * i386-tbl.h: Re-generate.
35
4c4898e8
JB		 362020-03-09 Jan Beulich <jbeulich@suse.com>
37
38 * i386-gen.c (struct template_arg, struct template_instance,
39 struct template_param, struct template, templates,
40 parse_template, expand_templates): New.
41 (process_i386_opcodes): Various local variables moved to
42 expand_templates. Call parse_template and expand_templates.
43 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
44 * i386-tbl.h: Re-generate.
45
bc49bfd8
JB		 462020-03-06 Jan Beulich <jbeulich@suse.com>
47
48 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
49 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
50 register and memory source templates. Replace VexW= by VexW*
51 where applicable.
52 * i386-tbl.h: Re-generate.
53
4873e243
JB		 542020-03-06 Jan Beulich <jbeulich@suse.com>
55
56 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
57 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
58 * i386-tbl.h: Re-generate.
59
672a349b
JB		 602020-03-06 Jan Beulich <jbeulich@suse.com>
61
62 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
63 * i386-tbl.h: Re-generate.
64
4ed21b58
JB		 652020-03-06 Jan Beulich <jbeulich@suse.com>
66
67 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
68 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
69 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
70 VexW0 on SSE2AVX variants.
71 (vmovq): Drop NoRex64 from XMM/XMM variants.
72 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
73 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
74 applicable use VexW0.
75 * i386-tbl.h: Re-generate.
76
643bb870
JB		 772020-03-06 Jan Beulich <jbeulich@suse.com>
78
79 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
80 * i386-opc.h (Rex64): Delete.
81 (struct i386_opcode_modifier): Remove rex64 field.
82 * i386-opc.tbl (crc32): Drop Rex64.
83 Replace Rex64 with Size64 everywhere else.
84 * i386-tbl.h: Re-generate.
85
a23b33b3
JB		 862020-03-06 Jan Beulich <jbeulich@suse.com>
87
88 * i386-dis.c (OP_E_memory): Exclude recording of used address
89 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
90 addressed memory operands for MPX insns.
91
a0497384
JB		 922020-03-06 Jan Beulich <jbeulich@suse.com>
93
94 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
95 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
96 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
97 (ptwrite): Split into non-64-bit and 64-bit forms.
98 * i386-tbl.h: Re-generate.
99
b630c145
JB		 1002020-03-06 Jan Beulich <jbeulich@suse.com>
101
102 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
103 template.
104 * i386-tbl.h: Re-generate.
105
a847e322
JB		 1062020-03-04 Jan Beulich <jbeulich@suse.com>
107
108 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
109 (prefix_table): Move vmmcall here. Add vmgexit.
110 (rm_table): Replace vmmcall entry by prefix_table[] escape.
111 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
112 (cpu_flags): Add CpuSEV_ES entry.
113 * i386-opc.h (CpuSEV_ES): New.
114 (union i386_cpu_flags): Add cpusev_es field.
115 * i386-opc.tbl (vmgexit): New.
116 * i386-init.h, i386-tbl.h: Re-generate.
117
3cd7f3e3
L		 1182020-03-03 H.J. Lu <hongjiu.lu@intel.com>
119
120 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
121 with MnemonicSize.
122 * i386-opc.h (IGNORESIZE): New.
123 (DEFAULTSIZE): Likewise.
124 (IgnoreSize): Removed.
125 (DefaultSize): Likewise.
126 (MnemonicSize): New.
127 (i386_opcode_modifier): Replace ignoresize/defaultsize with
128 mnemonicsize.
129 * i386-opc.tbl (IgnoreSize): New.
130 (DefaultSize): Likewise.
131 * i386-tbl.h: Regenerated.
132
b8ba1385
SB		 1332020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
134
135 PR 25627
136 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
137 instructions.
138
10d97a0f
L		 1392020-03-03 H.J. Lu <hongjiu.lu@intel.com>
140
141 PR gas/25622
142 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
143 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
144 * i386-tbl.h: Regenerated.
145
dc1e8a47
AM		 1462020-02-26 Alan Modra <amodra@gmail.com>
147
148 * aarch64-asm.c: Indent labels correctly.
149 * aarch64-dis.c: Likewise.
150 * aarch64-gen.c: Likewise.
151 * aarch64-opc.c: Likewise.
152 * alpha-dis.c: Likewise.
153 * i386-dis.c: Likewise.
154 * nds32-asm.c: Likewise.
155 * nfp-dis.c: Likewise.
156 * visium-dis.c: Likewise.
157
265b4673
CZ		 1582020-02-25 Claudiu Zissulescu <claziss@gmail.com>
159
160 * arc-regs.h (int_vector_base): Make it available for all ARC
161 CPUs.
162
bd0cf5a6
NC		 1632020-02-20 Nelson Chu <nelson.chu@sifive.com>
164
165 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
166 changed.
167
fa164239
JW		 1682020-02-19 Nelson Chu <nelson.chu@sifive.com>
169
170 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
171 c.mv/c.li if rs1 is zero.
172
272a84b1
L		 1732020-02-17 H.J. Lu <hongjiu.lu@intel.com>
174
175 * i386-gen.c (cpu_flag_init): Replace CpuABM with
176 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
177 CPU_POPCNT_FLAGS.
178 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
179 * i386-opc.h (CpuABM): Removed.
180 (CpuPOPCNT): New.
181 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
182 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
183 popcnt. Remove CpuABM from lzcnt.
184 * i386-init.h: Regenerated.
185 * i386-tbl.h: Likewise.
186
1f730c46
JB		 1872020-02-17 Jan Beulich <jbeulich@suse.com>
188
189 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
190 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
191 VexW1 instead of open-coding them.
192 * i386-tbl.h: Re-generate.
193
c8f8eebc
JB		 1942020-02-17 Jan Beulich <jbeulich@suse.com>
195
196 * i386-opc.tbl (AddrPrefixOpReg): Define.
197 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
198 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
199 templates. Drop NoRex64.
200 * i386-tbl.h: Re-generate.
201
b9915cbc
JB		 2022020-02-17 Jan Beulich <jbeulich@suse.com>
203
204 PR gas/6518
205 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
206 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
207 into Intel syntax instance (with Unpsecified) and AT&T one
208 (without).
209 (vcvtneps2bf16): Likewise, along with folding the two so far
210 separate ones.
211 * i386-tbl.h: Re-generate.
212
ce504911
L		 2132020-02-16 H.J. Lu <hongjiu.lu@intel.com>
214
215 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
216 CPU_ANY_SSE4A_FLAGS.
217
dabec65d
AM		 2182020-02-17 Alan Modra <amodra@gmail.com>
219
220 * i386-gen.c (cpu_flag_init): Correct last change.
221
af5c13b0
L		 2222020-02-16 H.J. Lu <hongjiu.lu@intel.com>
223
224 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
225 CPU_ANY_SSE4_FLAGS.
226
6867aac0
L		 2272020-02-14 H.J. Lu <hongjiu.lu@intel.com>
228
229 * i386-opc.tbl (movsx): Remove Intel syntax comments.
230 (movzx): Likewise.
231
65fca059
JB		 2322020-02-14 Jan Beulich <jbeulich@suse.com>
233
234 PR gas/25438
235 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
236 destination for Cpu64-only variant.
237 (movzx): Fold patterns.
238 * i386-tbl.h: Re-generate.
239
7deea9aa
JB		 2402020-02-13 Jan Beulich <jbeulich@suse.com>
241
242 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
243 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
244 CPU_ANY_SSE4_FLAGS entry.
245 * i386-init.h: Re-generate.
246
6c0946d0
JB		 2472020-02-12 Jan Beulich <jbeulich@suse.com>
248
249 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
250 with Unspecified, making the present one AT&T syntax only.
251 * i386-tbl.h: Re-generate.
252
ddb56fe6
JB		 2532020-02-12 Jan Beulich <jbeulich@suse.com>
254
255 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
256 * i386-tbl.h: Re-generate.
257
5990e377
JB		 2582020-02-12 Jan Beulich <jbeulich@suse.com>
259
260 PR gas/24546
261 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
262 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
263 Amd64 and Intel64 templates.
264 (call, jmp): Likewise for far indirect variants. Dro
265 Unspecified.
266 * i386-tbl.h: Re-generate.
267
50128d0c
JB		 2682020-02-11 Jan Beulich <jbeulich@suse.com>
269
270 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
271 * i386-opc.h (ShortForm): Delete.
272 (struct i386_opcode_modifier): Remove shortform field.
273 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
274 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
275 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
276 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
277 Drop ShortForm.
278 * i386-tbl.h: Re-generate.
279
1e05b5c4
JB		 2802020-02-11 Jan Beulich <jbeulich@suse.com>
281
282 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
283 fucompi): Drop ShortForm from operand-less templates.
284 * i386-tbl.h: Re-generate.
285
2f5dd314
AM		 2862020-02-11 Alan Modra <amodra@gmail.com>
287
288 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
289 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
290 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
291 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
292 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
293
5aae9ae9
MM		 2942020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
295
296 * arm-dis.c (print_insn_cde): Define 'V' parse character.
297 (cde_opcodes): Add VCX* instructions.
298
4934a27c
MM		 2992020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
300 Matthew Malcomson <matthew.malcomson@arm.com>
301
302 * arm-dis.c (struct cdeopcode32): New.
303 (CDE_OPCODE): New macro.
304 (cde_opcodes): New disassembly table.
305 (regnames): New option to table.
306 (cde_coprocs): New global variable.
307 (print_insn_cde): New
308 (print_insn_thumb32): Use print_insn_cde.
309 (parse_arm_disassembler_options): Parse coprocN args.
310
4b5aaf5f
L		 3112020-02-10 H.J. Lu <hongjiu.lu@intel.com>
312
313 PR gas/25516
314 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
315 with ISA64.
316 * i386-opc.h (AMD64): Removed.
317 (Intel64): Likewose.
318 (AMD64): New.
319 (INTEL64): Likewise.
320 (INTEL64ONLY): Likewise.
321 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
322 * i386-opc.tbl (Amd64): New.
323 (Intel64): Likewise.
324 (Intel64Only): Likewise.
325 Replace AMD64 with Amd64. Update sysenter/sysenter with
326 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
327 * i386-tbl.h: Regenerated.
328
9fc0b501
SB		 3292020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
330
331 PR 25469
332 * z80-dis.c: Add support for GBZ80 opcodes.
333
c5d7be0c
AM		 3342020-02-04 Alan Modra <amodra@gmail.com>
335
336 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
337
44e4546f
AM		 3382020-02-03 Alan Modra <amodra@gmail.com>
339
340 * m32c-ibld.c: Regenerate.
341
b2b1453a
AM		 3422020-02-01 Alan Modra <amodra@gmail.com>
343
344 * frv-ibld.c: Regenerate.
345
4102be5c
JB		 3462020-01-31 Jan Beulich <jbeulich@suse.com>
347
348 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
349 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
350 (OP_E_memory): Replace xmm_mdq_mode case label by
351 vex_scalar_w_dq_mode one.
352 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
353
825bd36c
JB		 3542020-01-31 Jan Beulich <jbeulich@suse.com>
355
356 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
357 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
358 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
359 (intel_operand_size): Drop vex_w_dq_mode case label.
360
c3036ed0
RS		 3612020-01-31 Richard Sandiford <richard.sandiford@arm.com>
362
363 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
364 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
365
0c115f84
AM		 3662020-01-30 Alan Modra <amodra@gmail.com>
367
368 * m32c-ibld.c: Regenerate.
369
bd434cc4
JM		 3702020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
371
372 * bpf-opc.c: Regenerate.
373
aeab2b26
JB		 3742020-01-30 Jan Beulich <jbeulich@suse.com>
375
376 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
377 (dis386): Use them to replace C2/C3 table entries.
378 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
379 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
380 ones. Use Size64 instead of DefaultSize on Intel64 ones.
381 * i386-tbl.h: Re-generate.
382
62b3f548
JB		 3832020-01-30 Jan Beulich <jbeulich@suse.com>
384
385 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
386 forms.
387 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
388 DefaultSize.
389 * i386-tbl.h: Re-generate.
390
1bd8ae10
AM		 3912020-01-30 Alan Modra <amodra@gmail.com>
392
393 * tic4x-dis.c (tic4x_dp): Make unsigned.
394
bc31405e
L		 3952020-01-27 H.J. Lu <hongjiu.lu@intel.com>
396 Jan Beulich <jbeulich@suse.com>
397
398 PR binutils/25445
399 * i386-dis.c (MOVSXD_Fixup): New function.
400 (movsxd_mode): New enum.
401 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
402 (intel_operand_size): Handle movsxd_mode.
403 (OP_E_register): Likewise.
404 (OP_G): Likewise.
405 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
406 register on movsxd. Add movsxd with 16-bit destination register
407 for AMD64 and Intel64 ISAs.
408 * i386-tbl.h: Regenerated.
409
7568c93b
TC		 4102020-01-27 Tamar Christina <tamar.christina@arm.com>
411
412 PR 25403
413 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
414 * aarch64-asm-2.c: Regenerate
415 * aarch64-dis-2.c: Likewise.
416 * aarch64-opc-2.c: Likewise.
417
c006a730
JB		 4182020-01-21 Jan Beulich <jbeulich@suse.com>
419
420 * i386-opc.tbl (sysret): Drop DefaultSize.
421 * i386-tbl.h: Re-generate.
422
c906a69a
JB		 4232020-01-21 Jan Beulich <jbeulich@suse.com>
424
425 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
426 Dword.
427 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
428 * i386-tbl.h: Re-generate.
429
26916852
NC		 4302020-01-20 Nick Clifton <nickc@redhat.com>
431
432 * po/de.po: Updated German translation.
433 * po/pt_BR.po: Updated Brazilian Portuguese translation.
434 * po/uk.po: Updated Ukranian translation.
435
4d6cbb64
AM		 4362020-01-20 Alan Modra <amodra@gmail.com>
437
438 * hppa-dis.c (fput_const): Remove useless cast.
439
2bddb71a
AM		 4402020-01-20 Alan Modra <amodra@gmail.com>
441
442 * arm-dis.c (print_insn_arm): Wrap 'T' value.
443
1b1bb2c6
NC		 4442020-01-18 Nick Clifton <nickc@redhat.com>
445
446 * configure: Regenerate.
447 * po/opcodes.pot: Regenerate.
448
ae774686
NC		 4492020-01-18 Nick Clifton <nickc@redhat.com>
450
451 Binutils 2.34 branch created.
452
07f1f3aa
CB		 4532020-01-17 Christian Biesinger <cbiesinger@google.com>
454
455 * opintl.h: Fix spelling error (seperate).
456
42e04b36
L		 4572020-01-17 H.J. Lu <hongjiu.lu@intel.com>
458
459 * i386-opc.tbl: Add {vex} pseudo prefix.
460 * i386-tbl.h: Regenerated.
461
2da2eaf4
AV		 4622020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
463
464 PR 25376
465 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
466 (neon_opcodes): Likewise.
467 (select_arm_features): Make sure we enable MVE bits when selecting
468 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
469 any architecture.
470
d0849eed
JB		 4712020-01-16 Jan Beulich <jbeulich@suse.com>
472
473 * i386-opc.tbl: Drop stale comment from XOP section.
474
9cf70a44
JB		 4752020-01-16 Jan Beulich <jbeulich@suse.com>
476
477 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
478 (extractps): Add VexWIG to SSE2AVX forms.
479 * i386-tbl.h: Re-generate.
480
4814632e
JB		 4812020-01-16 Jan Beulich <jbeulich@suse.com>
482
483 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
484 Size64 from and use VexW1 on SSE2AVX forms.
485 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
486 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
487 * i386-tbl.h: Re-generate.
488
aad09917
AM		 4892020-01-15 Alan Modra <amodra@gmail.com>
490
491 * tic4x-dis.c (tic4x_version): Make unsigned long.
492 (optab, optab_special, registernames): New file scope vars.
493 (tic4x_print_register): Set up registernames rather than
494 malloc'd registertable.
495 (tic4x_disassemble): Delete optable and optable_special. Use
496 optab and optab_special instead. Throw away old optab,
497 optab_special and registernames when info->mach changes.
498
7a6bf3be
SB		 4992020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
500
501 PR 25377
502 * z80-dis.c (suffix): Use .db instruction to generate double
503 prefix.
504
ca1eaac0
AM		 5052020-01-14 Alan Modra <amodra@gmail.com>
506
507 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
508 values to unsigned before shifting.
509
1d67fe3b
TT		 5102020-01-13 Thomas Troeger <tstroege@gmx.de>
511
512 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
513 flow instructions.
514 (print_insn_thumb16, print_insn_thumb32): Likewise.
515 (print_insn): Initialize the insn info.
516 * i386-dis.c (print_insn): Initialize the insn info fields, and
517 detect jumps.
518
5e4f7e05
CZ		 5192012-01-13 Claudiu Zissulescu <claziss@gmail.com>
520
521 * arc-opc.c (C_NE): Make it required.
522
b9fe6b8a
CZ		 5232012-01-13 Claudiu Zissulescu <claziss@gmail.com>
524
525 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
526 reserved register name.
527
90dee485
AM		 5282020-01-13 Alan Modra <amodra@gmail.com>
529
530 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
531 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
532
febda64f
AM		 5332020-01-13 Alan Modra <amodra@gmail.com>
534
535 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
536 result of wasm_read_leb128 in a uint64_t and check that bits
537 are not lost when copying to other locals. Use uint32_t for
538 most locals. Use PRId64 when printing int64_t.
539
df08b588
AM		 5402020-01-13 Alan Modra <amodra@gmail.com>
541
542 * score-dis.c: Formatting.
543 * score7-dis.c: Formatting.
544
b2c759ce
AM		 5452020-01-13 Alan Modra <amodra@gmail.com>
546
547 * score-dis.c (print_insn_score48): Use unsigned variables for
548 unsigned values. Don't left shift negative values.
549 (print_insn_score32): Likewise.
550 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
551
5496abe1
AM		 5522020-01-13 Alan Modra <amodra@gmail.com>
553
554 * tic4x-dis.c (tic4x_print_register): Remove dead code.
555
202e762b
AM		 5562020-01-13 Alan Modra <amodra@gmail.com>
557
558 * fr30-ibld.c: Regenerate.
559
7ef412cf
AM		 5602020-01-13 Alan Modra <amodra@gmail.com>
561
562 * xgate-dis.c (print_insn): Don't left shift signed value.
563 (ripBits): Formatting, use 1u.
564
7f578b95
AM		 5652020-01-10 Alan Modra <amodra@gmail.com>
566
567 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
568 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
569
441af85b
AM		 5702020-01-10 Alan Modra <amodra@gmail.com>
571
572 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
573 and XRREG value earlier to avoid a shift with negative exponent.
574 * m10200-dis.c (disassemble): Similarly.
575
bce58db4
NC		 5762020-01-09 Nick Clifton <nickc@redhat.com>
577
578 PR 25224
579 * z80-dis.c (ld_ii_ii): Use correct cast.
580
40c75bc8
SB		 5812020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
582
583 PR 25224
584 * z80-dis.c (ld_ii_ii): Use character constant when checking
585 opcode byte value.
586
d835a58b
JB		 5872020-01-09 Jan Beulich <jbeulich@suse.com>
588
589 * i386-dis.c (SEP_Fixup): New.
590 (SEP): Define.
591 (dis386_twobyte): Use it for sysenter/sysexit.
592 (enum x86_64_isa): Change amd64 enumerator to value 1.
593 (OP_J): Compare isa64 against intel64 instead of amd64.
594 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
595 forms.
596 * i386-tbl.h: Re-generate.
597
030a2e78
AM		 5982020-01-08 Alan Modra <amodra@gmail.com>
599
600 * z8k-dis.c: Include libiberty.h
601 (instr_data_s): Make max_fetched unsigned.
602 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
603 Don't exceed byte_info bounds.
604 (output_instr): Make num_bytes unsigned.
605 (unpack_instr): Likewise for nibl_count and loop.
606 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
607 idx unsigned.
608 * z8k-opc.h: Regenerate.
609
bb82aefe
SV		 6102020-01-07 Shahab Vahedi <shahab@synopsys.com>
611
612 * arc-tbl.h (llock): Use 'LLOCK' as class.
613 (llockd): Likewise.
614 (scond): Use 'SCOND' as class.
615 (scondd): Likewise.
616 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
617 (scondd): Likewise.
618
cc6aa1a6
AM		 6192020-01-06 Alan Modra <amodra@gmail.com>
620
621 * m32c-ibld.c: Regenerate.
622
660e62b1
AM		 6232020-01-06 Alan Modra <amodra@gmail.com>
624
625 PR 25344
626 * z80-dis.c (suffix): Don't use a local struct buffer copy.
627 Peek at next byte to prevent recursion on repeated prefix bytes.
628 Ensure uninitialised "mybuf" is not accessed.
629 (print_insn_z80): Don't zero n_fetch and n_used here,..
630 (print_insn_z80_buf): ..do it here instead.
631
c9ae58fe
AM		 6322020-01-04 Alan Modra <amodra@gmail.com>
633
634 * m32r-ibld.c: Regenerate.
635
5f57d4ec
AM		 6362020-01-04 Alan Modra <amodra@gmail.com>
637
638 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
639
2c5c1196
AM		 6402020-01-04 Alan Modra <amodra@gmail.com>
641
642 * crx-dis.c (match_opcode): Avoid shift left of signed value.
643
2e98c6c5
AM		 6442020-01-04 Alan Modra <amodra@gmail.com>
645
646 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
647
567dfba2
JB		 6482020-01-03 Jan Beulich <jbeulich@suse.com>
649
5437a02a
JB		 650 * aarch64-tbl.h (aarch64_opcode_table): Use
651 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
652
6532020-01-03 Jan Beulich <jbeulich@suse.com>
654
655 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
567dfba2
JB		 656 forms of SUDOT and USDOT.
657
8c45011a
JB		 6582020-01-03 Jan Beulich <jbeulich@suse.com>
659
5437a02a 660 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
8c45011a
JB		 661 uzip{1,2}.
662 * opcodes/aarch64-dis-2.c: Re-generate.
663
f4950f76
JB		 6642020-01-03 Jan Beulich <jbeulich@suse.com>
665
5437a02a 666 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
f4950f76
JB		 667 FMMLA encoding.
668 * opcodes/aarch64-dis-2.c: Re-generate.
669
6655dba2
SB		 6702020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
671
672 * z80-dis.c: Add support for eZ80 and Z80 instructions.
673
b14ce8bf
AM		 6742020-01-01 Alan Modra <amodra@gmail.com>
675
676 Update year range in copyright notice of all files.
677
0b114740 678For older changes see ChangeLog-2019
3499769a 679\f
0b114740 680Copyright (C) 2020 Free Software Foundation, Inc.
3499769a
AM		 681
682Copying and distribution of this file, with or without modification,
683are permitted in any medium without royalty provided the copyright
684notice and this notice are preserved.
685
686Local Variables:
687mode: change-log
688left-margin: 8
689fill-column: 74
690version-control: never
691End:
GDB Binutils - Deliverables
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