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2008-05-27 Kai Tietz <kai.tietz@onevision.com>
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
cbc80391
L		 12008-05-22 H.J. Lu <hongjiu.lu@intel.com>
2
3 * i386-opc.tbl: Add NoAVX to cvtpd2pi, cvtpi2pd and cvttpd2pi.
4 * i386-tbl.h: Regenerated.
5
116615c5
L		 62008-05-22 H.J. Lu <hongjiu.lu@intel.com>
7
8 PR gas/6517
9 * i386-opc.tbl: Break cvtsi2ss/cvtsi2sd/vcvtsi2sd/vcvtsi2ss
10 into 32bit and 64bit. Remove Reg64|Qword and add
11 IgnoreSize|No_qSuf on 32bit version.
12 * i386-tbl.h: Regenerated.
13
d9479f2d
L		 142008-05-21 H.J. Lu <hongjiu.lu@intel.com>
15
16 * i386-opc.tbl: Add NoAVX to movdq2q and movq2dq.
17 * i386-tbl.h: Regenerated.
18
3ce6fddb
NC		 192008-05-21 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
20
21 * cr16-dis.c (build_mask): Adjust the mask for 32-bit bcond.
22
8944f3c2
AM		 232008-05-14 Alan Modra <amodra@bigpond.net.au>
24
25 * Makefile.am: Run "make dep-am".
26 * Makefile.in: Regenerate.
27
f1f8f695
L		 282008-05-02 H.J. Lu <hongjiu.lu@intel.com>
29
30 * i386-dis.c (MOVBE_Fixup): New.
31 (Mo): Likewise.
32 (PREFIX_0F3880): Likewise.
33 (PREFIX_0F3881): Likewise.
34 (PREFIX_0F38F0): Updated.
35 (prefix_table): Add PREFIX_0F3880 and PREFIX_0F3881. Update
36 PREFIX_0F38F0 and PREFIX_0F38F1 for movbe.
37 (three_byte_table): Use PREFIX_0F3880 and PREFIX_0F3881.
38
39 * i386-gen.c (cpu_flag_init): Add CPU_MOVBE_FLAGS and
40 CPU_EPT_FLAGS.
41 (cpu_flags): Add CpuMovbe and CpuEPT.
42
43 * i386-opc.h (CpuMovbe): New.
44 (CpuEPT): Likewise.
45 (CpuLM): Updated.
46 (i386_cpu_flags): Add cpumovbe and cpuept.
47
48 * i386-opc.tbl: Add entries for movbe and EPT instructions.
49 * i386-init.h: Regenerated.
50 * i386-tbl.h: Likewise.
51
89aa3097
AN		 522008-04-29 Adam Nemet <anemet@caviumnetworks.com>
53
54 * mips-opc.c (mips_builtin_opcodes): Set field `match' to 0 for
55 the two drem and the two dremu macros.
56
39c5c168
AN		 572008-04-28 Adam Nemet <anemet@caviumnetworks.com>
58
59 * mips-opc.c (mips_builtin_opcodes): Mark prefx and c1
60 instructions FP_S. Mark l.s, li.s, lwc1, swc1, s.s, trunc.w.s and
61 cop1 macros INSN2_M_FP_S. Mark l.d, li.d, ldc1 and sdc1 macros
62 INSN2_M_FP_D. Mark trunc.w.d macro INSN2_M_FP_S and INSN2_M_FP_D.
63
f04d18b7
DM		 642008-04-25 David S. Miller <davem@davemloft.net>
65
66 * sparc-dis.c: Emit %stick instead of %sys_tick, and %stick_cmpr
67 instead of %sys_tick_cmpr, as suggested in architecture manuals.
68
6194aaab
L		 692008-04-23 Paolo Bonzini <bonzini@gnu.org>
70
71 * aclocal.m4: Regenerate.
72 * configure: Regenerate.
73
1a6b486f
DM		 742008-04-23 David S. Miller <davem@davemloft.net>
75
76 * sparc-opc.c (asi_table): Add UltraSPARC and Niagara
77 extended values.
78 (prefetch_table): Add missing values.
79
81f8a913
L		 802008-04-22 H.J. Lu <hongjiu.lu@intel.com>
81
82 * i386-gen.c (opcode_modifiers): Add NoAVX.
83
84 * i386-opc.h (NoAVX): New.
85 (OldGcc): Updated.
86 (i386_opcode_modifier): Add noavx.
87
88 * i386-opc.tbl: Add NoAVX to SSE, SSE2, SSE3 and SSSE3
89 instructions which don't have AVX equivalent.
90 * i386-tbl.h: Regenerated.
91
dae39acc
L		 922008-04-18 H.J. Lu <hongjiu.lu@intel.com>
93
94 * i386-dis.c (OP_VEX_FMA): New.
95 (OP_EX_VexImmW): Likewise.
96 (VexFMA): Likewise.
97 (Vex128FMA): Likewise.
98 (EXVexImmW): Likewise.
99 (get_vex_imm8): Likewise.
100 (OP_EX_VexReg): Likewise.
101 (vex_i4_done): Renamed to ...
102 (vex_w_done): This.
103 (prefix_table): Replace EXVexW with EXVexImmW on vpermil2ps
104 and vpermil2pd. Replace Vex/Vex128 with VexFMA/Vex128FMA on
105 FMA instructions.
106 (print_insn): Updated.
107 (OP_EX_VexW): Rewrite to swap register in VEX with EX.
108 (OP_REG_VexI4): Check invalid high registers.
109
ce886ab1
DR		 1102008-04-16 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
111 Michael Meissner <michael.meissner@amd.com>
112
113 * i386-opc.tbl: Fix protX to allow memory in the middle operand.
114 * i386-tbl.h: Regenerate from i386-opc.tbl.
8944f3c2 115
19a6653c
AM		 1162008-04-14 Edmar Wienskoski <edmar@freescale.com>
117
118 * ppc-dis.c (powerpc_dialect): Handle "e500mc". Extend "e500" to
119 accept Power E500MC instructions.
120 (print_ppc_disassembler_options): Document -Me500mc.
121 * ppc-opc.c (DUIS, DUI, T): New.
122 (XRT, XRTRA): Likewise.
123 (E500MC): Likewise.
124 (powerpc_opcodes): Add new Power E500MC instructions.
125
112b7c50
AK		 1262008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
127
128 * s390-dis.c (init_disasm): Evaluate disassembler_options.
129 (print_s390_disassembler_options): New function.
130 * disassemble.c (disassembler_usage): Invoke
131 print_s390_disassembler_options.
132
7ff42648
AK		 1332008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
134
135 * s390-mkopc.c (insertExpandedMnemonic): Expand string sizes
136 of local variables used for mnemonic parsing: prefix, suffix and
137 number.
138
45a5551e
AK		 1392008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
140
141 * s390-mkopc.c (s390_cond_ext_format): Add back the mnemonic
142 extensions for conditional jumps (o, p, m, nz, z, nm, np, no).
143 (s390_crb_extensions): New extensions table.
144 (insertExpandedMnemonic): Handle '$' tag.
145 * s390-opc.txt: Remove conditional jump variants which can now
146 be expanded automatically.
147 Replace '*' tag with '$' in the compare and branch instructions.
148
06c8514a
L		 1492008-04-07 H.J. Lu <hongjiu.lu@intel.com>
150
151 * i386-dis.c (PREFIX_VEX_38XX): Add a tab.
152 (PREFIX_VEX_3AXX): Likewis.
153
b122c285
L		 1542008-04-07 H.J. Lu <hongjiu.lu@intel.com>
155
156 * i386-opc.tbl: Remove 4 extra blank lines.
157
594ab6a3
L		 1582008-04-04 H.J. Lu <hongjiu.lu@intel.com>
159
160 * i386-gen.c (cpu_flag_init): Replace CPU_CLMUL_FLAGS/CpuCLMUL
161 with CPU_PCLMUL_FLAGS/CpuPCLMUL.
162 (cpu_flags): Replace CpuCLMUL with CpuPCLMUL.
163 * i386-opc.tbl: Likewise.
164
165 * i386-opc.h (CpuCLMUL): Renamed to ...
166 (CpuPCLMUL): This.
167 (CpuFMA): Updated.
168 (i386_cpu_flags): Replace cpuclmul with cpupclmul.
169
170 * i386-init.h: Regenerated.
171
c0f3af97
L		 1722008-04-03 H.J. Lu <hongjiu.lu@intel.com>
173
174 * i386-dis.c (OP_E_register): New.
175 (OP_E_memory): Likewise.
176 (OP_VEX): Likewise.
177 (OP_EX_Vex): Likewise.
178 (OP_EX_VexW): Likewise.
179 (OP_XMM_Vex): Likewise.
180 (OP_XMM_VexW): Likewise.
181 (OP_REG_VexI4): Likewise.
182 (PCLMUL_Fixup): Likewise.
183 (VEXI4_Fixup): Likewise.
184 (VZERO_Fixup): Likewise.
185 (VCMP_Fixup): Likewise.
186 (VPERMIL2_Fixup): Likewise.
187 (rex_original): Likewise.
188 (rex_ignored): Likewise.
189 (Mxmm): Likewise.
190 (XMM): Likewise.
191 (EXxmm): Likewise.
192 (EXxmmq): Likewise.
193 (EXymmq): Likewise.
194 (Vex): Likewise.
195 (Vex128): Likewise.
196 (Vex256): Likewise.
197 (VexI4): Likewise.
198 (EXdVex): Likewise.
199 (EXqVex): Likewise.
200 (EXVexW): Likewise.
201 (EXdVexW): Likewise.
202 (EXqVexW): Likewise.
203 (XMVex): Likewise.
204 (XMVexW): Likewise.
205 (XMVexI4): Likewise.
206 (PCLMUL): Likewise.
207 (VZERO): Likewise.
208 (VCMP): Likewise.
209 (VPERMIL2): Likewise.
210 (xmm_mode): Likewise.
211 (xmmq_mode): Likewise.
212 (ymmq_mode): Likewise.
213 (vex_mode): Likewise.
214 (vex128_mode): Likewise.
215 (vex256_mode): Likewise.
216 (USE_VEX_C4_TABLE): Likewise.
217 (USE_VEX_C5_TABLE): Likewise.
218 (USE_VEX_LEN_TABLE): Likewise.
219 (VEX_C4_TABLE): Likewise.
220 (VEX_C5_TABLE): Likewise.
221 (VEX_LEN_TABLE): Likewise.
222 (REG_VEX_XX): Likewise.
223 (MOD_VEX_XXX): Likewise.
224 (PREFIX_0F38DB..PREFIX_0F38DF): Likewise.
225 (PREFIX_0F3A44): Likewise.
226 (PREFIX_0F3ADF): Likewise.
227 (PREFIX_VEX_XXX): Likewise.
228 (VEX_OF): Likewise.
229 (VEX_OF38): Likewise.
230 (VEX_OF3A): Likewise.
231 (VEX_LEN_XXX): Likewise.
232 (vex): Likewise.
233 (need_vex): Likewise.
234 (need_vex_reg): Likewise.
235 (vex_i4_done): Likewise.
236 (vex_table): Likewise.
237 (vex_len_table): Likewise.
238 (OP_REG_VexI4): Likewise.
239 (vex_cmp_op): Likewise.
240 (pclmul_op): Likewise.
241 (vpermil2_op): Likewise.
242 (m_mode): Updated.
243 (es_reg): Likewise.
244 (PREFIX_0F38F0): Likewise.
245 (PREFIX_0F3A60): Likewise.
246 (reg_table): Add REG_VEX_71...REG_VEX_73 and REG_VEX_AE.
247 (prefix_table): Add PREFIX_0F38DB..PREFIX_0F38DF, PREFIX_0F3ADF
248 and PREFIX_VEX_XXX entries.
249 (x86_64_table): Use VEX_C4_TABLE and VEX_C5_TABLE.
250 (three_byte_table): Use PREFIX_0F38DB..PREFIX_0F38DF and
251 PREFIX_0F3ADF.
252 (mod_table): Use VEX_C4_TABLE, VEX_C5_TABLE and VEX_LEN_TABLE.
253 Add MOD_VEX_XXX entries.
254 (ckprefix): Initialize rex_original and rex_ignored. Store the
255 REX byte in rex_original.
256 (get_valid_dis386): Handle the implicit prefix in VEX prefix
257 bytes and USE_VEX_LEN_TABLE/USE_VEX_C4_TABLE/USE_VEX_C5_TABLE.
258 (print_insn): Set need_vex/need_vex_reg/vex_i4_done to 0 before
259 calling get_valid_dis386. Use rex_original and rex_ignored when
260 printing out REX.
261 (putop): Handle "XY".
262 (intel_operand_size): Handle VEX, xmm_mode, xmmq_mode and
263 ymmq_mode.
264 (OP_E_extended): Updated to use OP_E_register and
265 OP_E_memory.
266 (OP_XMM): Handle VEX.
267 (OP_EX): Likewise.
268 (XMM_Fixup): Likewise.
269 (CMP_Fixup): Use ARRAY_SIZE.
270
271 * i386-gen.c (cpu_flag_init): Add CpuAES, CPU_CLMUL_FLAGS,
272 CPU_FMA_FLAGS and CPU_AVX_FLAGS.
273 (operand_type_init): Add OPERAND_TYPE_REGYMM and
274 OPERAND_TYPE_VEX_IMM4.
275 (cpu_flags): Add CpuAVX, CpuAES, CpuCLMUL and CpuFMA.
276 (opcode_modifiers): Add Implicit1stXmm0, Vex, Vex256, VexNDD,
277 VexNDS, VexW0, VexW1, Vex0F, Vex0F38, Vex0F3A, Vex3Sources,
278 VexImmExt and SSE2AVX.
279 (operand_types): Add RegYMM, Ymmword and Vex_Imm4.
280
281 * i386-opc.h (CpuAVX): New.
282 (CpuAES): Likewise.
283 (CpuCLMUL): Likewise.
284 (CpuFMA): Likewise.
285 (Vex): Likewise.
286 (Vex256): Likewise.
287 (VexNDS): Likewise.
288 (VexNDD): Likewise.
289 (VexW0): Likewise.
290 (VexW1): Likewise.
291 (Vex0F): Likewise.
292 (Vex0F38): Likewise.
293 (Vex0F3A): Likewise.
294 (Vex3Sources): Likewise.
295 (VexImmExt): Likewise.
296 (SSE2AVX): Likewise.
297 (RegYMM): Likewise.
298 (Ymmword): Likewise.
299 (Vex_Imm4): Likewise.
300 (Implicit1stXmm0): Likewise.
301 (CpuXsave): Updated.
302 (CpuLM): Likewise.
303 (ByteOkIntel): Likewise.
304 (OldGcc): Likewise.
305 (Control): Likewise.
306 (Unspecified): Likewise.
307 (OTMax): Likewise.
308 (i386_cpu_flags): Add cpuavx, cpuaes, cpuclmul and cpufma.
309 (i386_opcode_modifier): Add implicit1stxmm0, vex, vex256,
310 vexnds, vexndd, vexw0, vexw1, vex0f, vex0f38, vex0f3a,
311 vex3sources, veximmext and sse2avx.
312 (i386_operand_type): Add regymm, ymmword and vex_imm4.
313
314 * i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions.
315
316 * i386-reg.tbl: Add AVX registers, ymm0..ymm15.
317
318 * i386-init.h: Regenerated.
319 * i386-tbl.h: Likewise.
320
b21c9cb4
BS		 3212008-03-26 Bernd Schmidt <bernd.schmidt@analog.com>
322
323 From Robin Getz <robin.getz@analog.com>
324 * bfin-dis.c (bu32): Typedef.
325 (enum const_forms_t): Add c_uimm32 and c_huimm32.
326 (constant_formats[]): Add uimm32 and huimm16.
327 (fmtconst_val): New.
328 (uimm32): Define.
329 (huimm32): Define.
330 (imm16_val): Define.
331 (luimm16_val): Define.
332 (struct saved_state): Define.
333 (GREG, DPREG, DREG, PREG, SPREG, FPREG, IREG, MREG, BREG, LREG,
334 A0XREG, A0WREG, A1XREG, A1WREG,CCREG, LC0REG, LT0REG, LB0REG,
335 LC1REG, LT1REG, LB1REG, RETSREG, PCREG): Define.
336 (get_allreg): New.
337 (decode_LDIMMhalf_0): Print out the whole register value.
338
ee171c8f
BS		 339 From Jie Zhang <jie.zhang@analog.com>
340 * bfin-dis.c (decode_dsp32mac_0): Decode (IU) option for
341 multiply and multiply-accumulate to data register instruction.
342
086134ec
BS		 343 * bfin-dis.c: (c_uimm4s4d, c_imm5d, c_imm7d, c_imm16d, c_uimm16s4d,
344 c_imm32, c_huimm32e): Define.
345 (constant_formats): Add flags for printing decimal, leading spaces, and
346 exact symbols.
347 (comment, parallel): Add global flags in all disassembly.
348 (fmtconst): Take advantage of new flags, and print default in hex.
349 (fmtconst_val): Likewise.
350 (decode_macfunc): Be consistant with spaces, tabs, comments,
351 capitalization in disassembly, fix minor coding style issues.
352 (reg_names, amod0, amod1, amod0amod2, aligndir, get_allreg): Likewise.
353 (decode_ProgCtrl_0, decode_PushPopMultiple_0, decode_CCflag_0,
354 decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0,
355 decode_REGMV_0, decode_ALU2op_0, decode_PTR2op_0, decode_LOGI2op_0,
356 decode_COMP3op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
357 decode_LDSTpmod_0, decode_dagMODim_0, decode_dagMODik_0,
358 decode_dspLDST_0, decode_LDST_0, decode_LDSTiiFP_0, decode_LDSTii_0,
359 decode_LoopSetup_0, decode_LDIMMhalf_0, decode_CALLa_0,
360 decode_LDSTidxI_0, decode_linkage_0, decode_dsp32alu_0,
361 decode_dsp32shift_0, decode_dsp32shiftimm_0, decode_pseudodbg_assert_0,
362 _print_insn_bfin, print_insn_bfin): Likewise.
363
58c85be7
RW		 3642008-03-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
365
366 * aclocal.m4: Regenerate.
367 * configure: Likewise.
368 * Makefile.in: Likewise.
369
50e7d84b
AM		 3702008-03-13 Alan Modra <amodra@bigpond.net.au>
371
372 * Makefile.am: Run "make dep-am".
373 * Makefile.in: Regenerate.
374 * configure: Regenerate.
375
de866fcc
AM		 3762008-03-07 Alan Modra <amodra@bigpond.net.au>
377
378 * ppc-opc.c (powerpc_opcodes): Order and format.
379
28dbc079
L		 3802008-03-01 H.J. Lu <hongjiu.lu@intel.com>
381
382 * i386-opc.tbl: Allow 16-bit near indirect branches for x86-64.
383 * i386-tbl.h: Regenerated.
384
849830bd
L		 3852008-02-23 H.J. Lu <hongjiu.lu@intel.com>
386
387 * i386-opc.tbl: Disallow 16-bit near indirect branches for
388 x86-64.
389 * i386-tbl.h: Regenerated.
390
743ddb6b
JB		 3912008-02-21 Jan Beulich <jbeulich@novell.com>
392
393 * i386-opc.tbl: Allow Dword for far indirect call. Allow Dword
394 and Fword for far indirect jmp. Allow Reg16 and Word for near
395 indirect jmp on x86-64. Disallow Fword for lcall.
396 * i386-tbl.h: Re-generate.
397
796d5313
NC		 3982008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
399
400 * cr16-opc.c (cr16_num_optab): Defined
401
65da13b5
L		 4022008-02-16 H.J. Lu <hongjiu.lu@intel.com>
403
404 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_INOUTPORTREG.
405 * i386-init.h: Regenerated.
406
0e336180
NC		 4072008-02-14 Nick Clifton <nickc@redhat.com>
408
409 PR binutils/5524
410 * configure.in (SHARED_LIBADD): Select the correct host specific
411 file extension for shared libraries.
412 * configure: Regenerate.
413
b7240065
JB		 4142008-02-13 Jan Beulich <jbeulich@novell.com>
415
416 * i386-opc.h (RegFlat): New.
417 * i386-reg.tbl (flat): Add.
418 * i386-tbl.h: Re-generate.
419
34b772a6
JB		 4202008-02-13 Jan Beulich <jbeulich@novell.com>
421
422 * i386-dis.c (a_mode): New.
423 (cond_jump_mode): Adjust.
424 (Ma): Change to a_mode.
425 (intel_operand_size): Handle a_mode.
426 * i386-opc.tbl: Allow Dword and Qword for bound.
427 * i386-tbl.h: Re-generate.
428
a60de03c
JB		 4292008-02-13 Jan Beulich <jbeulich@novell.com>
430
431 * i386-gen.c (process_i386_registers): Process new fields.
432 * i386-opc.h (reg_entry): Shrink reg_flags and reg_num to
433 unsigned char. Add dw2_regnum and Dw2Inval.
434 * i386-reg.tbl: Provide initializers for dw2_regnum. Add pseudo
435 register names.
436 * i386-tbl.h: Re-generate.
437
f03fe4c1
L		 4382008-02-11 H.J. Lu <hongjiu.lu@intel.com>
439
4b6bc8eb 440 * i386-gen.c (cpu_flag_init): Add CPU_XSAVE_FLAGS.
f03fe4c1
L		 441 * i386-init.h: Updated.
442
475a2301
L		 4432008-02-11 H.J. Lu <hongjiu.lu@intel.com>
444
445 * i386-gen.c (cpu_flags): Add CpuXsave.
446
447 * i386-opc.h (CpuXsave): New.
4b6bc8eb 448 (CpuLM): Updated.
475a2301
L		 449 (i386_cpu_flags): Add cpuxsave.
450
451 * i386-dis.c (MOD_0FAE_REG_4): New.
452 (RM_0F01_REG_2): Likewise.
453 (MOD_0FAE_REG_5): Updated.
454 (RM_0F01_REG_3): Likewise.
455 (reg_table): Use MOD_0FAE_REG_4.
456 (mod_table): Use RM_0F01_REG_2. Add MOD_0FAE_REG_4. Updated
457 for xrstor.
458 (rm_table): Add RM_0F01_REG_2.
459
460 * i386-opc.tbl: Add xsave, xrstor, xgetbv and xsetbv.
461 * i386-init.h: Regenerated.
462 * i386-tbl.h: Likewise.
463
595785c6 4642008-02-11 Jan Beulich <jbeulich@novell.com>
041179fc 465
595785c6
JB		 466 * i386-opc.tbl: Remove Disp32S from CpuNo64 opcodes. Remove
467 Disp16 from Cpu64 non-jump opcodes (including loop and j?cxz).
468 * i386-tbl.h: Re-generate.
469
bb8541b9
L		 4702008-02-04 H.J. Lu <hongjiu.lu@intel.com>
471
472 PR 5715
473 * configure: Regenerated.
474
57b592a3
AN		 4752008-02-04 Adam Nemet <anemet@caviumnetworks.com>
476
477 * mips-dis.c: Update copyright.
478 (mips_arch_choices): Add Octeon.
479 * mips-opc.c: Update copyright.
480 (IOCT): New macro.
481 (mips_builtin_opcodes): Add Octeon instruction synciobdma.
482
930bb4cf
AM		 4832008-01-29 Alan Modra <amodra@bigpond.net.au>
484
485 * ppc-opc.c: Support optional L form mtmsr.
486
82c18208
L		 4872008-01-24 H.J. Lu <hongjiu.lu@intel.com>
488
489 * i386-dis.c (OP_E_extended): Handle r12 like rsp.
490
599121aa
L		 4912008-01-23 H.J. Lu <hongjiu.lu@intel.com>
492
493 * i386-gen.c (cpu_flag_init): Add CpuLM to CPU_GENERIC64_FLAGS.
494 * i386-init.h: Regenerated.
495
80098f51
TG		 4962008-01-23 Tristan Gingold <gingold@adacore.com>
497
498 * ia64-dis.c (print_insn_ia64): Display symbolic name of ar.fcr,
499 ar.eflag, ar.csd, ar.ssd, ar.cflg, ar.fsr, ar.fir and ar.fdr.
500
115c7c25
L		 5012008-01-22 H.J. Lu <hongjiu.lu@intel.com>
502
503 * i386-gen.c (cpu_flag_init): Remove CpuMMX2.
504 (cpu_flags): Likewise.
505
506 * i386-opc.h (CpuMMX2): Removed.
507 (CpuSSE): Updated.
508
509 * i386-opc.tbl: Replace CpuMMX2 with CpuSSE|Cpu3dnowA.
510 * i386-init.h: Regenerated.
511 * i386-tbl.h: Likewise.
512
6305a203
L		 5132008-01-22 H.J. Lu <hongjiu.lu@intel.com>
514
515 * i386-gen.c (cpu_flag_init): Add CPU_VMX_FLAGS and
516 CPU_SMX_FLAGS.
517 * i386-init.h: Regenerated.
518
fd07a1c8
L		 5192008-01-15 H.J. Lu <hongjiu.lu@intel.com>
520
521 * i386-opc.tbl: Use Qword on movddup.
522 * i386-tbl.h: Regenerated.
523
321fd21e
L		 5242008-01-15 H.J. Lu <hongjiu.lu@intel.com>
525
526 * i386-opc.tbl: Put back 16bit movsx/movzx for AT&T syntax.
527 * i386-tbl.h: Regenerated.
528
4ee52178
L		 5292008-01-15 H.J. Lu <hongjiu.lu@intel.com>
530
531 * i386-dis.c (Mx): New.
532 (PREFIX_0FC3): Likewise.
533 (PREFIX_0FC7_REG_6): Updated.
534 (dis386_twobyte): Use PREFIX_0FC3.
535 (prefix_table): Add PREFIX_0FC3. Use Mq on movntq and movntsd.
536 Use Mx on movntps, movntpd, movntdq and movntdqa. Use Md on
537 movntss.
538
5c07affc
L		 5392008-01-14 H.J. Lu <hongjiu.lu@intel.com>
540
541 * i386-gen.c (opcode_modifiers): Add IntelSyntax.
542 (operand_types): Add Mem.
543
544 * i386-opc.h (IntelSyntax): New.
545 * i386-opc.h (Mem): New.
546 (Byte): Updated.
547 (Opcode_Modifier_Max): Updated.
548 (i386_opcode_modifier): Add intelsyntax.
549 (i386_operand_type): Add mem.
550
551 * i386-opc.tbl: Remove Reg16 from movnti. Add sizes to more
552 instructions.
553
554 * i386-reg.tbl: Add size for accumulator.
555
556 * i386-init.h: Regenerated.
557 * i386-tbl.h: Likewise.
558
0d6a2f58
L		 5592008-01-13 H.J. Lu <hongjiu.lu@intel.com>
560
561 * i386-opc.h (Byte): Fix a typo.
562
7d5e4556
L		 5632008-01-12 H.J. Lu <hongjiu.lu@intel.com>
564
565 PR gas/5534
566 * i386-gen.c (operand_type_init): Add Dword to
567 OPERAND_TYPE_ACC32. Add Qword to OPERAND_TYPE_ACC64.
568 (opcode_modifiers): Remove CheckSize, Byte, Word, Dword,
569 Qword and Xmmword.
570 (operand_types): Add Byte, Word, Dword, Fword, Qword, Tbyte,
571 Xmmword, Unspecified and Anysize.
572 (set_bitfield): Make Mmword an alias of Qword. Make Oword
573 an alias of Xmmword.
574
575 * i386-opc.h (CheckSize): Removed.
576 (Byte): Updated.
577 (Word): Likewise.
578 (Dword): Likewise.
579 (Qword): Likewise.
580 (Xmmword): Likewise.
581 (FWait): Updated.
582 (OTMax): Likewise.
583 (i386_opcode_modifier): Remove checksize, byte, word, dword,
584 qword and xmmword.
585 (Fword): New.
586 (TBYTE): Likewise.
587 (Unspecified): Likewise.
588 (Anysize): Likewise.
589 (i386_operand_type): Add byte, word, dword, fword, qword,
590 tbyte xmmword, unspecified and anysize.
591
592 * i386-opc.tbl: Updated to use Byte, Word, Dword, Fword, Qword,
593 Tbyte, Xmmword, Unspecified and Anysize.
594
595 * i386-reg.tbl: Add size for accumulator.
596
597 * i386-init.h: Regenerated.
598 * i386-tbl.h: Likewise.
599
b5b1fc4f
L		 6002008-01-10 H.J. Lu <hongjiu.lu@intel.com>
601
602 * i386-dis.c (REG_0F0E): Renamed to REG_0F0D.
603 (REG_0F18): Updated.
604 (reg_table): Updated.
605 (dis386_twobyte): Updated. Use "nopQ" on 0x19 to 0x1e.
606 (twobyte_has_modrm): Set 1 for 0x19 to 0x1e.
607
50e8458f
L		 6082008-01-08 H.J. Lu <hongjiu.lu@intel.com>
609
610 * i386-gen.c (set_bitfield): Use fail () on error.
611
3d4d5afa
L		 6122008-01-08 H.J. Lu <hongjiu.lu@intel.com>
613
614 * i386-gen.c (lineno): New.
615 (filename): Likewise.
616 (set_bitfield): Report filename and line numer on error.
617 (process_i386_opcodes): Set filename and update lineno.
618 (process_i386_registers): Likewise.
619
e1d4d893
L		 6202008-01-05 H.J. Lu <hongjiu.lu@intel.com>
621
622 * i386-gen.c (opcode_modifiers): Rename IntelMnemonic to
623 ATTSyntax.
624
625 * i386-opc.h (IntelMnemonic): Renamed to ..
626 (ATTSyntax): This
627 (Opcode_Modifier_Max): Updated.
628 (i386_opcode_modifier): Remove intelmnemonic. Add attsyntax
629 and intelsyntax.
630
8944f3c2 631 * i386-opc.tbl: Remove IntelMnemonic and update with ATTSyntax
e1d4d893
L		 632 on fsub, fubp, fsubr, fsubrp, div, fdivp, fdivr and fdivrp.
633 * i386-tbl.h: Regenerated.
634
6f143e4d
L		 6352008-01-04 H.J. Lu <hongjiu.lu@intel.com>
636
637 * i386-gen.c: Update copyright to 2008.
638 * i386-opc.h: Likewise.
639 * i386-opc.tbl: Likewise.
640
641 * i386-init.h: Regenerated.
642 * i386-tbl.h: Likewise.
643
c6add537
L		 6442008-01-04 H.J. Lu <hongjiu.lu@intel.com>
645
646 * i386-opc.tbl: Add NoRex64 to extractps, movmskpd, movmskps,
647 pextrb, pextrw, pinsrb, pinsrw and pmovmskb.
648 * i386-tbl.h: Regenerated.
649
3629bb00
L		 6502008-01-03 H.J. Lu <hongjiu.lu@intel.com>
651
652 * i386-gen.c (cpu_flag_init): Remove CpuSSE4_1_Or_5 and
653 CpuSSE4_2_Or_ABM.
654 (cpu_flags): Likewise.
655
656 * i386-opc.h (CpuSSE4_1_Or_5): Removed.
657 (CpuSSE4_2_Or_ABM): Likewise.
658 (CpuLM): Updated.
659 (i386_cpu_flags): Remove cpusse4_1_or_5 and cpusse4_2_or_abm.
660
661 * i386-opc.tbl: Replace CpuSSE4_1_Or_5, CpuSSE4_2_Or_ABM and
662 Cpu686|CpuPadLock with CpuSSE4_1|CpuSSE5, CpuABM|CpuSSE4_2
663 and CpuPadLock, respectively.
664 * i386-init.h: Regenerated.
665 * i386-tbl.h: Likewise.
666
24995bd6
L		 6672008-01-03 H.J. Lu <hongjiu.lu@intel.com>
668
669 * i386-gen.c (opcode_modifiers): Remove No_xSuf.
670
671 * i386-opc.h (No_xSuf): Removed.
672 (CheckSize): Updated.
673
674 * i386-tbl.h: Regenerated.
675
e0329a22
L		 6762008-01-02 H.J. Lu <hongjiu.lu@intel.com>
677
678 * i386-gen.c (cpu_flag_init): Add CpuSSE4_2_Or_ABM to
679 CPU_AMDFAM10_FLAGS, CPU_SSE4_2_FLAGS, CpuABM and
680 CPU_SSE5_FLAGS.
681 (cpu_flags): Add CpuSSE4_2_Or_ABM.
682
683 * i386-opc.h (CpuSSE4_2_Or_ABM): New.
684 (CpuLM): Updated.
685 (i386_cpu_flags): Add cpusse4_2_or_abm.
686
687 * i386-opc.tbl: Use CpuSSE4_2_Or_ABM instead of
688 CpuABM|CpuSSE4_2 on popcnt.
689 * i386-init.h: Regenerated.
690 * i386-tbl.h: Likewise.
691
f2a9c676
L		 6922008-01-02 H.J. Lu <hongjiu.lu@intel.com>
693
694 * i386-opc.h: Update comments.
695
d978b5be
L		 6962008-01-02 H.J. Lu <hongjiu.lu@intel.com>
697
698 * i386-gen.c (opcode_modifiers): Use Qword instead of QWord.
699 * i386-opc.h: Likewise.
700 * i386-opc.tbl: Likewise.
701
582d5edd
L		 7022008-01-02 H.J. Lu <hongjiu.lu@intel.com>
703
704 PR gas/5534
705 * i386-gen.c (opcode_modifiers): Add No_xSuf, CheckSize,
706 Byte, Word, Dword, QWord and Xmmword.
707
708 * i386-opc.h (No_xSuf): New.
709 (CheckSize): Likewise.
710 (Byte): Likewise.
711 (Word): Likewise.
712 (Dword): Likewise.
713 (QWord): Likewise.
714 (Xmmword): Likewise.
715 (FWait): Updated.
716 (i386_opcode_modifier): Add No_xSuf, CheckSize, Byte, Word,
717 Dword, QWord and Xmmword.
718
719 * i386-opc.tbl: Add CheckSize|QWord to movq if IgnoreSize is
720 used.
721 * i386-tbl.h: Regenerated.
722
3fe15143
MK		 7232008-01-02 Mark Kettenis <kettenis@gnu.org>
724
725 * m88k-dis.c (instructions): Fix fcvt.* instructions.
726 From Miod Vallat.
727
6c7ac64e 728For older changes see ChangeLog-2007
252b5132
RH		 729\f
730Local Variables:
2f6d2f85
NC		 731mode: change-log
732left-margin: 8
733fill-column: 74
252b5132
RH		 734version-control: never
735End:
GDB Binutils - Deliverables
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