[deliverable/binutils-gdb.git] / opcodes / ChangeLog

2015-07-30  H.J. Lu  <hongjiu.lu@intel.com>

	PR binutils/13571
	* i386-dis.c (MOD_0FC3): New.
	(PREFIX_0FC3): Renamed to ...
	(PREFIX_MOD_0_0FC3): This.
	(dis386_twobyte): Replace PREFIX_0FC3 with MOD_0FC3.
	(prefix_table): Replace Ma with Ev on movntiS.
	(mod_table): Add MOD_0FC3.

2015-07-27  H.J. Lu  <hongjiu.lu@intel.com>

	* configure: Regenerated.

2015-07-23  Alan Modra  <amodra@gmail.com>

	PR 18708
	* i386-dis.c (get64): Avoid signed integer overflow.

2015-07-22  Alexander Fomin  <alexander.fomin@intel.com>

	PR binutils/18631
	* i386-dis-evex.h (EVEX_W_0F78_P_2): Replace "EXxmmq" with
	"EXEvexHalfBcstXmmq" for the second operand.
	(EVEX_W_0F79_P_2): Likewise.
	(EVEX_W_0F7A_P_2): Likewise.
	(EVEX_W_0F7B_P_2): Likewise.

2015-07-16  Alessandro Marzocchi  <alessandro.marzocchi@gmail.com>

	* arm-dis.c (print_insn_coprocessor): Added support for quarter
	float bitfield format.
	(coprocessor_opcodes): Changed VFP vmov reg,immediate to use new
	quarter float bitfield format.

2015-07-14  H.J. Lu  <hongjiu.lu@intel.com>

	* configure: Regenerated.

2015-07-03  Alan Modra  <amodra@gmail.com>

	* ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
	* ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries.  Add
	PPC_OPCODE_7450 to 7450 entry.  Add PPC_OPCODE_750 to 750cl entry.

2015-07-01  Sandra Loosemore  <sandra@codesourcery.com>
	    Cesar Philippidis  <cesar@codesourcery.com>

	* nios2-dis.c (nios2_extract_opcode): New.
	(nios2_disassembler_state): New.
	(nios2_find_opcode_hash): Use mach parameter to select correct
	disassembler state.
	(nios2_print_insn_arg): Extend to support new R2 argument letters
	and formats.
	(print_insn_nios2): Check for 16-bit instruction at end of memory.
	* nios2-opc.c (nios2_builtin_regs): Add R2 register attributes.
	(NIOS2_NUM_OPCODES): Rename to...
	(NIOS2_NUM_R1_OPCODES): This.
	(nios2_r2_opcodes): New.
	(NIOS2_NUM_R2_OPCODES): New.
	(nios2_num_r2_opcodes): New.
	(nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New.
	(nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New.
	(nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New.
	(nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New.
	(nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings):	New.

2015-06-30  Amit Pawar  <Amit.Pawar@amd.com>

	* i386-dis.c (OP_Mwaitx): New.
	(rm_table): Add monitorx/mwaitx.
	* i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS
	and CPU_ZNVER1_FLAGS.  Add CPU_MWAITX_FLAGS.
	(operand_type_init): Add CpuMWAITX.
	* i386-opc.h (CpuMWAITX): New.
	(i386_cpu_flags): Add cpumwaitx.
	* i386-opc.tbl: Add monitorx and mwaitx.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2015-06-22  Peter Bergner  <bergner@vnet.ibm.com>

	* ppc-opc.c (insert_ls): Test for invalid LS operands.
	(insert_esync): New function.
	(LS, WC): Use insert_ls.
	(ESYNC): Use insert_esync.

2015-06-22  Nick Clifton  <nickc@redhat.com>

	* dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
	requested region lies beyond it.
	* bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
	looking for 32-bit insns.
	* mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
	data.
	* sh-dis.c (print_insn_sh): Likewise.
	* tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
	blocks of instructions.
	* vax-dis.c (print_insn_vax): Check that the requested address
	does not clash with the stop_vma.

2015-06-19  Peter Bergner  <bergner@vnet.ibm.com>

	* ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
	* ppc-opc.c (FXM4): Add non-zero optional value.
	(TBR): Likewise.
	(SXL): Likewise.
	(insert_fxm): Handle new default operand value.
	(extract_fxm): Likewise.
	(insert_tbr): Likewise.
	(extract_tbr): Likewise.

2015-06-16  Matthew Wahab  <matthew.wahab@arm.com>

	* arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".

2015-06-16  Szabolcs Nagy  <szabolcs.nagy@arm.com>

	* arm-dis.c (print_insn_coprocessor): Avoid negative shift.

2015-06-12  Peter Bergner  <bergner@vnet.ibm.com>

	* ppc-opc.c: Add comment accidentally removed by old commit.
	(MTMSRD_L): Delete.

2015-06-04  Peter Bergner  <bergner@vnet.ibm.com>

	* ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.

2015-06-04  Nick Clifton  <nickc@redhat.com>

	PR 18474
	* msp430-dis.c (msp430_nooperands): Fix check for emulated insns.

2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>

	* arm-dis.c (arm_opcodes): Add "setpan".
	(thumb_opcodes): Add "setpan".

2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>

	* arm-dis.c (select_arm_features): Rework to avoid used of redefined
	macros.

2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64-tbl.h (aarch64_feature_rdma): New.
	(RDMA): New.
	(aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Regenerate.
	* aarch64-opc-2.c: Regenerate.

2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64-tbl.h (aarch64_feature_lor): New.
	(LOR): New.
	(aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
	"stllrb", "stllrh".
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Regenerate.
	* aarch64-opc-2.c: Regenerate.

2015-06-01  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64-opc.c (F_ARCHEXT): New.
	(aarch64_sys_regs): Add "pan".
	(aarch64_sys_reg_supported_p): New.
	(aarch64_pstatefields): Add "pan".
	(aarch64_pstatefield_supported_p): New.

2015-06-01  Jan Beulich  <jbeulich@suse.com>

	* i386-tbl.h: Regenerate.

2015-06-01  Jan Beulich  <jbeulich@suse.com>

	* i386-dis.c (print_insn): Swap rounding mode specifier and
	general purpose register in Intel mode.

2015-06-01  Jan Beulich  <jbeulich@suse.com>

	* i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
	* i386-tbl.h: Regenerate.

2015-05-18  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
	* i386-init.h: Regenerated.

2015-05-15  H.J. Lu  <hongjiu.lu@intel.com>

	PR binutis/18386
	* i386-dis.c: Add comments for '@'.
	(x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
	(enum x86_64_isa): New.
	(isa64): Likewise.
	(print_i386_disassembler_options): Add amd64 and intel64.
	(print_insn): Handle amd64 and intel64.
	(putop): Handle '@'.
	(OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
	* i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
	* i386-opc.h (AMD64): New.
	(CpuIntel64): Likewise.
	(i386_cpu_flags): Add cpuamd64 and cpuintel64.
	* i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
	Mark direct call/jmp without Disp16|Disp32 as Intel64.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2015-05-14  Peter Bergner  <bergner@vnet.ibm.com>

	* ppc-opc.c (IH) New define.
	(powerpc_opcodes) <wait>: Do not enable for POWER7.
	<tlbie>: Add RS operand for POWER7.
	<slbia>: Add IH operand for POWER6.

2015-05-11  H.J. Lu  <hongjiu.lu@intel.com>

	* opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
	direct branch.
	(jmp): Likewise.
	* i386-tbl.h: Regenerated.

2015-05-11  H.J. Lu  <hongjiu.lu@intel.com>

	* configure.ac: Support bfd_iamcu_arch.
	* disassemble.c (disassembler): Support bfd_iamcu_arch.
	* i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
	CPU_IAMCU_COMPAT_FLAGS.
	(cpu_flags): Add CpuIAMCU.
	* i386-opc.h (CpuIAMCU): New.
	(i386_cpu_flags): Add cpuiamcu.
	* configure: Regenerated.
	* i386-init.h: Likewise.
	* i386-tbl.h: Likewise.

2015-05-08  H.J. Lu  <hongjiu.lu@intel.com>

	PR binutis/18386
	* i386-dis.c (X86_64_E8): New.
	(X86_64_E9): Likewise.
	Update comments on 'T', 'U', 'V'.  Add comments for '^'.
	(dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
	(x86_64_table): Add X86_64_E8 and X86_64_E9.
	(mod_table): Replace {T|} with ^ on Jcall/Jmp.
	(putop): Handle '^'.
	(OP_J): Ignore the operand size prefix in 64-bit.  Don't check
	REX_W.

2015-04-30  DJ Delorie  <dj@redhat.com>

	* disassemble.c (disassembler): Choose suitable disassembler based
	on E_ABI.
	* rl78-decode.opc (rl78_decode_opcode): Take ISA parameter.  Use
	it to decode mul/div insns.
	* rl78-decode.c: Regenerate.
	* rl78-dis.c (print_insn_rl78): Rename to...
	(print_insn_rl78_common): ...this, take ISA parameter.
	(print_insn_rl78): New.
	(print_insn_rl78_g10): New.
	(print_insn_rl78_g13): New.
	(print_insn_rl78_g14): New.
	(rl78_get_disassembler): New.

2015-04-29  Nick Clifton  <nickc@redhat.com>

	* po/fr.po: Updated French translation.

2015-04-27  Peter Bergner  <bergner@vnet.ibm.com>

	* ppc-opc.c (DCBT_EO): New define.
	(powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
	<lharx>: Likewise.
	<stbcx.>: Likewise.
	<sthcx.>: Likewise.
	<waitrsv>: Do not enable for POWER7 and later.
	<waitimpl>: Likewise.
	<dcbt>: Default to the two operand form of the instruction for all
	"old" cpus.  For "new" cpus, use the operand ordering that matches
	whether the cpu is server or embedded.
	<dcbtst>: Likewise.

2015-04-27  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* s390-opc.c: New instruction type VV0UU2.
	* s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
	and WFC.

2015-04-23  Jan Beulich  <jbeulich@suse.com>

	* i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
	* i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
	vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
	(vfpclasspd, vfpclassps): Add %XZ.

2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (PREFIX_UD_SHIFT): Removed.
	(PREFIX_UD_REPZ): Likewise.
	(PREFIX_UD_REPNZ): Likewise.
	(PREFIX_UD_DATA): Likewise.
	(PREFIX_UD_ADDR): Likewise.
	(PREFIX_UD_LOCK): Likewise.

2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (prefix_requirement): Removed.
	(print_insn): Don't set prefix_requirement.  Check
	dp->prefix_requirement instead of prefix_requirement.

2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>

	PR binutils/17898
	* i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
	(PREFIX_MOD_0_0FC7_REG_6): This.
	(PREFIX_MOD_3_0FC7_REG_6): New.
	(PREFIX_MOD_3_0FC7_REG_7): Likewise.
	(prefix_table): Replace PREFIX_0FC7_REG_6 with
	PREFIX_MOD_0_0FC7_REG_6.  Add PREFIX_MOD_3_0FC7_REG_6 and
	PREFIX_MOD_3_0FC7_REG_7.
	(mod_table): Replace PREFIX_0FC7_REG_6 with
	PREFIX_MOD_0_0FC7_REG_6.  Use PREFIX_MOD_3_0FC7_REG_6 and
	PREFIX_MOD_3_0FC7_REG_7.

2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
	(PREFIX_MANDATORY_REPNZ): Likewise.
	(PREFIX_MANDATORY_DATA): Likewise.
	(PREFIX_MANDATORY_ADDR): Likewise.
	(PREFIX_MANDATORY_LOCK): Likewise.
	(PREFIX_MANDATORY): Likewise.
	(PREFIX_UD_SHIFT): Set to 8
	(PREFIX_UD_REPZ): Updated.
	(PREFIX_UD_REPNZ): Likewise.
	(PREFIX_UD_DATA): Likewise.
	(PREFIX_UD_ADDR): Likewise.
	(PREFIX_UD_LOCK): Likewise.
	(PREFIX_IGNORED_SHIFT): New.
	(PREFIX_IGNORED_REPZ): Likewise.
	(PREFIX_IGNORED_REPNZ): Likewise.
	(PREFIX_IGNORED_DATA): Likewise.
	(PREFIX_IGNORED_ADDR): Likewise.
	(PREFIX_IGNORED_LOCK): Likewise.
	(PREFIX_OPCODE): Likewise.
	(PREFIX_IGNORED): Likewise.
	(Bad_Opcode): Replace PREFIX_MANDATORY with 0.
	(dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
	(three_byte_table): Likewise.
	(mod_table): Likewise.
	(mandatory_prefix): Renamed to ...
	(prefix_requirement): This.
	(prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
	Update PREFIX_90 entry.
	(get_valid_dis386): Check prefix_requirement to see if a prefix
	should be ignored.
	(print_insn): Replace mandatory_prefix with prefix_requirement.

2015-04-15  Renlin Li  <renlin.li@arm.com>

	* arm-dis.c (thumb32_opcodes): Define 'D' format control code,
	use it for ssat and ssat16.
	(print_insn_thumb32): Add handle case for 'D' control code.

2015-04-06  Ilya Tocar  <ilya.tocar@intel.com>
	    H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis-evex.h (evex_table): Fill prefix_requirement field.
	* i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
	PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
	PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
	PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
	(Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
	Fill prefix_requirement field.
	(struct dis386): Add prefix_requirement field.
	(dis386): Fill prefix_requirement field.
	(dis386_twobyte): Ditto.
	(twobyte_has_mandatory_prefix_: Remove.
	(reg_table): Fill prefix_requirement field.
	(prefix_table): Ditto.
	(x86_64_table): Ditto.
	(three_byte_table): Ditto.
	(xop_table): Ditto.
	(vex_table): Ditto.
	(vex_len_table): Ditto.
	(vex_w_table): Ditto.
	(mod_table): Ditto.
	(bad_opcode): Ditto.
	(print_insn): Use prefix_requirement.
	(FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
	FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
	(float_reg): Ditto.

2015-03-30  Mike Frysinger  <vapier@gentoo.org>

	* d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.

2015-03-29  H.J. Lu  <hongjiu.lu@intel.com>

	* Makefile.in: Regenerated.

2015-03-25  Anton Blanchard  <anton@samba.org>

	* ppc-dis.c (disassemble_init_powerpc): Only initialise
	powerpc_opcd_indices and vle_opcd_indices once.

2015-03-25  Anton Blanchard  <anton@samba.org>

	* ppc-opc.c (powerpc_opcodes): Add slbfee.

2015-03-24  Terry Guo  <terry.guo@arm.com>

	* arm-dis.c (opcode32): Updated to use new arm feature struct.
	(opcode16): Likewise.
	(coprocessor_opcodes): Replace bit with feature struct.
	(neon_opcodes): Likewise.
	(arm_opcodes): Likewise.
	(thumb_opcodes): Likewise.
	(thumb32_opcodes): Likewise.
	(print_insn_coprocessor): Likewise.
	(print_insn_arm): Likewise.
	(select_arm_features): Follow new feature struct.

2015-03-17  Ganesh Gopalasubramanian  <Ganesh.Gopalasubramanian@amd.com>

	* i386-dis.c (rm_table): Add clzero.
	* i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
	Add CPU_CLZERO_FLAGS.
	(cpu_flags): Add CpuCLZERO.
	* i386-opc.h: Add CpuCLZERO.
	* i386-opc.tbl: Add clzero.
	* i386-init.h: Re-generated.
	* i386-tbl.h: Re-generated.

2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>

	* mips-opc.c (decode_mips_operand): Fix constraint issues
	with u and y operands.

2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>

	* mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.

2015-03-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* s390-opc.c: Add new IBM z13 instructions.
	* s390-opc.txt: Likewise.

2015-03-10  Renlin Li  <renlin.li@arm.com>

	* aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
	stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
	related alias.
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Likewise.
	* aarch64-opc-2.c: Likewise.

2015-03-03  Jiong Wang  <jiong.wang@arm.com>

	* arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.

2015-02-25  Oleg Endo  <olegendo@gcc.gnu.org>

	* sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
	arch_sh_up.
	(pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
	arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.

2015-02-23  Vinay  <Vinay.G@kpit.com>

	* rl78-decode.opc (MOV): Added space between two operands for
	'mov' instruction in index addressing mode.
	* rl78-decode.c: Regenerate.

2015-02-19  Pedro Alves  <palves@redhat.com>

	* microblaze-dis.h [__cplusplus]: Wrap in extern "C".

2015-02-10  Pedro Alves  <palves@redhat.com>
	    Tom Tromey  <tromey@redhat.com>

	* microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
	microblaze_and, microblaze_xor.
	* microblaze-opc.h (opcodes): Adjust.

2015-01-28  James Bowman  <james.bowman@ftdichip.com>

	* Makefile.am: Add FT32 files.
	* configure.ac: Handle FT32.
	* disassemble.c (disassembler): Call print_insn_ft32.
	* ft32-dis.c: New file.
	* ft32-opc.c: New file.
	* Makefile.in: Regenerate.
	* configure: Regenerate.
	* po/POTFILES.in: Regenerate.

2015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>

	* nds32-asm.c (keyword_sr): Add new system registers.

2015-01-16  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* s390-dis.c (s390_extract_operand): Support vector register
	operands.
	(s390_print_insn_with_opcode): Support new operands types and add
	new handling of optional operands.
	* s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
	and include opcode/s390.h instead.
	(struct op_struct): New field `flags'.
	(insertOpcode, insertExpandedMnemonic): New parameter `flags'.
	(dumpTable): Dump flags.
	(main): Parse flags from the s390-opc.txt file.  Add z13 as cpu
	string.
	* s390-opc.c: Add new operands types, instruction formats, and
	instruction masks.
	(s390_opformats): Add new formats for .insn.
	* s390-opc.txt: Add new instructions.

2015-01-01  Alan Modra  <amodra@gmail.com>

	Update year range in copyright notice of all files.

For older changes see ChangeLog-2014
\f
Copyright (C) 2015 Free Software Foundation, Inc.

Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved.

Local Variables:
mode: change-log
left-margin: 8
fill-column: 74
version-control: never
End:
Commit	Line	Data
a8484f96 L	1	2015-07-30 H.J. Lu <hongjiu.lu@intel.com>
	2
	3	PR binutils/13571
	4	* i386-dis.c (MOD_0FC3): New.
	5	(PREFIX_0FC3): Renamed to ...
	6	(PREFIX_MOD_0_0FC3): This.
	7	(dis386_twobyte): Replace PREFIX_0FC3 with MOD_0FC3.
	8	(prefix_table): Replace Ma with Ev on movntiS.
	9	(mod_table): Add MOD_0FC3.
	10
37a42ee9 L	11	2015-07-27 H.J. Lu <hongjiu.lu@intel.com>
	12
	13	* configure: Regenerated.
	14
070fe95d AM	15	2015-07-23 Alan Modra <amodra@gmail.com>
	16
	17	PR 18708
	18	* i386-dis.c (get64): Avoid signed integer overflow.
	19
20c2a615 L	20	2015-07-22 Alexander Fomin <alexander.fomin@intel.com>
	21
	22	PR binutils/18631
	23	* i386-dis-evex.h (EVEX_W_0F78_P_2): Replace "EXxmmq" with
	24	"EXEvexHalfBcstXmmq" for the second operand.
	25	(EVEX_W_0F79_P_2): Likewise.
	26	(EVEX_W_0F7A_P_2): Likewise.
	27	(EVEX_W_0F7B_P_2): Likewise.
	28
6f1c2142 AM	29	2015-07-16 Alessandro Marzocchi <alessandro.marzocchi@gmail.com>
	30
	31	* arm-dis.c (print_insn_coprocessor): Added support for quarter
	32	float bitfield format.
	33	(coprocessor_opcodes): Changed VFP vmov reg,immediate to use new
	34	quarter float bitfield format.
	35
8a643cc3 L	36	2015-07-14 H.J. Lu <hongjiu.lu@intel.com>
	37
	38	* configure: Regenerated.
	39
ef5a96d5 AM	40	2015-07-03 Alan Modra <amodra@gmail.com>
	41
	42	* ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
	43	* ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries. Add
	44	PPC_OPCODE_7450 to 7450 entry. Add PPC_OPCODE_750 to 750cl entry.
	45
c8c8175b SL	46	2015-07-01 Sandra Loosemore <sandra@codesourcery.com>
	47	Cesar Philippidis <cesar@codesourcery.com>
	48
	49	* nios2-dis.c (nios2_extract_opcode): New.
	50	(nios2_disassembler_state): New.
	51	(nios2_find_opcode_hash): Use mach parameter to select correct
	52	disassembler state.
	53	(nios2_print_insn_arg): Extend to support new R2 argument letters
	54	and formats.
	55	(print_insn_nios2): Check for 16-bit instruction at end of memory.
	56	* nios2-opc.c (nios2_builtin_regs): Add R2 register attributes.
	57	(NIOS2_NUM_OPCODES): Rename to...
	58	(NIOS2_NUM_R1_OPCODES): This.
	59	(nios2_r2_opcodes): New.
	60	(NIOS2_NUM_R2_OPCODES): New.
	61	(nios2_num_r2_opcodes): New.
	62	(nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New.
	63	(nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New.
	64	(nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New.
	65	(nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New.
	66	(nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): New.
	67
9916071f AP	68	2015-06-30 Amit Pawar <Amit.Pawar@amd.com>
	69
	70	* i386-dis.c (OP_Mwaitx): New.
	71	(rm_table): Add monitorx/mwaitx.
	72	* i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS
	73	and CPU_ZNVER1_FLAGS. Add CPU_MWAITX_FLAGS.
	74	(operand_type_init): Add CpuMWAITX.
	75	* i386-opc.h (CpuMWAITX): New.
	76	(i386_cpu_flags): Add cpumwaitx.
	77	* i386-opc.tbl: Add monitorx and mwaitx.
	78	* i386-init.h: Regenerated.
	79	* i386-tbl.h: Likewise.
	80
7b934113 PB	81	2015-06-22 Peter Bergner <bergner@vnet.ibm.com>
	82
	83	* ppc-opc.c (insert_ls): Test for invalid LS operands.
	84	(insert_esync): New function.
	85	(LS, WC): Use insert_ls.
	86	(ESYNC): Use insert_esync.
	87
bdc4de1b NC	88	2015-06-22 Nick Clifton <nickc@redhat.com>
	89
	90	* dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
	91	requested region lies beyond it.
	92	* bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
	93	looking for 32-bit insns.
	94	* mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
	95	data.
	96	* sh-dis.c (print_insn_sh): Likewise.
	97	* tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
	98	blocks of instructions.
	99	* vax-dis.c (print_insn_vax): Check that the requested address
	100	does not clash with the stop_vma.
	101
11a0cf2e PB	102	2015-06-19 Peter Bergner <bergner@vnet.ibm.com>
11a0cf2e PB	103
070fe95d	104	* ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
11a0cf2e PB	105	* ppc-opc.c (FXM4): Add non-zero optional value.
	106	(TBR): Likewise.
	107	(SXL): Likewise.
	108	(insert_fxm): Handle new default operand value.
	109	(extract_fxm): Likewise.
	110	(insert_tbr): Likewise.
	111	(extract_tbr): Likewise.
	112
bdfa8b95 MW	113	2015-06-16 Matthew Wahab <matthew.wahab@arm.com>
	114
	115	* arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
	116
24b4cf66 SN	117	2015-06-16 Szabolcs Nagy <szabolcs.nagy@arm.com>
	118
	119	* arm-dis.c (print_insn_coprocessor): Avoid negative shift.
	120
99a2c561 PB	121	2015-06-12 Peter Bergner <bergner@vnet.ibm.com>
	122
	123	* ppc-opc.c: Add comment accidentally removed by old commit.
	124	(MTMSRD_L): Delete.
	125
40f77f82 AM	126	2015-06-04 Peter Bergner <bergner@vnet.ibm.com>
	127
	128	* ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.
	129
13be46a2 NC	130	2015-06-04 Nick Clifton <nickc@redhat.com>
	131
	132	PR 18474
	133	* msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
	134
ddfded2f MW	135	2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
	136
	137	* arm-dis.c (arm_opcodes): Add "setpan".
	138	(thumb_opcodes): Add "setpan".
	139
1af1dd51 MW	140	2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
	141
	142	* arm-dis.c (select_arm_features): Rework to avoid used of redefined
	143	macros.
	144
9e1f0fa7 MW	145	2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
	146
	147	* aarch64-tbl.h (aarch64_feature_rdma): New.
	148	(RDMA): New.
	149	(aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
	150	* aarch64-asm-2.c: Regenerate.
	151	* aarch64-dis-2.c: Regenerate.
	152	* aarch64-opc-2.c: Regenerate.
	153
290806fd MW	154	2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
	155
	156	* aarch64-tbl.h (aarch64_feature_lor): New.
	157	(LOR): New.
	158	(aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
	159	"stllrb", "stllrh".
	160	* aarch64-asm-2.c: Regenerate.
	161	* aarch64-dis-2.c: Regenerate.
	162	* aarch64-opc-2.c: Regenerate.
	163
f21cce2c MW	164	2015-06-01 Matthew Wahab <matthew.wahab@arm.com>
	165
	166	* aarch64-opc.c (F_ARCHEXT): New.
	167	(aarch64_sys_regs): Add "pan".
	168	(aarch64_sys_reg_supported_p): New.
	169	(aarch64_pstatefields): Add "pan".
	170	(aarch64_pstatefield_supported_p): New.
	171
d194d186 JB	172	2015-06-01 Jan Beulich <jbeulich@suse.com>
	173
	174	* i386-tbl.h: Regenerate.
	175
3a8547d2 JB	176	2015-06-01 Jan Beulich <jbeulich@suse.com>
	177
	178	* i386-dis.c (print_insn): Swap rounding mode specifier and
	179	general purpose register in Intel mode.
	180
015c54d5 JB	181	2015-06-01 Jan Beulich <jbeulich@suse.com>
	182
	183	* i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
	184	* i386-tbl.h: Regenerate.
	185
071f0063 L	186	2015-05-18 H.J. Lu <hongjiu.lu@intel.com>
	187
	188	* i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
	189	* i386-init.h: Regenerated.
	190
5db04b09 L	191	2015-05-15 H.J. Lu <hongjiu.lu@intel.com>
	192
	193	PR binutis/18386
	194	* i386-dis.c: Add comments for '@'.
	195	(x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
	196	(enum x86_64_isa): New.
	197	(isa64): Likewise.
	198	(print_i386_disassembler_options): Add amd64 and intel64.
	199	(print_insn): Handle amd64 and intel64.
	200	(putop): Handle '@'.
	201	(OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
	202	* i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
	203	* i386-opc.h (AMD64): New.
	204	(CpuIntel64): Likewise.
	205	(i386_cpu_flags): Add cpuamd64 and cpuintel64.
	206	* i386-opc.tbl: Add direct call/jmp with Disp16\|Disp32 for AMD64.
	207	Mark direct call/jmp without Disp16\|Disp32 as Intel64.
	208	* i386-init.h: Regenerated.
	209	* i386-tbl.h: Likewise.
	210
4bc0608a PB	211	2015-05-14 Peter Bergner <bergner@vnet.ibm.com>
	212
	213	* ppc-opc.c (IH) New define.
	214	(powerpc_opcodes) <wait>: Do not enable for POWER7.
	215	<tlbie>: Add RS operand for POWER7.
	216	<slbia>: Add IH operand for POWER6.
	217
70cead07 L	218	2015-05-11 H.J. Lu <hongjiu.lu@intel.com>
	219
	220	* opcodes/i386-opc.tbl (call): Remove Disp16\|Disp32 from 64-bit
	221	direct branch.
	222	(jmp): Likewise.
	223	* i386-tbl.h: Regenerated.
	224
7b6d09fb L	225	2015-05-11 H.J. Lu <hongjiu.lu@intel.com>
	226
	227	* configure.ac: Support bfd_iamcu_arch.
	228	* disassemble.c (disassembler): Support bfd_iamcu_arch.
	229	* i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
	230	CPU_IAMCU_COMPAT_FLAGS.
	231	(cpu_flags): Add CpuIAMCU.
	232	* i386-opc.h (CpuIAMCU): New.
	233	(i386_cpu_flags): Add cpuiamcu.
	234	* configure: Regenerated.
	235	* i386-init.h: Likewise.
	236	* i386-tbl.h: Likewise.
	237
31955f99 L	238	2015-05-08 H.J. Lu <hongjiu.lu@intel.com>
	239
	240	PR binutis/18386
	241	* i386-dis.c (X86_64_E8): New.
	242	(X86_64_E9): Likewise.
	243	Update comments on 'T', 'U', 'V'. Add comments for '^'.
	244	(dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
	245	(x86_64_table): Add X86_64_E8 and X86_64_E9.
	246	(mod_table): Replace {T\|} with ^ on Jcall/Jmp.
	247	(putop): Handle '^'.
	248	(OP_J): Ignore the operand size prefix in 64-bit. Don't check
	249	REX_W.
	250
0952813b DD	251	2015-04-30 DJ Delorie <dj@redhat.com>
	252
	253	* disassemble.c (disassembler): Choose suitable disassembler based
	254	on E_ABI.
	255	* rl78-decode.opc (rl78_decode_opcode): Take ISA parameter. Use
	256	it to decode mul/div insns.
	257	* rl78-decode.c: Regenerate.
	258	* rl78-dis.c (print_insn_rl78): Rename to...
	259	(print_insn_rl78_common): ...this, take ISA parameter.
	260	(print_insn_rl78): New.
	261	(print_insn_rl78_g10): New.
	262	(print_insn_rl78_g13): New.
	263	(print_insn_rl78_g14): New.
	264	(rl78_get_disassembler): New.
	265
f9d3ecaa NC	266	2015-04-29 Nick Clifton <nickc@redhat.com>
	267
	268	* po/fr.po: Updated French translation.
	269
4fff86c5 PB	270	2015-04-27 Peter Bergner <bergner@vnet.ibm.com>
	271
	272	* ppc-opc.c (DCBT_EO): New define.
	273	(powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
	274	<lharx>: Likewise.
	275	<stbcx.>: Likewise.
	276	<sthcx.>: Likewise.
	277	<waitrsv>: Do not enable for POWER7 and later.
	278	<waitimpl>: Likewise.
	279	<dcbt>: Default to the two operand form of the instruction for all
	280	"old" cpus. For "new" cpus, use the operand ordering that matches
	281	whether the cpu is server or embedded.
	282	<dcbtst>: Likewise.
	283
3b78cfe1 AK	284	2015-04-27 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
	285
	286	* s390-opc.c: New instruction type VV0UU2.
	287	* s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
	288	and WFC.
	289
04d824a4 JB	290	2015-04-23 Jan Beulich <jbeulich@suse.com>
	291
	292	* i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
	293	* i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
	294	vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
	295	(vfpclasspd, vfpclassps): Add %XZ.
	296
09708981 L	297	2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
	298
	299	* i386-dis.c (PREFIX_UD_SHIFT): Removed.
	300	(PREFIX_UD_REPZ): Likewise.
	301	(PREFIX_UD_REPNZ): Likewise.
	302	(PREFIX_UD_DATA): Likewise.
	303	(PREFIX_UD_ADDR): Likewise.
	304	(PREFIX_UD_LOCK): Likewise.
	305
3888916d L	306	2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
	307
	308	* i386-dis.c (prefix_requirement): Removed.
	309	(print_insn): Don't set prefix_requirement. Check
	310	dp->prefix_requirement instead of prefix_requirement.
	311
f24bcbaa L	312	2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
	313
	314	PR binutils/17898
	315	* i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
	316	(PREFIX_MOD_0_0FC7_REG_6): This.
	317	(PREFIX_MOD_3_0FC7_REG_6): New.
	318	(PREFIX_MOD_3_0FC7_REG_7): Likewise.
	319	(prefix_table): Replace PREFIX_0FC7_REG_6 with
	320	PREFIX_MOD_0_0FC7_REG_6. Add PREFIX_MOD_3_0FC7_REG_6 and
	321	PREFIX_MOD_3_0FC7_REG_7.
	322	(mod_table): Replace PREFIX_0FC7_REG_6 with
	323	PREFIX_MOD_0_0FC7_REG_6. Use PREFIX_MOD_3_0FC7_REG_6 and
	324	PREFIX_MOD_3_0FC7_REG_7.
	325
507bd325 L	326	2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
	327
	328	* i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
	329	(PREFIX_MANDATORY_REPNZ): Likewise.
	330	(PREFIX_MANDATORY_DATA): Likewise.
	331	(PREFIX_MANDATORY_ADDR): Likewise.
	332	(PREFIX_MANDATORY_LOCK): Likewise.
	333	(PREFIX_MANDATORY): Likewise.
	334	(PREFIX_UD_SHIFT): Set to 8
	335	(PREFIX_UD_REPZ): Updated.
	336	(PREFIX_UD_REPNZ): Likewise.
	337	(PREFIX_UD_DATA): Likewise.
	338	(PREFIX_UD_ADDR): Likewise.
	339	(PREFIX_UD_LOCK): Likewise.
	340	(PREFIX_IGNORED_SHIFT): New.
	341	(PREFIX_IGNORED_REPZ): Likewise.
	342	(PREFIX_IGNORED_REPNZ): Likewise.
	343	(PREFIX_IGNORED_DATA): Likewise.
	344	(PREFIX_IGNORED_ADDR): Likewise.
	345	(PREFIX_IGNORED_LOCK): Likewise.
	346	(PREFIX_OPCODE): Likewise.
	347	(PREFIX_IGNORED): Likewise.
	348	(Bad_Opcode): Replace PREFIX_MANDATORY with 0.
	349	(dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
	350	(three_byte_table): Likewise.
	351	(mod_table): Likewise.
	352	(mandatory_prefix): Renamed to ...
	353	(prefix_requirement): This.
	354	(prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
	355	Update PREFIX_90 entry.
	356	(get_valid_dis386): Check prefix_requirement to see if a prefix
	357	should be ignored.
	358	(print_insn): Replace mandatory_prefix with prefix_requirement.
	359
f0fba320 RL	360	2015-04-15 Renlin Li <renlin.li@arm.com>
	361
	362	* arm-dis.c (thumb32_opcodes): Define 'D' format control code,
	363	use it for ssat and ssat16.
	364	(print_insn_thumb32): Add handle case for 'D' control code.
	365
bf890a93 IT	366	2015-04-06 Ilya Tocar <ilya.tocar@intel.com>
	367	H.J. Lu <hongjiu.lu@intel.com>
	368
	369	* i386-dis-evex.h (evex_table): Fill prefix_requirement field.
	370	* i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
	371	PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
	372	PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
	373	PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
	374	(Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
	375	Fill prefix_requirement field.
	376	(struct dis386): Add prefix_requirement field.
	377	(dis386): Fill prefix_requirement field.
	378	(dis386_twobyte): Ditto.
	379	(twobyte_has_mandatory_prefix_: Remove.
	380	(reg_table): Fill prefix_requirement field.
	381	(prefix_table): Ditto.
	382	(x86_64_table): Ditto.
	383	(three_byte_table): Ditto.
	384	(xop_table): Ditto.
	385	(vex_table): Ditto.
	386	(vex_len_table): Ditto.
	387	(vex_w_table): Ditto.
	388	(mod_table): Ditto.
	389	(bad_opcode): Ditto.
	390	(print_insn): Use prefix_requirement.
	391	(FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
	392	FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
	393	(float_reg): Ditto.
	394
2f783c1f MF	395	2015-03-30 Mike Frysinger <vapier@gentoo.org>
	396
	397	* d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
	398
b9d94d62 L	399	2015-03-29 H.J. Lu <hongjiu.lu@intel.com>
	400
	401	* Makefile.in: Regenerated.
	402
27c49e9a AB	403	2015-03-25 Anton Blanchard <anton@samba.org>
	404
	405	* ppc-dis.c (disassemble_init_powerpc): Only initialise
	406	powerpc_opcd_indices and vle_opcd_indices once.
	407
c4e676f1 AB	408	2015-03-25 Anton Blanchard <anton@samba.org>
	409
	410	* ppc-opc.c (powerpc_opcodes): Add slbfee.
	411
823d2571 TG	412	2015-03-24 Terry Guo <terry.guo@arm.com>
	413
	414	* arm-dis.c (opcode32): Updated to use new arm feature struct.
	415	(opcode16): Likewise.
	416	(coprocessor_opcodes): Replace bit with feature struct.
	417	(neon_opcodes): Likewise.
	418	(arm_opcodes): Likewise.
	419	(thumb_opcodes): Likewise.
	420	(thumb32_opcodes): Likewise.
	421	(print_insn_coprocessor): Likewise.
	422	(print_insn_arm): Likewise.
	423	(select_arm_features): Follow new feature struct.
	424
029f3522 GG	425	2015-03-17 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
	426
	427	* i386-dis.c (rm_table): Add clzero.
	428	* i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
	429	Add CPU_CLZERO_FLAGS.
	430	(cpu_flags): Add CpuCLZERO.
	431	* i386-opc.h: Add CpuCLZERO.
	432	* i386-opc.tbl: Add clzero.
	433	* i386-init.h: Re-generated.
	434	* i386-tbl.h: Re-generated.
	435
6914869a AB	436	2015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
	437
	438	* mips-opc.c (decode_mips_operand): Fix constraint issues
	439	with u and y operands.
	440
21e20815 AB	441	2015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
	442
	443	* mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
	444
6b1d7593 AK	445	2015-03-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
	446
	447	* s390-opc.c: Add new IBM z13 instructions.
	448	* s390-opc.txt: Likewise.
	449
c8f89a34 JW	450	2015-03-10 Renlin Li <renlin.li@arm.com>
	451
	452	* aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
	453	stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
	454	related alias.
	455	* aarch64-asm-2.c: Regenerate.
	456	* aarch64-dis-2.c: Likewise.
	457	* aarch64-opc-2.c: Likewise.
	458
d8282f0e JW	459	2015-03-03 Jiong Wang <jiong.wang@arm.com>
	460
	461	* arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
	462
ac994365 OE	463	2015-02-25 Oleg Endo <olegendo@gcc.gnu.org>
	464
	465	* sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
	466	arch_sh_up.
	467	(pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
	468	arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
	469
fd63f640 V	470	2015-02-23 Vinay <Vinay.G@kpit.com>
	471
	472	* rl78-decode.opc (MOV): Added space between two operands for
	473	'mov' instruction in index addressing mode.
	474	* rl78-decode.c: Regenerate.
	475
f63c1776 PA	476	2015-02-19 Pedro Alves <palves@redhat.com>
	477
	478	* microblaze-dis.h [__cplusplus]: Wrap in extern "C".
	479
07774fcc PA	480	2015-02-10 Pedro Alves <palves@redhat.com>
	481	Tom Tromey <tromey@redhat.com>
	482
	483	* microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
	484	microblaze_and, microblaze_xor.
	485	* microblaze-opc.h (opcodes): Adjust.
	486
3f8107ab AM	487	2015-01-28 James Bowman <james.bowman@ftdichip.com>
	488
	489	* Makefile.am: Add FT32 files.
	490	* configure.ac: Handle FT32.
	491	* disassemble.c (disassembler): Call print_insn_ft32.
	492	* ft32-dis.c: New file.
	493	* ft32-opc.c: New file.
	494	* Makefile.in: Regenerate.
	495	* configure: Regenerate.
	496	* po/POTFILES.in: Regenerate.
	497
e5fe4957 KLC	498	2015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
	499
	500	* nds32-asm.c (keyword_sr): Add new system registers.
	501
1e2e8c52 AK	502	2015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
	503
	504	* s390-dis.c (s390_extract_operand): Support vector register
	505	operands.
	506	(s390_print_insn_with_opcode): Support new operands types and add
	507	new handling of optional operands.
	508	* s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
	509	and include opcode/s390.h instead.
	510	(struct op_struct): New field `flags'.
	511	(insertOpcode, insertExpandedMnemonic): New parameter `flags'.
	512	(dumpTable): Dump flags.
	513	(main): Parse flags from the s390-opc.txt file. Add z13 as cpu
	514	string.
	515	* s390-opc.c: Add new operands types, instruction formats, and
	516	instruction masks.
	517	(s390_opformats): Add new formats for .insn.
	518	* s390-opc.txt: Add new instructions.
	519
b90efa5b	520	2015-01-01 Alan Modra <amodra@gmail.com>
bffb6004	521
b90efa5b	522	Update year range in copyright notice of all files.
bffb6004	523
b90efa5b	524	For older changes see ChangeLog-2014
252b5132	525	\f
b90efa5b	526	Copyright (C) 2015 Free Software Foundation, Inc.
752937aa NC	527
	528	Copying and distribution of this file, with or without modification,
	529	are permitted in any medium without royalty provided the copyright
	530	notice and this notice are preserved.
	531
252b5132	532	Local Variables:
2f6d2f85 NC	533	mode: change-log
	534	left-margin: 8
	535	fill-column: 74
252b5132 RH	536	version-control: never
252b5132 RH	537	End: