projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
xtensa message pluralization
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
52eab766
AB		 12017-11-07 Andrew Burgess <andrew.burgess@embecosm.com>
2
3 * arc-nps400-tbl.h: Change incorrect use of NONE to MISC.
4
6003e27e
AM		 52017-11-07 Alan Modra <amodra@gmail.com>
6
7 * opintl.h: Formatting, comment fixes.
8 (gettext, ngettext): Redefine when ENABLE_NLS.
9 (ngettext, dngettext, dcngettext): Define when !ENABLE_NLS.
10 (_): Define using gettext.
11 (textdomain, bindtextdomain): Use safer "do nothing".
12
fdddd290 132017-11-03 Claudiu Zissulescu <claziss@synopsys.com>
14
15 * arc-dis.c (print_hex): New variable.
16 (parse_option): Check for hex option.
17 (print_insn_arc): Use hexadecimal representation for short
18 immediate values when requested.
19 (print_arc_disassembler_options): Add hex option to the list.
20
3334eba7 212017-11-03 Claudiu Zissulescu <claziss@synopsys.com>
22
23 * arc-tbl.h (abss, abssh, adc, adcs, adds, aslacc, asls, aslsacc)
24 (asrs, asrsr, cbflyhf0r, cbflyhf1r, cmacchfr, cmacchnfr, cmachfr)
25 (cmachnfr, cmpychfr, cmpychnfr, cmpyhfmr, cmpyhfr, cmpyhnfr, divf)
26 (dmachbl, dmachbm, dmachf, dmachfr, dmacwhf, dmpyhbl, dmpyhbm)
27 (dmpyhf, dmpyhfr, dmpyhwf, dmpywhf, dsync, flagacc, getacc, macdf)
28 (macf, macfr, macwhfl, macwhflr, macwhfm, macwhfmr, macwhkl)
29 (macwhkul, macwhl, macwhul, mpydf, mpyf, mpyfr, mpywhfl, mpywhflr)
30 (mpywhfm, mpywhfmr, mpywhkl, mpywhkul, mpywhl, mpywhul, msubdf)
31 (msubf, msubfr, msubwhfl, msubwhflr, msubwhfm, msubwhfmr, mul64)
32 (negs, negsh, normacc, qmachf, qmpyh, qmpyhf, rndh, satf, sath)
33 (sbcs, setacc, sflag, sqrt, sqrtf, subs, swi_s, vabs2h, vabss2h)
34 (vadd4b, vadds2, vadds2h, vadds4h, vaddsubs, vaddsubs2h)
35 (vaddsubs4h, valgn2h, vasl2h, vasls2h, vasr2h, vasrs2h, vasrsr2h)
36 (vext2bhl, vext2bhlf, vext2bhm, vext2bhmf, vlsr2h, vmac2hf)
37 (vmac2hfr, vmac2hnfr, vmax2h, vmin2h, vmpy2h, vmpy2hf, vmpy2hfr)
38 (vmpy2hwf, vmsub2hf, vmsub2hfr, vmsub2hnfr, vneg2h, vnegs2h)
39 (vnorm2h, vpack2hbl, vpack2hblf, vpack2hbm, vpack2hbmf, vpack2hl)
40 (vpack2hm, vperm, vrep2hl, vrep2hm, vsext2bhl, vsext2bhm, vsub4b)
41 (vsubadds, vsubadds2h, vsubadds4h, vsubs2, vsubs2h, vsubs4h):
42 Changed opcodes.
43 (prealloc, prefetch*): Place them before ld instruction.
44 * arc-opc.c (skip_this_opcode): Add ARITH class.
45
e5d70d6b
AM		 462017-10-25 Alan Modra <amodra@gmail.com>
47
48 PR 22348
49 * cr16-dis.c (cr16_cinvs, instruction, cr16_currInsn): Make static.
50 (cr16_words, cr16_allWords, processing_argument_number): Likewise.
51 (imm4flag, size_changed): Likewise.
52 * crx-dis.c (crx_cinvs, NUMCINVS, instruction, currInsn): Likewise.
53 (words, allWords, processing_argument_number): Likewise.
54 (cst4flag, size_changed): Likewise.
55 * crx-opc.c (crx_cst4_map): Rename from cst4_map.
56 (crx_cst4_maps): Rename from cst4_maps.
57 (crx_no_op_insn): Rename from no_op_insn.
58
63a25ea0
AW		 592017-10-24 Andrew Waterman <andrew@sifive.com>
60
61 * riscv-opc.c (match_c_addi16sp) : New function.
62 (match_c_addi4spn): New function.
63 (match_c_lui): Don't allow 0-immediate encodings.
64 (riscv_opcodes) <addi>: Use the above functions.
65 <add>: Likewise.
66 <c.addi4spn>: Likewise.
67 <c.addi16sp>: Likewise.
68
fe4e2a3c
IT		 692017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
70
71 * i386-init.h: Regenerate
72 * i386-tbl.h: Likewise
73
2739ef6d
IT		 742017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
75
76 * i386-dis.c (enum): Add PREFIX_EVEX_0F3854, PREFIX_EVEX_0F388F.
77 (enum): Add EVEX_W_0F3854_P_2.
78 * i386-dis-evex.h (evex_table): Updated.
79 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BITALG,
80 CPU_ANY_AVX512_BITALG_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
81 (cpu_flags): Add CpuAVX512_BITALG.
82 * i386-opc.h (enum): Add CpuAVX512_BITALG.
83 (i386_cpu_flags): Add cpuavx512_bitalg..
84 * i386-opc.tbl: Add Intel AVX512_BITALG instructions.
85 * i386-init.h: Regenerate.
86 * i386-tbl.h: Likewise.
87
882017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
89
90 * i386-dis.c (enum): Add PREFIX_EVEX_0F3850, PREFIX_EVEX_0F3851.
91 * i386-dis-evex.h (evex_table): Updated.
92 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VNNI,
93 CPU_ANY_AVX512_VNNI_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
94 (cpu_flags): Add CpuAVX512_VNNI.
95 * i386-opc.h (enum): Add CpuAVX512_VNNI.
96 (i386_cpu_flags): Add cpuavx512_vnni.
97 * i386-opc.tbl Add Intel AVX512_VNNI instructions.
98 * i386-init.h: Regenerate.
99 * i386-tbl.h: Likewise.
100
1012017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
102
103 * i386-dis.c (enum): Add PREFIX_EVEX_0F3A44.
104 (enum): Remove VEX_LEN_0F3A44_P_2.
105 (vex_len_table): Ditto.
106 (enum): Remove VEX_W_0F3A44_P_2.
107 (vew_w_table): Ditto.
108 (prefix_table): Adjust instructions (see prefixes above).
109 * i386-dis-evex.h (evex_table):
110 Add new instructions (see prefixes above).
111 * i386-gen.c (cpu_flag_init): Add VPCLMULQDQ.
112 (bitfield_cpu_flags): Ditto.
113 * i386-opc.h (enum): Ditto.
114 (i386_cpu_flags): Ditto.
115 (CpuUnused): Comment out to avoid zero-width field problem.
116 * i386-opc.tbl (vpclmulqdq): New instruction.
117 * i386-init.h: Regenerate.
118 * i386-tbl.h: Ditto.
119
1202017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
121
122 * i386-dis.c (enum): Add PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD,
123 PREFIX_EVEX_0F38DE, PREFIX_EVEX_0F38DF.
124 (enum): Remove VEX_LEN_0F38DC_P_2, VEX_LEN_0F38DD_P_2,
125 VEX_LEN_0F38DE_P_2, VEX_LEN_0F38DF_P_2.
126 (vex_len_table): Ditto.
127 (enum): Remove VEX_W_0F38DC_P_2, VEX_W_0F38DD_P_2,
128 VEX_W_0F38DE_P_2, VEX_W_0F38DF_P_2.
129 (vew_w_table): Ditto.
130 (prefix_table): Adjust instructions (see prefixes above).
131 * i386-dis-evex.h (evex_table):
132 Add new instructions (see prefixes above).
133 * i386-gen.c (cpu_flag_init): Add VAES.
134 (bitfield_cpu_flags): Ditto.
135 * i386-opc.h (enum): Ditto.
136 (i386_cpu_flags): Ditto.
137 * i386-opc.tbl (vaes{enc,dec}{last,}): New instructions.
138 * i386-init.h: Regenerate.
139 * i386-tbl.h: Ditto.
140
1412017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
142
143 * i386-dis.c (enum): Add PREFIX_0F38CF, PREFIX_0F3ACE, PREFIX_0F3ACF,
144 PREFIX_VEX_0F38CF, PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF,
145 PREFIX_EVEX_0F38CF, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF.
146 (enum): Add VEX_W_0F38CF_P_2, VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2,
147 EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2.
148 (prefix_table): Updated (see prefixes above).
149 (three_byte_table): Likewise.
150 (vex_w_table): Likewise.
151 * i386-dis-evex.h: Likewise.
152 * i386-gen.c (cpu_flag_init): Add CPU_GFNI_FLAGS, CpuGFNI.
153 (cpu_flags): Add CpuGFNI.
154 * i386-opc.h (enum): Add CpuGFNI.
155 (i386_cpu_flags): Add cpugfni.
156 * i386-opc.tbl: Add Intel GFNI instructions.
157 * i386-init.h: Regenerate.
158 * i386-tbl.h: Likewise.
159
1602017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
161
162 * i386-dis.c (enum): Add b_scalar_mode, w_scalar_mode.
163 Define EXbScalar and EXwScalar for OP_EX.
164 (enum): Add PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863,
165 PREFIX_EVEX_0F3870, PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3872,
166 PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
167 PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73.
168 (enum): Add EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2,
169 EVEX_W_0F3870_P_2, EVEX_W_0F3871_P_2, EVEX_W_0F3872_P_2,
170 EVEX_W_0F3873_P_2, EVEX_W_0F3A70_P_2, EVEX_W_0F3A71_P_2,
171 EVEX_W_0F3A72_P_2, EVEX_W_0F3A73_P_2.
172 (intel_operand_size): Handle b_scalar_mode and w_scalar_mode.
173 (OP_E_memory): Likewise.
174 * i386-dis-evex.h: Updated.
175 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VBMI2,
176 CPU_ANY_AVX512_VBMI2_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
177 (cpu_flags): Add CpuAVX512_VBMI2.
178 * i386-opc.h (enum): Add CpuAVX512_VBMI2.
179 (i386_cpu_flags): Add cpuavx512_vbmi2.
180 * i386-opc.tbl: Add Intel AVX512_VBMI2 instructions.
181 * i386-init.h: Regenerate.
182 * i386-tbl.h: Likewise.
183
2a6969e1
EB		 1842017-10-18 Eric Botcazou <ebotcazou@adacore.com>
185
186 * visium-dis.c (disassem_class1) <case 0>: Print the operands.
187
3b4b0a62
JB		 1882017-10-12 James Bowman <james.bowman@ftdichip.com>
189
190 * ft32-dis.c (print_insn_ft32): Replace FT32_FLD_K8 with K15.
191 * ft32-opc.c (ft32_opc_info): Replace FT32_FLD_K8 with
192 K15. Add jmpix pattern.
193
8e464506
AK		 1942017-10-09 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
195
196 * s390-opc.txt (prno, tpei, irbm): New instructions added.
197
ee6767da
AK		 1982017-10-09 Heiko Carstens <heiko.carstens@de.ibm.com>
199
200 * s390-opc.c (INSTR_SI_RD): New macro.
201 (INSTR_S_RD): Adjust example instruction.
202 * s390-opc.txt (lpsw, ssm, ts): Change S_RD instruction format to
203 SI_RD.
204
d2e6c9a3
AF		 2052017-10-01 Alexander Fedotov <alfedotov@gmail.com>
206
207 * ppc-opc.c (vle_opcodes): Add e_lmvsprw, e_lmvgprw,
208 e_lmvsrrw, e_lmvcsrrw and e_lmvcsrrw as official mnemonics for
209 VLE multimple load/store instructions. Old e_ldm* variants are
210 kept as aliases.
211 Add missing e_lmvmcsrrw and e_stmvmcsrrw.
212
8e43602e
NC		 2132017-09-27 Nick Clifton <nickc@redhat.com>
214
215 PR 22179
216 * riscv-opc.c (riscv_opcodes): Add fmv.x.w and fmv.w.x as the new
217 names for the fmv.x.s and fmv.s.x instructions respectively.
218
58a0b827
NC		 2192017-09-26 do <do@nerilex.org>
220
221 PR 22123
222 * m68k-opc.c (m68k_opcodes): Allow macw and macl instructions to
223 be used on CPUs that have emacs support.
224
57a024f4
SDJ		 2252017-09-21 Sergio Durigan Junior <sergiodj@redhat.com>
226
227 * aarch64-opc.c (expand_fp_imm): Initialize 'imm'.
228
4ec521f2
KLC		 2292017-09-09 Kamil Rytarowski <n54@gmx.com>
230
231 * nds32-asm.c: Rename __BIT() to N32_BIT().
232 * nds32-asm.h: Likewise.
233 * nds32-dis.c: Likewise.
234
4e9ac44a
L		 2352017-09-09 H.J. Lu <hongjiu.lu@intel.com>
236
237 * i386-dis.c (last_active_prefix): Removed.
238 (ckprefix): Don't set last_active_prefix.
239 (NOTRACK_Fixup): Don't check last_active_prefix.
240
b55f3386
NC		 2412017-08-31 Nick Clifton <nickc@redhat.com>
242
243 * po/fr.po: Updated French translation.
244
59e8523b
JB		 2452017-08-31 James Bowman <james.bowman@ftdichip.com>
246
247 * ft32-dis.c (print_insn_ft32): Correct display of non-address
248 fields.
249
74081948
AF		 2502017-08-23 Alexander Fedotov <alexander.fedotov@nxp.com>
251 Edmar Wienskoski <edmar.wienskoski@nxp.com>
252
253 * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_SPE2 and
254 PPC_OPCODE_EFS2 flag to "e200z4" entry.
255 New entries efs2 and spe2.
256 Add PPC_OPCODE_SPE2 and PPC_OPCODE_EFS2 flag to "vle" entry.
257 (SPE2_OPCD_SEGS): New macro.
258 (spe2_opcd_indices): New.
259 (disassemble_init_powerpc): Handle SPE2 opcodes.
260 (lookup_spe2): New function.
261 (print_insn_powerpc): call lookup_spe2.
262 * ppc-opc.c (insert_evuimm1_ex0): New function.
263 (extract_evuimm1_ex0): Likewise.
264 (insert_evuimm_lt8): Likewise.
265 (extract_evuimm_lt8): Likewise.
266 (insert_off_spe2): Likewise.
267 (extract_off_spe2): Likewise.
268 (insert_Ddd): Likewise.
269 (extract_Ddd): Likewise.
270 (DD): New operand.
271 (EVUIMM_LT8): Likewise.
272 (EVUIMM_LT16): Adjust.
273 (MMMM): New operand.
274 (EVUIMM_1): Likewise.
275 (EVUIMM_1_EX0): Likewise.
276 (EVUIMM_2): Adjust.
277 (NNN): New operand.
278 (VX_OFF_SPE2): Likewise.
279 (BBB): Likewise.
280 (DDD): Likewise.
281 (VX_MASK_DDD): New mask.
282 (HH): New operand.
283 (VX_RA_CONST): New macro.
284 (VX_RA_CONST_MASK): Likewise.
285 (VX_RB_CONST): Likewise.
286 (VX_RB_CONST_MASK): Likewise.
287 (VX_OFF_SPE2_MASK): Likewise.
288 (VX_SPE_CRFD): Likewise.
289 (VX_SPE_CRFD_MASK VX): Likewise.
290 (VX_SPE2_CLR): Likewise.
291 (VX_SPE2_CLR_MASK): Likewise.
292 (VX_SPE2_SPLATB): Likewise.
293 (VX_SPE2_SPLATB_MASK): Likewise.
294 (VX_SPE2_OCTET): Likewise.
295 (VX_SPE2_OCTET_MASK): Likewise.
296 (VX_SPE2_DDHH): Likewise.
297 (VX_SPE2_DDHH_MASK): Likewise.
298 (VX_SPE2_HH): Likewise.
299 (VX_SPE2_HH_MASK): Likewise.
300 (VX_SPE2_EVMAR): Likewise.
301 (VX_SPE2_EVMAR_MASK): Likewise.
302 (PPCSPE2): Likewise.
303 (PPCEFS2): Likewise.
304 (vle_opcodes): Add EFS2 and some missing SPE opcodes.
305 (powerpc_macros): Map old SPE instructions have new names
306 with the same opcodes. Add SPE2 instructions which just are
307 mapped to SPE2.
308 (spe2_opcodes): Add SPE2 opcodes.
309
b80c7270
AM		 3102017-08-23 Alan Modra <amodra@gmail.com>
311
312 * ppc-opc.c: Formatting and comment fixes. Move insert and
313 extract functions earlier, deleting forward declarations.
314 (insert_nbi, insert_raq, insert_rbx): Expand use of RT_MASK and
315 RA_MASK.
316
67d888f5
PD		 3172017-08-22 Palmer Dabbelt <palmer@dabbelt.com>
318
319 * riscv-opc.c (riscv_opcodes): Mark "c.nop" as an alias.
320
e3c2f928
AF		 3212017-08-21 Alexander Fedotov <alexander.fedotov@nxp.com>
322 Edmar Wienskoski <edmar.wienskoski@nxp.com>
323
324 * ppc-opc.c (insert_evuimm2_ex0): New function.
325 (extract_evuimm2_ex0): Likewise.
326 (insert_evuimm4_ex0): Likewise.
327 (extract_evuimm4_ex0): Likewise.
328 (insert_evuimm8_ex0): Likewise.
329 (extract_evuimm8_ex0): Likewise.
330 (insert_evuimm_lt16): Likewise.
331 (extract_evuimm_lt16): Likewise.
332 (insert_rD_rS_even): Likewise.
333 (extract_rD_rS_even): Likewise.
334 (insert_off_lsp): Likewise.
335 (extract_off_lsp): Likewise.
336 (RD_EVEN): New operand.
337 (RS_EVEN): Likewise.
338 (RSQ): Adjust.
339 (EVUIMM_LT16): New operand.
340 (HTM_SI): Adjust.
341 (EVUIMM_2_EX0): New operand.
342 (EVUIMM_4): Adjust.
343 (EVUIMM_4_EX0): New operand.
344 (EVUIMM_8): Adjust.
345 (EVUIMM_8_EX0): New operand.
346 (WS): Adjust.
347 (VX_OFF): New operand.
348 (VX_LSP): New macro.
349 (VX_LSP_MASK): Likewise.
350 (VX_LSP_OFF_MASK): Likewise.
351 (PPC_OPCODE_LSP): Likewise.
352 (vle_opcodes): Add LSP opcodes.
353 * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_LSP flag to "vle" entry.
354
cc4a945a
JW		 3552017-08-09 Jiong Wang <jiong.wang@arm.com>
356
357 * arm-dis.c (thumb32_opcodes): Use format 'R' instead of 'S' for
358 register operands in CRC instructions.
359 (print_insn_thumb32): Remove "<bitfield>S" support. Updated the
360 comments.
361
b28b8b5e
L		 3622017-08-07 H.J. Lu <hongjiu.lu@intel.com>
363
364 * disassemble.c (disassembler): Mark big and mach with
365 ATTRIBUTE_UNUSED.
366
e347efc3
MR		 3672017-08-07 Maciej W. Rozycki <macro@imgtec.com>
368
369 * disassemble.c (disassembler): Remove arch/mach/endian
370 assertions.
371
7cbc739c
NC		 3722017-07-25 Nick Clifton <nickc@redhat.com>
373
374 PR 21739
375 * arc-opc.c (insert_rhv2): Use lower case first letter in error
376 message.
377 (insert_r0): Likewise.
378 (insert_r1): Likewise.
379 (insert_r2): Likewise.
380 (insert_r3): Likewise.
381 (insert_sp): Likewise.
382 (insert_gp): Likewise.
383 (insert_pcl): Likewise.
384 (insert_blink): Likewise.
385 (insert_ilink1): Likewise.
386 (insert_ilink2): Likewise.
387 (insert_ras): Likewise.
388 (insert_rbs): Likewise.
389 (insert_rcs): Likewise.
390 (insert_simm3s): Likewise.
391 (insert_rrange): Likewise.
392 (insert_r13el): Likewise.
393 (insert_fpel): Likewise.
394 (insert_blinkel): Likewise.
395 (insert_pclel): Likewise.
396 (insert_nps_bitop_size_2b): Likewise.
397 (insert_nps_imm_offset): Likewise.
398 (insert_nps_imm_entry): Likewise.
399 (insert_nps_size_16bit): Likewise.
400 (insert_nps_##NAME##_pos): Likewise.
401 (insert_nps_##NAME): Likewise.
402 (insert_nps_bitop_ins_ext): Likewise.
403 (insert_nps_##NAME): Likewise.
404 (insert_nps_min_hofs): Likewise.
405 (insert_nps_##NAME): Likewise.
406 (insert_nps_rbdouble_64): Likewise.
407 (insert_nps_misc_imm_offset): Likewise.
408 * riscv-dis.c (print_riscv_disassembler_options): Fix typo in
409 option description.
410
7684e580
JW		 4112017-07-24 Laurent Desnogues <laurent.desnogues@arm.com>
412 Jiong Wang <jiong.wang@arm.com>
413
414 * aarch64-gen.c (print_decision_tree_1): Reverse the index of PATTERN to
415 correct the print.
416 * aarch64-dis-2.c: Regenerated.
417
47826cdb
AK		 4182017-07-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
419
420 * s390-mkopc.c (main): Enable z14 as CPU string in the opcode
421 table.
422
2d2dbad0
NC		 4232017-07-20 Nick Clifton <nickc@redhat.com>
424
425 * po/de.po: Updated German translation.
426
70b448ba 4272017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
428
429 * arc-regs.h (sec_stat): New aux register.
430 (aux_kernel_sp): Likewise.
431 (aux_sec_u_sp): Likewise.
432 (aux_sec_k_sp): Likewise.
433 (sec_vecbase_build): Likewise.
434 (nsc_table_top): Likewise.
435 (nsc_table_base): Likewise.
436 (ersec_stat): Likewise.
437 (aux_sec_except): Likewise.
438
7179e0e6
CZ		 4392017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
440
441 * arc-opc.c (extract_uimm12_20): New function.
442 (UIMM12_20): New operand.
443 (SIMM3_5_S): Adjust.
444 * arc-tbl.h (sjli): Add new instruction.
445
684d5a10
JEM		 4462017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
447 John Eric Martin <John.Martin@emmicro-us.com>
448
449 * arc-opc.c (UIMM10_6_S_JLIOFF): Define.
450 (UIMM3_23): Adjust accordingly.
451 * arc-regs.h: Add/correct jli_base register.
452 * arc-tbl.h (jli_s): Likewise.
453
de194d85
YC		 4542017-07-18 Nick Clifton <nickc@redhat.com>
455
456 PR 21775
457 * aarch64-opc.c: Fix spelling typos.
458 * i386-dis.c: Likewise.
459
0f6329bd
RB		 4602017-07-14 Ravi Bangoria <ravi.bangoria@linux.vnet.ibm.com>
461
462 * dis-buf.c (buffer_read_memory): Change type of end_addr_offset,
463 max_addr_offset and octets variables to size_t.
464
429d795d
AM		 4652017-07-12 Alan Modra <amodra@gmail.com>
466
467 * po/da.po: Update from translationproject.org/latest/opcodes/.
468 * po/de.po: Likewise.
469 * po/es.po: Likewise.
470 * po/fi.po: Likewise.
471 * po/fr.po: Likewise.
472 * po/id.po: Likewise.
473 * po/it.po: Likewise.
474 * po/nl.po: Likewise.
475 * po/pt_BR.po: Likewise.
476 * po/ro.po: Likewise.
477 * po/sv.po: Likewise.
478 * po/tr.po: Likewise.
479 * po/uk.po: Likewise.
480 * po/vi.po: Likewise.
481 * po/zh_CN.po: Likewise.
482
4162bb66
AM		 4832017-07-11 Yao Qi <yao.qi@linaro.org>
484 Alan Modra <amodra@gmail.com>
485
486 * cgen.sh: Mark generated files read-only.
487 * epiphany-asm.c: Regenerate.
488 * epiphany-desc.c: Regenerate.
489 * epiphany-desc.h: Regenerate.
490 * epiphany-dis.c: Regenerate.
491 * epiphany-ibld.c: Regenerate.
492 * epiphany-opc.c: Regenerate.
493 * epiphany-opc.h: Regenerate.
494 * fr30-asm.c: Regenerate.
495 * fr30-desc.c: Regenerate.
496 * fr30-desc.h: Regenerate.
497 * fr30-dis.c: Regenerate.
498 * fr30-ibld.c: Regenerate.
499 * fr30-opc.c: Regenerate.
500 * fr30-opc.h: Regenerate.
501 * frv-asm.c: Regenerate.
502 * frv-desc.c: Regenerate.
503 * frv-desc.h: Regenerate.
504 * frv-dis.c: Regenerate.
505 * frv-ibld.c: Regenerate.
506 * frv-opc.c: Regenerate.
507 * frv-opc.h: Regenerate.
508 * ip2k-asm.c: Regenerate.
509 * ip2k-desc.c: Regenerate.
510 * ip2k-desc.h: Regenerate.
511 * ip2k-dis.c: Regenerate.
512 * ip2k-ibld.c: Regenerate.
513 * ip2k-opc.c: Regenerate.
514 * ip2k-opc.h: Regenerate.
515 * iq2000-asm.c: Regenerate.
516 * iq2000-desc.c: Regenerate.
517 * iq2000-desc.h: Regenerate.
518 * iq2000-dis.c: Regenerate.
519 * iq2000-ibld.c: Regenerate.
520 * iq2000-opc.c: Regenerate.
521 * iq2000-opc.h: Regenerate.
522 * lm32-asm.c: Regenerate.
523 * lm32-desc.c: Regenerate.
524 * lm32-desc.h: Regenerate.
525 * lm32-dis.c: Regenerate.
526 * lm32-ibld.c: Regenerate.
527 * lm32-opc.c: Regenerate.
528 * lm32-opc.h: Regenerate.
529 * lm32-opinst.c: Regenerate.
530 * m32c-asm.c: Regenerate.
531 * m32c-desc.c: Regenerate.
532 * m32c-desc.h: Regenerate.
533 * m32c-dis.c: Regenerate.
534 * m32c-ibld.c: Regenerate.
535 * m32c-opc.c: Regenerate.
536 * m32c-opc.h: Regenerate.
537 * m32r-asm.c: Regenerate.
538 * m32r-desc.c: Regenerate.
539 * m32r-desc.h: Regenerate.
540 * m32r-dis.c: Regenerate.
541 * m32r-ibld.c: Regenerate.
542 * m32r-opc.c: Regenerate.
543 * m32r-opc.h: Regenerate.
544 * m32r-opinst.c: Regenerate.
545 * mep-asm.c: Regenerate.
546 * mep-desc.c: Regenerate.
547 * mep-desc.h: Regenerate.
548 * mep-dis.c: Regenerate.
549 * mep-ibld.c: Regenerate.
550 * mep-opc.c: Regenerate.
551 * mep-opc.h: Regenerate.
552 * mt-asm.c: Regenerate.
553 * mt-desc.c: Regenerate.
554 * mt-desc.h: Regenerate.
555 * mt-dis.c: Regenerate.
556 * mt-ibld.c: Regenerate.
557 * mt-opc.c: Regenerate.
558 * mt-opc.h: Regenerate.
559 * or1k-asm.c: Regenerate.
560 * or1k-desc.c: Regenerate.
561 * or1k-desc.h: Regenerate.
562 * or1k-dis.c: Regenerate.
563 * or1k-ibld.c: Regenerate.
564 * or1k-opc.c: Regenerate.
565 * or1k-opc.h: Regenerate.
566 * or1k-opinst.c: Regenerate.
567 * xc16x-asm.c: Regenerate.
568 * xc16x-desc.c: Regenerate.
569 * xc16x-desc.h: Regenerate.
570 * xc16x-dis.c: Regenerate.
571 * xc16x-ibld.c: Regenerate.
572 * xc16x-opc.c: Regenerate.
573 * xc16x-opc.h: Regenerate.
574 * xstormy16-asm.c: Regenerate.
575 * xstormy16-desc.c: Regenerate.
576 * xstormy16-desc.h: Regenerate.
577 * xstormy16-dis.c: Regenerate.
578 * xstormy16-ibld.c: Regenerate.
579 * xstormy16-opc.c: Regenerate.
580 * xstormy16-opc.h: Regenerate.
581
7639175c
AM		 5822017-07-07 Alan Modra <amodra@gmail.com>
583
584 * cgen-dis.in: Include disassemble.h, not dis-asm.h.
585 * m32c-dis.c: Regenerate.
586 * mep-dis.c: Regenerate.
587
e4bdd679
BP		 5882017-07-05 Borislav Petkov <bp@suse.de>
589
590 * i386-dis.c: Enable ModRM.reg /6 aliases.
591
60c96dbf
RR		 5922017-07-04 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
593
594 * opcodes/arm-dis.c: Support MVFR2 in disassembly
595 with vmrs and vmsr.
596
0d702cfe
TG		 5972017-07-04 Tristan Gingold <gingold@adacore.com>
598
599 * configure: Regenerate.
600
15e6ed8c
TG		 6012017-07-03 Tristan Gingold <gingold@adacore.com>
602
603 * po/opcodes.pot: Regenerate.
604
b1d3c886
MR		 6052017-06-30 Maciej W. Rozycki <macro@imgtec.com>
606
607 * mips-opc.c (mips_builtin_opcodes): Move "lsa" and "dlsa"
608 entries to the MSA ASE instruction block.
609
909b4e3d
MR		 6102017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
611 Maciej W. Rozycki <macro@imgtec.com>
612
613 * micromips-opc.c (XPA, XPAVZ): New macros.
614 (micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and
615 "mthgc0".
616
f5b2fd52
MR		 6172017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
618 Maciej W. Rozycki <macro@imgtec.com>
619
620 * micromips-opc.c (I36): New macro.
621 (micromips_opcodes): Add "eretnc".
622
9785fc2a
MR		 6232017-06-30 Maciej W. Rozycki <macro@imgtec.com>
624 Andrew Bennett <andrew.bennett@imgtec.com>
625
626 * mips-dis.c (mips_calculate_combination_ases): Handle the
627 ASE_XPA_VIRT flag.
628 (parse_mips_ase_option): New function.
629 (parse_mips_dis_option): Factor out ASE option handling to the
630 new function. Call `mips_calculate_combination_ases'.
631 * mips-opc.c (XPAVZ): New macro.
632 (mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0",
633 "mfhgc0", "mthc0" and "mthgc0".
634
60804c53
MR		 6352017-06-29 Maciej W. Rozycki <macro@imgtec.com>
636
637 * mips-dis.c (mips_calculate_combination_ases): New function.
638 (mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT
639 calculation to the new function.
640 (set_default_mips_dis_options): Call the new function.
641
2e74f9dd
AK		 6422017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
643
644 * arc-dis.c (parse_disassembler_options): Use
645 FOR_EACH_DISASSEMBLER_OPTION.
646
e1e94c49
AK		 6472017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
648
649 * arc-dis.c (parse_option): Use disassembler_options_cmp to compare
650 disassembler option strings.
651 (parse_cpu_option): Likewise.
652
65a55fbb
TC		 6532017-06-28 Tamar Christina <tamar.christina@arm.com>
654
655 * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod.
656 * aarch64-dis.c (aarch64_ext_reglane): Likewise.
657 * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New.
658 (aarch64_feature_dotprod, DOT_INSN): New.
659 (udot, sdot): New.
660 * aarch64-dis-2.c: Regenerated.
661
c604a79a
JW		 6622017-06-28 Jiong Wang <jiong.wang@arm.com>
663
664 * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
665
38bf472a
MR		 6662017-06-28 Maciej W. Rozycki <macro@imgtec.com>
667 Matthew Fortune <matthew.fortune@imgtec.com>
4151f684 668 Andrew Bennett <andrew.bennett@imgtec.com>
38bf472a
MR		 669
670 * mips-formats.h (INT_BIAS): New macro.
671 (INT_ADJ): Redefine in INT_BIAS terms.
672 * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
673 (mips_print_save_restore): New function.
674 (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
675 (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
676 call.
677 (print_insn_args): Handle OP_SAVE_RESTORE_LIST.
678 (print_mips16_insn_arg): Call `mips_print_save_restore' for
679 OP_SAVE_RESTORE_LIST handling, factored out from here.
680 * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
681 (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
682 (mips_builtin_opcodes): Add "restore" and "save" entries.
683 * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
684 (IAMR2): New macro.
685 (mips16_opcodes): Add "copyw" and "ucopyw" entries.
686
9bdfdbf9
AW		 6872017-06-23 Andrew Waterman <andrew@sifive.com>
688
689 * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
690 alias; do not mark SLTI instruction as an alias.
691
2234eee6
L		 6922017-06-21 H.J. Lu <hongjiu.lu@intel.com>
693
694 * i386-dis.c (RM_0FAE_REG_5): Removed.
695 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
696 (PREFIX_MOD_3_0F01_REG_5_RM_0): New.
697 (PREFIX_MOD_3_0FAE_REG_5): Likewise.
698 (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1. Add
699 PREFIX_MOD_3_0F01_REG_5_RM_0.
700 (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5. Add
701 PREFIX_MOD_3_0FAE_REG_5.
702 (mod_table): Update MOD_0FAE_REG_5.
703 (rm_table): Update RM_0F01_REG_5. Remove RM_0FAE_REG_5.
704 * i386-opc.tbl: Update incsspd, incsspq and setssbsy.
705 * i386-tbl.h: Regenerated.
706
c2f76402
L		 7072017-06-21 H.J. Lu <hongjiu.lu@intel.com>
708
709 * i386-dis.c (prefix_table): Replace savessp with saveprevssp.
710 * i386-opc.tbl: Likewise.
711 * i386-tbl.h: Regenerated.
712
9fef80d6
L		 7132017-06-21 H.J. Lu <hongjiu.lu@intel.com>
714
715 * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"
716 and "jmp{&|}".
717 (NOTRACK_Fixup): Support memory indirect branch with NOTRACK
718 prefix.
719
0f6d864d
NC		 7202017-06-19 Nick Clifton <nickc@redhat.com>
721
722 PR binutils/21614
723 * score-dis.c (score_opcodes): Add sentinel.
724
e197589b
AM		 7252017-06-16 Alan Modra <amodra@gmail.com>
726
727 * rx-decode.c: Regenerate.
728
0d96e4df
L		 7292017-06-15 H.J. Lu <hongjiu.lu@intel.com>
730
731 PR binutils/21594
732 * i386-dis.c (OP_E_register): Check valid bnd register.
733 (OP_G): Likewise.
734
cd3ea7c6
NC		 7352017-06-15 Nick Clifton <nickc@redhat.com>
736
737 PR binutils/21595
738 * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
739 range value.
740
63323b5b
NC		 7412017-06-15 Nick Clifton <nickc@redhat.com>
742
743 PR binutils/21588
744 * rl78-decode.opc (OP_BUF_LEN): Define.
745 (GETBYTE): Check for the index exceeding OP_BUF_LEN.
746 (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
747 array.
748 * rl78-decode.c: Regenerate.
749
08c7881b
NC		 7502017-06-15 Nick Clifton <nickc@redhat.com>
751
752 PR binutils/21586
753 * bfin-dis.c (gregs): Clip index to prevent overflow.
754 (regs): Likewise.
755 (regs_lo): Likewise.
756 (regs_hi): Likewise.
757
e64519d1
NC		 7582017-06-14 Nick Clifton <nickc@redhat.com>
759
760 PR binutils/21576
761 * score7-dis.c (score_opcodes): Add sentinel.
762
6394c606
YQ		 7632017-06-14 Yao Qi <yao.qi@linaro.org>
764
765 * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
766 * arm-dis.c: Likewise.
767 * ia64-dis.c: Likewise.
768 * mips-dis.c: Likewise.
769 * spu-dis.c: Likewise.
770 * disassemble.h (print_insn_aarch64): New declaration, moved from
771 include/dis-asm.h.
772 (print_insn_big_arm, print_insn_big_mips): Likewise.
773 (print_insn_i386, print_insn_ia64): Likewise.
774 (print_insn_little_arm, print_insn_little_mips): Likewise.
775
db5fa770
NC		 7762017-06-14 Nick Clifton <nickc@redhat.com>
777
778 PR binutils/21587
779 * rx-decode.opc: Include libiberty.h
780 (GET_SCALE): New macro - validates access to SCALE array.
781 (GET_PSCALE): New macro - validates access to PSCALE array.
782 (DIs, SIs, S2Is, rx_disp): Use new macros.
783 * rx-decode.c: Regenerate.
784
05c966f3
AV		 7852017-07-14 Andre Vieira <andre.simoesdiasvieira@arm.com>
786
787 * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
788
10045478
AK		 7892017-05-30 Anton Kolesov <anton.kolesov@synopsys.com>
790
791 * arc-dis.c (enforced_isa_mask): Declare.
792 (cpu_types): Likewise.
793 (parse_cpu_option): New function.
794 (parse_disassembler_options): Use it.
795 (print_insn_arc): Use enforced_isa_mask.
796 (print_arc_disassembler_options): Document new options.
797
88c1242d
YQ		 7982017-05-24 Yao Qi <yao.qi@linaro.org>
799
800 * alpha-dis.c: Include disassemble.h, don't include
801 dis-asm.h.
802 * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
803 * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
804 * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
805 * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
806 * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
807 * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
808 * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
809 * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
810 * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
811 * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
812 * moxie-dis.c, msp430-dis.c, mt-dis.c:
813 * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
814 * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
815 * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
816 * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
817 * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
818 * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
819 * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
820 * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
821 * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
822 * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
823 * z80-dis.c, z8k-dis.c: Likewise.
824 * disassemble.h: New file.
825
ab20fa4a
YQ		 8262017-05-24 Yao Qi <yao.qi@linaro.org>
827
828 * rl78-dis.c (rl78_get_disassembler): If parameter abfd
829 is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
830
003ca0fd
YQ		 8312017-05-24 Yao Qi <yao.qi@linaro.org>
832
833 * disassemble.c (disassembler): Add arguments a, big and mach.
834 Use them.
835
04ef582a
L		 8362017-05-22 H.J. Lu <hongjiu.lu@intel.com>
837
838 * i386-dis.c (NOTRACK_Fixup): New.
839 (NOTRACK): Likewise.
840 (NOTRACK_PREFIX): Likewise.
841 (last_active_prefix): Likewise.
842 (reg_table): Use NOTRACK on indirect call and jmp.
843 (ckprefix): Set last_active_prefix.
844 (prefix_name): Return "notrack" for NOTRACK_PREFIX.
845 * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
846 * i386-opc.h (NoTrackPrefixOk): New.
847 (i386_opcode_modifier): Add notrackprefixok.
848 * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
849 Add notrack.
850 * i386-tbl.h: Regenerated.
851
64517994
JM		 8522017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
853
854 * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
855 (X_IMM2): Define.
856 (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
857 bfd_mach_sparc_v9m8.
858 (print_insn_sparc): Handle new operand types.
859 * sparc-opc.c (MASK_M8): Define.
860 (v6): Add MASK_M8.
861 (v6notlet): Likewise.
862 (v7): Likewise.
863 (v8): Likewise.
864 (v9): Likewise.
865 (v9a): Likewise.
866 (v9b): Likewise.
867 (v9c): Likewise.
868 (v9d): Likewise.
869 (v9e): Likewise.
870 (v9v): Likewise.
871 (v9m): Likewise.
872 (v9andleon): Likewise.
873 (m8): Define.
874 (HWS_VM8): Define.
875 (HWS2_VM8): Likewise.
876 (sparc_opcode_archs): Add entry for "m8".
877 (sparc_opcodes): Add OSA2017 and M8 instructions
878 dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
879 fpx{ll,ra,rl}64x,
880 ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
881 ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
882 revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
883 stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
884 (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
885 ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
886 ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
887 ASI_CORE_SELECT_COMMIT_NHT.
888
535b785f
AM		 8892017-05-18 Alan Modra <amodra@gmail.com>
890
891 * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
892 * aarch64-dis.c: Likewise.
893 * aarch64-gen.c: Likewise.
894 * aarch64-opc.c: Likewise.
895
25499ac7
MR		 8962017-05-15 Maciej W. Rozycki <macro@imgtec.com>
897 Matthew Fortune <matthew.fortune@imgtec.com>
898
899 * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
900 ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
901 (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
902 (print_insn_arg) <OP_REG28>: Add handler.
903 (validate_insn_args) <OP_REG28>: Handle.
904 (print_mips16_insn_arg): Handle MIPS16 instructions that require
905 32-bit encoding and 9-bit immediates.
906 (print_insn_mips16): Handle MIPS16 instructions that require
907 32-bit encoding and MFC0/MTC0 operand decoding.
908 * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
909 <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
910 (RD_C0, WR_C0, E2, E2MT): New macros.
911 (mips16_opcodes): Add entries for MIPS16e2 instructions:
912 GP-relative "addiu" and its "addu" spelling, "andi", "cache",
913 "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
914 "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
915 "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
916 "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
917 instructions, "swl", "swr", "sync" and its "sync_acquire",
918 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
919 "xori", "dmt", "dvpe", "emt" and "evpe". Add split
920 regular/extended entries for original MIPS16 ISA revision
921 instructions whose extended forms are subdecoded in the MIPS16e2
922 ISA revision: "li", "sll" and "srl".
923
fdfb4752
MR		 9242017-05-15 Maciej W. Rozycki <macro@imgtec.com>
925
926 * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
927 reference in CP0 move operand decoding.
928
a4f89915
MR		 9292017-05-12 Maciej W. Rozycki <macro@imgtec.com>
930
931 * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
932 type to hexadecimal.
933 (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
934
99e2d67a
MR		 9352017-05-11 Maciej W. Rozycki <macro@imgtec.com>
936
937 * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
938 "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
939 "sync_rmb" and "sync_wmb" as aliases.
940 * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
941 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
942
53a346d8
CZ		 9432017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
944
945 * arc-dis.c (parse_option): Update quarkse_em option..
946 * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
947 QUARKSE1.
948 (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
949
f91d48de
KC		 9502017-05-03 Kito Cheng <kito.cheng@gmail.com>
951
952 * riscv-dis.c (print_insn_args): Handle 'Co' operands.
953
43e379d7
MC		 9542017-05-01 Michael Clark <michaeljclark@mac.com>
955
956 * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
957 register.
958
a4ddc54e
MR		 9592017-05-02 Maciej W. Rozycki <macro@imgtec.com>
960
961 * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
962 and branches and not synthetic data instructions.
963
fe50e98c
BE		 9642017-05-02 Bernd Edlinger <bernd.edlinger@hotmail.de>
965
966 * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
967
126124cc
CZ		 9682017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
969
970 * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
971 * arc-opc.c (insert_r13el): New function.
972 (R13_EL): Define.
973 * arc-tbl.h: Add new enter/leave variants.
974
be6a24d8
CZ		 9752017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
976
977 * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
978
0348fd79
MR		 9792017-04-25 Maciej W. Rozycki <macro@imgtec.com>
980
981 * mips-dis.c (print_mips_disassembler_options): Add
982 `no-aliases'.
983
6e3d1f07
MR		 9842017-04-25 Maciej W. Rozycki <macro@imgtec.com>
985
986 * mips16-opc.c (AL): New macro.
987 (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
988 of "ld" and "lw" as aliases.
989
957f6b39
TC		 9902017-04-24 Tamar Christina <tamar.christina@arm.com>
991
992 * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
993 arguments.
994
a8cc8a54
AM		 9952017-04-22 Alexander Fedotov <alfedotov@gmail.com>
996 Alan Modra <amodra@gmail.com>
997
998 * ppc-opc.c (ELEV): Define.
999 (vle_opcodes): Add se_rfgi and e_sc.
1000 (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
1001 for E200Z4.
1002
3ab87b68
JM		 10032017-04-21 Jose E. Marchesi <jose.marchesi@oracle.com>
1004
1005 * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
1006
792f174f
NC		 10072017-04-21 Nick Clifton <nickc@redhat.com>
1008
1009 PR binutils/21380
1010 * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
1011 LD3R and LD4R.
1012
42742084
AM		 10132017-04-13 Alan Modra <amodra@gmail.com>
1014
1015 * epiphany-desc.c: Regenerate.
1016 * fr30-desc.c: Regenerate.
1017 * frv-desc.c: Regenerate.
1018 * ip2k-desc.c: Regenerate.
1019 * iq2000-desc.c: Regenerate.
1020 * lm32-desc.c: Regenerate.
1021 * m32c-desc.c: Regenerate.
1022 * m32r-desc.c: Regenerate.
1023 * mep-desc.c: Regenerate.
1024 * mt-desc.c: Regenerate.
1025 * or1k-desc.c: Regenerate.
1026 * xc16x-desc.c: Regenerate.
1027 * xstormy16-desc.c: Regenerate.
1028
9a85b496
AM		 10292017-04-11 Alan Modra <amodra@gmail.com>
1030
ef85eab0 1031 * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
c03dc33b
AM		 1032 PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm". Formatting. Set
1033 PPC_OPCODE_TMR for e6500.
9a85b496
AM		 1034 * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
1035 (PPCVEC3): Define as PPC_OPCODE_POWER9.
9570835e
AM		 1036 (PPCVSX2): Define as PPC_OPCODE_POWER8.
1037 (PPCVSX3): Define as PPC_OPCODE_POWER9.
ef85eab0 1038 (PPCHTM): Define as PPC_OPCODE_POWER8.
c03dc33b 1039 (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
9a85b496 1040
62adc510
AM		 10412017-04-10 Alan Modra <amodra@gmail.com>
1042
1043 * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
1044 * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
1045 (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
1046 removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
1047
aa808707
PC		 10482017-04-09 Pip Cet <pipcet@gmail.com>
1049
1050 * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
1051 appropriate floating-point precision directly.
1052
ac8f0f72
AM		 10532017-04-07 Alan Modra <amodra@gmail.com>
1054
1055 * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
1056 lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
1057 lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
1058 lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
1059 vector instructions with E6500 not PPCVEC2.
1060
62ecb94c
PC		 10612017-04-06 Pip Cet <pipcet@gmail.com>
1062
1063 * Makefile.am: Add wasm32-dis.c.
1064 * configure.ac: Add wasm32-dis.c to wasm32 target.
1065 * disassemble.c: Add wasm32 disassembler code.
1066 * wasm32-dis.c: New file.
1067 * Makefile.in: Regenerate.
1068 * configure: Regenerate.
1069 * po/POTFILES.in: Regenerate.
1070 * po/opcodes.pot: Regenerate.
1071
f995bbe8
PA		 10722017-04-05 Pedro Alves <palves@redhat.com>
1073
1074 * arc-dis.c (parse_option, parse_disassembler_options): Constify.
1075 * arm-dis.c (parse_arm_disassembler_options): Constify.
1076 * ppc-dis.c (powerpc_init_dialect): Constify local.
1077 * vax-dis.c (parse_disassembler_options): Constify.
1078
b5292032
PD		 10792017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
1080
1081 * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
1082 RISCV_GP_SYMBOL.
1083
f96bd6c2
PC		 10842017-03-30 Pip Cet <pipcet@gmail.com>
1085
1086 * configure.ac: Add (empty) bfd_wasm32_arch target.
1087 * configure: Regenerate
1088 * po/opcodes.pot: Regenerate.
1089
f7c514a3
JM		 10902017-03-29 Sheldon Lobo <sheldon.lobo@oracle.com>
1091
1092 Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
1093 OSA2015.
1094 * opcodes/sparc-opc.c (asi_table): New ASIs.
1095
52be03fd
AM		 10962017-03-29 Alan Modra <amodra@gmail.com>
1097
1098 * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add
1099 "raw" option.
1100 (lookup_powerpc): Don't special case -1 dialect. Handle
1101 PPC_OPCODE_RAW.
1102 (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
1103 lookup_powerpc call, pass it on second.
1104
9b753937
AM		 11052017-03-27 Alan Modra <amodra@gmail.com>
1106
1107 PR 21303
1108 * ppc-dis.c (struct ppc_mopt): Comment.
1109 (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
1110
c0c31e91
RZ		 11112017-03-27 Rinat Zelig <rinat@mellanox.com>
1112
1113 * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
1114 * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
1115 F_NPS_M, F_NPS_CORE, F_NPS_ALL.
1116 (insert_nps_misc_imm_offset): New function.
1117 (extract_nps_misc imm_offset): New function.
1118 (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
1119 (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
1120
2253c8f0
AK		 11212017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1122
1123 * s390-mkopc.c (main): Remove vx2 check.
1124 * s390-opc.txt: Remove vx2 instruction flags.
1125
645d3342
RZ		 11262017-03-21 Rinat Zelig <rinat@mellanox.com>
1127
1128 * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
1129 * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
1130 (insert_nps_imm_offset): New function.
1131 (extract_nps_imm_offset): New function.
1132 (insert_nps_imm_entry): New function.
1133 (extract_nps_imm_entry): New function.
1134
4b94dd2d
AM		 11352017-03-17 Alan Modra <amodra@gmail.com>
1136
1137 PR 21248
1138 * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
1139 mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after
1140 those spr mnemonics they alias. Similarly for mtibatl, mtibatu.
1141
b416fe87
KC		 11422017-03-14 Kito Cheng <kito.cheng@gmail.com>
1143
1144 * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
1145 <c.andi>: Likewise.
1146 <c.addiw> Likewise.
1147
03b039a5
KC		 11482017-03-14 Kito Cheng <kito.cheng@gmail.com>
1149
1150 * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
1151
2c232b83
AW		 11522017-03-13 Andrew Waterman <andrew@sifive.com>
1153
1154 * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
1155 <srl> Likewise.
1156 <srai> Likewise.
1157 <sra> Likewise.
1158
86fa6981
L		 11592017-03-09 H.J. Lu <hongjiu.lu@intel.com>
1160
1161 * i386-gen.c (opcode_modifiers): Replace S with Load.
1162 * i386-opc.h (S): Removed.
1163 (Load): New.
1164 (i386_opcode_modifier): Replace s with load.
1165 * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
1166 and {evex}. Replace S with Load.
1167 * i386-tbl.h: Regenerated.
1168
c1fe188b
L		 11692017-03-09 H.J. Lu <hongjiu.lu@intel.com>
1170
1171 * i386-opc.tbl: Use CpuCET on rdsspq.
1172 * i386-tbl.h: Regenerated.
1173
4b8b687e
PB		 11742017-03-08 Peter Bergner <bergner@vnet.ibm.com>
1175
1176 * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
1177 <vsx>: Do not use PPC_OPCODE_VSX3;
1178
1437d063
PB		 11792017-03-08 Peter Bergner <bergner@vnet.ibm.com>
1180
1181 * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
1182
603555e5
L		 11832017-03-06 H.J. Lu <hongjiu.lu@intel.com>
1184
1185 * i386-dis.c (REG_0F1E_MOD_3): New enum.
1186 (MOD_0F1E_PREFIX_1): Likewise.
1187 (MOD_0F38F5_PREFIX_2): Likewise.
1188 (MOD_0F38F6_PREFIX_0): Likewise.
1189 (RM_0F1E_MOD_3_REG_7): Likewise.
1190 (PREFIX_MOD_0_0F01_REG_5): Likewise.
1191 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
1192 (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
1193 (PREFIX_0F1E): Likewise.
1194 (PREFIX_MOD_0_0FAE_REG_5): Likewise.
1195 (PREFIX_0F38F5): Likewise.
1196 (dis386_twobyte): Use PREFIX_0F1E.
1197 (reg_table): Add REG_0F1E_MOD_3.
1198 (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
1199 PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
1200 PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
1201 PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
1202 (three_byte_table): Use PREFIX_0F38F5.
1203 (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
1204 Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
1205 (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
1206 RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
1207 PREFIX_MOD_3_0F01_REG_5_RM_2.
1208 * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
1209 (cpu_flags): Add CpuCET.
1210 * i386-opc.h (CpuCET): New enum.
1211 (CpuUnused): Commented out.
1212 (i386_cpu_flags): Add cpucet.
1213 * i386-opc.tbl: Add Intel CET instructions.
1214 * i386-init.h: Regenerated.
1215 * i386-tbl.h: Likewise.
1216
73f07bff
AM		 12172017-03-06 Alan Modra <amodra@gmail.com>
1218
1219 PR 21124
1220 * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
1221 (extract_raq, extract_ras, extract_rbx): New functions.
1222 (powerpc_operands): Use opposite corresponding insert function.
1223 (Q_MASK): Define.
1224 (powerpc_opcodes): Apply Q_MASK to all quad insns with even
1225 register restriction.
1226
65b48a81
PB		 12272017-02-28 Peter Bergner <bergner@vnet.ibm.com>
1228
1229 * disassemble.c Include "safe-ctype.h".
1230 (disassemble_init_for_target): Handle s390 init.
1231 (remove_whitespace_and_extra_commas): New function.
1232 (disassembler_options_cmp): Likewise.
1233 * arm-dis.c: Include "libiberty.h".
1234 (NUM_ELEM): Delete.
1235 (regnames): Use long disassembler style names.
1236 Add force-thumb and no-force-thumb options.
1237 (NUM_ARM_REGNAMES): Rename from this...
1238 (NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE.
1239 (get_arm_regname_num_options): Delete.
1240 (set_arm_regname_option): Likewise.
1241 (get_arm_regnames): Likewise.
1242 (parse_disassembler_options): Likewise.
1243 (parse_arm_disassembler_option): Rename from this...
1244 (parse_arm_disassembler_options): ...to this. Make static.
1245 Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
1246 (print_insn): Use parse_arm_disassembler_options.
1247 (disassembler_options_arm): New function.
1248 (print_arm_disassembler_options): Handle updated regnames.
1249 * ppc-dis.c: Include "libiberty.h".
1250 (ppc_opts): Add "32" and "64" entries.
1251 (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
1252 (powerpc_init_dialect): Add break to switch statement.
1253 Use new FOR_EACH_DISASSEMBLER_OPTION macro.
1254 (disassembler_options_powerpc): New function.
1255 (print_ppc_disassembler_options): Use ARRAY_SIZE.
1256 Remove printing of "32" and "64".
1257 * s390-dis.c: Include "libiberty.h".
1258 (init_flag): Remove unneeded variable.
1259 (struct s390_options_t): New structure type.
1260 (options): New structure.
1261 (init_disasm): Rename from this...
1262 (disassemble_init_s390): ...to this. Add initializations for
1263 current_arch_mask and option_use_insn_len_bits_p. Remove init_flag.
1264 (print_insn_s390): Delete call to init_disasm.
1265 (disassembler_options_s390): New function.
1266 (print_s390_disassembler_options): Print using information from
1267 struct 'options'.
1268 * po/opcodes.pot: Regenerate.
1269
15c7c1d8
JB		 12702017-02-28 Jan Beulich <jbeulich@suse.com>
1271
1272 * i386-dis.c (PCMPESTR_Fixup): New.
1273 (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
1274 (prefix_table): Use PCMPESTR_Fixup.
1275 (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
1276 PCMPESTR_Fixup.
1277 (vex_w_table): Delete VPCMPESTR{I,M} entries.
1278 * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
1279 Split 64-bit and non-64-bit variants.
1280 * opcodes/i386-tbl.h: Re-generate.
1281
582e12bf
RS		 12822017-02-24 Richard Sandiford <richard.sandiford@arm.com>
1283
1284 * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
1285 (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
1286 (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
1287 (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
1288 (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
1289 (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
1290 (OP_SVE_V_HSD): New macros.
1291 (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
1292 (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
1293 (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
1294 (aarch64_opcode_table): Add new SVE instructions.
1295 (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
1296 for rotation operands. Add new SVE operands.
1297 * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
1298 (ins_sve_quad_index): Likewise.
1299 (ins_imm_rotate): Split into...
1300 (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
1301 * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
1302 (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
1303 functions.
1304 (aarch64_ins_sve_addr_ri_s4): New function.
1305 (aarch64_ins_sve_quad_index): Likewise.
1306 (do_misc_encoding): Handle "MOV Zn.Q, Qm".
1307 * aarch64-asm-2.c: Regenerate.
1308 * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
1309 (ext_sve_quad_index): Likewise.
1310 (ext_imm_rotate): Split into...
1311 (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
1312 * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
1313 (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
1314 functions.
1315 (aarch64_ext_sve_addr_ri_s4): New function.
1316 (aarch64_ext_sve_quad_index): Likewise.
1317 (aarch64_ext_sve_index): Allow quad indices.
1318 (do_misc_decoding): Likewise.
1319 * aarch64-dis-2.c: Regenerate.
1320 * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
1321 aarch64_field_kinds.
1322 (OPD_F_OD_MASK): Widen by one bit.
1323 (OPD_F_NO_ZR): Bump accordingly.
1324 (get_operand_field_width): New function.
1325 * aarch64-opc.c (fields): Add new SVE fields.
1326 (operand_general_constraint_met_p): Handle new SVE operands.
1327 (aarch64_print_operand): Likewise.
1328 * aarch64-opc-2.c: Regenerate.
1329
f482d304
RS		 13302017-02-24 Richard Sandiford <richard.sandiford@arm.com>
1331
1332 * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
1333 (aarch64_feature_compnum): ...this.
1334 (SIMD_V8_3): Replace with...
1335 (COMPNUM): ...this.
1336 (CNUM_INSN): New macro.
1337 (aarch64_opcode_table): Use it for the complex number instructions.
1338
7db2c588
JB		 13392017-02-24 Jan Beulich <jbeulich@suse.com>
1340
1341 * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
1342
1e9d41d4
SL		 13432017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
1344
1345 Add support for associating SPARC ASIs with an architecture level.
1346 * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
1347 * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
1348 decoding of SPARC ASIs.
1349
53c4d625
JB		 13502017-02-23 Jan Beulich <jbeulich@suse.com>
1351
1352 * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
1353 82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
1354
11648de5
JB		 13552017-02-21 Jan Beulich <jbeulich@suse.com>
1356
1357 * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
1358 1 (instead of to itself). Correct typo.
1359
f98d33be
AW		 13602017-02-14 Andrew Waterman <andrew@sifive.com>
1361
1362 * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
1363 pseudoinstructions.
1364
773fb663
RS		 13652017-02-15 Richard Sandiford <richard.sandiford@arm.com>
1366
1367 * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
1368 (aarch64_sys_reg_supported_p): Handle them.
1369
cc07cda6
CZ		 13702017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
1371
1372 * arc-opc.c (UIMM6_20R): Define.
1373 (SIMM12_20): Use above.
1374 (SIMM12_20R): Define.
1375 (SIMM3_5_S): Use above.
1376 (UIMM7_A32_11R_S): Define.
1377 (UIMM7_9_S): Use above.
1378 (UIMM3_13R_S): Define.
1379 (SIMM11_A32_7_S): Use above.
1380 (SIMM9_8R): Define.
1381 (UIMM10_A32_8_S): Use above.
1382 (UIMM8_8R_S): Define.
1383 (W6): Use above.
1384 (arc_relax_opcodes): Use all above defines.
1385
66a5a740
VG		 13862017-02-15 Vineet Gupta <vgupta@synopsys.com>
1387
1388 * arc-regs.h: Distinguish some of the registers different on
1389 ARC700 and HS38 cpus.
1390
7e0de605
AM		 13912017-02-14 Alan Modra <amodra@gmail.com>
1392
1393 PR 21118
1394 * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
1395 with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
1396
54064fdb
AM		 13972017-02-11 Stafford Horne <shorne@gmail.com>
1398 Alan Modra <amodra@gmail.com>
1399
1400 * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
1401 Use insn_bytes_value and insn_int_value directly instead. Don't
1402 free allocated memory until function exit.
1403
dce75bf9
NP		 14042017-02-10 Nicholas Piggin <npiggin@gmail.com>
1405
1406 * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
1407
1b7e3d2f
NC		 14082017-02-03 Nick Clifton <nickc@redhat.com>
1409
1410 PR 21096
1411 * aarch64-opc.c (print_register_list): Ensure that the register
1412 list index will fir into the tb buffer.
1413 (print_register_offset_address): Likewise.
1414 * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
1415
8ec5cf65
AD		 14162017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
1417
1418 PR 21056
1419 * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
1420 instructions when the previous fetch packet ends with a 32-bit
1421 instruction.
1422
a1aa5e81
DD		 14232017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
1424
1425 * pru-opc.c: Remove vague reference to a future GDB port.
1426
add3afb2
NC		 14272017-01-20 Nick Clifton <nickc@redhat.com>
1428
1429 * po/ga.po: Updated Irish translation.
1430
c13a63b0
SN		 14312017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
1432
1433 * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
1434
9608051a
YQ		 14352017-01-13 Yao Qi <yao.qi@linaro.org>
1436
1437 * m68k-dis.c (match_insn_m68k): Extend comments. Return -1
1438 if FETCH_DATA returns 0.
1439 (m68k_scan_mask): Likewise.
1440 (print_insn_m68k): Update code to handle -1 return value.
1441
f622ea96
YQ		 14422017-01-13 Yao Qi <yao.qi@linaro.org>
1443
1444 * m68k-dis.c (enum print_insn_arg_error): New.
1445 (NEXTBYTE): Replace -3 with
1446 PRINT_INSN_ARG_MEMORY_ERROR.
1447 (NEXTULONG): Likewise.
1448 (NEXTSINGLE): Likewise.
1449 (NEXTDOUBLE): Likewise.
1450 (NEXTDOUBLE): Likewise.
1451 (NEXTPACKED): Likewise.
1452 (FETCH_ARG): Likewise.
1453 (FETCH_DATA): Update comments.
1454 (print_insn_arg): Update comments. Replace magic numbers with
1455 enum.
1456 (match_insn_m68k): Likewise.
1457
620214f7
IT		 14582017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1459
1460 * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
1461 * i386-dis-evex.h (evex_table): Updated.
1462 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
1463 CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
1464 (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
1465 * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
1466 (i386_cpu_flags): Add cpuavx512_vpopcntdq.
1467 * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
1468 * i386-init.h: Regenerate.
1469 * i386-tbl.h: Ditto.
1470
d95014a2
YQ		 14712017-01-12 Yao Qi <yao.qi@linaro.org>
1472
1473 * msp430-dis.c (msp430_singleoperand): Return -1 if
1474 msp430dis_opcode_signed returns false.
1475 (msp430_doubleoperand): Likewise.
1476 (msp430_branchinstr): Return -1 if
1477 msp430dis_opcode_unsigned returns false.
1478 (msp430x_calla_instr): Likewise.
1479 (print_insn_msp430): Likewise.
1480
0ae60c3e
NC		 14812017-01-05 Nick Clifton <nickc@redhat.com>
1482
1483 PR 20946
1484 * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
1485 could not be matched.
1486 (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
1487 NULL.
1488
d74d4880
SN		 14892017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
1490
1491 * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
1492 (aarch64_opcode_table): Use RCPC_INSN.
1493
cc917fd9
KC		 14942017-01-03 Kito Cheng <kito.cheng@gmail.com>
1495
1496 * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
1497 extension.
1498 * riscv-opcodes/all-opcodes: Likewise.
1499
b52d3cfc
DP		 15002017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
1501
1502 * riscv-dis.c (print_insn_args): Add fall through comment.
1503
f90c58d5
NC		 15042017-01-03 Nick Clifton <nickc@redhat.com>
1505
1506 * po/sr.po: New Serbian translation.
1507 * configure.ac (ALL_LINGUAS): Add sr.
1508 * configure: Regenerate.
1509
f47b0d4a
AM		 15102017-01-02 Alan Modra <amodra@gmail.com>
1511
1512 * epiphany-desc.h: Regenerate.
1513 * epiphany-opc.h: Regenerate.
1514 * fr30-desc.h: Regenerate.
1515 * fr30-opc.h: Regenerate.
1516 * frv-desc.h: Regenerate.
1517 * frv-opc.h: Regenerate.
1518 * ip2k-desc.h: Regenerate.
1519 * ip2k-opc.h: Regenerate.
1520 * iq2000-desc.h: Regenerate.
1521 * iq2000-opc.h: Regenerate.
1522 * lm32-desc.h: Regenerate.
1523 * lm32-opc.h: Regenerate.
1524 * m32c-desc.h: Regenerate.
1525 * m32c-opc.h: Regenerate.
1526 * m32r-desc.h: Regenerate.
1527 * m32r-opc.h: Regenerate.
1528 * mep-desc.h: Regenerate.
1529 * mep-opc.h: Regenerate.
1530 * mt-desc.h: Regenerate.
1531 * mt-opc.h: Regenerate.
1532 * or1k-desc.h: Regenerate.
1533 * or1k-opc.h: Regenerate.
1534 * xc16x-desc.h: Regenerate.
1535 * xc16x-opc.h: Regenerate.
1536 * xstormy16-desc.h: Regenerate.
1537 * xstormy16-opc.h: Regenerate.
1538
2571583a
AM		 15392017-01-02 Alan Modra <amodra@gmail.com>
1540
1541 Update year range in copyright notice of all files.
1542
5c1ad6b5 1543For older changes see ChangeLog-2016
3499769a 1544\f
5c1ad6b5 1545Copyright (C) 2017 Free Software Foundation, Inc.
3499769a
AM		 1546
1547Copying and distribution of this file, with or without modification,
1548are permitted in any medium without royalty provided the copyright
1549notice and this notice are preserved.
1550
1551Local Variables:
1552mode: change-log
1553left-margin: 8
1554fill-column: 74
1555version-control: never
1556End:
GDB Binutils - Deliverables
This page took 0.176274 seconds and 4 git commands to generate.