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[AArch64] Add ARMv8.3 combined pointer authentication branch instructions
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
74f5402d
SN		 12016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
2
3 * aarch64-tbl.h (arch64_opcode_table): Add braa, brab, blraa, blrab, braaz,
4 brabz, blraaz, blrabz, retaa, retab, eretaa, eretab.
5 * aarch64-asm-2.c: Regenerate.
6 * aarch64-dis-2.c: Regenerate.
7 * aarch64-opc-2.c: Regenerate.
8
c84364ec
SN		 92016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
10
11 * aarch64-tbl.h (arch64_opcode_table): Add pacga.
12 (AARCH64_OPERANDS): Add Rm_SP.
13 * aarch64-opc.c (aarch64_print_operand): Handle AARCH64_OPND_Rm_SP.
14 * aarch64-asm-2.c: Regenerate.
15 * aarch64-dis-2.c: Regenerate.
16 * aarch64-opc-2.c: Regenerate.
17
a2cfc830
SN		 182016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
19
20 * aarch64-tbl.h (arch64_opcode_table): Add pacia, pacib, pacda, pacdb, autia,
21 autib, autda, autdb, paciza, pacizb, pacdza, pacdzb, autiza, autizb, autdza,
22 autdzb, xpaci, xpacd.
23 * aarch64-asm-2.c: Regenerate.
24 * aarch64-dis-2.c: Regenerate.
25 * aarch64-opc-2.c: Regenerate.
26
b0bfa7b5
SN		 272016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
28
29 * aarch64-opc.c (aarch64_sys_regs): Add apiakeylo_el1, apiakeyhi_el1,
30 apibkeylo_el1, apibkeyhi_el1, apdakeylo_el1, apdakeyhi_el1,
31 apdbkeylo_el1, apdbkeyhi_el1, apgakeylo_el1 and apgakeyhi_el1.
32 (aarch64_sys_reg_supported_p): Add feature test for new registers.
33
8787d804
SN		 342016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
35
36 * aarch64-tbl.h (aarch64_feature_v8_3, ARMV8_3, V8_3_INSN): New.
37 (arch64_opcode_table): Add xpaclri, pacia1716, pacib1716, autia1716,
38 autib1716, paciaz, paciasp, pacibz, pacibsp, autiaz, autiasp, autibz,
39 autibsp.
40 * aarch64-asm-2.c: Regenerate.
41 * aarch64-dis-2.c: Regenerate.
42
3d731f69
SN		 432016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
44
45 * aarch64-gen.c (find_alias_opcode): Increase max_num_aliases to 32.
46
60227d64
L		 472016-11-09 H.J. Lu <hongjiu.lu@intel.com>
48
49 PR binutils/20799
50 * i386-dis-evex.h (evex_table): Replace EdqwS with Edqw.
51 * i386-dis.c (EdqwS): Removed.
52 (dqw_swap_mode): Likewise.
53 (intel_operand_size): Don't check dqw_swap_mode.
54 (OP_E_register): Likewise.
55 (OP_E_memory): Likewise.
56 (OP_G): Likewise.
57 (OP_EX): Likewise.
58 * i386-opc.tbl: Remove "S" from EVEX vpextrw.
59 * i386-tbl.h: Regerated.
60
7efeed17
L		 612016-11-09 H.J. Lu <hongjiu.lu@intel.com>
62
63 * i386-opc.tbl: Merge AVX512F vmovq.
1032d6eb 64 * i386-tbl.h: Regerated.
7efeed17 65
1f334aeb
L		 662016-11-08 H.J. Lu <hongjiu.lu@intel.com>
67
68 PR binutils/20701
69 * i386-dis.c (THREE_BYTE_0F7A): Removed.
70 (dis386_twobyte): Don't use THREE_BYTE_0F7A.
71 (three_byte_table): Remove THREE_BYTE_0F7A.
72
48c97fa1
L		 732016-11-07 H.J. Lu <hongjiu.lu@intel.com>
74
75 PR binutils/20775
76 * i386-dis.c (FGRPd9_2): Replace 0 with 1.
77 (FGRPd9_4): Replace 1 with 2.
78 (FGRPd9_5): Replace 2 with 3.
79 (FGRPd9_6): Replace 3 with 4.
80 (FGRPd9_7): Replace 4 with 5.
81 (FGRPda_5): Replace 5 with 6.
82 (FGRPdb_4): Replace 6 with 7.
83 (FGRPde_3): Replace 7 with 8.
84 (FGRPdf_4): Replace 8 with 9.
85 (fgrps): Add an entry for Bad_Opcode.
86
b437d035
AB		 872016-11-04 Andrew Burgess <andrew.burgess@embecosm.com>
88
89 * arc-opc.c (arc_flag_operands): Add F_DI14.
90 (arc_flag_classes): Add C_DI14.
91 * arc-nps400-tbl.h: Add new exc instructions.
92
5a736821
GM		 932016-11-03 Graham Markall <graham.markall@embecosm.com>
94
95 * arc-dis.c (arc_insn_length): Return length 8 for instructions with
96 major opcode 0xa.
97 * arc-nps-400-tbl.h: Add dcmac instruction.
98 * arc-opc.c (arc_operands): Added operands for dcmac instruction.
99 (insert_nps_rbdouble_64): Added.
100 (extract_nps_rbdouble_64): Added.
101 (insert_nps_proto_size): Added.
102 (extract_nps_proto_size): Added.
103
bdfe53e3
AB		 1042016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
105
106 * arc-dis.c (struct arc_operand_iterator): Remove all fields
107 relating to long instruction processing, add new limm field.
108 (OPCODE): Rename to...
109 (OPCODE_32BIT_INSN): ...this.
110 (OPCODE_AC): Delete.
111 (skip_this_opcode): Handle different instruction lengths, update
112 macro name.
113 (special_flag_p): Update parameter type.
114 (find_format_from_table): Update for more instruction lengths.
115 (find_format_long_instructions): Delete.
116 (find_format): Update for more instruction lengths.
117 (arc_insn_length): Likewise.
118 (extract_operand_value): Update for more instruction lengths.
119 (operand_iterator_next): Remove code relating to long
120 instructions.
121 (arc_opcode_to_insn_type): New function.
122 (print_insn_arc):Update for more instructions lengths.
123 * arc-ext.c (extInstruction_t): Change argument type.
124 * arc-ext.h (extInstruction_t): Change argument type.
125 * arc-fxi.h: Change type unsigned to unsigned long long
126 extensively throughout.
127 * arc-nps400-tbl.h: Add long instructions taken from
128 arc_long_opcodes table in arc-opc.c.
129 * arc-opc.c: Update parameter types on insert/extract handlers.
130 (arc_long_opcodes): Delete.
131 (arc_num_long_opcodes): Delete.
132 (arc_opcode_len): Update for more instruction lengths.
133
90f61cce
GM		 1342016-11-03 Graham Markall <graham.markall@embecosm.com>
135
136 * arc-dis.c (print_insn_arc): Swap highbyte and lowbyte.
137
06fe285f
GM		 1382016-11-03 Graham Markall <graham.markall@embecosm.com>
139
140 * arc-dis.c (find_format_from_table): Replace use of ARC_SHORT
141 with arc_opcode_len.
142 (find_format_long_instructions): Likewise.
143 * arc-opc.c (arc_opcode_len): New function.
144
ecf64ec6
AB		 1452016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
146
147 * arc-nps400-tbl.h: Fix some instruction masks.
148
d039fef3
L		 1492016-11-03 H.J. Lu <hongjiu.lu@intel.com>
150
151 * i386-dis.c (REG_82): Removed.
152 (X86_64_82_REG_0): Likewise.
153 (X86_64_82_REG_1): Likewise.
154 (X86_64_82_REG_2): Likewise.
155 (X86_64_82_REG_3): Likewise.
156 (X86_64_82_REG_4): Likewise.
157 (X86_64_82_REG_5): Likewise.
158 (X86_64_82_REG_6): Likewise.
159 (X86_64_82_REG_7): Likewise.
160 (X86_64_82): New.
161 (dis386): Use X86_64_82 instead of REG_82.
162 (reg_table): Remove REG_82.
163 (x86_64_table): Add X86_64_82. Remove X86_64_82_REG_0,
164 X86_64_82_REG_1, X86_64_82_REG_2, X86_64_82_REG_3,
165 X86_64_82_REG_4, X86_64_82_REG_5, X86_64_82_REG_6 and
166 X86_64_82_REG_7.
167
8b89fe14
L		 1682016-11-03 H.J. Lu <hongjiu.lu@intel.com>
169
170 PR binutils/20754
171 * i386-dis.c (REG_82): New.
172 (X86_64_82_REG_0): Likewise.
173 (X86_64_82_REG_1): Likewise.
174 (X86_64_82_REG_2): Likewise.
175 (X86_64_82_REG_3): Likewise.
176 (X86_64_82_REG_4): Likewise.
177 (X86_64_82_REG_5): Likewise.
178 (X86_64_82_REG_6): Likewise.
179 (X86_64_82_REG_7): Likewise.
180 (dis386): Use REG_82.
181 (reg_table): Add REG_82.
182 (x86_64_table): Add X86_64_82_REG_0, X86_64_82_REG_1,
183 X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4,
184 X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7.
185
7148c369
L		 1862016-11-03 H.J. Lu <hongjiu.lu@intel.com>
187
188 * i386-dis.c (REG_82): Renamed to ...
189 (REG_83): This.
190 (dis386): Updated.
191 (reg_table): Likewise.
192
47acf0bd
IT		 1932016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
194
195 * i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853.
196 * i386-dis-evex.h (evex_table): Updated.
197 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS,
198 CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
199 (cpu_flags): Add CpuAVX512_4VNNIW.
200 * i386-opc.h (enum): (AVX512_4VNNIW): New.
201 (i386_cpu_flags): Add cpuavx512_4vnniw.
202 * i386-opc.tbl: Add Intel AVX512_4VNNIW instructions.
203 * i386-init.h: Regenerate.
204 * i386-tbl.h: Ditto.
205
920d2ddc
IT		 2062016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
207
208 * i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,
209 PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.
210 * i386-dis-evex.h (evex_table): Updated.
211 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,
212 CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
213 (cpu_flags): Add CpuAVX512_4FMAPS.
214 (opcode_modifiers): Add ImplicitQuadGroup modifier.
215 * i386-opc.h (AVX512_4FMAP): New.
216 (i386_cpu_flags): Add cpuavx512_4fmaps.
217 (ImplicitQuadGroup): New.
218 (i386_opcode_modifier): Add implicitquadgroup.
219 * i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.
220 * i386-init.h: Regenerate.
221 * i386-tbl.h: Ditto.
222
e23eba97
NC		 2232016-11-01 Palmer Dabbelt <palmer@dabbelt.com>
224 Andrew Waterman <andrew@sifive.com>
225
226 Add support for RISC-V architecture.
227 * configure.ac: Add entry for bfd_riscv_arch.
228 * configure: Regenerate.
229 * disassemble.c (disassembler): Add support for riscv.
230 (disassembler_usage): Likewise.
231 * riscv-dis.c: New file.
232 * riscv-opc.c: New file.
233
b5cefcca
L		 2342016-10-21 H.J. Lu <hongjiu.lu@intel.com>
235
236 * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
237 (prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
238 (rm_table): Update the RM_0FAE_REG_7 entry.
239 * i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
240 (cpu_flags): Remove CpuPCOMMIT.
241 * i386-opc.h (CpuPCOMMIT): Removed.
242 (i386_cpu_flags): Remove cpupcommit.
243 * i386-opc.tbl: Remove pcommit.
244 * i386-init.h: Regenerated.
245 * i386-tbl.h: Likewise.
246
9889cbb1
L		 2472016-10-20 H.J. Lu <hongjiu.lu@intel.com>
248
249 PR binutis/20705
250 * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
251 the highest bit in VEX.vvvv for the 3-byte VEX prefix in
252 32-bit mode. Don't check vex.register_specifier in 32-bit
253 mode.
254 (OP_VEX): Check for invalid mask registers.
255
28596323
L		 2562016-10-18 H.J. Lu <hongjiu.lu@intel.com>
257
258 PR binutis/20699
259 * i386-dis.c (OP_E_memory): Check addr32flag in stead of
260 sizeflag.
261
da8d7d66
L		 2622016-10-18 H.J. Lu <hongjiu.lu@intel.com>
263
264 PR binutis/20704
265 * i386-dis.c (three_byte_table): Remove the remaining SSE5 support.
266
eaf02703
MR		 2672016-10-18 Maciej W. Rozycki <macro@imgtec.com>
268
269 * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'
270 local variable to `index_regno'.
271
decf5bd1
CM		 2722016-10-17 Cupertino Miranda <cmiranda@synopsys.com>
273
274 * arc-tbl.h: Removed any "inv.+" instructions from the table.
275
e5b06ef0
CZ		 2762016-10-14 Claudiu Zissulescu <claziss@synopsys.com>
277
278 * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
279 usage on ISA basis.
280
93562a34
JW		 2812016-10-11 Jiong Wang <jiong.wang@arm.com>
282
283 PR target/20666
284 * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
285
362c0c4d
JW		 2862016-10-07 Jiong Wang <jiong.wang@arm.com>
287
288 PR target/20667
289 * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
290 available.
291
1047201f
AM		 2922016-10-07 Alan Modra <amodra@gmail.com>
293
294 * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
295
1a0670f3
AM		 2962016-10-06 Alan Modra <amodra@gmail.com>
297
298 * aarch64-opc.c: Spell fall through comments consistently.
299 * i386-dis.c: Likewise.
300 * aarch64-dis.c: Add missing fall through comments.
301 * aarch64-opc.c: Likewise.
302 * arc-dis.c: Likewise.
303 * arm-dis.c: Likewise.
304 * i386-dis.c: Likewise.
305 * m68k-dis.c: Likewise.
306 * mep-asm.c: Likewise.
307 * ns32k-dis.c: Likewise.
308 * sh-dis.c: Likewise.
309 * tic4x-dis.c: Likewise.
310 * tic6x-dis.c: Likewise.
311 * vax-dis.c: Likewise.
312
2b804145
AM		 3132016-10-06 Alan Modra <amodra@gmail.com>
314
315 * arc-ext.c (create_map): Add missing break.
316 * msp430-decode.opc (encode_as): Likewise.
317 * msp430-decode.c: Regenerate.
318
616ec358
AM		 3192016-10-06 Alan Modra <amodra@gmail.com>
320
321 * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
322 * crx-dis.c (print_insn_crx): Likewise.
323
72da393d
L		 3242016-09-30 H.J. Lu <hongjiu.lu@intel.com>
325
326 PR binutils/20657
327 * i386-dis.c (putop): Don't assign alt twice.
328
744ce302
JW		 3292016-09-29 Jiong Wang <jiong.wang@arm.com>
330
331 PR target/20553
332 * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
333
a5721ba2
AM		 3342016-09-29 Alan Modra <amodra@gmail.com>
335
336 * ppc-opc.c (L): Make compulsory.
337 (LOPT): New, optional form of L.
338 (HTM_R): Define as LOPT.
339 (L0, L1): Delete.
340 (L32OPT): New, optional for 32-bit L.
341 (L2OPT): New, 2-bit L for dcbf.
342 (SVC_LEC): Update.
343 (L2): Define.
344 (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
345 (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
346 <dcbf>: Use L2OPT.
347 <tlbiel, tlbie>: Use LOPT.
348 <wclr, wclrall>: Use L2.
349
c5da1932
VZ		 3502016-09-26 Vlad Zakharov <vzakhar@synopsys.com>
351
352 * Makefile.in: Regenerate.
353 * configure: Likewise.
354
2b848ebd
CZ		 3552016-09-26 Claudiu Zissulescu <claziss@synopsys.com>
356
357 * arc-ext-tbl.h (EXTINSN2OPF): Define.
358 (EXTINSN2OP): Use EXTINSN2OPF.
359 (bspeekm, bspop, modapp): New extension instructions.
360 * arc-opc.c (F_DNZ_ND): Define.
361 (F_DNZ_D): Likewise.
362 (F_SIZEB1): Changed.
363 (C_DNZ_D): Define.
364 (C_HARD): Changed.
365 * arc-tbl.h (dbnz): New instruction.
366 (prealloc): Allow it for ARC EM.
367 (xbfu): Likewise.
368
ad43e107
RS		 3692016-09-21 Richard Sandiford <richard.sandiford@arm.com>
370
371 * aarch64-opc.c (print_immediate_offset_address): Print spaces
372 after commas in addresses.
373 (aarch64_print_operand): Likewise.
374
ab3b8fcf
RS		 3752016-09-21 Richard Sandiford <richard.sandiford@arm.com>
376
377 * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
378 rather than "should be" or "expected to be" in error messages.
379
bb7eff52
RS		 3802016-09-21 Richard Sandiford <richard.sandiford@arm.com>
381
382 * aarch64-dis.c (remove_dot_suffix): New function, split out from...
383 (print_mnemonic_name): ...here.
384 (print_comment): New function.
385 (print_aarch64_insn): Call it.
386 * aarch64-opc.c (aarch64_conds): Add SVE names.
387 (aarch64_print_operand): Print alternative condition names in
388 a comment.
389
c0890d26
RS		 3902016-09-21 Richard Sandiford <richard.sandiford@arm.com>
391
392 * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
393 (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
394 (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
395 (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
396 (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
397 (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
398 (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
399 (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
400 (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
401 (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
402 (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
403 (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
404 (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
405 (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
406 (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
407 (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
408 (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
409 (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
410 (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
411 (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
412 (OP_SVE_XWU, OP_SVE_XXU): New macros.
413 (aarch64_feature_sve): New variable.
414 (SVE): New macro.
415 (_SVE_INSN): Likewise.
416 (aarch64_opcode_table): Add SVE instructions.
417 * aarch64-opc.h (extract_fields): Declare.
418 * aarch64-opc-2.c: Regenerate.
419 * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
420 * aarch64-asm-2.c: Regenerate.
421 * aarch64-dis.c (extract_fields): Make global.
422 (do_misc_decoding): Handle the new SVE aarch64_ops.
423 * aarch64-dis-2.c: Regenerate.
424
116b6019
RS		 4252016-09-21 Richard Sandiford <richard.sandiford@arm.com>
426
427 * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
428 (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
429 aarch64_field_kinds.
430 * aarch64-opc.c (fields): Add corresponding entries.
431 * aarch64-asm.c (aarch64_get_variant): New function.
432 (aarch64_encode_variant_using_iclass): Likewise.
433 (aarch64_opcode_encode): Call it.
434 * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
435 (aarch64_opcode_decode): Call it.
436
047cd301
RS		 4372016-09-21 Richard Sandiford <richard.sandiford@arm.com>
438
439 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
440 and FP register operands.
441 * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
442 (FLD_SVE_Vn): New aarch64_field_kinds.
443 * aarch64-opc.c (fields): Add corresponding entries.
444 (aarch64_print_operand): Handle the new SVE core and FP register
445 operands.
446 * aarch64-opc-2.c: Regenerate.
447 * aarch64-asm-2.c: Likewise.
448 * aarch64-dis-2.c: Likewise.
449
165d4950
RS		 4502016-09-21 Richard Sandiford <richard.sandiford@arm.com>
451
452 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
453 immediate operands.
454 * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
455 * aarch64-opc.c (fields): Add corresponding entry.
456 (operand_general_constraint_met_p): Handle the new SVE FP immediate
457 operands.
458 (aarch64_print_operand): Likewise.
459 * aarch64-opc-2.c: Regenerate.
460 * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
461 (ins_sve_float_zero_one): New inserters.
462 * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
463 (aarch64_ins_sve_float_half_two): Likewise.
464 (aarch64_ins_sve_float_zero_one): Likewise.
465 * aarch64-asm-2.c: Regenerate.
466 * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
467 (ext_sve_float_zero_one): New extractors.
468 * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
469 (aarch64_ext_sve_float_half_two): Likewise.
470 (aarch64_ext_sve_float_zero_one): Likewise.
471 * aarch64-dis-2.c: Regenerate.
472
e950b345
RS		 4732016-09-21 Richard Sandiford <richard.sandiford@arm.com>
474
475 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
476 integer immediate operands.
477 * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
478 (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
479 (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
480 * aarch64-opc.c (fields): Add corresponding entries.
481 (operand_general_constraint_met_p): Handle the new SVE integer
482 immediate operands.
483 (aarch64_print_operand): Likewise.
484 (aarch64_sve_dupm_mov_immediate_p): New function.
485 * aarch64-opc-2.c: Regenerate.
486 * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
487 (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
488 * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
489 (aarch64_ins_limm): ...here.
490 (aarch64_ins_inv_limm): New function.
491 (aarch64_ins_sve_aimm): Likewise.
492 (aarch64_ins_sve_asimm): Likewise.
493 (aarch64_ins_sve_limm_mov): Likewise.
494 (aarch64_ins_sve_shlimm): Likewise.
495 (aarch64_ins_sve_shrimm): Likewise.
496 * aarch64-asm-2.c: Regenerate.
497 * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
498 (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
499 * aarch64-dis.c (decode_limm): New function, split out from...
500 (aarch64_ext_limm): ...here.
501 (aarch64_ext_inv_limm): New function.
502 (decode_sve_aimm): Likewise.
503 (aarch64_ext_sve_aimm): Likewise.
504 (aarch64_ext_sve_asimm): Likewise.
505 (aarch64_ext_sve_limm_mov): Likewise.
506 (aarch64_top_bit): Likewise.
507 (aarch64_ext_sve_shlimm): Likewise.
508 (aarch64_ext_sve_shrimm): Likewise.
509 * aarch64-dis-2.c: Regenerate.
510
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RS		 5112016-09-21 Richard Sandiford <richard.sandiford@arm.com>
512
513 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
514 operands.
515 * aarch64-opc.c (aarch64_operand_modifiers): Initialize
516 the AARCH64_MOD_MUL_VL entry.
517 (value_aligned_p): Cope with non-power-of-two alignments.
518 (operand_general_constraint_met_p): Handle the new MUL VL addresses.
519 (print_immediate_offset_address): Likewise.
520 (aarch64_print_operand): Likewise.
521 * aarch64-opc-2.c: Regenerate.
522 * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
523 (ins_sve_addr_ri_s9xvl): New inserters.
524 * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
525 (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
526 (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
527 * aarch64-asm-2.c: Regenerate.
528 * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
529 (ext_sve_addr_ri_s9xvl): New extractors.
530 * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
531 (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
532 (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
533 (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
534 * aarch64-dis-2.c: Regenerate.
535
4df068de
RS		 5362016-09-21 Richard Sandiford <richard.sandiford@arm.com>
537
538 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
539 address operands.
540 * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
541 (FLD_SVE_xs_22): New aarch64_field_kinds.
542 (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
543 (get_operand_specific_data): New function.
544 * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
545 FLD_SVE_xs_14 and FLD_SVE_xs_22.
546 (operand_general_constraint_met_p): Handle the new SVE address
547 operands.
548 (sve_reg): New array.
549 (get_addr_sve_reg_name): New function.
550 (aarch64_print_operand): Handle the new SVE address operands.
551 * aarch64-opc-2.c: Regenerate.
552 * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
553 (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
554 (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
555 * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
556 (aarch64_ins_sve_addr_rr_lsl): Likewise.
557 (aarch64_ins_sve_addr_rz_xtw): Likewise.
558 (aarch64_ins_sve_addr_zi_u5): Likewise.
559 (aarch64_ins_sve_addr_zz): Likewise.
560 (aarch64_ins_sve_addr_zz_lsl): Likewise.
561 (aarch64_ins_sve_addr_zz_sxtw): Likewise.
562 (aarch64_ins_sve_addr_zz_uxtw): Likewise.
563 * aarch64-asm-2.c: Regenerate.
564 * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
565 (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
566 (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
567 * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
568 (aarch64_ext_sve_addr_ri_u6): Likewise.
569 (aarch64_ext_sve_addr_rr_lsl): Likewise.
570 (aarch64_ext_sve_addr_rz_xtw): Likewise.
571 (aarch64_ext_sve_addr_zi_u5): Likewise.
572 (aarch64_ext_sve_addr_zz): Likewise.
573 (aarch64_ext_sve_addr_zz_lsl): Likewise.
574 (aarch64_ext_sve_addr_zz_sxtw): Likewise.
575 (aarch64_ext_sve_addr_zz_uxtw): Likewise.
576 * aarch64-dis-2.c: Regenerate.
577
2442d846
RS		 5782016-09-21 Richard Sandiford <richard.sandiford@arm.com>
579
580 * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
581 AARCH64_OPND_SVE_PATTERN_SCALED.
582 * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
583 * aarch64-opc.c (fields): Add a corresponding entry.
584 (set_multiplier_out_of_range_error): New function.
585 (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
586 (operand_general_constraint_met_p): Handle
587 AARCH64_OPND_SVE_PATTERN_SCALED.
588 (print_register_offset_address): Use PRIi64 to print the
589 shift amount.
590 (aarch64_print_operand): Likewise. Handle
591 AARCH64_OPND_SVE_PATTERN_SCALED.
592 * aarch64-opc-2.c: Regenerate.
593 * aarch64-asm.h (ins_sve_scale): New inserter.
594 * aarch64-asm.c (aarch64_ins_sve_scale): New function.
595 * aarch64-asm-2.c: Regenerate.
596 * aarch64-dis.h (ext_sve_scale): New inserter.
597 * aarch64-dis.c (aarch64_ext_sve_scale): New function.
598 * aarch64-dis-2.c: Regenerate.
599
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RS		 6002016-09-21 Richard Sandiford <richard.sandiford@arm.com>
601
602 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
603 AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
604 * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
605 (FLD_SVE_prfop): Likewise.
606 * aarch64-opc.c: Include libiberty.h.
607 (aarch64_sve_pattern_array): New variable.
608 (aarch64_sve_prfop_array): Likewise.
609 (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
610 (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
611 AARCH64_OPND_SVE_PRFOP.
612 * aarch64-asm-2.c: Regenerate.
613 * aarch64-dis-2.c: Likewise.
614 * aarch64-opc-2.c: Likewise.
615
d50c751e
RS		 6162016-09-21 Richard Sandiford <richard.sandiford@arm.com>
617
618 * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
619 AARCH64_OPND_QLF_P_[ZM].
620 (aarch64_print_operand): Print /z and /m where appropriate.
621
f11ad6bc
RS		 6222016-09-21 Richard Sandiford <richard.sandiford@arm.com>
623
624 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
625 * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
626 (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
627 (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
628 (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
629 * aarch64-opc.c (fields): Add corresponding entries here.
630 (operand_general_constraint_met_p): Check that SVE register lists
631 have the correct length. Check the ranges of SVE index registers.
632 Check for cases where p8-p15 are used in 3-bit predicate fields.
633 (aarch64_print_operand): Handle the new SVE operands.
634 * aarch64-opc-2.c: Regenerate.
635 * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
636 * aarch64-asm.c (aarch64_ins_sve_index): New function.
637 (aarch64_ins_sve_reglist): Likewise.
638 * aarch64-asm-2.c: Regenerate.
639 * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
640 * aarch64-dis.c (aarch64_ext_sve_index): New function.
641 (aarch64_ext_sve_reglist): Likewise.
642 * aarch64-dis-2.c: Regenerate.
643
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RS		 6442016-09-21 Richard Sandiford <richard.sandiford@arm.com>
645
646 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
647 (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
648 (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
649 * aarch64-opc.c (aarch64_match_operands_constraint): Check for
650 tied operands.
651
01dbfe4c
RS		 6522016-09-21 Richard Sandiford <richard.sandiford@arm.com>
653
654 * aarch64-opc.c (get_offset_int_reg_name): New function.
655 (print_immediate_offset_address): Likewise.
656 (print_register_offset_address): Take the base and offset
657 registers as parameters.
658 (aarch64_print_operand): Update caller accordingly. Use
659 print_immediate_offset_address.
660
72e9f319
RS		 6612016-09-21 Richard Sandiford <richard.sandiford@arm.com>
662
663 * aarch64-opc.c (BANK): New macro.
664 (R32, R64): Take a register number as argument
665 (int_reg): Use BANK.
666
8a7f0c1b
RS		 6672016-09-21 Richard Sandiford <richard.sandiford@arm.com>
668
669 * aarch64-opc.c (print_register_list): Add a prefix parameter.
670 (aarch64_print_operand): Update accordingly.
671
aa2aa4c6
RS		 6722016-09-21 Richard Sandiford <richard.sandiford@arm.com>
673
674 * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
675 for FPIMM.
676 * aarch64-asm.h (ins_fpimm): New inserter.
677 * aarch64-asm.c (aarch64_ins_fpimm): New function.
678 * aarch64-asm-2.c: Regenerate.
679 * aarch64-dis.h (ext_fpimm): New extractor.
680 * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
681 (aarch64_ext_fpimm): New function.
682 * aarch64-dis-2.c: Regenerate.
683
b5464a68
RS		 6842016-09-21 Richard Sandiford <richard.sandiford@arm.com>
685
686 * aarch64-asm.c: Include libiberty.h.
687 (insert_fields): New function.
688 (aarch64_ins_imm): Use it.
689 * aarch64-dis.c (extract_fields): New function.
690 (aarch64_ext_imm): Use it.
691
42408347
RS		 6922016-09-21 Richard Sandiford <richard.sandiford@arm.com>
693
694 * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
695 with an esize parameter.
696 (operand_general_constraint_met_p): Update accordingly.
697 Fix misindented code.
698 * aarch64-asm.c (aarch64_ins_limm): Update call to
699 aarch64_logical_immediate_p.
700
4989adac
RS		 7012016-09-21 Richard Sandiford <richard.sandiford@arm.com>
702
703 * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
704
bd11d5d8
RS		 7052016-09-21 Richard Sandiford <richard.sandiford@arm.com>
706
707 * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
708
f807f43d
CZ		 7092016-09-15 Claudiu Zissulescu <claziss@synopsys.com>
710
711 * arc-dis.c (find_format): Walk the linked list pointed by einsn.
712
fd486b63
PB		 7132016-09-14 Peter Bergner <bergner@vnet.ibm.com>
714
715 * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
716 <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
717 xor3>: Delete mnemonics.
718 <cp_abort>: Rename mnemonic from ...
719 <cpabort>: ...to this.
720 <setb>: Change to a X form instruction.
721 <sync>: Change to 1 operand form.
722 <copy>: Delete mnemonic.
723 <copy_first>: Rename mnemonic from ...
724 <copy>: ...to this.
725 <paste, paste.>: Delete mnemonics.
726 <paste_last>: Rename mnemonic from ...
727 <paste.>: ...to this.
728
dce08442
AK		 7292016-09-14 Anton Kolesov <Anton.Kolesov@synopsys.com>
730
731 * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
732
952c3f51
AK		 7332016-09-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
734
735 * s390-mkopc.c (main): Support alternate arch strings.
736
8b71537b
PS		 7372016-09-12 Patrick Steuer <steuer@linux.vnet.ibm.com>
738
739 * s390-opc.txt: Fix kmctr instruction type.
740
5b64d091
L		 7412016-09-07 H.J. Lu <hongjiu.lu@intel.com>
742
743 * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
744 * i386-init.h: Regenerated.
745
7763838e
CM		 7462016-08-30 Cupertino Miranda <cmiranda@synopsys.com>
747
748 * opcodes/arc-dis.c (print_insn_arc): Changed.
749
1b8b6532
JM		 7502016-08-26 Jose E. Marchesi <jose.marchesi@oracle.com>
751
752 * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
753 camellia_fl.
754
1a336194
TP		 7552016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
756
757 * arm-dis.c (psr_name): Use hex as case labels. Add detection for
758 MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
759 FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
760
6b40c462
L		 7612016-08-24 H.J. Lu <hongjiu.lu@intel.com>
762
763 * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
764 (PREFIX_MOD_3_0FAE_REG_4): Likewise.
765 (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
766 PREFIX_MOD_3_0FAE_REG_4.
767 (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
768 PREFIX_MOD_3_0FAE_REG_4.
769 * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
770 (cpu_flags): Add CpuPTWRITE.
771 * i386-opc.h (CpuPTWRITE): New.
772 (i386_cpu_flags): Add cpuptwrite.
773 * i386-opc.tbl: Add ptwrite instruction.
774 * i386-init.h: Regenerated.
775 * i386-tbl.h: Likewise.
776
ab548d2d
AK		 7772016-08-24 Anton Kolesov <Anton.Kolesov@synopsys.com>
778
779 * arc-dis.h: Wrap around in extern "C".
780
344bde0a
RS		 7812016-08-23 Richard Sandiford <richard.sandiford@arm.com>
782
783 * aarch64-tbl.h (V8_2_INSN): New macro.
784 (aarch64_opcode_table): Use it.
785
5ce912d8
RS		 7862016-08-23 Richard Sandiford <richard.sandiford@arm.com>
787
788 * aarch64-tbl.h (aarch64_opcode_table): Make more use of
789 CORE_INSN, __FP_INSN and SIMD_INSN.
790
9d30b0bd
RS		 7912016-08-23 Richard Sandiford <richard.sandiford@arm.com>
792
793 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
794 (aarch64_opcode_table): Update uses accordingly.
795
dfdaec14
AJ		 7962016-07-25 Andrew Jenner <andrew@codesourcery.com>
797 Kwok Cheung Yeung <kcy@codesourcery.com>
798
799 opcodes/
800 * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
801 'e_cmplwi' to 'e_cmpli' instead.
802 (OPVUPRT, OPVUPRT_MASK): Define.
803 (powerpc_opcodes): Add E200Z4 insns.
804 (vle_opcodes): Add context save/restore insns.
805
7bd374a4
MR		 8062016-07-27 Maciej W. Rozycki <macro@imgtec.com>
807
808 * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
809 "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
810 "j".
811
db18dbab
GM		 8122016-07-27 Graham Markall <graham.markall@embecosm.com>
813
814 * arc-nps400-tbl.h: Change block comments to GNU format.
815 * arc-dis.c: Add new globals addrtypenames,
816 addrtypenames_max, and addtypeunknown.
817 (get_addrtype): New function.
818 (print_insn_arc): Print colons and address types when
819 required.
820 * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
821 define insert and extract functions for all address types.
822 (arc_operands): Add operands for colon and all address
823 types.
824 * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
825 * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
826 insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
827 * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
828 * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
829 insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
830
fecd57f9
L		 8312016-07-21 H.J. Lu <hongjiu.lu@intel.com>
832
833 * configure: Regenerated.
834
37fd5ef3
CZ		 8352016-07-20 Claudiu Zissulescu <claziss@synopsys.com>
836
837 * arc-dis.c (skipclass): New structure.
838 (decodelist): New variable.
839 (is_compatible_p): New function.
840 (new_element): Likewise.
841 (skip_class_p): Likewise.
842 (find_format_from_table): Use skip_class_p function.
843 (find_format): Decode first the extension instructions.
844 (print_insn_arc): Select either ARCEM or ARCHS based on elf
845 e_flags.
846 (parse_option): New function.
847 (parse_disassembler_options): Likewise.
848 (print_arc_disassembler_options): Likewise.
849 (print_insn_arc): Use parse_disassembler_options function. Proper
850 select ARCv2 cpu variant.
851 * disassemble.c (disassembler_usage): Add ARC disassembler
852 options.
853
92281a5b
MR		 8542016-07-13 Maciej W. Rozycki <macro@imgtec.com>
855
856 * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
857 annotation from the "nal" entry and reorder it beyond "bltzal".
858
6e7ced37
JM		 8592016-07-12 Jose E. Marchesi <jose.marchesi@oracle.com>
860
861 * sparc-opc.c (ldtxa): New macro.
862 (sparc_opcodes): Use the macro defined above to add entries for
863 the LDTXA instructions.
864 (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
865 instruction.
866
2f831b9a 8672016-07-07 James Bowman <james.bowman@ftdichip.com>
868
869 * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
870 and "jmpc".
871
c07315e0
JB		 8722016-07-01 Jan Beulich <jbeulich@suse.com>
873
874 * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
875 (movzb): Adjust to cover all permitted suffixes.
876 (movzw): New.
877 * i386-tbl.h: Re-generate.
878
9243100a
JB		 8792016-07-01 Jan Beulich <jbeulich@suse.com>
880
881 * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
882 (lgdt): Remove Tbyte from non-64-bit variant.
883 (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
884 xsaves64, xsavec64): Remove Disp16.
885 (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
886 Remove Disp32S from non-64-bit variants. Remove Disp16 from
887 64-bit variants.
888 (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
889 vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
890 vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
891 64-bit variants.
892 * i386-tbl.h: Re-generate.
893
8325cc63
JB		 8942016-07-01 Jan Beulich <jbeulich@suse.com>
895
896 * i386-opc.tbl (xlat): Remove RepPrefixOk.
897 * i386-tbl.h: Re-generate.
898
838441e4
YQ		 8992016-06-30 Yao Qi <yao.qi@linaro.org>
900
901 * arm-dis.c (print_insn): Fix typo in comment.
902
dab26bf4
RS		 9032016-06-28 Richard Sandiford <richard.sandiford@arm.com>
904
905 * aarch64-opc.c (operand_general_constraint_met_p): Check the
906 range of ldst_elemlist operands.
907 (print_register_list): Use PRIi64 to print the index.
908 (aarch64_print_operand): Likewise.
909
5703197e
TS		 9102016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
911
912 * mcore-opc.h: Remove sentinal.
913 * mcore-dis.c (print_insn_mcore): Adjust.
914
ce440d63
GM		 9152016-06-23 Graham Markall <graham.markall@embecosm.com>
916
917 * arc-opc.c: Correct description of availability of NPS400
918 features.
919
6fd3a02d
PB		 9202016-06-22 Peter Bergner <bergner@vnet.ibm.com>
921
922 * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
923 (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
924 mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
925 xor3>: New mnemonics.
926 <setb>: Change to a VX form instruction.
927 (insert_sh6): Add support for rldixor.
928 (extract_sh6): Likewise.
929
6b477896
TS		 9302016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
931
932 * arc-ext.h: Wrap in extern C.
933
bdd582db
GM		 9342016-06-21 Graham Markall <graham.markall@embecosm.com>
935
936 * arc-dis.c (arc_insn_length): Add comment on instruction length.
937 Use same method for determining instruction length on ARC700 and
938 NPS-400.
939 (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
940 * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
941 with the NPS400 subclass.
942 * arc-opc.c: Likewise.
943
96074adc
JM		 9442016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
945
946 * sparc-opc.c (rdasr): New macro.
947 (wrasr): Likewise.
948 (rdpr): Likewise.
949 (wrpr): Likewise.
950 (rdhpr): Likewise.
951 (wrhpr): Likewise.
952 (sparc_opcodes): Use the macros above to fix and expand the
953 definition of read/write instructions from/to
954 asr/privileged/hyperprivileged instructions.
955 * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
956 %hva_mask_nz. Prefer softint_set and softint_clear over
957 set_softint and clear_softint.
958 (print_insn_sparc): Support %ver in Rd.
959
7a10c22f
JM		 9602016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
961
962 * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
963 architecture according to the hardware capabilities they require.
964
4f26fb3a
JM		 9652016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
966
967 * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
968 (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
969 bfd_mach_sparc_v9{c,d,e,v,m}.
970 * sparc-opc.c (MASK_V9C): Define.
971 (MASK_V9D): Likewise.
972 (MASK_V9E): Likewise.
973 (MASK_V9V): Likewise.
974 (MASK_V9M): Likewise.
975 (v6): Add MASK_V9{C,D,E,V,M}.
976 (v6notlet): Likewise.
977 (v7): Likewise.
978 (v8): Likewise.
979 (v9): Likewise.
980 (v9andleon): Likewise.
981 (v9a): Likewise.
982 (v9b): Likewise.
983 (v9c): Define.
984 (v9d): Likewise.
985 (v9e): Likewise.
986 (v9v): Likewise.
987 (v9m): Likewise.
988 (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
989
3ee6e4fb
NC		 9902016-06-15 Nick Clifton <nickc@redhat.com>
991
992 * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
993 constants to match expected behaviour.
994 (nds32_parse_opcode): Likewise. Also for whitespace.
995
02f3be19
AB		 9962016-06-15 Andrew Burgess <andrew.burgess@embecosm.com>
997
998 * arc-opc.c (extract_rhv1): Extract value from insn.
999
6f9f37ed 10002016-06-14 Graham Markall <graham.markall@embecosm.com>
28215275
GM		 1001
1002 * arc-nps400-tbl.h: Add ldbit instruction.
1003 * arc-opc.c: Add flag classes required for ldbit.
1004
6f9f37ed 10052016-06-14 Graham Markall <graham.markall@embecosm.com>
9ba75c88
GM		 1006
1007 * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
1008 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1009 support the above instructions.
1010
6f9f37ed 10112016-06-14 Graham Markall <graham.markall@embecosm.com>
14053c19
GM		 1012
1013 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
1014 imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
1015 csma, cbba, zncv, and hofs.
1016 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1017 support the above instructions.
1018
10192016-06-06 Graham Markall <graham.markall@embecosm.com>
1020
1021 * arc-nps400-tbl.h: Add andab and orab instructions.
1022
10232016-06-06 Graham Markall <graham.markall@embecosm.com>
1024
1025 * arc-nps400-tbl.h: Add addl-like instructions.
1026
10272016-06-06 Graham Markall <graham.markall@embecosm.com>
1028
1029 * arc-nps400-tbl.h: Add mxb and imxb instructions.
1030
10312016-06-06 Graham Markall <graham.markall@embecosm.com>
1032
1033 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
1034 instructions.
1035
b2cc3f6f
AK		 10362016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1037
1038 * s390-dis.c (option_use_insn_len_bits_p): New file scope
1039 variable.
1040 (init_disasm): Handle new command line option "insnlength".
1041 (print_s390_disassembler_options): Mention new option in help
1042 output.
1043 (print_insn_s390): Use the encoded insn length when dumping
1044 unknown instructions.
1045
1857fe72
DC		 10462016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
1047
1048 * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
1049 to the address and set as symbol address for LDS/ STS immediate operands.
1050
14b57c7c
AM		 10512016-06-07 Alan Modra <amodra@gmail.com>
1052
1053 * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
1054 cpu for "vle" to e500.
1055 * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
1056 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
1057 (PPCNONE): Delete, substitute throughout.
1058 (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
1059 except for major opcode 4 and 31.
1060 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
1061
4d1464f2
MW		 10622016-06-07 Matthew Wahab <matthew.wahab@arm.com>
1063
1064 * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
1065 ARM_EXT_RAS in relevant entries.
1066
026122a6
PB		 10672016-06-03 Peter Bergner <bergner@vnet.ibm.com>
1068
1069 PR binutils/20196
1070 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
1071 opcodes for E6500.
1072
07f5af7d
L		 10732016-06-03 H.J. Lu <hongjiu.lu@intel.com>
1074
1075 PR binutis/18386
1076 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
1077 (indir_v_mode): New.
1078 Add comments for '&'.
1079 (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
1080 (putop): Handle '&'.
1081 (intel_operand_size): Handle indir_v_mode.
1082 (OP_E_register): Likewise.
1083 * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
1084 64-bit indirect call/jmp for AMD64.
1085 * i386-tbl.h: Regenerated
1086
4eb6f892
AB		 10872016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
1088
1089 * arc-dis.c (struct arc_operand_iterator): New structure.
1090 (find_format_from_table): All the old content from find_format,
1091 with some minor adjustments, and parameter renaming.
1092 (find_format_long_instructions): New function.
1093 (find_format): Rewritten.
1094 (arc_insn_length): Add LSB parameter.
1095 (extract_operand_value): New function.
1096 (operand_iterator_next): New function.
1097 (print_insn_arc): Use new functions to find opcode, and iterator
1098 over operands.
1099 * arc-opc.c (insert_nps_3bit_dst_short): New function.
1100 (extract_nps_3bit_dst_short): New function.
1101 (insert_nps_3bit_src2_short): New function.
1102 (extract_nps_3bit_src2_short): New function.
1103 (insert_nps_bitop1_size): New function.
1104 (extract_nps_bitop1_size): New function.
1105 (insert_nps_bitop2_size): New function.
1106 (extract_nps_bitop2_size): New function.
1107 (insert_nps_bitop_mod4_msb): New function.
1108 (extract_nps_bitop_mod4_msb): New function.
1109 (insert_nps_bitop_mod4_lsb): New function.
1110 (extract_nps_bitop_mod4_lsb): New function.
1111 (insert_nps_bitop_dst_pos3_pos4): New function.
1112 (extract_nps_bitop_dst_pos3_pos4): New function.
1113 (insert_nps_bitop_ins_ext): New function.
1114 (extract_nps_bitop_ins_ext): New function.
1115 (arc_operands): Add new operands.
1116 (arc_long_opcodes): New global array.
1117 (arc_num_long_opcodes): New global.
1118 * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
1119
1fe0971e
TS		 11202016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1121
1122 * nds32-asm.h: Add extern "C".
1123 * sh-opc.h: Likewise.
1124
315f180f
GM		 11252016-06-01 Graham Markall <graham.markall@embecosm.com>
1126
1127 * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
1128 0,b,limm to the rflt instruction.
1129
a2b5fccc
TS		 11302016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1131
1132 * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
1133 constant.
1134
0cbd0046
L		 11352016-05-29 H.J. Lu <hongjiu.lu@intel.com>
1136
1137 PR gas/20145
1138 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
1139 CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
1140 CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
1141 CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
1142 CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
1143 * i386-init.h: Regenerated.
1144
1848e567
L		 11452016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1146
1147 PR gas/20145
1148 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
1149 CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
1150 CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
1151 Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
1152 CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
1153 CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
1154 CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
1155 Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
1156 CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
1157 CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
1158 CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
1159 for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
1160 CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
1161 CpuRegMask for AVX512.
1162 (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
1163 and CpuRegMask.
1164 (set_bitfield_from_cpu_flag_init): New function.
1165 (set_bitfield): Remove const on f. Call
1166 set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
1167 * i386-opc.h (CpuRegMMX): New.
1168 (CpuRegXMM): Likewise.
1169 (CpuRegYMM): Likewise.
1170 (CpuRegZMM): Likewise.
1171 (CpuRegMask): Likewise.
1172 (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
1173 and cpuregmask.
1174 * i386-init.h: Regenerated.
1175 * i386-tbl.h: Likewise.
1176
e92bae62
L		 11772016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1178
1179 PR gas/20154
1180 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
1181 (opcode_modifiers): Add AMD64 and Intel64.
1182 (main): Properly verify CpuMax.
1183 * i386-opc.h (CpuAMD64): Removed.
1184 (CpuIntel64): Likewise.
1185 (CpuMax): Set to CpuNo64.
1186 (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
1187 (AMD64): New.
1188 (Intel64): Likewise.
1189 (i386_opcode_modifier): Add amd64 and intel64.
1190 (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
1191 on call and jmp.
1192 * i386-init.h: Regenerated.
1193 * i386-tbl.h: Likewise.
1194
e89c5eaa
L		 11952016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1196
1197 PR gas/20154
1198 * i386-gen.c (main): Fail if CpuMax is incorrect.
1199 * i386-opc.h (CpuMax): Set to CpuIntel64.
1200 * i386-tbl.h: Regenerated.
1201
77d66e7b
NC		 12022016-05-27 Nick Clifton <nickc@redhat.com>
1203
1204 PR target/20150
1205 * msp430-dis.c (msp430dis_read_two_bytes): New function.
1206 (msp430dis_opcode_unsigned): New function.
1207 (msp430dis_opcode_signed): New function.
1208 (msp430_singleoperand): Use the new opcode reading functions.
1209 Only disassenmble bytes if they were successfully read.
1210 (msp430_doubleoperand): Likewise.
1211 (msp430_branchinstr): Likewise.
1212 (msp430x_callx_instr): Likewise.
1213 (print_insn_msp430): Check that it is safe to read bytes before
1214 attempting disassembly. Use the new opcode reading functions.
1215
19dfcc89
PB		 12162016-05-26 Peter Bergner <bergner@vnet.ibm.com>
1217
1218 * ppc-opc.c (CY): New define. Document it.
1219 (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
1220
f3ad7637
L		 12212016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1222
1223 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
1224 CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
1225 and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
1226 CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
1227 CPU_ANY_AVX_FLAGS.
1228 * i386-init.h: Regenerated.
1229
f1360d58
L		 12302016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1231
1232 PR gas/20141
1233 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
1234 CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
1235 * i386-init.h: Regenerated.
1236
293f5f65
L		 12372016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1238
1239 * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
1240 CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
1241 * i386-init.h: Regenerated.
1242
d9eca1df
CZ		 12432016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1244
1245 * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
1246 information.
1247 (print_insn_arc): Set insn_type information.
1248 * arc-opc.c (C_CC): Add F_CLASS_COND.
1249 * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
1250 (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
1251 (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
1252 (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
1253 (brne, brne_s, jeq_s, jne_s): Likewise.
1254
87789e08
CZ		 12552016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1256
1257 * arc-tbl.h (neg): New instruction variant.
1258
c810e0b8
CZ		 12592016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
1260
1261 * arc-dis.c (find_format, find_format, get_auxreg)
1262 (print_insn_arc): Changed.
1263 * arc-ext.h (INSERT_XOP): Likewise.
1264
3d207518
TS		 12652016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1266
1267 * tic54x-dis.c (sprint_mmr): Adjust.
1268 * tic54x-opc.c: Likewise.
1269
514e58b7
AM		 12702016-05-19 Alan Modra <amodra@gmail.com>
1271
1272 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
1273
e43de63c
AM		 12742016-05-19 Alan Modra <amodra@gmail.com>
1275
1276 * ppc-opc.c: Formatting.
1277 (NSISIGNOPT): Define.
1278 (powerpc_opcodes <subis>): Use NSISIGNOPT.
1279
1401d2fe
MR		 12802016-05-18 Maciej W. Rozycki <macro@imgtec.com>
1281
1282 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
1283 replacing references to `micromips_ase' throughout.
1284 (_print_insn_mips): Don't use file-level microMIPS annotation to
1285 determine the disassembly mode with the symbol table.
1286
1178da44
PB		 12872016-05-13 Peter Bergner <bergner@vnet.ibm.com>
1288
1289 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
1290
8f4f9071
MF		 12912016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
1292
1293 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
1294 mips64r6.
1295 * mips-opc.c (D34): New macro.
1296 (mips_builtin_opcodes): Define bposge32c for DSPr3.
1297
8bc52696
AF		 12982016-05-10 Alexander Fomin <alexander.fomin@intel.com>
1299
1300 * i386-dis.c (prefix_table): Add RDPID instruction.
1301 * i386-gen.c (cpu_flag_init): Add RDPID flag.
1302 (cpu_flags): Add RDPID bitfield.
1303 * i386-opc.h (enum): Add RDPID element.
1304 (i386_cpu_flags): Add RDPID field.
1305 * i386-opc.tbl: Add RDPID instruction.
1306 * i386-init.h: Regenerate.
1307 * i386-tbl.h: Regenerate.
1308
39d911fc
TP		 13092016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1310
1311 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
1312 branch type of a symbol.
1313 (print_insn): Likewise.
1314
16a1fa25
TP		 13152016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1316
1317 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1318 Mainline Security Extensions instructions.
1319 (thumb_opcodes): Add entries for narrow ARMv8-M Security
1320 Extensions instructions.
1321 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1322 instructions.
1323 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1324 special registers.
1325
d751b79e
JM		 13262016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
1327
1328 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1329
945e0f82
CZ		 13302016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
1331
1332 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1333 (arcExtMap_genOpcode): Likewise.
1334 * arc-opc.c (arg_32bit_rc): Define new variable.
1335 (arg_32bit_u6): Likewise.
1336 (arg_32bit_limm): Likewise.
1337
20f55f38
SN		 13382016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
1339
1340 * aarch64-gen.c (VERIFIER): Define.
1341 * aarch64-opc.c (VERIFIER): Define.
1342 (verify_ldpsw): Use static linkage.
1343 * aarch64-opc.h (verify_ldpsw): Remove.
1344 * aarch64-tbl.h: Use VERIFIER for verifiers.
1345
4bd13cde
NC		 13462016-04-28 Nick Clifton <nickc@redhat.com>
1347
1348 PR target/19722
1349 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1350 * aarch64-opc.c (verify_ldpsw): New function.
1351 * aarch64-opc.h (verify_ldpsw): New prototype.
1352 * aarch64-tbl.h: Add initialiser for verifier field.
1353 (LDPSW): Set verifier to verify_ldpsw.
1354
c0f92bf9
L		 13552016-04-23 H.J. Lu <hongjiu.lu@intel.com>
1356
1357 PR binutils/19983
1358 PR binutils/19984
1359 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1360 smaller than address size.
1361
e6c7cdec
TS		 13622016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1363
1364 * alpha-dis.c: Regenerate.
1365 * crx-dis.c: Likewise.
1366 * disassemble.c: Likewise.
1367 * epiphany-opc.c: Likewise.
1368 * fr30-opc.c: Likewise.
1369 * frv-opc.c: Likewise.
1370 * ip2k-opc.c: Likewise.
1371 * iq2000-opc.c: Likewise.
1372 * lm32-opc.c: Likewise.
1373 * lm32-opinst.c: Likewise.
1374 * m32c-opc.c: Likewise.
1375 * m32r-opc.c: Likewise.
1376 * m32r-opinst.c: Likewise.
1377 * mep-opc.c: Likewise.
1378 * mt-opc.c: Likewise.
1379 * or1k-opc.c: Likewise.
1380 * or1k-opinst.c: Likewise.
1381 * tic80-opc.c: Likewise.
1382 * xc16x-opc.c: Likewise.
1383 * xstormy16-opc.c: Likewise.
1384
537aefaf
AB		 13852016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1386
1387 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1388 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1389 calcsd, and calcxd instructions.
1390 * arc-opc.c (insert_nps_bitop_size): Delete.
1391 (extract_nps_bitop_size): Delete.
1392 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1393 (extract_nps_qcmp_m3): Define.
1394 (extract_nps_qcmp_m2): Define.
1395 (extract_nps_qcmp_m1): Define.
1396 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1397 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1398 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1399 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1400 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1401 NPS_QCMP_M3.
1402
c8f785f2
AB		 14032016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1404
1405 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1406
6fd8e7c2
L		 14072016-04-15 H.J. Lu <hongjiu.lu@intel.com>
1408
1409 * Makefile.in: Regenerated with automake 1.11.6.
1410 * aclocal.m4: Likewise.
1411
4b0c052e
AB		 14122016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1413
1414 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1415 instructions.
1416 * arc-opc.c (insert_nps_cmem_uimm16): New function.
1417 (extract_nps_cmem_uimm16): New function.
1418 (arc_operands): Add NPS_XLDST_UIMM16 operand.
1419
cb040366
AB		 14202016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1421
1422 * arc-dis.c (arc_insn_length): New function.
1423 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1424 (find_format): Change insnLen parameter to unsigned.
1425
accc0180
NC		 14262016-04-13 Nick Clifton <nickc@redhat.com>
1427
1428 PR target/19937
1429 * v850-opc.c (v850_opcodes): Correct masks for long versions of
1430 the LD.B and LD.BU instructions.
1431
f36e33da
CZ		 14322016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1433
1434 * arc-dis.c (find_format): Check for extension flags.
1435 (print_flags): New function.
1436 (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1437 .extAuxRegister.
1438 * arc-ext.c (arcExtMap_coreRegName): Use
1439 LAST_EXTENSION_CORE_REGISTER.
1440 (arcExtMap_coreReadWrite): Likewise.
1441 (dump_ARC_extmap): Update printing.
1442 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1443 (arc_aux_regs): Add cpu field.
1444 * arc-regs.h: Add cpu field, lower case name aux registers.
1445
1c2e355e
CZ		 14462016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1447
1448 * arc-tbl.h: Add rtsc, sleep with no arguments.
1449
b99747ae
CZ		 14502016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1451
1452 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1453 Initialize.
1454 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1455 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1456 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1457 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1458 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1459 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1460 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1461 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1462 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1463 (arc_opcode arc_opcodes): Null terminate the array.
1464 (arc_num_opcodes): Remove.
1465 * arc-ext.h (INSERT_XOP): Define.
1466 (extInstruction_t): Likewise.
1467 (arcExtMap_instName): Delete.
1468 (arcExtMap_insn): New function.
1469 (arcExtMap_genOpcode): Likewise.
1470 * arc-ext.c (ExtInstruction): Remove.
1471 (create_map): Zero initialize instruction fields.
1472 (arcExtMap_instName): Remove.
1473 (arcExtMap_insn): New function.
1474 (dump_ARC_extmap): More info while debuging.
1475 (arcExtMap_genOpcode): New function.
1476 * arc-dis.c (find_format): New function.
1477 (print_insn_arc): Use find_format.
1478 (arc_get_disassembler): Enable dump_ARC_extmap only when
1479 debugging.
1480
92708cec
MR		 14812016-04-11 Maciej W. Rozycki <macro@imgtec.com>
1482
1483 * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1484 instruction bits out.
1485
a42a4f84
AB		 14862016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1487
1488 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1489 * arc-opc.c (arc_flag_operands): Add new flags.
1490 (arc_flag_classes): Add new classes.
1491
1328504b
AB		 14922016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1493
1494 * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1495
820f03ff
AB		 14962016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
1497
1498 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1499 encode1, rflt, crc16, and crc32 instructions.
1500 * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1501 (arc_flag_classes): Add C_NPS_R.
1502 (insert_nps_bitop_size_2b): New function.
1503 (extract_nps_bitop_size_2b): Likewise.
1504 (insert_nps_bitop_uimm8): Likewise.
1505 (extract_nps_bitop_uimm8): Likewise.
1506 (arc_operands): Add new operand entries.
1507
8ddf6b2a
CZ		 15082016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
1509
b99747ae
CZ		 1510 * arc-regs.h: Add a new subclass field. Add double assist
1511 accumulator register values.
1512 * arc-tbl.h: Use DPA subclass to mark the double assist
1513 instructions. Use DPX/SPX subclas to mark the FPX instructions.
1514 * arc-opc.c (RSP): Define instead of SP.
1515 (arc_aux_regs): Add the subclass field.
8ddf6b2a 1516
589a7d88
JW		 15172016-04-05 Jiong Wang <jiong.wang@arm.com>
1518
1519 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1520
0a191de9 15212016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
2cce10e7
AB		 1522
1523 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1524 NPS_R_SRC1.
1525
0a106562
AB		 15262016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
1527
1528 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1529 issues. No functional changes.
1530
bd05ac5f
CZ		 15312016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
1532
b99747ae
CZ		 1533 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1534 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1535 (RTT): Remove duplicate.
1536 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1537 (PCT_CONFIG*): Remove.
1538 (D1L, D1H, D2H, D2L): Define.
bd05ac5f 1539
9885948f
CZ		 15402016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1541
b99747ae 1542 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
9885948f 1543
f2dd8838
CZ		 15442016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1545
b99747ae
CZ		 1546 * arc-tbl.h (invld07): Remove.
1547 * arc-ext-tbl.h: New file.
1548 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1549 * arc-opc.c (arc_opcodes): Add ext-tbl include.
f2dd8838 1550
0d2f91fe
JK		 15512016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
1552
1553 Fix -Wstack-usage warnings.
1554 * aarch64-dis.c (print_operands): Substitute size.
1555 * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1556
a6b71f42
JM		 15572016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
1558
1559 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1560 to get a proper diagnostic when an invalid ASR register is used.
1561
9780e045
NC		 15622016-03-22 Nick Clifton <nickc@redhat.com>
1563
1564 * configure: Regenerate.
1565
e23e8ebe
AB		 15662016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1567
1568 * arc-nps400-tbl.h: New file.
1569 * arc-opc.c: Add top level comment.
1570 (insert_nps_3bit_dst): New function.
1571 (extract_nps_3bit_dst): New function.
1572 (insert_nps_3bit_src2): New function.
1573 (extract_nps_3bit_src2): New function.
1574 (insert_nps_bitop_size): New function.
1575 (extract_nps_bitop_size): New function.
1576 (arc_flag_operands): Add nps400 entries.
1577 (arc_flag_classes): Add nps400 entries.
1578 (arc_operands): Add nps400 entries.
1579 (arc_opcodes): Add nps400 include.
1580
1ae8ab47
AB		 15812016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1582
1583 * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1584 the new class enum values.
1585
8699fc3e
AB		 15862016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1587
1588 * arc-dis.c (print_insn_arc): Handle nps400.
1589
24740d83
AB		 15902016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1591
1592 * arc-opc.c (BASE): Delete.
1593
8678914f
NC		 15942016-03-18 Nick Clifton <nickc@redhat.com>
1595
1596 PR target/19721
1597 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1598 of MOV insn that aliases an ORR insn.
1599
cc933301
JW		 16002016-03-16 Jiong Wang <jiong.wang@arm.com>
1601
1602 * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1603
f86f5863
TS		 16042016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1605
1606 * mcore-opc.h: Add const qualifiers.
1607 * microblaze-opc.h (struct op_code_struct): Likewise.
1608 * sh-opc.h: Likewise.
1609 * tic4x-dis.c (tic4x_print_indirect): Likewise.
1610 (tic4x_print_op): Likewise.
1611
62de1c63
AM		 16122016-03-02 Alan Modra <amodra@gmail.com>
1613
d11698cd 1614 * or1k-desc.h: Regenerate.
62de1c63 1615 * fr30-ibld.c: Regenerate.
c697cf0b 1616 * rl78-decode.c: Regenerate.
62de1c63 1617
020efce5
NC		 16182016-03-01 Nick Clifton <nickc@redhat.com>
1619
1620 PR target/19747
1621 * rl78-dis.c (print_insn_rl78_common): Fix typo.
1622
b0c11777
RL		 16232016-02-24 Renlin Li <renlin.li@arm.com>
1624
1625 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1626 (print_insn_coprocessor): Support fp16 instructions.
1627
3e309328
RL		 16282016-02-24 Renlin Li <renlin.li@arm.com>
1629
1630 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1631 vminnm, vrint(mpna).
1632
8afc7bea
RL		 16332016-02-24 Renlin Li <renlin.li@arm.com>
1634
1635 * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1636 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1637
4fd7268a
L		 16382016-02-15 H.J. Lu <hongjiu.lu@intel.com>
1639
1640 * i386-dis.c (print_insn): Parenthesize expression to prevent
1641 truncated addresses.
1642 (OP_J): Likewise.
1643
4670103e
CZ		 16442016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
1645 Janek van Oirschot <jvanoirs@synopsys.com>
1646
b99747ae
CZ		 1647 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1648 variable.
4670103e 1649
c1d9289f
NC		 16502016-02-04 Nick Clifton <nickc@redhat.com>
1651
1652 PR target/19561
1653 * msp430-dis.c (print_insn_msp430): Add a special case for
1654 decoding an RRC instruction with the ZC bit set in the extension
1655 word.
1656
a143b004
AB		 16572016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1658
1659 * cgen-ibld.in (insert_normal): Rework calculation of shift.
1660 * epiphany-ibld.c: Regenerate.
1661 * fr30-ibld.c: Regenerate.
1662 * frv-ibld.c: Regenerate.
1663 * ip2k-ibld.c: Regenerate.
1664 * iq2000-ibld.c: Regenerate.
1665 * lm32-ibld.c: Regenerate.
1666 * m32c-ibld.c: Regenerate.
1667 * m32r-ibld.c: Regenerate.
1668 * mep-ibld.c: Regenerate.
1669 * mt-ibld.c: Regenerate.
1670 * or1k-ibld.c: Regenerate.
1671 * xc16x-ibld.c: Regenerate.
1672 * xstormy16-ibld.c: Regenerate.
1673
b89807c6
AB		 16742016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1675
1676 * epiphany-dis.c: Regenerated from latest cpu files.
1677
d8c823c8
MM		 16782016-02-01 Michael McConville <mmcco@mykolab.com>
1679
1680 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1681 test bit.
1682
5bc5ae88
RL		 16832016-01-25 Renlin Li <renlin.li@arm.com>
1684
1685 * arm-dis.c (mapping_symbol_for_insn): New function.
1686 (find_ifthen_state): Call mapping_symbol_for_insn().
1687
0bff6e2d
MW		 16882016-01-20 Matthew Wahab <matthew.wahab@arm.com>
1689
1690 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1691 of MSR UAO immediate operand.
1692
100b4f2e
MR		 16932016-01-18 Maciej W. Rozycki <macro@imgtec.com>
1694
1695 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1696 instruction support.
1697
5c14705f
AM		 16982016-01-17 Alan Modra <amodra@gmail.com>
1699
1700 * configure: Regenerate.
1701
4d82fe66
NC		 17022016-01-14 Nick Clifton <nickc@redhat.com>
1703
1704 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1705 instructions that can support stack pointer operations.
1706 * rl78-decode.c: Regenerate.
1707 * rl78-dis.c: Fix display of stack pointer in MOVW based
1708 instructions.
1709
651657fa
MW		 17102016-01-14 Matthew Wahab <matthew.wahab@arm.com>
1711
1712 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1713 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
1714 erxtatus_el1 and erxaddr_el1.
1715
105bde57
MW		 17162016-01-12 Matthew Wahab <matthew.wahab@arm.com>
1717
1718 * arm-dis.c (arm_opcodes): Add "esb".
1719 (thumb_opcodes): Likewise.
1720
afa8d405
PB		 17212016-01-11 Peter Bergner <bergner@vnet.ibm.com>
1722
1723 * ppc-opc.c <xscmpnedp>: Delete.
1724 <xvcmpnedp>: Likewise.
1725 <xvcmpnedp.>: Likewise.
1726 <xvcmpnesp>: Likewise.
1727 <xvcmpnesp.>: Likewise.
1728
83c3256e
AS		 17292016-01-08 Andreas Schwab <schwab@linux-m68k.org>
1730
1731 PR gas/13050
1732 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1733 addition to ISA_A.
1734
6f2750fe
AM		 17352016-01-01 Alan Modra <amodra@gmail.com>
1736
1737 Update year range in copyright notice of all files.
1738
3499769a
AM		 1739For older changes see ChangeLog-2015
1740\f
1741Copyright (C) 2016 Free Software Foundation, Inc.
1742
1743Copying and distribution of this file, with or without modification,
1744are permitted in any medium without royalty provided the copyright
1745notice and this notice are preserved.
1746
1747Local Variables:
1748mode: change-log
1749left-margin: 8
1750fill-column: 74
1751version-control: never
1752End:
GDB Binutils - Deliverables
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