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Stop using nowarnings in gdb/testsuite/gdb.multi/
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
6479e48e
MW		 12015-12-10 Matthew Wahab <matthew.wahab@arm.com>
2
3 * aarch64-opc.c (aarch64_sys_regs): Add "uao".
4 (aarch64_sys_reg_supported_p): Add comment. Add checks for "uao".
5 (aarch64_pstatefields): Add "uao".
6 (aarch64_pstatefield_supported_p): Add checks for "uao".
7
47f81142
MW		 82015-12-10 Matthew Wahab <matthew.wahab@arm.com>
9
10 * aarch64-opc.c (aarch64_sys_regs): Add "vsesr_el2", "erridr_el1",
11 "errselr_el1", "erxfr_el1", "erxctlr", "erxaddr_el1",
12 "erxmisc0_el1", "erxmisc1_el1", "disr_el1" and "vdisr_el2".
13 (aarch64_sys_reg_supported_p): Add architecture feature tests for
14 new registers.
15
c8a6db6f
MW		 162015-12-10 Matthew Wahab <matthew.wahab@arm.com>
17
18 * aarch64-asm-2.c: Regenerate.
19 * aarch64-dis-2.c: Regenerate.
20 * aarch64-tbl.h (aarch64_feature_ras): New.
21 (RAS): New.
22 (aarch64_opcode_table): Add "esb".
23
8eab4136
L		 242015-12-09 H.J. Lu <hongjiu.lu@intel.com>
25
26 * i386-dis.c (MOD_0F01_REG_5): New.
27 (RM_0F01_REG_5): Likewise.
28 (reg_table): Use MOD_0F01_REG_5.
29 (mod_table): Add MOD_0F01_REG_5.
30 (rm_table): Add RM_0F01_REG_5.
31 * i386-gen.c (cpu_flag_init): Add CPU_OSPKE_FLAGS.
32 (cpu_flags): Add CpuOSPKE.
33 * i386-opc.h (CpuOSPKE): New.
34 (i386_cpu_flags): Add cpuospke.
35 * i386-opc.tbl: Add rdpkru and wrpkru instructions.
36 * i386-init.h: Regenerated.
37 * i386-tbl.h: Likewise.
38
1eac08cc
DD		 392015-12-07 DJ Delorie <dj@redhat.com>
40
41 * rl78-decode.opc: Enable MULU for all ISAs.
42 * rl78-decode.c: Regenerate.
43
dd2887fc
AM		 442015-12-07 Alan Modra <amodra@gmail.com>
45
46 * opcodes/ppc-opc.c (powerpc_opcodes): Sort power9 insns by
47 major opcode/xop.
48
24b368f8
CZ		 492015-12-04 Claudiu Zissulescu <claziss@synopsys.com>
50
51 * arc-dis.c (special_flag_p): Match full mnemonic.
52 * arc-opc.c (print_insn_arc): Check section size to read
53 appropriate number of bytes. Fix printing.
54 * arc-tbl.h: Fix instruction table. Allow clri/seti instruction without
55 arguments.
56
3395762e
AV		 572015-12-02 Andre Vieira <andre.simoesdiasvieira@arm.com>
58
59 * arm-dis.c (arm_opcodes): <ldaexh>: Fix typo...
60 <ldah>: ... to this.
61
622b9eb1
MW		 622015-11-27 Matthew Wahab <matthew.wahab@arm.com>
63
64 * aarch64-asm-2.c: Regenerate.
65 * aarch64-dis-2.c: Regenerate.
66 * aarch64-opc-2.c: Regenerate.
67 * aarch64-tbl.h (QL_FIX2FP_H, QL_FP2FIX_H): New.
68 (QL_INT2FP_H, QL_FP2INT_H): New.
69 (QL_FP2_H, QL_FP3_H, QL_FP4_H): New
70 (QL_DST_H): New.
71 (QL_FCCMP_H): New.
72 (aarch64_opcode_table): Add 16-bit variants of scvt, ucvtf,
73 fcvtzs, fcvtzu, fcvtns, fcvtnu, scvtf, ucvtf, fcvtas, fcvtau,
74 fmov, fcvtpos, fcvtpu, fcvtms, fcvtmu, fcvtzs, fcvtzu, fccmp,
75 fccmpe, fcmp, fcmpe, fabs, fneg, fsqrt, frintn, frintp, frintm,
76 frintz, frinta, frintx, frinti, fmul, fdiv, fadd, fsub, fmax,
77 fmin, fmaxnm, fminnm, fnmul, fmadd, fmsub, fnmadd, fnmsub and
78 fcsel.
79
cf86120b
MW		 802015-11-27 Matthew Wahab <matthew.wahab@arm.com>
81
82 * aarch64-opc.c (half_conv_t): New.
83 (expand_fp_imm): Replace is_dp flag with the parameter size to
84 specify the number of bytes for the required expansion. Treat
85 a 16-bit expansion like a 32-bit expansion. Add check for an
86 unsupported size request. Update comment.
87 (aarch64_print_operand): Update to support 16-bit floating point
88 values. Update for changes to expand_fp_imm.
89
3bd894a7
MW		 902015-11-27 Matthew Wahab <matthew.wahab@arm.com>
91
92 * aarch64-tbl.h (aarch64_feature_fp_f16): New.
93 (FP_F16): New.
94
64357d2e
MW		 952015-11-27 Matthew Wahab <matthew.wahab@arm.com>
96
97 * aarch64-asm-2.c: Regenerate.
98 * aarch64-dis-2.c: Regenerate.
99 * aarch64-opc-2.c: Regenerate.
100 * aarch64-tbl.h (aarchr64_opcode_table): Update "rev", add
101 "rev64".
102
d685192a
MW		 1032015-11-27 Matthew Wahab <matthew.wahab@arm.com>
104
105 * aarch64-asm-2.c: Regenerate.
106 * aarch64-asm.c (convert_bfc_to_bfm): New.
107 (convert_to_real): Add case for OP_BFC.
108 * aarch64-dis-2.c: Regenerate.
109 * aarch64-dis.c: (convert_bfm_to_bfc): New.
110 (convert_to_alias): Add case for OP_BFC.
111 * aarch64-opc-2.c: Regenerate.
112 * aarch64-opc.c (operand_general_constraint_met_p): Weaken assert
113 to allow width operand in three-operand instructions.
114 * aarch64-tbl.h (QL_BF1): New.
115 (aarch64_feature_v8_2): New.
116 (ARMV8_2): New.
117 (aarch64_opcode_table): Add "bfc".
118
35822b38
MW		 1192015-11-27 Matthew Wahab <matthew.wahab@arm.com>
120
121 * aarch64-asm-2.c: Regenerate.
122 * aarch64-dis-2.c: Regenerate.
123 * aarch64-dis.c: Weaken assert.
124 * aarch64-gen.c: Include the instruction in the list of its
125 possible aliases.
126
1a04d1a7
MW		 1272015-11-27 Matthew Wahab <matthew.wahab@arm.com>
128
129 * aarch64-opc.c (aarch64_sys_regs): Add "id_aa64mmfr2_el1".
130 (aarch64_sys_reg_supported_p): Add ARMv8.2 system register
131 feature test.
132
e49d43ff
TG		 1332015-11-23 Tristan Gingold <gingold@adacore.com>
134
135 * arm-dis.c (print_insn): Also set is_thumb for Mach-O.
136
250aafa4
MW		 1372015-11-20 Matthew Wahab <matthew.wahab@arm.com>
138
139 * aarch64-opc.c (aarch64_sys_regs): Add spsr_el12, elr_el12,
140 sctlr_el12, cpacr_el12, ttbr1_el2, ttbr0_el12, ttbr1_el12,
141 tcr_el12, afsr0_el12, afsr1_el12, esr_el12, far_el12, mair_el12,
142 amair_el12, vbar_el12, contextidr_el2, contextidr_el12,
143 cntkctl_el12, cntp_tval_el02, cntp_ctl_el02, cntp_cval_el02,
144 cntv_tval_el02, cntv_ctl_el02, cntv_cval_el02, cnthv_tval_el2,
145 cnthv_ctl_el2, cnthv_cval_el2.
146 (aarch64_sys_reg_supported_p): Update for the new system
147 registers.
148
a915c10f
NC		 1492015-11-20 Nick Clifton <nickc@redhat.com>
150
151 PR binutils/19224
152 * h8300-dis.c (bfd_h8_disassemble): Remove redundant if clause.
153
f8c2a965
NC		 1542015-11-20 Nick Clifton <nickc@redhat.com>
155
156 * po/zh_CN.po: Updated simplified Chinese translation.
157
c2825638
MW		 1582015-11-19 Matthew Wahab <matthew.wahab@arm.com>
159
160 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
161 of MSR PAN immediate operand.
162
e7286c56
NC		 1632015-11-16 Nick Clifton <nickc@redhat.com>
164
165 * rx-dis.c (condition_names): Replace always and never with
166 invalid, since the always/never conditions can never be legal.
167
d8bd95ef
TG		 1682015-11-13 Tristan Gingold <gingold@adacore.com>
169
170 * configure: Regenerate.
171
a680de9a
PB		 1722015-11-11 Alan Modra <amodra@gmail.com>
173 Peter Bergner <bergner@vnet.ibm.com>
174
175 * ppc-dis.c (ppc_opts): Add "power9" and "pwr9" entries.
176 Add PPC_OPCODE_VSX3 to the vsx entry.
177 (powerpc_init_dialect): Set default dialect to power9.
178 * ppc-opc.c (insert_dcmxs, extract_dcmxs, insert_dxd, extract_dxd,
179 insert_dxdn, extract_dxdn, insert_l0, extract_l0, insert_l1,
180 extract_l1 insert_xtq6, extract_xtq6): New static functions.
181 (insert_esync): Test for illegal L operand value.
182 (DCMX, DCMXS, DXD, NDXD, L0, L1, RC, FC, UIM6, X_R, RIC, PRS, XSQ6,
183 XTQ6, LRAND, IMM8, DQX, DQX_MASK, DX, DX_MASK, VXVAPS_MASK, VXVA,XVA,
184 XX2VA, XVARC, XBF_MASK, XX2UIM4_MASK, XX2BFD_MASK, XX2DCMXS_MASK,
185 XVA_MASK, XRLA_MASK, XBFRARB_MASK, XLRAND_MASK, POWER9, PPCVEC3,
186 PPCVSX3): New defines.
187 (powerpc_opcodes) <ps_cmpu0, ps_cmpo0, ps_cmpu1, ps_cmpo1, fcmpu,
188 fcmpo, ftdiv, ftsqrt>: Use XBF_MASK.
189 <mcrxr>: Use XBFRARB_MASK.
190 <addpcis, bcdcfn., bcdcfsq., bcdcfz., bcdcpsgn., bcdctn., bcdctsq.,
191 bcdctz., bcds., bcdsetsgn., bcdsr., bcdtrunc., bcdus., bcdutrunc.,
192 cmpeqb, cmprb, cnttzd, cnttzd., cnttzw, cnttzw., copy, copy_first,
193 cp_abort, darn, dtstsfi, dtstsfiq, extswsli, extswsli., ldat, ldmx,
194 lwat, lxsd, lxsibzx, lxsihzx, lxssp, lxv, lxvb16x, lxvh8x, lxvl, lxvll,
195 lxvwsx, lxvx, maddhd, maddhdu, maddld, mcrxrx, mfvsrld, modsd, modsw,
196 modud, moduw, msgsync, mtvsrdd, mtvsrws, paste, paste., paste_last,
197 rmieg, setb, slbieg, slbsync, stdat, stop, stwat, stxsd, stxsibx,
198 stxsihx, stxssp, stxv, stxvb16x, stxvh8x, stxvl, stxvll, stxvx,
199 subpcis, urfid, vbpermd, vclzlsbb, vcmpneb, vcmpneb., vcmpneh,
200 vcmpneh., vcmpnew, vcmpnew., vcmpnezb, vcmpnezb., vcmpnezh, vcmpnezh.,
201 vcmpnezw, vcmpnezw., vctzb, vctzd, vctzh, vctzlsbb, vctzw, vextractd,
202 vextractub, vextractuh, vextractuw, vextsb2d, vextsb2w, vextsh2d,
203 vextsh2w, vextsw2d, vextublx, vextubrx, vextuhlx, vextuhrx, vextuwlx,
204 vextuwrx, vinsertb, vinsertd, vinserth, vinsertw, vmul10cuq,
205 vmul10ecuq, vmul10euq, vmul10uq, vnegd, vnegw, vpermr, vprtybd,
206 vprtybq, vprtybw, vrldmi, vrldnm, vrlwmi, vrlwnm, vslv, vsrv, wait,
207 xsabsqp, xsaddqp, xsaddqpo, xscmpeqdp, xscmpexpdp, xscmpexpqp,
208 xscmpgedp, xscmpgtdp, xscmpnedp, xscmpoqp, xscmpuqp, xscpsgnqp,
209 xscvdphp, xscvdpqp, xscvhpdp, xscvqpdp, xscvqpdpo, xscvqpsdz,
210 xscvqpswz, xscvqpudz, xscvqpuwz, xscvsdqp, xscvudqp, xsdivqp,
211 xsdivqpo, xsiexpdp, xsiexpqp, xsmaddqp, xsmaddqpo, xsmaxcdp,
212 xsmaxjdp, xsmincdp, xsminjdp, xsmsubqp, xsmsubqpo, xsmulqp, xsmulqpo,
213 xsnabsqp, xsnegqp, xsnmaddqp, xsnmaddqpo, xsnmsubqp, xsnmsubqpo,
214 xsrqpi, xsrqpix, xsrqpxp, xssqrtqp, xssqrtqpo, xssubqp, xssubqpo,
215 xststdcdp, xststdcqp, xststdcsp, xsxexpdp, xsxexpqp, xsxsigdp,
216 xsxsigqp, xvcmpnedp, xvcmpnedp., xvcmpnesp, xvcmpnesp., xvcvhpsp,
217 xvcvsphp, xviexpdp, xviexpsp, xvtstdcdp, xvtstdcsp, xvxexpdp,
218 xvxexpsp, xvxsigdp, xvxsigsp, xxbrd, xxbrh, xxbrq, xxbrw, xxextractuw,
219 xxinsertw, xxperm, xxpermr, xxspltib>: New instructions.
220 <doze, nap, sleep, rvwinkle, waitasec, lxvx, stxvx>: Disable on POWER9.
221 <tlbiel, tlbie, sync, slbmfev, slbmfee>: Add additional operands.
222
854eb72b
NC		 2232015-11-02 Nick Clifton <nickc@redhat.com>
224
225 * rx-decode.opc (rx_decode_opcode): Decode extra NOP
226 instructions.
227 * rx-decode.c: Regenerate.
228
e292aa7a
NC		 2292015-11-02 Nick Clifton <nickc@redhat.com>
230
231 * rx-decode.opc (rx_disp): If the displacement is zero, set the
232 type to RX_Operand_Zero_Indirect.
233 * rx-decode.c: Regenerate.
234 * rx-dis (print_insn): Handle RX_Operand_Zero_Indirect.
235
43cdf5ae
YQ		 2362015-10-28 Yao Qi <yao.qi@linaro.org>
237
238 * aarch64-dis.c (aarch64_decode_insn): Add one argument
239 noaliases_p. Update comments. Pass noaliases_p rather than
240 no_aliases to aarch64_opcode_decode.
241 (print_insn_aarch64_word): Pass no_aliases to
242 aarch64_decode_insn.
243
c2f28758
VK		 2442015-10-27 Vinay <Vinay.G@kpit.com>
245
246 PR binutils/19159
247 * rl78-decode.opc (MOV): Added offset to DE register in index
248 addressing mode.
249 * rl78-decode.c: Regenerate.
250
46662804
VK		 2512015-10-27 Vinay Kumar <vinay.g@kpit.com>
252
253 PR binutils/19158
254 * rl78-decode.opc: Add 's' print operator to instructions that
255 access system registers.
256 * rl78-decode.c: Regenerate.
257 * rl78-dis.c (print_insn_rl78_common): Decode all system
258 registers.
259
02f12cd4
VK		 2602015-10-27 Vinay Kumar <vinay.g@kpit.com>
261
262 PR binutils/19157
263 * rl78-decode.opc: Add 'a' print operator to mov instructions
264 using stack pointer plus index addressing.
265 * rl78-decode.c: Regenerate.
266
485f23cf
AK		 2672015-10-14 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
268
269 * s390-opc.c: Fix comment.
270 * s390-opc.txt: Change instruction type for troo, trot, trto, and
271 trtt to RRF_U0RER since the second parameter does not need to be a
272 register pair.
273
3f94e60d
NC		 2742015-10-08 Nick Clifton <nickc@redhat.com>
275
276 * arc-dis.c (print_insn_arc): Initiallise insn array.
277
875880c6
YQ		 2782015-10-07 Yao Qi <yao.qi@linaro.org>
279
280 * aarch64-dis.c (aarch64_ext_sysins_op): Access field
281 'name' rather than 'template'.
282 * aarch64-opc.c (aarch64_print_operand): Likewise.
283
886a2506
NC		 2842015-10-07 Claudiu Zissulescu <claziss@synopsys.com>
285
286 * arc-dis.c: Revamped file for ARC support
287 * arc-dis.h: Likewise.
288 * arc-ext.c: Likewise.
289 * arc-ext.h: Likewise.
290 * arc-opc.c: Likewise.
291 * arc-fxi.h: New file.
292 * arc-regs.h: Likewise.
293 * arc-tbl.h: Likewise.
294
36f4aab1
YQ		 2952015-10-02 Yao Qi <yao.qi@linaro.org>
296
297 * aarch64-dis.c (disas_aarch64_insn): Remove static. Change
298 argument insn type to aarch64_insn. Rename to ...
299 (aarch64_decode_insn): ... it.
300 (print_insn_aarch64_word): Caller updated.
301
7232d389
YQ		 3022015-10-02 Yao Qi <yao.qi@linaro.org>
303
304 * aarch64-dis.c (disas_aarch64_insn): Remove argument PC.
305 (print_insn_aarch64_word): Caller updated.
306
7ecc513a
DV		 3072015-09-29 Dominik Vogt <vogt@linux.vnet.ibm.com>
308
309 * s390-mkopc.c (main): Parse htm and vx flag.
310 * s390-opc.txt: Mark instructions from the hardware transactional
311 memory and vector facilities with the "htm"/"vx" flag.
312
b08b78e7
NC		 3132015-09-28 Nick Clifton <nickc@redhat.com>
314
315 * po/de.po: Updated German translation.
316
36f7a941
TR		 3172015-09-28 Tom Rix <tom@bumblecow.com>
318
319 * ppc-opc.c (PPC500): Mark some opcodes as invalid
320
b6518b38
NC		 3212015-09-23 Nick Clifton <nickc@redhat.com>
322
323 * bfin-dis.c (fmtconst): Remove unnecessary call to the abs
324 function.
325 * tic30-dis.c (print_branch): Likewise.
326 * cgen-asm.c (cgen_parse_signed_integer): Cast integer to signed
327 value before left shifting.
328 * fr30-ibld.c (fr30_cgen_extract_operand): Likewise.
329 * hppa-dis.c (print_insn_hppa): Likewise.
330 * mips-dis.c (mips_cp0sel_names_mipsr5900): Delete unused static
331 array.
332 * msp430-dis.c (msp430_singleoperand): Likewise.
333 (msp430_doubleoperand): Likewise.
334 (print_insn_msp430): Likewise.
335 * nds32-asm.c (parse_operand): Likewise.
336 * sh-opc.h (MASK): Likewise.
337 * v850-dis.c (get_operand_value): Likewise.
338
f04265ec
NC		 3392015-09-22 Nick Clifton <nickc@redhat.com>
340
341 * rx-decode.opc (bwl): Use RX_Bad_Size.
342 (sbwl): Likewise.
343 (ubwl): Likewise. Rename to ubw.
344 (uBWL): Rename to uBW.
345 Replace all references to uBWL with uBW.
346 * rx-decode.c: Regenerate.
347 * rx-dis.c (size_names): Add entry for RX_Bad_Size.
348 (opsize_names): Likewise.
349 (print_insn_rx): Detect and report RX_Bad_Size.
350
6dca4fd1
AB		 3512015-09-22 Anton Blanchard <anton@samba.org>
352
353 * ppc-opc.c (powerpc_opcodes): Add mfdscr, mfctrl, mtdscr and mtctrl.
354
38074311
JM		 3552015-08-25 Jose E. Marchesi <jose.marchesi@oracle.com>
356
357 * sparc-dis.c (print_insn_sparc): Handle the privileged register
358 %pmcdper.
359
5f40e14d
JS		 3602015-08-24 Jan Stancek <jstancek@redhat.com>
361
362 * i386-dis.c (print_insn): Fix decoding of three byte operands.
363
ab4e4ed5
AF		 3642015-08-21 Alexander Fomin <alexander.fomin@intel.com>
365
366 PR binutils/18257
367 * i386-dis.c: Use MOD_TABLE for most of mask instructions.
368 (MOD enum): Add MOD_VEX_W_0_0F41_P_0_LEN_1,
369 MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
370 MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
371 MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
372 MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
373 MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
374 MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
375 MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
376 MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
377 MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
378 MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
379 MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
380 MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
381 MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
382 MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
383 MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
384 MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
385 MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
386 MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
387 MOD_VEX_W_0_0F92_P_3_LEN_0, MOD_VEX_W_1_0F92_P_3_LEN_0,
388 MOD_VEX_W_0_0F93_P_0_LEN_0, MOD_VEX_W_0_0F93_P_2_LEN_0,
389 MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0,
390 MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
391 MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
392 MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
393 MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
394 MOD_VEX_W_0_0F3A30_P_2_LEN_0, MOD_VEX_W_1_0F3A30_P_2_LEN_0,
395 MOD_VEX_W_0_0F3A31_P_2_LEN_0, MOD_VEX_W_1_0F3A31_P_2_LEN_0,
396 MOD_VEX_W_0_0F3A32_P_2_LEN_0, MOD_VEX_W_1_0F3A32_P_2_LEN_0,
397 MOD_VEX_W_0_0F3A33_P_2_LEN_0, MOD_VEX_W_1_0F3A33_P_2_LEN_0.
398 (vex_w_table): Replace terminals with MOD_TABLE entries for
399 most of mask instructions.
400
919b75f7
AM		 4012015-08-17 Alan Modra <amodra@gmail.com>
402
403 * cgen.sh: Trim trailing space from cgen output.
404 * ia64-gen.c (print_dependency_table): Don't generate trailing space.
405 (print_dis_table): Likewise.
406 * opc2c.c (dump_lines): Likewise.
407 (orig_filename): Warning fix.
408 * ia64-asmtab.c: Regenerate.
409
4ab90a7a
AV		 4102015-08-13 Andre Vieira <andre.simoesdiasvieira@arm.com>
411
412 * arm-dis.c (print_insn_arm): Disassembling for all targets V6
413 and higher with ARM instruction set will now mark the 26-bit
414 versions of teq,tst,cmn and cmp as UNPREDICTABLE.
415 (arm_opcodes): Fix for unpredictable nop being recognized as a
416 teq.
417
40fc1451
SD		 4182015-08-12 Simon Dardis <simon.dardis@imgtec.com>
419
420 * micromips-opc.c (micromips_opcodes): Re-order table so that move
421 based on 'or' is first.
422 * mips-opc.c (mips_builtin_opcodes): Ditto.
423
922c5db5
NC		 4242015-08-11 Nick Clifton <nickc@redhat.com>
425
426 PR 18800
427 * aarch64-tbl.h (aarch64_opcode_table): Fix mask for SIMD EXT
428 instruction.
429
75fb7498
RS		 4302015-08-10 Robert Suchanek <robert.suchanek@imgtec.com>
431
432 * mips-opc.c (mips_builtin_opcodes): Add "sigrie".
433
36aed29d
AP		 4342015-08-07 Amit Pawar <Amit.Pawar@amd.com>
435
436 * i386-gen.c: Remove CpuFMA4 from CPU_ZNVER1_FLAGS.
437 * i386-init.h: Regenerated.
438
a8484f96
L		 4392015-07-30 H.J. Lu <hongjiu.lu@intel.com>
440
441 PR binutils/13571
442 * i386-dis.c (MOD_0FC3): New.
443 (PREFIX_0FC3): Renamed to ...
444 (PREFIX_MOD_0_0FC3): This.
445 (dis386_twobyte): Replace PREFIX_0FC3 with MOD_0FC3.
446 (prefix_table): Replace Ma with Ev on movntiS.
447 (mod_table): Add MOD_0FC3.
448
37a42ee9
L		 4492015-07-27 H.J. Lu <hongjiu.lu@intel.com>
450
451 * configure: Regenerated.
452
070fe95d
AM		 4532015-07-23 Alan Modra <amodra@gmail.com>
454
455 PR 18708
456 * i386-dis.c (get64): Avoid signed integer overflow.
457
20c2a615
L		 4582015-07-22 Alexander Fomin <alexander.fomin@intel.com>
459
460 PR binutils/18631
461 * i386-dis-evex.h (EVEX_W_0F78_P_2): Replace "EXxmmq" with
462 "EXEvexHalfBcstXmmq" for the second operand.
463 (EVEX_W_0F79_P_2): Likewise.
464 (EVEX_W_0F7A_P_2): Likewise.
465 (EVEX_W_0F7B_P_2): Likewise.
466
6f1c2142
AM		 4672015-07-16 Alessandro Marzocchi <alessandro.marzocchi@gmail.com>
468
469 * arm-dis.c (print_insn_coprocessor): Added support for quarter
470 float bitfield format.
471 (coprocessor_opcodes): Changed VFP vmov reg,immediate to use new
472 quarter float bitfield format.
473
8a643cc3
L		 4742015-07-14 H.J. Lu <hongjiu.lu@intel.com>
475
476 * configure: Regenerated.
477
ef5a96d5
AM		 4782015-07-03 Alan Modra <amodra@gmail.com>
479
480 * ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
481 * ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries. Add
482 PPC_OPCODE_7450 to 7450 entry. Add PPC_OPCODE_750 to 750cl entry.
483
c8c8175b
SL		 4842015-07-01 Sandra Loosemore <sandra@codesourcery.com>
485 Cesar Philippidis <cesar@codesourcery.com>
486
487 * nios2-dis.c (nios2_extract_opcode): New.
488 (nios2_disassembler_state): New.
489 (nios2_find_opcode_hash): Use mach parameter to select correct
490 disassembler state.
491 (nios2_print_insn_arg): Extend to support new R2 argument letters
492 and formats.
493 (print_insn_nios2): Check for 16-bit instruction at end of memory.
494 * nios2-opc.c (nios2_builtin_regs): Add R2 register attributes.
495 (NIOS2_NUM_OPCODES): Rename to...
496 (NIOS2_NUM_R1_OPCODES): This.
497 (nios2_r2_opcodes): New.
498 (NIOS2_NUM_R2_OPCODES): New.
499 (nios2_num_r2_opcodes): New.
500 (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New.
501 (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New.
502 (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New.
503 (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New.
504 (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): New.
505
9916071f
AP		 5062015-06-30 Amit Pawar <Amit.Pawar@amd.com>
507
508 * i386-dis.c (OP_Mwaitx): New.
509 (rm_table): Add monitorx/mwaitx.
510 * i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS
511 and CPU_ZNVER1_FLAGS. Add CPU_MWAITX_FLAGS.
512 (operand_type_init): Add CpuMWAITX.
513 * i386-opc.h (CpuMWAITX): New.
514 (i386_cpu_flags): Add cpumwaitx.
515 * i386-opc.tbl: Add monitorx and mwaitx.
516 * i386-init.h: Regenerated.
517 * i386-tbl.h: Likewise.
518
7b934113
PB		 5192015-06-22 Peter Bergner <bergner@vnet.ibm.com>
520
521 * ppc-opc.c (insert_ls): Test for invalid LS operands.
522 (insert_esync): New function.
523 (LS, WC): Use insert_ls.
524 (ESYNC): Use insert_esync.
525
bdc4de1b
NC		 5262015-06-22 Nick Clifton <nickc@redhat.com>
527
528 * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
529 requested region lies beyond it.
530 * bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
531 looking for 32-bit insns.
532 * mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
533 data.
534 * sh-dis.c (print_insn_sh): Likewise.
535 * tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
536 blocks of instructions.
537 * vax-dis.c (print_insn_vax): Check that the requested address
538 does not clash with the stop_vma.
539
11a0cf2e
PB		 5402015-06-19 Peter Bergner <bergner@vnet.ibm.com>
541
070fe95d 542 * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
11a0cf2e
PB		 543 * ppc-opc.c (FXM4): Add non-zero optional value.
544 (TBR): Likewise.
545 (SXL): Likewise.
546 (insert_fxm): Handle new default operand value.
547 (extract_fxm): Likewise.
548 (insert_tbr): Likewise.
549 (extract_tbr): Likewise.
550
bdfa8b95
MW		 5512015-06-16 Matthew Wahab <matthew.wahab@arm.com>
552
553 * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
554
24b4cf66
SN		 5552015-06-16 Szabolcs Nagy <szabolcs.nagy@arm.com>
556
557 * arm-dis.c (print_insn_coprocessor): Avoid negative shift.
558
99a2c561
PB		 5592015-06-12 Peter Bergner <bergner@vnet.ibm.com>
560
561 * ppc-opc.c: Add comment accidentally removed by old commit.
562 (MTMSRD_L): Delete.
563
40f77f82
AM		 5642015-06-04 Peter Bergner <bergner@vnet.ibm.com>
565
566 * ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.
567
13be46a2
NC		 5682015-06-04 Nick Clifton <nickc@redhat.com>
569
570 PR 18474
571 * msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
572
ddfded2f
MW		 5732015-06-02 Matthew Wahab <matthew.wahab@arm.com>
574
575 * arm-dis.c (arm_opcodes): Add "setpan".
576 (thumb_opcodes): Add "setpan".
577
1af1dd51
MW		 5782015-06-02 Matthew Wahab <matthew.wahab@arm.com>
579
580 * arm-dis.c (select_arm_features): Rework to avoid used of redefined
581 macros.
582
9e1f0fa7
MW		 5832015-06-02 Matthew Wahab <matthew.wahab@arm.com>
584
585 * aarch64-tbl.h (aarch64_feature_rdma): New.
586 (RDMA): New.
587 (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
588 * aarch64-asm-2.c: Regenerate.
589 * aarch64-dis-2.c: Regenerate.
590 * aarch64-opc-2.c: Regenerate.
591
290806fd
MW		 5922015-06-02 Matthew Wahab <matthew.wahab@arm.com>
593
594 * aarch64-tbl.h (aarch64_feature_lor): New.
595 (LOR): New.
596 (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
597 "stllrb", "stllrh".
598 * aarch64-asm-2.c: Regenerate.
599 * aarch64-dis-2.c: Regenerate.
600 * aarch64-opc-2.c: Regenerate.
601
f21cce2c
MW		 6022015-06-01 Matthew Wahab <matthew.wahab@arm.com>
603
604 * aarch64-opc.c (F_ARCHEXT): New.
605 (aarch64_sys_regs): Add "pan".
606 (aarch64_sys_reg_supported_p): New.
607 (aarch64_pstatefields): Add "pan".
608 (aarch64_pstatefield_supported_p): New.
609
d194d186
JB		 6102015-06-01 Jan Beulich <jbeulich@suse.com>
611
612 * i386-tbl.h: Regenerate.
613
3a8547d2
JB		 6142015-06-01 Jan Beulich <jbeulich@suse.com>
615
616 * i386-dis.c (print_insn): Swap rounding mode specifier and
617 general purpose register in Intel mode.
618
015c54d5
JB		 6192015-06-01 Jan Beulich <jbeulich@suse.com>
620
621 * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
622 * i386-tbl.h: Regenerate.
623
071f0063
L		 6242015-05-18 H.J. Lu <hongjiu.lu@intel.com>
625
626 * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
627 * i386-init.h: Regenerated.
628
5db04b09
L		 6292015-05-15 H.J. Lu <hongjiu.lu@intel.com>
630
631 PR binutis/18386
632 * i386-dis.c: Add comments for '@'.
633 (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
634 (enum x86_64_isa): New.
635 (isa64): Likewise.
636 (print_i386_disassembler_options): Add amd64 and intel64.
637 (print_insn): Handle amd64 and intel64.
638 (putop): Handle '@'.
639 (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
640 * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
641 * i386-opc.h (AMD64): New.
642 (CpuIntel64): Likewise.
643 (i386_cpu_flags): Add cpuamd64 and cpuintel64.
644 * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
645 Mark direct call/jmp without Disp16|Disp32 as Intel64.
646 * i386-init.h: Regenerated.
647 * i386-tbl.h: Likewise.
648
4bc0608a
PB		 6492015-05-14 Peter Bergner <bergner@vnet.ibm.com>
650
651 * ppc-opc.c (IH) New define.
652 (powerpc_opcodes) <wait>: Do not enable for POWER7.
653 <tlbie>: Add RS operand for POWER7.
654 <slbia>: Add IH operand for POWER6.
655
70cead07
L		 6562015-05-11 H.J. Lu <hongjiu.lu@intel.com>
657
658 * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
659 direct branch.
660 (jmp): Likewise.
661 * i386-tbl.h: Regenerated.
662
7b6d09fb
L		 6632015-05-11 H.J. Lu <hongjiu.lu@intel.com>
664
665 * configure.ac: Support bfd_iamcu_arch.
666 * disassemble.c (disassembler): Support bfd_iamcu_arch.
667 * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
668 CPU_IAMCU_COMPAT_FLAGS.
669 (cpu_flags): Add CpuIAMCU.
670 * i386-opc.h (CpuIAMCU): New.
671 (i386_cpu_flags): Add cpuiamcu.
672 * configure: Regenerated.
673 * i386-init.h: Likewise.
674 * i386-tbl.h: Likewise.
675
31955f99
L		 6762015-05-08 H.J. Lu <hongjiu.lu@intel.com>
677
678 PR binutis/18386
679 * i386-dis.c (X86_64_E8): New.
680 (X86_64_E9): Likewise.
681 Update comments on 'T', 'U', 'V'. Add comments for '^'.
682 (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
683 (x86_64_table): Add X86_64_E8 and X86_64_E9.
684 (mod_table): Replace {T|} with ^ on Jcall/Jmp.
685 (putop): Handle '^'.
686 (OP_J): Ignore the operand size prefix in 64-bit. Don't check
687 REX_W.
688
0952813b
DD		 6892015-04-30 DJ Delorie <dj@redhat.com>
690
691 * disassemble.c (disassembler): Choose suitable disassembler based
692 on E_ABI.
693 * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter. Use
694 it to decode mul/div insns.
695 * rl78-decode.c: Regenerate.
696 * rl78-dis.c (print_insn_rl78): Rename to...
697 (print_insn_rl78_common): ...this, take ISA parameter.
698 (print_insn_rl78): New.
699 (print_insn_rl78_g10): New.
700 (print_insn_rl78_g13): New.
701 (print_insn_rl78_g14): New.
702 (rl78_get_disassembler): New.
703
f9d3ecaa
NC		 7042015-04-29 Nick Clifton <nickc@redhat.com>
705
706 * po/fr.po: Updated French translation.
707
4fff86c5
PB		 7082015-04-27 Peter Bergner <bergner@vnet.ibm.com>
709
710 * ppc-opc.c (DCBT_EO): New define.
711 (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
712 <lharx>: Likewise.
713 <stbcx.>: Likewise.
714 <sthcx.>: Likewise.
715 <waitrsv>: Do not enable for POWER7 and later.
716 <waitimpl>: Likewise.
717 <dcbt>: Default to the two operand form of the instruction for all
718 "old" cpus. For "new" cpus, use the operand ordering that matches
719 whether the cpu is server or embedded.
720 <dcbtst>: Likewise.
721
3b78cfe1
AK		 7222015-04-27 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
723
724 * s390-opc.c: New instruction type VV0UU2.
725 * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
726 and WFC.
727
04d824a4
JB		 7282015-04-23 Jan Beulich <jbeulich@suse.com>
729
730 * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
731 * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
732 vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
733 (vfpclasspd, vfpclassps): Add %XZ.
734
09708981
L		 7352015-04-15 H.J. Lu <hongjiu.lu@intel.com>
736
737 * i386-dis.c (PREFIX_UD_SHIFT): Removed.
738 (PREFIX_UD_REPZ): Likewise.
739 (PREFIX_UD_REPNZ): Likewise.
740 (PREFIX_UD_DATA): Likewise.
741 (PREFIX_UD_ADDR): Likewise.
742 (PREFIX_UD_LOCK): Likewise.
743
3888916d
L		 7442015-04-15 H.J. Lu <hongjiu.lu@intel.com>
745
746 * i386-dis.c (prefix_requirement): Removed.
747 (print_insn): Don't set prefix_requirement. Check
748 dp->prefix_requirement instead of prefix_requirement.
749
f24bcbaa
L		 7502015-04-15 H.J. Lu <hongjiu.lu@intel.com>
751
752 PR binutils/17898
753 * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
754 (PREFIX_MOD_0_0FC7_REG_6): This.
755 (PREFIX_MOD_3_0FC7_REG_6): New.
756 (PREFIX_MOD_3_0FC7_REG_7): Likewise.
757 (prefix_table): Replace PREFIX_0FC7_REG_6 with
758 PREFIX_MOD_0_0FC7_REG_6. Add PREFIX_MOD_3_0FC7_REG_6 and
759 PREFIX_MOD_3_0FC7_REG_7.
760 (mod_table): Replace PREFIX_0FC7_REG_6 with
761 PREFIX_MOD_0_0FC7_REG_6. Use PREFIX_MOD_3_0FC7_REG_6 and
762 PREFIX_MOD_3_0FC7_REG_7.
763
507bd325
L		 7642015-04-15 H.J. Lu <hongjiu.lu@intel.com>
765
766 * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
767 (PREFIX_MANDATORY_REPNZ): Likewise.
768 (PREFIX_MANDATORY_DATA): Likewise.
769 (PREFIX_MANDATORY_ADDR): Likewise.
770 (PREFIX_MANDATORY_LOCK): Likewise.
771 (PREFIX_MANDATORY): Likewise.
772 (PREFIX_UD_SHIFT): Set to 8
773 (PREFIX_UD_REPZ): Updated.
774 (PREFIX_UD_REPNZ): Likewise.
775 (PREFIX_UD_DATA): Likewise.
776 (PREFIX_UD_ADDR): Likewise.
777 (PREFIX_UD_LOCK): Likewise.
778 (PREFIX_IGNORED_SHIFT): New.
779 (PREFIX_IGNORED_REPZ): Likewise.
780 (PREFIX_IGNORED_REPNZ): Likewise.
781 (PREFIX_IGNORED_DATA): Likewise.
782 (PREFIX_IGNORED_ADDR): Likewise.
783 (PREFIX_IGNORED_LOCK): Likewise.
784 (PREFIX_OPCODE): Likewise.
785 (PREFIX_IGNORED): Likewise.
786 (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
787 (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
788 (three_byte_table): Likewise.
789 (mod_table): Likewise.
790 (mandatory_prefix): Renamed to ...
791 (prefix_requirement): This.
792 (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
793 Update PREFIX_90 entry.
794 (get_valid_dis386): Check prefix_requirement to see if a prefix
795 should be ignored.
796 (print_insn): Replace mandatory_prefix with prefix_requirement.
797
f0fba320
RL		 7982015-04-15 Renlin Li <renlin.li@arm.com>
799
800 * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
801 use it for ssat and ssat16.
802 (print_insn_thumb32): Add handle case for 'D' control code.
803
bf890a93
IT		 8042015-04-06 Ilya Tocar <ilya.tocar@intel.com>
805 H.J. Lu <hongjiu.lu@intel.com>
806
807 * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
808 * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
809 PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
810 PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
811 PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
812 (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
813 Fill prefix_requirement field.
814 (struct dis386): Add prefix_requirement field.
815 (dis386): Fill prefix_requirement field.
816 (dis386_twobyte): Ditto.
817 (twobyte_has_mandatory_prefix_: Remove.
818 (reg_table): Fill prefix_requirement field.
819 (prefix_table): Ditto.
820 (x86_64_table): Ditto.
821 (three_byte_table): Ditto.
822 (xop_table): Ditto.
823 (vex_table): Ditto.
824 (vex_len_table): Ditto.
825 (vex_w_table): Ditto.
826 (mod_table): Ditto.
827 (bad_opcode): Ditto.
828 (print_insn): Use prefix_requirement.
829 (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
830 FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
831 (float_reg): Ditto.
832
2f783c1f
MF		 8332015-03-30 Mike Frysinger <vapier@gentoo.org>
834
835 * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
836
b9d94d62
L		 8372015-03-29 H.J. Lu <hongjiu.lu@intel.com>
838
839 * Makefile.in: Regenerated.
840
27c49e9a
AB		 8412015-03-25 Anton Blanchard <anton@samba.org>
842
843 * ppc-dis.c (disassemble_init_powerpc): Only initialise
844 powerpc_opcd_indices and vle_opcd_indices once.
845
c4e676f1
AB		 8462015-03-25 Anton Blanchard <anton@samba.org>
847
848 * ppc-opc.c (powerpc_opcodes): Add slbfee.
849
823d2571
TG		 8502015-03-24 Terry Guo <terry.guo@arm.com>
851
852 * arm-dis.c (opcode32): Updated to use new arm feature struct.
853 (opcode16): Likewise.
854 (coprocessor_opcodes): Replace bit with feature struct.
855 (neon_opcodes): Likewise.
856 (arm_opcodes): Likewise.
857 (thumb_opcodes): Likewise.
858 (thumb32_opcodes): Likewise.
859 (print_insn_coprocessor): Likewise.
860 (print_insn_arm): Likewise.
861 (select_arm_features): Follow new feature struct.
862
029f3522
GG		 8632015-03-17 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
864
865 * i386-dis.c (rm_table): Add clzero.
866 * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
867 Add CPU_CLZERO_FLAGS.
868 (cpu_flags): Add CpuCLZERO.
869 * i386-opc.h: Add CpuCLZERO.
870 * i386-opc.tbl: Add clzero.
871 * i386-init.h: Re-generated.
872 * i386-tbl.h: Re-generated.
873
6914869a
AB		 8742015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
875
876 * mips-opc.c (decode_mips_operand): Fix constraint issues
877 with u and y operands.
878
21e20815
AB		 8792015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
880
881 * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
882
6b1d7593
AK		 8832015-03-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
884
885 * s390-opc.c: Add new IBM z13 instructions.
886 * s390-opc.txt: Likewise.
887
c8f89a34
JW		 8882015-03-10 Renlin Li <renlin.li@arm.com>
889
890 * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
891 stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
892 related alias.
893 * aarch64-asm-2.c: Regenerate.
894 * aarch64-dis-2.c: Likewise.
895 * aarch64-opc-2.c: Likewise.
896
d8282f0e
JW		 8972015-03-03 Jiong Wang <jiong.wang@arm.com>
898
899 * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
900
ac994365
OE		 9012015-02-25 Oleg Endo <olegendo@gcc.gnu.org>
902
903 * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
904 arch_sh_up.
905 (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
906 arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
907
fd63f640
V		 9082015-02-23 Vinay <Vinay.G@kpit.com>
909
910 * rl78-decode.opc (MOV): Added space between two operands for
911 'mov' instruction in index addressing mode.
912 * rl78-decode.c: Regenerate.
913
f63c1776
PA		 9142015-02-19 Pedro Alves <palves@redhat.com>
915
916 * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
917
07774fcc
PA		 9182015-02-10 Pedro Alves <palves@redhat.com>
919 Tom Tromey <tromey@redhat.com>
920
921 * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
922 microblaze_and, microblaze_xor.
923 * microblaze-opc.h (opcodes): Adjust.
924
3f8107ab
AM		 9252015-01-28 James Bowman <james.bowman@ftdichip.com>
926
927 * Makefile.am: Add FT32 files.
928 * configure.ac: Handle FT32.
929 * disassemble.c (disassembler): Call print_insn_ft32.
930 * ft32-dis.c: New file.
931 * ft32-opc.c: New file.
932 * Makefile.in: Regenerate.
933 * configure: Regenerate.
934 * po/POTFILES.in: Regenerate.
935
e5fe4957
KLC		 9362015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
937
938 * nds32-asm.c (keyword_sr): Add new system registers.
939
1e2e8c52
AK		 9402015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
941
942 * s390-dis.c (s390_extract_operand): Support vector register
943 operands.
944 (s390_print_insn_with_opcode): Support new operands types and add
945 new handling of optional operands.
946 * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
947 and include opcode/s390.h instead.
948 (struct op_struct): New field `flags'.
949 (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
950 (dumpTable): Dump flags.
951 (main): Parse flags from the s390-opc.txt file. Add z13 as cpu
952 string.
953 * s390-opc.c: Add new operands types, instruction formats, and
954 instruction masks.
955 (s390_opformats): Add new formats for .insn.
956 * s390-opc.txt: Add new instructions.
957
b90efa5b 9582015-01-01 Alan Modra <amodra@gmail.com>
bffb6004 959
b90efa5b 960 Update year range in copyright notice of all files.
bffb6004 961
b90efa5b 962For older changes see ChangeLog-2014
252b5132 963\f
b90efa5b 964Copyright (C) 2015 Free Software Foundation, Inc.
752937aa
NC		 965
966Copying and distribution of this file, with or without modification,
967are permitted in any medium without royalty provided the copyright
968notice and this notice are preserved.
969
252b5132 970Local Variables:
2f6d2f85
NC		 971mode: change-log
972left-margin: 8
973fill-column: 74
252b5132
RH		 974version-control: never
975End:
GDB Binutils - Deliverables
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