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PR 6848
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
7dc6076f
AK		 12008-08-15 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
2
3 * s390-opc.c (INSTR_RRF_FFRU, MASK_RRF_FFRU): New instruction format.
4 * s390-opc.txt (lxr, rrdtr, rrxtr): Fix instruction format.
5
7357c5b6
AM		 62008-08-15 Alan Modra <amodra@bigpond.net.au>
7
8 PR 6526
9 * configure.in: Invoke AC_USE_SYSTEM_EXTENSIONS.
10 * Makefile.in: Regenerate.
11 * aclocal.m4: Regenerate.
12 * config.in: Regenerate.
13 * configure: Regenerate.
14
899d85be
AM		 152008-08-14 Sebastian Huber <sebastian.huber@embedded-brains.de>
16
17 PR 6825
18 * ppc-opc.c (powerpc_opcodes): Enable rfci, mfpmr, mtpmr for e300.
19
dfb07592
L		 202008-08-12 H.J. Lu <hongjiu.lu@intel.com>
21
22 * i386-opc.tbl: Add syscall and sysret for Cpu64.
23
24 * i386-tbl.h: Regenerated.
25
323ee3f4
AM		 262008-08-04 Alan Modra <amodra@bigpond.net.au>
27
28 * Makefile.am (POTFILES.in): Set LC_ALL=C.
29 * Makefile.in: Regenerate.
30 * po/POTFILES.in: Regenerate.
31
9b4e5766
PB		 322008-08-01 Peter Bergner <bergner@vnet.ibm.com>
33
34 * ppc-dis.c (powerpc_init_dialect): Handle power7 and vsx options.
35 (print_insn_powerpc): Prepend 'vs' when printing VSX registers.
36 (print_ppc_disassembler_options): Document -Mpower7 and -Mvsx.
37 * ppc-opc.c (insert_xt6): New static function.
38 (extract_xt6): Likewise.
39 (insert_xa6): Likewise.
40 (extract_xa6: Likewise.
41 (insert_xb6): Likewise.
42 (extract_xb6): Likewise.
43 (insert_xb6s): Likewise.
44 (extract_xb6s): Likewise.
45 (XS6, XT6, XA6, XB6, XB6S, DM, XX3, XX3DM, XX1_MASK, XX3_MASK,
46 XX3DM_MASK, PPCVSX): New.
47 (powerpc_opcodes): Add opcodes "lxvd2x", "lxvd2ux", "stxvd2x",
48 "stxvd2ux", "xxmrghd", "xxmrgld", "xxpermdi", "xvmovdp", "xvcpsgndp".
49
20fd6e2e
PA		 502008-08-01 Pedro Alves <pedro@codesourcery.com>
51
52 * Makefile.am ($(srcdir)/ia64-asmtab.c): Remove line continuation.
53 * Makefile.in: Regenerate.
54
a656ed5b
L		 552008-08-01 H.J. Lu <hongjiu.lu@intel.com>
56
57 * i386-reg.tbl: Use Dw2Inval on AVX registers.
58 * i386-tbl.h: Regenerated.
59
081ba1b3
AM		 602008-07-30 Michael J. Eager <eager@eagercon.com>
61
62 * ppc-dis.c (print_insn_powerpc): Disassemble FSL/FCR/UDI fields.
63 * ppc-opc.c (powerpc_operands): Add Xilinx APU related operands.
64 (insert_sprg, PPC405): Use PPC_OPCODE_405.
65 (powerpc_opcodes): Add Xilinx APU related opcodes.
66
0af1713e
AM		 672008-07-30 Alan Modra <amodra@bigpond.net.au>
68
69 * bfin-dis.c, cris-dis.c, i386-dis.c, or32-opc.c: Silence gcc warnings.
70
30c09090
RS		 712008-07-10 Richard Sandiford <rdsandiford@googlemail.com>
72
73 * mips-dis.c (_print_insn_mips): Use ELF_ST_IS_MIPS16.
74
c27e721e
AN		 752008-07-07 Adam Nemet <anemet@caviumnetworks.com>
76
77 * mips-opc.c (CP): New macro.
78 (mips_builtin_opcodes): Mark c0, c2 and c3 as CP. Add Octeon to the
79 membership of di, dmfc0, dmtc0, ei, mfc0 and mtc0. Add dmfc2 and
80 dmtc2 Octeon instructions.
81
bd2e2557
SS		 822008-07-07 Stan Shebs <stan@codesourcery.com>
83
84 * dis-init.c (init_disassemble_info): Init endian_code field.
85 * arm-dis.c (print_insn): Disassemble code according to
86 setting of endian_code.
87 (print_insn_big_arm): Detect when BE8 extension flag has been set.
88
6ba2a415
RS		 892008-06-30 Richard Sandiford <rdsandiford@googlemail.com>
90
91 * mips-dis.c (_print_insn_mips): Use bfd_asymbol_flavour to check
92 for ELF symbols.
93
c8187e15
PB		 942008-06-25 Peter Bergner <bergner@vnet.ibm.com>
95
96 * ppc-dis.c (powerpc_init_dialect): Handle -M464.
97 (print_ppc_disassembler_options): Likewise.
98 * ppc-opc.c (PPC464): Define.
99 (powerpc_opcodes): Add mfdcrux and mtdcrux.
100
7a283e07
RW		 1012008-06-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
102
103 * configure: Regenerate.
104
fa452fa6
PB		 1052008-06-13 Peter Bergner <bergner@vnet.ibm.com>
106
107 * ppc-dis.c (print_insn_powerpc): Update prototye to use new
108 ppc_cpu_t typedef.
109 (struct dis_private): New.
110 (POWERPC_DIALECT): New define.
111 (powerpc_dialect): Renamed to...
112 (powerpc_init_dialect): This. Update to use ppc_cpu_t and
113 struct dis_private.
114 (print_insn_big_powerpc): Update for using structure in
115 info->private_data.
116 (print_insn_little_powerpc): Likewise.
117 (operand_value_powerpc): Change type of dialect param to ppc_cpu_t.
118 (skip_optional_operands): Likewise.
119 (print_insn_powerpc): Likewise. Remove initialization of dialect.
120 * ppc-opc.c (extract_bat, extract_bba, extract_bdm, extract_bdp,
121 extract_bo, extract_boe, extract_fxm, extract_mb6, extract_mbe,
122 extract_nb, extract_nsi, extract_rbs, extract_sh6, extract_spr,
123 extract_sprg, extract_tbr insert_bat, insert_bba, insert_bdm,
124 insert_bdp, insert_bo, insert_boe, insert_fxm, insert_mb6, insert_mbe,
125 insert_nsi, insert_ral, insert_ram, insert_raq, insert_ras, insert_rbs,
126 insert_sh6, insert_spr, insert_sprg, insert_tbr): Change the dialect
127 param to be of type ppc_cpu_t. Update prototype.
128
bb35fb24
NC		 1292008-06-12 Adam Nemet <anemet@caviumnetworks.com>
130
131 * mips-dis.c (print_insn_args): Handle field descriptors +x, +p,
132 +s, +S.
133 * mips-opc.c (mips_builtin_opcodes): Add Octeon instructions
134 baddu, bbit*, cins*, dmul, pop, dpop, exts*, mtm*, mtp*, syncs,
135 syncw, syncws, vm3mulu, vm0 and vmulu.
136
dd3cbb7e
NC		 137 * mips-dis.c (print_insn_args): Handle field descriptor +Q.
138 * mips-opc.c (mips_builtin_opcodes): Add Octeon instructions seq,
139 seqi, sne and snei.
140
a5dabbb0
L		 1412008-05-30 H.J. Lu <hongjiu.lu@intel.com>
142
143 * i386-opc.tbl: Add vmovd with 64bit operand.
144 * i386-tbl.h: Regenerated.
145
725a9891
MS		 1462008-05-27 Martin Schwidefsky <schwidefsky@de.ibm.com>
147
148 * s390-opc.c (INSTR_RRF_R0RR): Fix RRF_R0RR operand format.
149
cbc80391
L		 1502008-05-22 H.J. Lu <hongjiu.lu@intel.com>
151
152 * i386-opc.tbl: Add NoAVX to cvtpd2pi, cvtpi2pd and cvttpd2pi.
153 * i386-tbl.h: Regenerated.
154
116615c5
L		 1552008-05-22 H.J. Lu <hongjiu.lu@intel.com>
156
157 PR gas/6517
158 * i386-opc.tbl: Break cvtsi2ss/cvtsi2sd/vcvtsi2sd/vcvtsi2ss
159 into 32bit and 64bit. Remove Reg64|Qword and add
160 IgnoreSize|No_qSuf on 32bit version.
161 * i386-tbl.h: Regenerated.
162
d9479f2d
L		 1632008-05-21 H.J. Lu <hongjiu.lu@intel.com>
164
165 * i386-opc.tbl: Add NoAVX to movdq2q and movq2dq.
166 * i386-tbl.h: Regenerated.
167
3ce6fddb
NC		 1682008-05-21 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
169
170 * cr16-dis.c (build_mask): Adjust the mask for 32-bit bcond.
171
8944f3c2
AM		 1722008-05-14 Alan Modra <amodra@bigpond.net.au>
173
174 * Makefile.am: Run "make dep-am".
175 * Makefile.in: Regenerate.
176
f1f8f695
L		 1772008-05-02 H.J. Lu <hongjiu.lu@intel.com>
178
179 * i386-dis.c (MOVBE_Fixup): New.
180 (Mo): Likewise.
181 (PREFIX_0F3880): Likewise.
182 (PREFIX_0F3881): Likewise.
183 (PREFIX_0F38F0): Updated.
184 (prefix_table): Add PREFIX_0F3880 and PREFIX_0F3881. Update
185 PREFIX_0F38F0 and PREFIX_0F38F1 for movbe.
186 (three_byte_table): Use PREFIX_0F3880 and PREFIX_0F3881.
187
188 * i386-gen.c (cpu_flag_init): Add CPU_MOVBE_FLAGS and
189 CPU_EPT_FLAGS.
190 (cpu_flags): Add CpuMovbe and CpuEPT.
191
192 * i386-opc.h (CpuMovbe): New.
193 (CpuEPT): Likewise.
194 (CpuLM): Updated.
195 (i386_cpu_flags): Add cpumovbe and cpuept.
196
197 * i386-opc.tbl: Add entries for movbe and EPT instructions.
198 * i386-init.h: Regenerated.
199 * i386-tbl.h: Likewise.
200
89aa3097
AN		 2012008-04-29 Adam Nemet <anemet@caviumnetworks.com>
202
203 * mips-opc.c (mips_builtin_opcodes): Set field `match' to 0 for
204 the two drem and the two dremu macros.
205
39c5c168
AN		 2062008-04-28 Adam Nemet <anemet@caviumnetworks.com>
207
208 * mips-opc.c (mips_builtin_opcodes): Mark prefx and c1
209 instructions FP_S. Mark l.s, li.s, lwc1, swc1, s.s, trunc.w.s and
210 cop1 macros INSN2_M_FP_S. Mark l.d, li.d, ldc1 and sdc1 macros
211 INSN2_M_FP_D. Mark trunc.w.d macro INSN2_M_FP_S and INSN2_M_FP_D.
212
f04d18b7
DM		 2132008-04-25 David S. Miller <davem@davemloft.net>
214
215 * sparc-dis.c: Emit %stick instead of %sys_tick, and %stick_cmpr
216 instead of %sys_tick_cmpr, as suggested in architecture manuals.
217
6194aaab
L		 2182008-04-23 Paolo Bonzini <bonzini@gnu.org>
219
220 * aclocal.m4: Regenerate.
221 * configure: Regenerate.
222
1a6b486f
DM		 2232008-04-23 David S. Miller <davem@davemloft.net>
224
225 * sparc-opc.c (asi_table): Add UltraSPARC and Niagara
226 extended values.
227 (prefetch_table): Add missing values.
228
81f8a913
L		 2292008-04-22 H.J. Lu <hongjiu.lu@intel.com>
230
231 * i386-gen.c (opcode_modifiers): Add NoAVX.
232
233 * i386-opc.h (NoAVX): New.
234 (OldGcc): Updated.
235 (i386_opcode_modifier): Add noavx.
236
237 * i386-opc.tbl: Add NoAVX to SSE, SSE2, SSE3 and SSSE3
238 instructions which don't have AVX equivalent.
239 * i386-tbl.h: Regenerated.
240
dae39acc
L		 2412008-04-18 H.J. Lu <hongjiu.lu@intel.com>
242
243 * i386-dis.c (OP_VEX_FMA): New.
244 (OP_EX_VexImmW): Likewise.
245 (VexFMA): Likewise.
246 (Vex128FMA): Likewise.
247 (EXVexImmW): Likewise.
248 (get_vex_imm8): Likewise.
249 (OP_EX_VexReg): Likewise.
250 (vex_i4_done): Renamed to ...
251 (vex_w_done): This.
252 (prefix_table): Replace EXVexW with EXVexImmW on vpermil2ps
253 and vpermil2pd. Replace Vex/Vex128 with VexFMA/Vex128FMA on
254 FMA instructions.
255 (print_insn): Updated.
256 (OP_EX_VexW): Rewrite to swap register in VEX with EX.
257 (OP_REG_VexI4): Check invalid high registers.
258
ce886ab1
DR		 2592008-04-16 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
260 Michael Meissner <michael.meissner@amd.com>
261
262 * i386-opc.tbl: Fix protX to allow memory in the middle operand.
263 * i386-tbl.h: Regenerate from i386-opc.tbl.
8944f3c2 264
19a6653c
AM		 2652008-04-14 Edmar Wienskoski <edmar@freescale.com>
266
267 * ppc-dis.c (powerpc_dialect): Handle "e500mc". Extend "e500" to
268 accept Power E500MC instructions.
269 (print_ppc_disassembler_options): Document -Me500mc.
270 * ppc-opc.c (DUIS, DUI, T): New.
271 (XRT, XRTRA): Likewise.
272 (E500MC): Likewise.
273 (powerpc_opcodes): Add new Power E500MC instructions.
274
112b7c50
AK		 2752008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
276
277 * s390-dis.c (init_disasm): Evaluate disassembler_options.
278 (print_s390_disassembler_options): New function.
279 * disassemble.c (disassembler_usage): Invoke
280 print_s390_disassembler_options.
281
7ff42648
AK		 2822008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
283
284 * s390-mkopc.c (insertExpandedMnemonic): Expand string sizes
285 of local variables used for mnemonic parsing: prefix, suffix and
286 number.
287
45a5551e
AK		 2882008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
289
290 * s390-mkopc.c (s390_cond_ext_format): Add back the mnemonic
291 extensions for conditional jumps (o, p, m, nz, z, nm, np, no).
292 (s390_crb_extensions): New extensions table.
293 (insertExpandedMnemonic): Handle '$' tag.
294 * s390-opc.txt: Remove conditional jump variants which can now
295 be expanded automatically.
296 Replace '*' tag with '$' in the compare and branch instructions.
297
06c8514a
L		 2982008-04-07 H.J. Lu <hongjiu.lu@intel.com>
299
300 * i386-dis.c (PREFIX_VEX_38XX): Add a tab.
301 (PREFIX_VEX_3AXX): Likewis.
302
b122c285
L		 3032008-04-07 H.J. Lu <hongjiu.lu@intel.com>
304
305 * i386-opc.tbl: Remove 4 extra blank lines.
306
594ab6a3
L		 3072008-04-04 H.J. Lu <hongjiu.lu@intel.com>
308
309 * i386-gen.c (cpu_flag_init): Replace CPU_CLMUL_FLAGS/CpuCLMUL
310 with CPU_PCLMUL_FLAGS/CpuPCLMUL.
311 (cpu_flags): Replace CpuCLMUL with CpuPCLMUL.
312 * i386-opc.tbl: Likewise.
313
314 * i386-opc.h (CpuCLMUL): Renamed to ...
315 (CpuPCLMUL): This.
316 (CpuFMA): Updated.
317 (i386_cpu_flags): Replace cpuclmul with cpupclmul.
318
319 * i386-init.h: Regenerated.
320
c0f3af97
L		 3212008-04-03 H.J. Lu <hongjiu.lu@intel.com>
322
323 * i386-dis.c (OP_E_register): New.
324 (OP_E_memory): Likewise.
325 (OP_VEX): Likewise.
326 (OP_EX_Vex): Likewise.
327 (OP_EX_VexW): Likewise.
328 (OP_XMM_Vex): Likewise.
329 (OP_XMM_VexW): Likewise.
330 (OP_REG_VexI4): Likewise.
331 (PCLMUL_Fixup): Likewise.
332 (VEXI4_Fixup): Likewise.
333 (VZERO_Fixup): Likewise.
334 (VCMP_Fixup): Likewise.
335 (VPERMIL2_Fixup): Likewise.
336 (rex_original): Likewise.
337 (rex_ignored): Likewise.
338 (Mxmm): Likewise.
339 (XMM): Likewise.
340 (EXxmm): Likewise.
341 (EXxmmq): Likewise.
342 (EXymmq): Likewise.
343 (Vex): Likewise.
344 (Vex128): Likewise.
345 (Vex256): Likewise.
346 (VexI4): Likewise.
347 (EXdVex): Likewise.
348 (EXqVex): Likewise.
349 (EXVexW): Likewise.
350 (EXdVexW): Likewise.
351 (EXqVexW): Likewise.
352 (XMVex): Likewise.
353 (XMVexW): Likewise.
354 (XMVexI4): Likewise.
355 (PCLMUL): Likewise.
356 (VZERO): Likewise.
357 (VCMP): Likewise.
358 (VPERMIL2): Likewise.
359 (xmm_mode): Likewise.
360 (xmmq_mode): Likewise.
361 (ymmq_mode): Likewise.
362 (vex_mode): Likewise.
363 (vex128_mode): Likewise.
364 (vex256_mode): Likewise.
365 (USE_VEX_C4_TABLE): Likewise.
366 (USE_VEX_C5_TABLE): Likewise.
367 (USE_VEX_LEN_TABLE): Likewise.
368 (VEX_C4_TABLE): Likewise.
369 (VEX_C5_TABLE): Likewise.
370 (VEX_LEN_TABLE): Likewise.
371 (REG_VEX_XX): Likewise.
372 (MOD_VEX_XXX): Likewise.
373 (PREFIX_0F38DB..PREFIX_0F38DF): Likewise.
374 (PREFIX_0F3A44): Likewise.
375 (PREFIX_0F3ADF): Likewise.
376 (PREFIX_VEX_XXX): Likewise.
377 (VEX_OF): Likewise.
378 (VEX_OF38): Likewise.
379 (VEX_OF3A): Likewise.
380 (VEX_LEN_XXX): Likewise.
381 (vex): Likewise.
382 (need_vex): Likewise.
383 (need_vex_reg): Likewise.
384 (vex_i4_done): Likewise.
385 (vex_table): Likewise.
386 (vex_len_table): Likewise.
387 (OP_REG_VexI4): Likewise.
388 (vex_cmp_op): Likewise.
389 (pclmul_op): Likewise.
390 (vpermil2_op): Likewise.
391 (m_mode): Updated.
392 (es_reg): Likewise.
393 (PREFIX_0F38F0): Likewise.
394 (PREFIX_0F3A60): Likewise.
395 (reg_table): Add REG_VEX_71...REG_VEX_73 and REG_VEX_AE.
396 (prefix_table): Add PREFIX_0F38DB..PREFIX_0F38DF, PREFIX_0F3ADF
397 and PREFIX_VEX_XXX entries.
398 (x86_64_table): Use VEX_C4_TABLE and VEX_C5_TABLE.
399 (three_byte_table): Use PREFIX_0F38DB..PREFIX_0F38DF and
400 PREFIX_0F3ADF.
401 (mod_table): Use VEX_C4_TABLE, VEX_C5_TABLE and VEX_LEN_TABLE.
402 Add MOD_VEX_XXX entries.
403 (ckprefix): Initialize rex_original and rex_ignored. Store the
404 REX byte in rex_original.
405 (get_valid_dis386): Handle the implicit prefix in VEX prefix
406 bytes and USE_VEX_LEN_TABLE/USE_VEX_C4_TABLE/USE_VEX_C5_TABLE.
407 (print_insn): Set need_vex/need_vex_reg/vex_i4_done to 0 before
408 calling get_valid_dis386. Use rex_original and rex_ignored when
409 printing out REX.
410 (putop): Handle "XY".
411 (intel_operand_size): Handle VEX, xmm_mode, xmmq_mode and
412 ymmq_mode.
413 (OP_E_extended): Updated to use OP_E_register and
414 OP_E_memory.
415 (OP_XMM): Handle VEX.
416 (OP_EX): Likewise.
417 (XMM_Fixup): Likewise.
418 (CMP_Fixup): Use ARRAY_SIZE.
419
420 * i386-gen.c (cpu_flag_init): Add CpuAES, CPU_CLMUL_FLAGS,
421 CPU_FMA_FLAGS and CPU_AVX_FLAGS.
422 (operand_type_init): Add OPERAND_TYPE_REGYMM and
423 OPERAND_TYPE_VEX_IMM4.
424 (cpu_flags): Add CpuAVX, CpuAES, CpuCLMUL and CpuFMA.
425 (opcode_modifiers): Add Implicit1stXmm0, Vex, Vex256, VexNDD,
426 VexNDS, VexW0, VexW1, Vex0F, Vex0F38, Vex0F3A, Vex3Sources,
427 VexImmExt and SSE2AVX.
428 (operand_types): Add RegYMM, Ymmword and Vex_Imm4.
429
430 * i386-opc.h (CpuAVX): New.
431 (CpuAES): Likewise.
432 (CpuCLMUL): Likewise.
433 (CpuFMA): Likewise.
434 (Vex): Likewise.
435 (Vex256): Likewise.
436 (VexNDS): Likewise.
437 (VexNDD): Likewise.
438 (VexW0): Likewise.
439 (VexW1): Likewise.
440 (Vex0F): Likewise.
441 (Vex0F38): Likewise.
442 (Vex0F3A): Likewise.
443 (Vex3Sources): Likewise.
444 (VexImmExt): Likewise.
445 (SSE2AVX): Likewise.
446 (RegYMM): Likewise.
447 (Ymmword): Likewise.
448 (Vex_Imm4): Likewise.
449 (Implicit1stXmm0): Likewise.
450 (CpuXsave): Updated.
451 (CpuLM): Likewise.
452 (ByteOkIntel): Likewise.
453 (OldGcc): Likewise.
454 (Control): Likewise.
455 (Unspecified): Likewise.
456 (OTMax): Likewise.
457 (i386_cpu_flags): Add cpuavx, cpuaes, cpuclmul and cpufma.
458 (i386_opcode_modifier): Add implicit1stxmm0, vex, vex256,
459 vexnds, vexndd, vexw0, vexw1, vex0f, vex0f38, vex0f3a,
460 vex3sources, veximmext and sse2avx.
461 (i386_operand_type): Add regymm, ymmword and vex_imm4.
462
463 * i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions.
464
465 * i386-reg.tbl: Add AVX registers, ymm0..ymm15.
466
467 * i386-init.h: Regenerated.
468 * i386-tbl.h: Likewise.
469
b21c9cb4
BS		 4702008-03-26 Bernd Schmidt <bernd.schmidt@analog.com>
471
472 From Robin Getz <robin.getz@analog.com>
473 * bfin-dis.c (bu32): Typedef.
474 (enum const_forms_t): Add c_uimm32 and c_huimm32.
475 (constant_formats[]): Add uimm32 and huimm16.
476 (fmtconst_val): New.
477 (uimm32): Define.
478 (huimm32): Define.
479 (imm16_val): Define.
480 (luimm16_val): Define.
481 (struct saved_state): Define.
482 (GREG, DPREG, DREG, PREG, SPREG, FPREG, IREG, MREG, BREG, LREG,
483 A0XREG, A0WREG, A1XREG, A1WREG,CCREG, LC0REG, LT0REG, LB0REG,
484 LC1REG, LT1REG, LB1REG, RETSREG, PCREG): Define.
485 (get_allreg): New.
486 (decode_LDIMMhalf_0): Print out the whole register value.
487
ee171c8f
BS		 488 From Jie Zhang <jie.zhang@analog.com>
489 * bfin-dis.c (decode_dsp32mac_0): Decode (IU) option for
490 multiply and multiply-accumulate to data register instruction.
491
086134ec
BS		 492 * bfin-dis.c: (c_uimm4s4d, c_imm5d, c_imm7d, c_imm16d, c_uimm16s4d,
493 c_imm32, c_huimm32e): Define.
494 (constant_formats): Add flags for printing decimal, leading spaces, and
495 exact symbols.
496 (comment, parallel): Add global flags in all disassembly.
497 (fmtconst): Take advantage of new flags, and print default in hex.
498 (fmtconst_val): Likewise.
499 (decode_macfunc): Be consistant with spaces, tabs, comments,
500 capitalization in disassembly, fix minor coding style issues.
501 (reg_names, amod0, amod1, amod0amod2, aligndir, get_allreg): Likewise.
502 (decode_ProgCtrl_0, decode_PushPopMultiple_0, decode_CCflag_0,
503 decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0,
504 decode_REGMV_0, decode_ALU2op_0, decode_PTR2op_0, decode_LOGI2op_0,
505 decode_COMP3op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
506 decode_LDSTpmod_0, decode_dagMODim_0, decode_dagMODik_0,
507 decode_dspLDST_0, decode_LDST_0, decode_LDSTiiFP_0, decode_LDSTii_0,
508 decode_LoopSetup_0, decode_LDIMMhalf_0, decode_CALLa_0,
509 decode_LDSTidxI_0, decode_linkage_0, decode_dsp32alu_0,
510 decode_dsp32shift_0, decode_dsp32shiftimm_0, decode_pseudodbg_assert_0,
511 _print_insn_bfin, print_insn_bfin): Likewise.
512
58c85be7
RW		 5132008-03-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
514
515 * aclocal.m4: Regenerate.
516 * configure: Likewise.
517 * Makefile.in: Likewise.
518
50e7d84b
AM		 5192008-03-13 Alan Modra <amodra@bigpond.net.au>
520
521 * Makefile.am: Run "make dep-am".
522 * Makefile.in: Regenerate.
523 * configure: Regenerate.
524
de866fcc
AM		 5252008-03-07 Alan Modra <amodra@bigpond.net.au>
526
527 * ppc-opc.c (powerpc_opcodes): Order and format.
528
28dbc079
L		 5292008-03-01 H.J. Lu <hongjiu.lu@intel.com>
530
531 * i386-opc.tbl: Allow 16-bit near indirect branches for x86-64.
532 * i386-tbl.h: Regenerated.
533
849830bd
L		 5342008-02-23 H.J. Lu <hongjiu.lu@intel.com>
535
536 * i386-opc.tbl: Disallow 16-bit near indirect branches for
537 x86-64.
538 * i386-tbl.h: Regenerated.
539
743ddb6b
JB		 5402008-02-21 Jan Beulich <jbeulich@novell.com>
541
542 * i386-opc.tbl: Allow Dword for far indirect call. Allow Dword
543 and Fword for far indirect jmp. Allow Reg16 and Word for near
544 indirect jmp on x86-64. Disallow Fword for lcall.
545 * i386-tbl.h: Re-generate.
546
796d5313
NC		 5472008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
548
549 * cr16-opc.c (cr16_num_optab): Defined
550
65da13b5
L		 5512008-02-16 H.J. Lu <hongjiu.lu@intel.com>
552
553 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_INOUTPORTREG.
554 * i386-init.h: Regenerated.
555
0e336180
NC		 5562008-02-14 Nick Clifton <nickc@redhat.com>
557
558 PR binutils/5524
559 * configure.in (SHARED_LIBADD): Select the correct host specific
560 file extension for shared libraries.
561 * configure: Regenerate.
562
b7240065
JB		 5632008-02-13 Jan Beulich <jbeulich@novell.com>
564
565 * i386-opc.h (RegFlat): New.
566 * i386-reg.tbl (flat): Add.
567 * i386-tbl.h: Re-generate.
568
34b772a6
JB		 5692008-02-13 Jan Beulich <jbeulich@novell.com>
570
571 * i386-dis.c (a_mode): New.
572 (cond_jump_mode): Adjust.
573 (Ma): Change to a_mode.
574 (intel_operand_size): Handle a_mode.
575 * i386-opc.tbl: Allow Dword and Qword for bound.
576 * i386-tbl.h: Re-generate.
577
a60de03c
JB		 5782008-02-13 Jan Beulich <jbeulich@novell.com>
579
580 * i386-gen.c (process_i386_registers): Process new fields.
581 * i386-opc.h (reg_entry): Shrink reg_flags and reg_num to
582 unsigned char. Add dw2_regnum and Dw2Inval.
583 * i386-reg.tbl: Provide initializers for dw2_regnum. Add pseudo
584 register names.
585 * i386-tbl.h: Re-generate.
586
f03fe4c1
L		 5872008-02-11 H.J. Lu <hongjiu.lu@intel.com>
588
4b6bc8eb 589 * i386-gen.c (cpu_flag_init): Add CPU_XSAVE_FLAGS.
f03fe4c1
L		 590 * i386-init.h: Updated.
591
475a2301
L		 5922008-02-11 H.J. Lu <hongjiu.lu@intel.com>
593
594 * i386-gen.c (cpu_flags): Add CpuXsave.
595
596 * i386-opc.h (CpuXsave): New.
4b6bc8eb 597 (CpuLM): Updated.
475a2301
L		 598 (i386_cpu_flags): Add cpuxsave.
599
600 * i386-dis.c (MOD_0FAE_REG_4): New.
601 (RM_0F01_REG_2): Likewise.
602 (MOD_0FAE_REG_5): Updated.
603 (RM_0F01_REG_3): Likewise.
604 (reg_table): Use MOD_0FAE_REG_4.
605 (mod_table): Use RM_0F01_REG_2. Add MOD_0FAE_REG_4. Updated
606 for xrstor.
607 (rm_table): Add RM_0F01_REG_2.
608
609 * i386-opc.tbl: Add xsave, xrstor, xgetbv and xsetbv.
610 * i386-init.h: Regenerated.
611 * i386-tbl.h: Likewise.
612
595785c6 6132008-02-11 Jan Beulich <jbeulich@novell.com>
041179fc 614
595785c6
JB		 615 * i386-opc.tbl: Remove Disp32S from CpuNo64 opcodes. Remove
616 Disp16 from Cpu64 non-jump opcodes (including loop and j?cxz).
617 * i386-tbl.h: Re-generate.
618
bb8541b9
L		 6192008-02-04 H.J. Lu <hongjiu.lu@intel.com>
620
621 PR 5715
622 * configure: Regenerated.
623
57b592a3
AN		 6242008-02-04 Adam Nemet <anemet@caviumnetworks.com>
625
626 * mips-dis.c: Update copyright.
627 (mips_arch_choices): Add Octeon.
628 * mips-opc.c: Update copyright.
629 (IOCT): New macro.
630 (mips_builtin_opcodes): Add Octeon instruction synciobdma.
631
930bb4cf
AM		 6322008-01-29 Alan Modra <amodra@bigpond.net.au>
633
634 * ppc-opc.c: Support optional L form mtmsr.
635
82c18208
L		 6362008-01-24 H.J. Lu <hongjiu.lu@intel.com>
637
638 * i386-dis.c (OP_E_extended): Handle r12 like rsp.
639
599121aa
L		 6402008-01-23 H.J. Lu <hongjiu.lu@intel.com>
641
642 * i386-gen.c (cpu_flag_init): Add CpuLM to CPU_GENERIC64_FLAGS.
643 * i386-init.h: Regenerated.
644
80098f51
TG		 6452008-01-23 Tristan Gingold <gingold@adacore.com>
646
647 * ia64-dis.c (print_insn_ia64): Display symbolic name of ar.fcr,
648 ar.eflag, ar.csd, ar.ssd, ar.cflg, ar.fsr, ar.fir and ar.fdr.
649
115c7c25
L		 6502008-01-22 H.J. Lu <hongjiu.lu@intel.com>
651
652 * i386-gen.c (cpu_flag_init): Remove CpuMMX2.
653 (cpu_flags): Likewise.
654
655 * i386-opc.h (CpuMMX2): Removed.
656 (CpuSSE): Updated.
657
658 * i386-opc.tbl: Replace CpuMMX2 with CpuSSE|Cpu3dnowA.
659 * i386-init.h: Regenerated.
660 * i386-tbl.h: Likewise.
661
6305a203
L		 6622008-01-22 H.J. Lu <hongjiu.lu@intel.com>
663
664 * i386-gen.c (cpu_flag_init): Add CPU_VMX_FLAGS and
665 CPU_SMX_FLAGS.
666 * i386-init.h: Regenerated.
667
fd07a1c8
L		 6682008-01-15 H.J. Lu <hongjiu.lu@intel.com>
669
670 * i386-opc.tbl: Use Qword on movddup.
671 * i386-tbl.h: Regenerated.
672
321fd21e
L		 6732008-01-15 H.J. Lu <hongjiu.lu@intel.com>
674
675 * i386-opc.tbl: Put back 16bit movsx/movzx for AT&T syntax.
676 * i386-tbl.h: Regenerated.
677
4ee52178
L		 6782008-01-15 H.J. Lu <hongjiu.lu@intel.com>
679
680 * i386-dis.c (Mx): New.
681 (PREFIX_0FC3): Likewise.
682 (PREFIX_0FC7_REG_6): Updated.
683 (dis386_twobyte): Use PREFIX_0FC3.
684 (prefix_table): Add PREFIX_0FC3. Use Mq on movntq and movntsd.
685 Use Mx on movntps, movntpd, movntdq and movntdqa. Use Md on
686 movntss.
687
5c07affc
L		 6882008-01-14 H.J. Lu <hongjiu.lu@intel.com>
689
690 * i386-gen.c (opcode_modifiers): Add IntelSyntax.
691 (operand_types): Add Mem.
692
693 * i386-opc.h (IntelSyntax): New.
694 * i386-opc.h (Mem): New.
695 (Byte): Updated.
696 (Opcode_Modifier_Max): Updated.
697 (i386_opcode_modifier): Add intelsyntax.
698 (i386_operand_type): Add mem.
699
700 * i386-opc.tbl: Remove Reg16 from movnti. Add sizes to more
701 instructions.
702
703 * i386-reg.tbl: Add size for accumulator.
704
705 * i386-init.h: Regenerated.
706 * i386-tbl.h: Likewise.
707
0d6a2f58
L		 7082008-01-13 H.J. Lu <hongjiu.lu@intel.com>
709
710 * i386-opc.h (Byte): Fix a typo.
711
7d5e4556
L		 7122008-01-12 H.J. Lu <hongjiu.lu@intel.com>
713
714 PR gas/5534
715 * i386-gen.c (operand_type_init): Add Dword to
716 OPERAND_TYPE_ACC32. Add Qword to OPERAND_TYPE_ACC64.
717 (opcode_modifiers): Remove CheckSize, Byte, Word, Dword,
718 Qword and Xmmword.
719 (operand_types): Add Byte, Word, Dword, Fword, Qword, Tbyte,
720 Xmmword, Unspecified and Anysize.
721 (set_bitfield): Make Mmword an alias of Qword. Make Oword
722 an alias of Xmmword.
723
724 * i386-opc.h (CheckSize): Removed.
725 (Byte): Updated.
726 (Word): Likewise.
727 (Dword): Likewise.
728 (Qword): Likewise.
729 (Xmmword): Likewise.
730 (FWait): Updated.
731 (OTMax): Likewise.
732 (i386_opcode_modifier): Remove checksize, byte, word, dword,
733 qword and xmmword.
734 (Fword): New.
735 (TBYTE): Likewise.
736 (Unspecified): Likewise.
737 (Anysize): Likewise.
738 (i386_operand_type): Add byte, word, dword, fword, qword,
739 tbyte xmmword, unspecified and anysize.
740
741 * i386-opc.tbl: Updated to use Byte, Word, Dword, Fword, Qword,
742 Tbyte, Xmmword, Unspecified and Anysize.
743
744 * i386-reg.tbl: Add size for accumulator.
745
746 * i386-init.h: Regenerated.
747 * i386-tbl.h: Likewise.
748
b5b1fc4f
L		 7492008-01-10 H.J. Lu <hongjiu.lu@intel.com>
750
751 * i386-dis.c (REG_0F0E): Renamed to REG_0F0D.
752 (REG_0F18): Updated.
753 (reg_table): Updated.
754 (dis386_twobyte): Updated. Use "nopQ" on 0x19 to 0x1e.
755 (twobyte_has_modrm): Set 1 for 0x19 to 0x1e.
756
50e8458f
L		 7572008-01-08 H.J. Lu <hongjiu.lu@intel.com>
758
759 * i386-gen.c (set_bitfield): Use fail () on error.
760
3d4d5afa
L		 7612008-01-08 H.J. Lu <hongjiu.lu@intel.com>
762
763 * i386-gen.c (lineno): New.
764 (filename): Likewise.
765 (set_bitfield): Report filename and line numer on error.
766 (process_i386_opcodes): Set filename and update lineno.
767 (process_i386_registers): Likewise.
768
e1d4d893
L		 7692008-01-05 H.J. Lu <hongjiu.lu@intel.com>
770
771 * i386-gen.c (opcode_modifiers): Rename IntelMnemonic to
772 ATTSyntax.
773
774 * i386-opc.h (IntelMnemonic): Renamed to ..
775 (ATTSyntax): This
776 (Opcode_Modifier_Max): Updated.
777 (i386_opcode_modifier): Remove intelmnemonic. Add attsyntax
778 and intelsyntax.
779
8944f3c2 780 * i386-opc.tbl: Remove IntelMnemonic and update with ATTSyntax
e1d4d893
L		 781 on fsub, fubp, fsubr, fsubrp, div, fdivp, fdivr and fdivrp.
782 * i386-tbl.h: Regenerated.
783
6f143e4d
L		 7842008-01-04 H.J. Lu <hongjiu.lu@intel.com>
785
786 * i386-gen.c: Update copyright to 2008.
787 * i386-opc.h: Likewise.
788 * i386-opc.tbl: Likewise.
789
790 * i386-init.h: Regenerated.
791 * i386-tbl.h: Likewise.
792
c6add537
L		 7932008-01-04 H.J. Lu <hongjiu.lu@intel.com>
794
795 * i386-opc.tbl: Add NoRex64 to extractps, movmskpd, movmskps,
796 pextrb, pextrw, pinsrb, pinsrw and pmovmskb.
797 * i386-tbl.h: Regenerated.
798
3629bb00
L		 7992008-01-03 H.J. Lu <hongjiu.lu@intel.com>
800
801 * i386-gen.c (cpu_flag_init): Remove CpuSSE4_1_Or_5 and
802 CpuSSE4_2_Or_ABM.
803 (cpu_flags): Likewise.
804
805 * i386-opc.h (CpuSSE4_1_Or_5): Removed.
806 (CpuSSE4_2_Or_ABM): Likewise.
807 (CpuLM): Updated.
808 (i386_cpu_flags): Remove cpusse4_1_or_5 and cpusse4_2_or_abm.
809
810 * i386-opc.tbl: Replace CpuSSE4_1_Or_5, CpuSSE4_2_Or_ABM and
811 Cpu686|CpuPadLock with CpuSSE4_1|CpuSSE5, CpuABM|CpuSSE4_2
812 and CpuPadLock, respectively.
813 * i386-init.h: Regenerated.
814 * i386-tbl.h: Likewise.
815
24995bd6
L		 8162008-01-03 H.J. Lu <hongjiu.lu@intel.com>
817
818 * i386-gen.c (opcode_modifiers): Remove No_xSuf.
819
820 * i386-opc.h (No_xSuf): Removed.
821 (CheckSize): Updated.
822
823 * i386-tbl.h: Regenerated.
824
e0329a22
L		 8252008-01-02 H.J. Lu <hongjiu.lu@intel.com>
826
827 * i386-gen.c (cpu_flag_init): Add CpuSSE4_2_Or_ABM to
828 CPU_AMDFAM10_FLAGS, CPU_SSE4_2_FLAGS, CpuABM and
829 CPU_SSE5_FLAGS.
830 (cpu_flags): Add CpuSSE4_2_Or_ABM.
831
832 * i386-opc.h (CpuSSE4_2_Or_ABM): New.
833 (CpuLM): Updated.
834 (i386_cpu_flags): Add cpusse4_2_or_abm.
835
836 * i386-opc.tbl: Use CpuSSE4_2_Or_ABM instead of
837 CpuABM|CpuSSE4_2 on popcnt.
838 * i386-init.h: Regenerated.
839 * i386-tbl.h: Likewise.
840
f2a9c676
L		 8412008-01-02 H.J. Lu <hongjiu.lu@intel.com>
842
843 * i386-opc.h: Update comments.
844
d978b5be
L		 8452008-01-02 H.J. Lu <hongjiu.lu@intel.com>
846
847 * i386-gen.c (opcode_modifiers): Use Qword instead of QWord.
848 * i386-opc.h: Likewise.
849 * i386-opc.tbl: Likewise.
850
582d5edd
L		 8512008-01-02 H.J. Lu <hongjiu.lu@intel.com>
852
853 PR gas/5534
854 * i386-gen.c (opcode_modifiers): Add No_xSuf, CheckSize,
855 Byte, Word, Dword, QWord and Xmmword.
856
857 * i386-opc.h (No_xSuf): New.
858 (CheckSize): Likewise.
859 (Byte): Likewise.
860 (Word): Likewise.
861 (Dword): Likewise.
862 (QWord): Likewise.
863 (Xmmword): Likewise.
864 (FWait): Updated.
865 (i386_opcode_modifier): Add No_xSuf, CheckSize, Byte, Word,
866 Dword, QWord and Xmmword.
867
868 * i386-opc.tbl: Add CheckSize|QWord to movq if IgnoreSize is
869 used.
870 * i386-tbl.h: Regenerated.
871
3fe15143
MK		 8722008-01-02 Mark Kettenis <kettenis@gnu.org>
873
874 * m88k-dis.c (instructions): Fix fcvt.* instructions.
875 From Miod Vallat.
876
6c7ac64e 877For older changes see ChangeLog-2007
252b5132
RH		 878\f
879Local Variables:
2f6d2f85
NC		 880mode: change-log
881left-margin: 8
882fill-column: 74
252b5132
RH		 883version-control: never
884End:
GDB Binutils - Deliverables
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