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[deliverable/binutils-gdb.git] / opcodes / ChangeLog
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782e11fd
AM		 12008-09-30 Alan Modra <amodra@bigpond.net.au>
2
3 * Makefile.am: Run "make dep-am".
4 * Makefile.in: Regenerate.
5
1927a18f
L		 62008-09-29 H.J. Lu <hongjiu.lu@intel.com>
7
8 * aclocal.m4: Regenerated.
9 * configure: Likewise.
10 * Makefile.in: Likewise.
11
afac680a
NC		 122008-09-29 Nick Clifton <nickc@redhat.com>
13
14 * po/vi.po: Updated Vietnamese translation.
15 * po/fr.po: Updated French translation.
16
b40d5eb9
AK		 172008-09-26 Florian Krohm <fkrohm@us.ibm.com>
18
19 * s390-opc.txt (thder, thdr): Change RRE_RR to RRE_FF.
20 (cfxr, cfdr, cfer, clclu): Add esa flag.
21 (sqd): Instruction added.
22 (qadtr, qaxtr): Change RRF_FFFU to RRF_FUFF.
23 * s390-opc.c: (INSTR_RRF_FFFU, MASK_RRF_FFFU): Removed.
24
d0411736
AM		 252008-09-14 Arnold Metselaar <arnold.metselaar@planet.nl>
26
27 * z80-dis.c (prt_rr_nn): Fix register pair for two byte opcodes.
28 (tab_elt opc_ed): Add "ld r,a" and "ld r,a" instructions.
29
3e126784
L		 302008-09-11 H.J. Lu <hongjiu.lu@intel.com>
31
32 * i386-opc.tbl: Fix memory operand size for cmpXXXs[sd].
33 * i386-tbl.h: Regenerated.
34
ddab3d59
JB		 352008-08-28 Jan Beulich <jbeulich@novell.com>
36
37 * i386-dis.c (dis386): Adjust far return mnemonics.
38 * i386-opc.tbl: Add retf.
39 * i386-tbl.h: Re-generate.
40
b19d5385
JB		 412008-08-28 Jan Beulich <jbeulich@novell.com>
42
43 * i386-dis.c (dis386_twobyte): Adjust cmovXX mnemonics.
44
1ca35711
L		 452008-08-28 H.J. Lu <hongjiu.lu@intel.com>
46
47 * ia64-dis.c (print_insn_ia64): Handle cr.iib0 and cr.iib1.
48 * ia64-gen.c (lookup_specifier): Likewise.
49
50 * ia64-ic.tbl: Add support for cr.iib0 and cr.iib1.
51 * ia64-raw.tbl: Likewise.
52 * ia64-waw.tbl: Likewise.
53 * ia64-asmtab.c: Regenerated.
54
515c56e7
L		 552008-08-27 H.J. Lu <hongjiu.lu@intel.com>
56
57 * i386-opc.tbl: Correct fidivr operand size.
58
59 * i386-tbl.h: Regenerated.
60
da594c4a
AM		 612008-08-24 Alan Modra <amodra@bigpond.net.au>
62
63 * configure.in: Update a number of obsolete autoconf macros.
64 * aclocal.m4: Regenerate.
65
a5ff0eb2
L		 662008-08-20 H.J. Lu <hongjiu.lu@intel.com>
67
68 AVX Programming Reference (August, 2008)
69 * i386-dis.c (PREFIX_VEX_38DB): New.
70 (PREFIX_VEX_38DC): Likewise.
71 (PREFIX_VEX_38DD): Likewise.
72 (PREFIX_VEX_38DE): Likewise.
73 (PREFIX_VEX_38DF): Likewise.
74 (PREFIX_VEX_3ADF): Likewise.
75 (VEX_LEN_38DB_P_2): Likewise.
76 (VEX_LEN_38DC_P_2): Likewise.
77 (VEX_LEN_38DD_P_2): Likewise.
78 (VEX_LEN_38DE_P_2): Likewise.
79 (VEX_LEN_38DF_P_2): Likewise.
80 (VEX_LEN_3ADF_P_2): Likewise.
81 (PREFIX_VEX_3A04): Updated.
82 (VEX_LEN_3A06_P_2): Likewise.
83 (prefix_table): Add PREFIX_VEX_38DB, PREFIX_VEX_38DC,
84 PREFIX_VEX_38DD, PREFIX_VEX_38DE and PREFIX_VEX_3ADF.
85 (x86_64_table): Likewise.
86 (vex_len_table): Add VEX_LEN_38DB_P_2, VEX_LEN_38DC_P_2,
87 VEX_LEN_38DD_P_2, VEX_LEN_38DE_P_2, VEX_LEN_38DF_P_2 and
88 VEX_LEN_3ADF_P_2.
89
90 * i386-opc.tbl: Add AES + AVX instructions.
91 * i386-init.h: Regenerated.
92 * i386-tbl.h: Likewise.
93
7dc6076f
AK		 942008-08-15 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
95
96 * s390-opc.c (INSTR_RRF_FFRU, MASK_RRF_FFRU): New instruction format.
97 * s390-opc.txt (lxr, rrdtr, rrxtr): Fix instruction format.
98
7357c5b6
AM		 992008-08-15 Alan Modra <amodra@bigpond.net.au>
100
101 PR 6526
102 * configure.in: Invoke AC_USE_SYSTEM_EXTENSIONS.
103 * Makefile.in: Regenerate.
104 * aclocal.m4: Regenerate.
105 * config.in: Regenerate.
106 * configure: Regenerate.
107
899d85be
AM		 1082008-08-14 Sebastian Huber <sebastian.huber@embedded-brains.de>
109
110 PR 6825
111 * ppc-opc.c (powerpc_opcodes): Enable rfci, mfpmr, mtpmr for e300.
112
dfb07592
L		 1132008-08-12 H.J. Lu <hongjiu.lu@intel.com>
114
115 * i386-opc.tbl: Add syscall and sysret for Cpu64.
116
117 * i386-tbl.h: Regenerated.
118
323ee3f4
AM		 1192008-08-04 Alan Modra <amodra@bigpond.net.au>
120
121 * Makefile.am (POTFILES.in): Set LC_ALL=C.
122 * Makefile.in: Regenerate.
123 * po/POTFILES.in: Regenerate.
124
9b4e5766
PB		 1252008-08-01 Peter Bergner <bergner@vnet.ibm.com>
126
127 * ppc-dis.c (powerpc_init_dialect): Handle power7 and vsx options.
128 (print_insn_powerpc): Prepend 'vs' when printing VSX registers.
129 (print_ppc_disassembler_options): Document -Mpower7 and -Mvsx.
130 * ppc-opc.c (insert_xt6): New static function.
131 (extract_xt6): Likewise.
132 (insert_xa6): Likewise.
133 (extract_xa6: Likewise.
134 (insert_xb6): Likewise.
135 (extract_xb6): Likewise.
136 (insert_xb6s): Likewise.
137 (extract_xb6s): Likewise.
138 (XS6, XT6, XA6, XB6, XB6S, DM, XX3, XX3DM, XX1_MASK, XX3_MASK,
139 XX3DM_MASK, PPCVSX): New.
140 (powerpc_opcodes): Add opcodes "lxvd2x", "lxvd2ux", "stxvd2x",
141 "stxvd2ux", "xxmrghd", "xxmrgld", "xxpermdi", "xvmovdp", "xvcpsgndp".
142
20fd6e2e
PA		 1432008-08-01 Pedro Alves <pedro@codesourcery.com>
144
145 * Makefile.am ($(srcdir)/ia64-asmtab.c): Remove line continuation.
146 * Makefile.in: Regenerate.
147
a656ed5b
L		 1482008-08-01 H.J. Lu <hongjiu.lu@intel.com>
149
150 * i386-reg.tbl: Use Dw2Inval on AVX registers.
151 * i386-tbl.h: Regenerated.
152
081ba1b3
AM		 1532008-07-30 Michael J. Eager <eager@eagercon.com>
154
155 * ppc-dis.c (print_insn_powerpc): Disassemble FSL/FCR/UDI fields.
156 * ppc-opc.c (powerpc_operands): Add Xilinx APU related operands.
157 (insert_sprg, PPC405): Use PPC_OPCODE_405.
158 (powerpc_opcodes): Add Xilinx APU related opcodes.
159
0af1713e
AM		 1602008-07-30 Alan Modra <amodra@bigpond.net.au>
161
162 * bfin-dis.c, cris-dis.c, i386-dis.c, or32-opc.c: Silence gcc warnings.
163
30c09090
RS		 1642008-07-10 Richard Sandiford <rdsandiford@googlemail.com>
165
166 * mips-dis.c (_print_insn_mips): Use ELF_ST_IS_MIPS16.
167
c27e721e
AN		 1682008-07-07 Adam Nemet <anemet@caviumnetworks.com>
169
170 * mips-opc.c (CP): New macro.
171 (mips_builtin_opcodes): Mark c0, c2 and c3 as CP. Add Octeon to the
172 membership of di, dmfc0, dmtc0, ei, mfc0 and mtc0. Add dmfc2 and
173 dmtc2 Octeon instructions.
174
bd2e2557
SS		 1752008-07-07 Stan Shebs <stan@codesourcery.com>
176
177 * dis-init.c (init_disassemble_info): Init endian_code field.
178 * arm-dis.c (print_insn): Disassemble code according to
179 setting of endian_code.
180 (print_insn_big_arm): Detect when BE8 extension flag has been set.
181
6ba2a415
RS		 1822008-06-30 Richard Sandiford <rdsandiford@googlemail.com>
183
184 * mips-dis.c (_print_insn_mips): Use bfd_asymbol_flavour to check
185 for ELF symbols.
186
c8187e15
PB		 1872008-06-25 Peter Bergner <bergner@vnet.ibm.com>
188
189 * ppc-dis.c (powerpc_init_dialect): Handle -M464.
190 (print_ppc_disassembler_options): Likewise.
191 * ppc-opc.c (PPC464): Define.
192 (powerpc_opcodes): Add mfdcrux and mtdcrux.
193
7a283e07
RW		 1942008-06-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
195
196 * configure: Regenerate.
197
fa452fa6
PB		 1982008-06-13 Peter Bergner <bergner@vnet.ibm.com>
199
200 * ppc-dis.c (print_insn_powerpc): Update prototye to use new
201 ppc_cpu_t typedef.
202 (struct dis_private): New.
203 (POWERPC_DIALECT): New define.
204 (powerpc_dialect): Renamed to...
205 (powerpc_init_dialect): This. Update to use ppc_cpu_t and
206 struct dis_private.
207 (print_insn_big_powerpc): Update for using structure in
208 info->private_data.
209 (print_insn_little_powerpc): Likewise.
210 (operand_value_powerpc): Change type of dialect param to ppc_cpu_t.
211 (skip_optional_operands): Likewise.
212 (print_insn_powerpc): Likewise. Remove initialization of dialect.
213 * ppc-opc.c (extract_bat, extract_bba, extract_bdm, extract_bdp,
214 extract_bo, extract_boe, extract_fxm, extract_mb6, extract_mbe,
215 extract_nb, extract_nsi, extract_rbs, extract_sh6, extract_spr,
216 extract_sprg, extract_tbr insert_bat, insert_bba, insert_bdm,
217 insert_bdp, insert_bo, insert_boe, insert_fxm, insert_mb6, insert_mbe,
218 insert_nsi, insert_ral, insert_ram, insert_raq, insert_ras, insert_rbs,
219 insert_sh6, insert_spr, insert_sprg, insert_tbr): Change the dialect
220 param to be of type ppc_cpu_t. Update prototype.
221
bb35fb24
NC		 2222008-06-12 Adam Nemet <anemet@caviumnetworks.com>
223
224 * mips-dis.c (print_insn_args): Handle field descriptors +x, +p,
225 +s, +S.
226 * mips-opc.c (mips_builtin_opcodes): Add Octeon instructions
227 baddu, bbit*, cins*, dmul, pop, dpop, exts*, mtm*, mtp*, syncs,
228 syncw, syncws, vm3mulu, vm0 and vmulu.
229
dd3cbb7e
NC		 230 * mips-dis.c (print_insn_args): Handle field descriptor +Q.
231 * mips-opc.c (mips_builtin_opcodes): Add Octeon instructions seq,
232 seqi, sne and snei.
233
a5dabbb0
L		 2342008-05-30 H.J. Lu <hongjiu.lu@intel.com>
235
236 * i386-opc.tbl: Add vmovd with 64bit operand.
237 * i386-tbl.h: Regenerated.
238
725a9891
MS		 2392008-05-27 Martin Schwidefsky <schwidefsky@de.ibm.com>
240
241 * s390-opc.c (INSTR_RRF_R0RR): Fix RRF_R0RR operand format.
242
cbc80391
L		 2432008-05-22 H.J. Lu <hongjiu.lu@intel.com>
244
245 * i386-opc.tbl: Add NoAVX to cvtpd2pi, cvtpi2pd and cvttpd2pi.
246 * i386-tbl.h: Regenerated.
247
116615c5
L		 2482008-05-22 H.J. Lu <hongjiu.lu@intel.com>
249
250 PR gas/6517
251 * i386-opc.tbl: Break cvtsi2ss/cvtsi2sd/vcvtsi2sd/vcvtsi2ss
252 into 32bit and 64bit. Remove Reg64|Qword and add
253 IgnoreSize|No_qSuf on 32bit version.
254 * i386-tbl.h: Regenerated.
255
d9479f2d
L		 2562008-05-21 H.J. Lu <hongjiu.lu@intel.com>
257
258 * i386-opc.tbl: Add NoAVX to movdq2q and movq2dq.
259 * i386-tbl.h: Regenerated.
260
3ce6fddb
NC		 2612008-05-21 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
262
263 * cr16-dis.c (build_mask): Adjust the mask for 32-bit bcond.
264
8944f3c2
AM		 2652008-05-14 Alan Modra <amodra@bigpond.net.au>
266
267 * Makefile.am: Run "make dep-am".
268 * Makefile.in: Regenerate.
269
f1f8f695
L		 2702008-05-02 H.J. Lu <hongjiu.lu@intel.com>
271
272 * i386-dis.c (MOVBE_Fixup): New.
273 (Mo): Likewise.
274 (PREFIX_0F3880): Likewise.
275 (PREFIX_0F3881): Likewise.
276 (PREFIX_0F38F0): Updated.
277 (prefix_table): Add PREFIX_0F3880 and PREFIX_0F3881. Update
278 PREFIX_0F38F0 and PREFIX_0F38F1 for movbe.
279 (three_byte_table): Use PREFIX_0F3880 and PREFIX_0F3881.
280
281 * i386-gen.c (cpu_flag_init): Add CPU_MOVBE_FLAGS and
282 CPU_EPT_FLAGS.
283 (cpu_flags): Add CpuMovbe and CpuEPT.
284
285 * i386-opc.h (CpuMovbe): New.
286 (CpuEPT): Likewise.
287 (CpuLM): Updated.
288 (i386_cpu_flags): Add cpumovbe and cpuept.
289
290 * i386-opc.tbl: Add entries for movbe and EPT instructions.
291 * i386-init.h: Regenerated.
292 * i386-tbl.h: Likewise.
293
89aa3097
AN		 2942008-04-29 Adam Nemet <anemet@caviumnetworks.com>
295
296 * mips-opc.c (mips_builtin_opcodes): Set field `match' to 0 for
297 the two drem and the two dremu macros.
298
39c5c168
AN		 2992008-04-28 Adam Nemet <anemet@caviumnetworks.com>
300
301 * mips-opc.c (mips_builtin_opcodes): Mark prefx and c1
302 instructions FP_S. Mark l.s, li.s, lwc1, swc1, s.s, trunc.w.s and
303 cop1 macros INSN2_M_FP_S. Mark l.d, li.d, ldc1 and sdc1 macros
304 INSN2_M_FP_D. Mark trunc.w.d macro INSN2_M_FP_S and INSN2_M_FP_D.
305
f04d18b7
DM		 3062008-04-25 David S. Miller <davem@davemloft.net>
307
308 * sparc-dis.c: Emit %stick instead of %sys_tick, and %stick_cmpr
309 instead of %sys_tick_cmpr, as suggested in architecture manuals.
310
6194aaab
L		 3112008-04-23 Paolo Bonzini <bonzini@gnu.org>
312
313 * aclocal.m4: Regenerate.
314 * configure: Regenerate.
315
1a6b486f
DM		 3162008-04-23 David S. Miller <davem@davemloft.net>
317
318 * sparc-opc.c (asi_table): Add UltraSPARC and Niagara
319 extended values.
320 (prefetch_table): Add missing values.
321
81f8a913
L		 3222008-04-22 H.J. Lu <hongjiu.lu@intel.com>
323
324 * i386-gen.c (opcode_modifiers): Add NoAVX.
325
326 * i386-opc.h (NoAVX): New.
327 (OldGcc): Updated.
328 (i386_opcode_modifier): Add noavx.
329
330 * i386-opc.tbl: Add NoAVX to SSE, SSE2, SSE3 and SSSE3
331 instructions which don't have AVX equivalent.
332 * i386-tbl.h: Regenerated.
333
dae39acc
L		 3342008-04-18 H.J. Lu <hongjiu.lu@intel.com>
335
336 * i386-dis.c (OP_VEX_FMA): New.
337 (OP_EX_VexImmW): Likewise.
338 (VexFMA): Likewise.
339 (Vex128FMA): Likewise.
340 (EXVexImmW): Likewise.
341 (get_vex_imm8): Likewise.
342 (OP_EX_VexReg): Likewise.
343 (vex_i4_done): Renamed to ...
344 (vex_w_done): This.
345 (prefix_table): Replace EXVexW with EXVexImmW on vpermil2ps
346 and vpermil2pd. Replace Vex/Vex128 with VexFMA/Vex128FMA on
347 FMA instructions.
348 (print_insn): Updated.
349 (OP_EX_VexW): Rewrite to swap register in VEX with EX.
350 (OP_REG_VexI4): Check invalid high registers.
351
ce886ab1
DR		 3522008-04-16 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
353 Michael Meissner <michael.meissner@amd.com>
354
355 * i386-opc.tbl: Fix protX to allow memory in the middle operand.
356 * i386-tbl.h: Regenerate from i386-opc.tbl.
8944f3c2 357
19a6653c
AM		 3582008-04-14 Edmar Wienskoski <edmar@freescale.com>
359
360 * ppc-dis.c (powerpc_dialect): Handle "e500mc". Extend "e500" to
361 accept Power E500MC instructions.
362 (print_ppc_disassembler_options): Document -Me500mc.
363 * ppc-opc.c (DUIS, DUI, T): New.
364 (XRT, XRTRA): Likewise.
365 (E500MC): Likewise.
366 (powerpc_opcodes): Add new Power E500MC instructions.
367
112b7c50
AK		 3682008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
369
370 * s390-dis.c (init_disasm): Evaluate disassembler_options.
371 (print_s390_disassembler_options): New function.
372 * disassemble.c (disassembler_usage): Invoke
373 print_s390_disassembler_options.
374
7ff42648
AK		 3752008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
376
377 * s390-mkopc.c (insertExpandedMnemonic): Expand string sizes
378 of local variables used for mnemonic parsing: prefix, suffix and
379 number.
380
45a5551e
AK		 3812008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
382
383 * s390-mkopc.c (s390_cond_ext_format): Add back the mnemonic
384 extensions for conditional jumps (o, p, m, nz, z, nm, np, no).
385 (s390_crb_extensions): New extensions table.
386 (insertExpandedMnemonic): Handle '$' tag.
387 * s390-opc.txt: Remove conditional jump variants which can now
388 be expanded automatically.
389 Replace '*' tag with '$' in the compare and branch instructions.
390
06c8514a
L		 3912008-04-07 H.J. Lu <hongjiu.lu@intel.com>
392
393 * i386-dis.c (PREFIX_VEX_38XX): Add a tab.
394 (PREFIX_VEX_3AXX): Likewis.
395
b122c285
L		 3962008-04-07 H.J. Lu <hongjiu.lu@intel.com>
397
398 * i386-opc.tbl: Remove 4 extra blank lines.
399
594ab6a3
L		 4002008-04-04 H.J. Lu <hongjiu.lu@intel.com>
401
402 * i386-gen.c (cpu_flag_init): Replace CPU_CLMUL_FLAGS/CpuCLMUL
403 with CPU_PCLMUL_FLAGS/CpuPCLMUL.
404 (cpu_flags): Replace CpuCLMUL with CpuPCLMUL.
405 * i386-opc.tbl: Likewise.
406
407 * i386-opc.h (CpuCLMUL): Renamed to ...
408 (CpuPCLMUL): This.
409 (CpuFMA): Updated.
410 (i386_cpu_flags): Replace cpuclmul with cpupclmul.
411
412 * i386-init.h: Regenerated.
413
c0f3af97
L		 4142008-04-03 H.J. Lu <hongjiu.lu@intel.com>
415
416 * i386-dis.c (OP_E_register): New.
417 (OP_E_memory): Likewise.
418 (OP_VEX): Likewise.
419 (OP_EX_Vex): Likewise.
420 (OP_EX_VexW): Likewise.
421 (OP_XMM_Vex): Likewise.
422 (OP_XMM_VexW): Likewise.
423 (OP_REG_VexI4): Likewise.
424 (PCLMUL_Fixup): Likewise.
425 (VEXI4_Fixup): Likewise.
426 (VZERO_Fixup): Likewise.
427 (VCMP_Fixup): Likewise.
428 (VPERMIL2_Fixup): Likewise.
429 (rex_original): Likewise.
430 (rex_ignored): Likewise.
431 (Mxmm): Likewise.
432 (XMM): Likewise.
433 (EXxmm): Likewise.
434 (EXxmmq): Likewise.
435 (EXymmq): Likewise.
436 (Vex): Likewise.
437 (Vex128): Likewise.
438 (Vex256): Likewise.
439 (VexI4): Likewise.
440 (EXdVex): Likewise.
441 (EXqVex): Likewise.
442 (EXVexW): Likewise.
443 (EXdVexW): Likewise.
444 (EXqVexW): Likewise.
445 (XMVex): Likewise.
446 (XMVexW): Likewise.
447 (XMVexI4): Likewise.
448 (PCLMUL): Likewise.
449 (VZERO): Likewise.
450 (VCMP): Likewise.
451 (VPERMIL2): Likewise.
452 (xmm_mode): Likewise.
453 (xmmq_mode): Likewise.
454 (ymmq_mode): Likewise.
455 (vex_mode): Likewise.
456 (vex128_mode): Likewise.
457 (vex256_mode): Likewise.
458 (USE_VEX_C4_TABLE): Likewise.
459 (USE_VEX_C5_TABLE): Likewise.
460 (USE_VEX_LEN_TABLE): Likewise.
461 (VEX_C4_TABLE): Likewise.
462 (VEX_C5_TABLE): Likewise.
463 (VEX_LEN_TABLE): Likewise.
464 (REG_VEX_XX): Likewise.
465 (MOD_VEX_XXX): Likewise.
466 (PREFIX_0F38DB..PREFIX_0F38DF): Likewise.
467 (PREFIX_0F3A44): Likewise.
468 (PREFIX_0F3ADF): Likewise.
469 (PREFIX_VEX_XXX): Likewise.
470 (VEX_OF): Likewise.
471 (VEX_OF38): Likewise.
472 (VEX_OF3A): Likewise.
473 (VEX_LEN_XXX): Likewise.
474 (vex): Likewise.
475 (need_vex): Likewise.
476 (need_vex_reg): Likewise.
477 (vex_i4_done): Likewise.
478 (vex_table): Likewise.
479 (vex_len_table): Likewise.
480 (OP_REG_VexI4): Likewise.
481 (vex_cmp_op): Likewise.
482 (pclmul_op): Likewise.
483 (vpermil2_op): Likewise.
484 (m_mode): Updated.
485 (es_reg): Likewise.
486 (PREFIX_0F38F0): Likewise.
487 (PREFIX_0F3A60): Likewise.
488 (reg_table): Add REG_VEX_71...REG_VEX_73 and REG_VEX_AE.
489 (prefix_table): Add PREFIX_0F38DB..PREFIX_0F38DF, PREFIX_0F3ADF
490 and PREFIX_VEX_XXX entries.
491 (x86_64_table): Use VEX_C4_TABLE and VEX_C5_TABLE.
492 (three_byte_table): Use PREFIX_0F38DB..PREFIX_0F38DF and
493 PREFIX_0F3ADF.
494 (mod_table): Use VEX_C4_TABLE, VEX_C5_TABLE and VEX_LEN_TABLE.
495 Add MOD_VEX_XXX entries.
496 (ckprefix): Initialize rex_original and rex_ignored. Store the
497 REX byte in rex_original.
498 (get_valid_dis386): Handle the implicit prefix in VEX prefix
499 bytes and USE_VEX_LEN_TABLE/USE_VEX_C4_TABLE/USE_VEX_C5_TABLE.
500 (print_insn): Set need_vex/need_vex_reg/vex_i4_done to 0 before
501 calling get_valid_dis386. Use rex_original and rex_ignored when
502 printing out REX.
503 (putop): Handle "XY".
504 (intel_operand_size): Handle VEX, xmm_mode, xmmq_mode and
505 ymmq_mode.
506 (OP_E_extended): Updated to use OP_E_register and
507 OP_E_memory.
508 (OP_XMM): Handle VEX.
509 (OP_EX): Likewise.
510 (XMM_Fixup): Likewise.
511 (CMP_Fixup): Use ARRAY_SIZE.
512
513 * i386-gen.c (cpu_flag_init): Add CpuAES, CPU_CLMUL_FLAGS,
514 CPU_FMA_FLAGS and CPU_AVX_FLAGS.
515 (operand_type_init): Add OPERAND_TYPE_REGYMM and
516 OPERAND_TYPE_VEX_IMM4.
517 (cpu_flags): Add CpuAVX, CpuAES, CpuCLMUL and CpuFMA.
518 (opcode_modifiers): Add Implicit1stXmm0, Vex, Vex256, VexNDD,
519 VexNDS, VexW0, VexW1, Vex0F, Vex0F38, Vex0F3A, Vex3Sources,
520 VexImmExt and SSE2AVX.
521 (operand_types): Add RegYMM, Ymmword and Vex_Imm4.
522
523 * i386-opc.h (CpuAVX): New.
524 (CpuAES): Likewise.
525 (CpuCLMUL): Likewise.
526 (CpuFMA): Likewise.
527 (Vex): Likewise.
528 (Vex256): Likewise.
529 (VexNDS): Likewise.
530 (VexNDD): Likewise.
531 (VexW0): Likewise.
532 (VexW1): Likewise.
533 (Vex0F): Likewise.
534 (Vex0F38): Likewise.
535 (Vex0F3A): Likewise.
536 (Vex3Sources): Likewise.
537 (VexImmExt): Likewise.
538 (SSE2AVX): Likewise.
539 (RegYMM): Likewise.
540 (Ymmword): Likewise.
541 (Vex_Imm4): Likewise.
542 (Implicit1stXmm0): Likewise.
543 (CpuXsave): Updated.
544 (CpuLM): Likewise.
545 (ByteOkIntel): Likewise.
546 (OldGcc): Likewise.
547 (Control): Likewise.
548 (Unspecified): Likewise.
549 (OTMax): Likewise.
550 (i386_cpu_flags): Add cpuavx, cpuaes, cpuclmul and cpufma.
551 (i386_opcode_modifier): Add implicit1stxmm0, vex, vex256,
552 vexnds, vexndd, vexw0, vexw1, vex0f, vex0f38, vex0f3a,
553 vex3sources, veximmext and sse2avx.
554 (i386_operand_type): Add regymm, ymmword and vex_imm4.
555
556 * i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions.
557
558 * i386-reg.tbl: Add AVX registers, ymm0..ymm15.
559
560 * i386-init.h: Regenerated.
561 * i386-tbl.h: Likewise.
562
b21c9cb4
BS		 5632008-03-26 Bernd Schmidt <bernd.schmidt@analog.com>
564
565 From Robin Getz <robin.getz@analog.com>
566 * bfin-dis.c (bu32): Typedef.
567 (enum const_forms_t): Add c_uimm32 and c_huimm32.
568 (constant_formats[]): Add uimm32 and huimm16.
569 (fmtconst_val): New.
570 (uimm32): Define.
571 (huimm32): Define.
572 (imm16_val): Define.
573 (luimm16_val): Define.
574 (struct saved_state): Define.
575 (GREG, DPREG, DREG, PREG, SPREG, FPREG, IREG, MREG, BREG, LREG,
576 A0XREG, A0WREG, A1XREG, A1WREG,CCREG, LC0REG, LT0REG, LB0REG,
577 LC1REG, LT1REG, LB1REG, RETSREG, PCREG): Define.
578 (get_allreg): New.
579 (decode_LDIMMhalf_0): Print out the whole register value.
580
ee171c8f
BS		 581 From Jie Zhang <jie.zhang@analog.com>
582 * bfin-dis.c (decode_dsp32mac_0): Decode (IU) option for
583 multiply and multiply-accumulate to data register instruction.
584
086134ec
BS		 585 * bfin-dis.c: (c_uimm4s4d, c_imm5d, c_imm7d, c_imm16d, c_uimm16s4d,
586 c_imm32, c_huimm32e): Define.
587 (constant_formats): Add flags for printing decimal, leading spaces, and
588 exact symbols.
589 (comment, parallel): Add global flags in all disassembly.
590 (fmtconst): Take advantage of new flags, and print default in hex.
591 (fmtconst_val): Likewise.
592 (decode_macfunc): Be consistant with spaces, tabs, comments,
593 capitalization in disassembly, fix minor coding style issues.
594 (reg_names, amod0, amod1, amod0amod2, aligndir, get_allreg): Likewise.
595 (decode_ProgCtrl_0, decode_PushPopMultiple_0, decode_CCflag_0,
596 decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0,
597 decode_REGMV_0, decode_ALU2op_0, decode_PTR2op_0, decode_LOGI2op_0,
598 decode_COMP3op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
599 decode_LDSTpmod_0, decode_dagMODim_0, decode_dagMODik_0,
600 decode_dspLDST_0, decode_LDST_0, decode_LDSTiiFP_0, decode_LDSTii_0,
601 decode_LoopSetup_0, decode_LDIMMhalf_0, decode_CALLa_0,
602 decode_LDSTidxI_0, decode_linkage_0, decode_dsp32alu_0,
603 decode_dsp32shift_0, decode_dsp32shiftimm_0, decode_pseudodbg_assert_0,
604 _print_insn_bfin, print_insn_bfin): Likewise.
605
58c85be7
RW		 6062008-03-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
607
608 * aclocal.m4: Regenerate.
609 * configure: Likewise.
610 * Makefile.in: Likewise.
611
50e7d84b
AM		 6122008-03-13 Alan Modra <amodra@bigpond.net.au>
613
614 * Makefile.am: Run "make dep-am".
615 * Makefile.in: Regenerate.
616 * configure: Regenerate.
617
de866fcc
AM		 6182008-03-07 Alan Modra <amodra@bigpond.net.au>
619
620 * ppc-opc.c (powerpc_opcodes): Order and format.
621
28dbc079
L		 6222008-03-01 H.J. Lu <hongjiu.lu@intel.com>
623
624 * i386-opc.tbl: Allow 16-bit near indirect branches for x86-64.
625 * i386-tbl.h: Regenerated.
626
849830bd
L		 6272008-02-23 H.J. Lu <hongjiu.lu@intel.com>
628
629 * i386-opc.tbl: Disallow 16-bit near indirect branches for
630 x86-64.
631 * i386-tbl.h: Regenerated.
632
743ddb6b
JB		 6332008-02-21 Jan Beulich <jbeulich@novell.com>
634
635 * i386-opc.tbl: Allow Dword for far indirect call. Allow Dword
636 and Fword for far indirect jmp. Allow Reg16 and Word for near
637 indirect jmp on x86-64. Disallow Fword for lcall.
638 * i386-tbl.h: Re-generate.
639
796d5313
NC		 6402008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
641
642 * cr16-opc.c (cr16_num_optab): Defined
643
65da13b5
L		 6442008-02-16 H.J. Lu <hongjiu.lu@intel.com>
645
646 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_INOUTPORTREG.
647 * i386-init.h: Regenerated.
648
0e336180
NC		 6492008-02-14 Nick Clifton <nickc@redhat.com>
650
651 PR binutils/5524
652 * configure.in (SHARED_LIBADD): Select the correct host specific
653 file extension for shared libraries.
654 * configure: Regenerate.
655
b7240065
JB		 6562008-02-13 Jan Beulich <jbeulich@novell.com>
657
658 * i386-opc.h (RegFlat): New.
659 * i386-reg.tbl (flat): Add.
660 * i386-tbl.h: Re-generate.
661
34b772a6
JB		 6622008-02-13 Jan Beulich <jbeulich@novell.com>
663
664 * i386-dis.c (a_mode): New.
665 (cond_jump_mode): Adjust.
666 (Ma): Change to a_mode.
667 (intel_operand_size): Handle a_mode.
668 * i386-opc.tbl: Allow Dword and Qword for bound.
669 * i386-tbl.h: Re-generate.
670
a60de03c
JB		 6712008-02-13 Jan Beulich <jbeulich@novell.com>
672
673 * i386-gen.c (process_i386_registers): Process new fields.
674 * i386-opc.h (reg_entry): Shrink reg_flags and reg_num to
675 unsigned char. Add dw2_regnum and Dw2Inval.
676 * i386-reg.tbl: Provide initializers for dw2_regnum. Add pseudo
677 register names.
678 * i386-tbl.h: Re-generate.
679
f03fe4c1
L		 6802008-02-11 H.J. Lu <hongjiu.lu@intel.com>
681
4b6bc8eb 682 * i386-gen.c (cpu_flag_init): Add CPU_XSAVE_FLAGS.
f03fe4c1
L		 683 * i386-init.h: Updated.
684
475a2301
L		 6852008-02-11 H.J. Lu <hongjiu.lu@intel.com>
686
687 * i386-gen.c (cpu_flags): Add CpuXsave.
688
689 * i386-opc.h (CpuXsave): New.
4b6bc8eb 690 (CpuLM): Updated.
475a2301
L		 691 (i386_cpu_flags): Add cpuxsave.
692
693 * i386-dis.c (MOD_0FAE_REG_4): New.
694 (RM_0F01_REG_2): Likewise.
695 (MOD_0FAE_REG_5): Updated.
696 (RM_0F01_REG_3): Likewise.
697 (reg_table): Use MOD_0FAE_REG_4.
698 (mod_table): Use RM_0F01_REG_2. Add MOD_0FAE_REG_4. Updated
699 for xrstor.
700 (rm_table): Add RM_0F01_REG_2.
701
702 * i386-opc.tbl: Add xsave, xrstor, xgetbv and xsetbv.
703 * i386-init.h: Regenerated.
704 * i386-tbl.h: Likewise.
705
595785c6 7062008-02-11 Jan Beulich <jbeulich@novell.com>
041179fc 707
595785c6
JB		 708 * i386-opc.tbl: Remove Disp32S from CpuNo64 opcodes. Remove
709 Disp16 from Cpu64 non-jump opcodes (including loop and j?cxz).
710 * i386-tbl.h: Re-generate.
711
bb8541b9
L		 7122008-02-04 H.J. Lu <hongjiu.lu@intel.com>
713
714 PR 5715
715 * configure: Regenerated.
716
57b592a3
AN		 7172008-02-04 Adam Nemet <anemet@caviumnetworks.com>
718
719 * mips-dis.c: Update copyright.
720 (mips_arch_choices): Add Octeon.
721 * mips-opc.c: Update copyright.
722 (IOCT): New macro.
723 (mips_builtin_opcodes): Add Octeon instruction synciobdma.
724
930bb4cf
AM		 7252008-01-29 Alan Modra <amodra@bigpond.net.au>
726
727 * ppc-opc.c: Support optional L form mtmsr.
728
82c18208
L		 7292008-01-24 H.J. Lu <hongjiu.lu@intel.com>
730
731 * i386-dis.c (OP_E_extended): Handle r12 like rsp.
732
599121aa
L		 7332008-01-23 H.J. Lu <hongjiu.lu@intel.com>
734
735 * i386-gen.c (cpu_flag_init): Add CpuLM to CPU_GENERIC64_FLAGS.
736 * i386-init.h: Regenerated.
737
80098f51
TG		 7382008-01-23 Tristan Gingold <gingold@adacore.com>
739
740 * ia64-dis.c (print_insn_ia64): Display symbolic name of ar.fcr,
741 ar.eflag, ar.csd, ar.ssd, ar.cflg, ar.fsr, ar.fir and ar.fdr.
742
115c7c25
L		 7432008-01-22 H.J. Lu <hongjiu.lu@intel.com>
744
745 * i386-gen.c (cpu_flag_init): Remove CpuMMX2.
746 (cpu_flags): Likewise.
747
748 * i386-opc.h (CpuMMX2): Removed.
749 (CpuSSE): Updated.
750
751 * i386-opc.tbl: Replace CpuMMX2 with CpuSSE|Cpu3dnowA.
752 * i386-init.h: Regenerated.
753 * i386-tbl.h: Likewise.
754
6305a203
L		 7552008-01-22 H.J. Lu <hongjiu.lu@intel.com>
756
757 * i386-gen.c (cpu_flag_init): Add CPU_VMX_FLAGS and
758 CPU_SMX_FLAGS.
759 * i386-init.h: Regenerated.
760
fd07a1c8
L		 7612008-01-15 H.J. Lu <hongjiu.lu@intel.com>
762
763 * i386-opc.tbl: Use Qword on movddup.
764 * i386-tbl.h: Regenerated.
765
321fd21e
L		 7662008-01-15 H.J. Lu <hongjiu.lu@intel.com>
767
768 * i386-opc.tbl: Put back 16bit movsx/movzx for AT&T syntax.
769 * i386-tbl.h: Regenerated.
770
4ee52178
L		 7712008-01-15 H.J. Lu <hongjiu.lu@intel.com>
772
773 * i386-dis.c (Mx): New.
774 (PREFIX_0FC3): Likewise.
775 (PREFIX_0FC7_REG_6): Updated.
776 (dis386_twobyte): Use PREFIX_0FC3.
777 (prefix_table): Add PREFIX_0FC3. Use Mq on movntq and movntsd.
778 Use Mx on movntps, movntpd, movntdq and movntdqa. Use Md on
779 movntss.
780
5c07affc
L		 7812008-01-14 H.J. Lu <hongjiu.lu@intel.com>
782
783 * i386-gen.c (opcode_modifiers): Add IntelSyntax.
784 (operand_types): Add Mem.
785
786 * i386-opc.h (IntelSyntax): New.
787 * i386-opc.h (Mem): New.
788 (Byte): Updated.
789 (Opcode_Modifier_Max): Updated.
790 (i386_opcode_modifier): Add intelsyntax.
791 (i386_operand_type): Add mem.
792
793 * i386-opc.tbl: Remove Reg16 from movnti. Add sizes to more
794 instructions.
795
796 * i386-reg.tbl: Add size for accumulator.
797
798 * i386-init.h: Regenerated.
799 * i386-tbl.h: Likewise.
800
0d6a2f58
L		 8012008-01-13 H.J. Lu <hongjiu.lu@intel.com>
802
803 * i386-opc.h (Byte): Fix a typo.
804
7d5e4556
L		 8052008-01-12 H.J. Lu <hongjiu.lu@intel.com>
806
807 PR gas/5534
808 * i386-gen.c (operand_type_init): Add Dword to
809 OPERAND_TYPE_ACC32. Add Qword to OPERAND_TYPE_ACC64.
810 (opcode_modifiers): Remove CheckSize, Byte, Word, Dword,
811 Qword and Xmmword.
812 (operand_types): Add Byte, Word, Dword, Fword, Qword, Tbyte,
813 Xmmword, Unspecified and Anysize.
814 (set_bitfield): Make Mmword an alias of Qword. Make Oword
815 an alias of Xmmword.
816
817 * i386-opc.h (CheckSize): Removed.
818 (Byte): Updated.
819 (Word): Likewise.
820 (Dword): Likewise.
821 (Qword): Likewise.
822 (Xmmword): Likewise.
823 (FWait): Updated.
824 (OTMax): Likewise.
825 (i386_opcode_modifier): Remove checksize, byte, word, dword,
826 qword and xmmword.
827 (Fword): New.
828 (TBYTE): Likewise.
829 (Unspecified): Likewise.
830 (Anysize): Likewise.
831 (i386_operand_type): Add byte, word, dword, fword, qword,
832 tbyte xmmword, unspecified and anysize.
833
834 * i386-opc.tbl: Updated to use Byte, Word, Dword, Fword, Qword,
835 Tbyte, Xmmword, Unspecified and Anysize.
836
837 * i386-reg.tbl: Add size for accumulator.
838
839 * i386-init.h: Regenerated.
840 * i386-tbl.h: Likewise.
841
b5b1fc4f
L		 8422008-01-10 H.J. Lu <hongjiu.lu@intel.com>
843
844 * i386-dis.c (REG_0F0E): Renamed to REG_0F0D.
845 (REG_0F18): Updated.
846 (reg_table): Updated.
847 (dis386_twobyte): Updated. Use "nopQ" on 0x19 to 0x1e.
848 (twobyte_has_modrm): Set 1 for 0x19 to 0x1e.
849
50e8458f
L		 8502008-01-08 H.J. Lu <hongjiu.lu@intel.com>
851
852 * i386-gen.c (set_bitfield): Use fail () on error.
853
3d4d5afa
L		 8542008-01-08 H.J. Lu <hongjiu.lu@intel.com>
855
856 * i386-gen.c (lineno): New.
857 (filename): Likewise.
858 (set_bitfield): Report filename and line numer on error.
859 (process_i386_opcodes): Set filename and update lineno.
860 (process_i386_registers): Likewise.
861
e1d4d893
L		 8622008-01-05 H.J. Lu <hongjiu.lu@intel.com>
863
864 * i386-gen.c (opcode_modifiers): Rename IntelMnemonic to
865 ATTSyntax.
866
867 * i386-opc.h (IntelMnemonic): Renamed to ..
868 (ATTSyntax): This
869 (Opcode_Modifier_Max): Updated.
870 (i386_opcode_modifier): Remove intelmnemonic. Add attsyntax
871 and intelsyntax.
872
8944f3c2 873 * i386-opc.tbl: Remove IntelMnemonic and update with ATTSyntax
e1d4d893
L		 874 on fsub, fubp, fsubr, fsubrp, div, fdivp, fdivr and fdivrp.
875 * i386-tbl.h: Regenerated.
876
6f143e4d
L		 8772008-01-04 H.J. Lu <hongjiu.lu@intel.com>
878
879 * i386-gen.c: Update copyright to 2008.
880 * i386-opc.h: Likewise.
881 * i386-opc.tbl: Likewise.
882
883 * i386-init.h: Regenerated.
884 * i386-tbl.h: Likewise.
885
c6add537
L		 8862008-01-04 H.J. Lu <hongjiu.lu@intel.com>
887
888 * i386-opc.tbl: Add NoRex64 to extractps, movmskpd, movmskps,
889 pextrb, pextrw, pinsrb, pinsrw and pmovmskb.
890 * i386-tbl.h: Regenerated.
891
3629bb00
L		 8922008-01-03 H.J. Lu <hongjiu.lu@intel.com>
893
894 * i386-gen.c (cpu_flag_init): Remove CpuSSE4_1_Or_5 and
895 CpuSSE4_2_Or_ABM.
896 (cpu_flags): Likewise.
897
898 * i386-opc.h (CpuSSE4_1_Or_5): Removed.
899 (CpuSSE4_2_Or_ABM): Likewise.
900 (CpuLM): Updated.
901 (i386_cpu_flags): Remove cpusse4_1_or_5 and cpusse4_2_or_abm.
902
903 * i386-opc.tbl: Replace CpuSSE4_1_Or_5, CpuSSE4_2_Or_ABM and
904 Cpu686|CpuPadLock with CpuSSE4_1|CpuSSE5, CpuABM|CpuSSE4_2
905 and CpuPadLock, respectively.
906 * i386-init.h: Regenerated.
907 * i386-tbl.h: Likewise.
908
24995bd6
L		 9092008-01-03 H.J. Lu <hongjiu.lu@intel.com>
910
911 * i386-gen.c (opcode_modifiers): Remove No_xSuf.
912
913 * i386-opc.h (No_xSuf): Removed.
914 (CheckSize): Updated.
915
916 * i386-tbl.h: Regenerated.
917
e0329a22
L		 9182008-01-02 H.J. Lu <hongjiu.lu@intel.com>
919
920 * i386-gen.c (cpu_flag_init): Add CpuSSE4_2_Or_ABM to
921 CPU_AMDFAM10_FLAGS, CPU_SSE4_2_FLAGS, CpuABM and
922 CPU_SSE5_FLAGS.
923 (cpu_flags): Add CpuSSE4_2_Or_ABM.
924
925 * i386-opc.h (CpuSSE4_2_Or_ABM): New.
926 (CpuLM): Updated.
927 (i386_cpu_flags): Add cpusse4_2_or_abm.
928
929 * i386-opc.tbl: Use CpuSSE4_2_Or_ABM instead of
930 CpuABM|CpuSSE4_2 on popcnt.
931 * i386-init.h: Regenerated.
932 * i386-tbl.h: Likewise.
933
f2a9c676
L		 9342008-01-02 H.J. Lu <hongjiu.lu@intel.com>
935
936 * i386-opc.h: Update comments.
937
d978b5be
L		 9382008-01-02 H.J. Lu <hongjiu.lu@intel.com>
939
940 * i386-gen.c (opcode_modifiers): Use Qword instead of QWord.
941 * i386-opc.h: Likewise.
942 * i386-opc.tbl: Likewise.
943
582d5edd
L		 9442008-01-02 H.J. Lu <hongjiu.lu@intel.com>
945
946 PR gas/5534
947 * i386-gen.c (opcode_modifiers): Add No_xSuf, CheckSize,
948 Byte, Word, Dword, QWord and Xmmword.
949
950 * i386-opc.h (No_xSuf): New.
951 (CheckSize): Likewise.
952 (Byte): Likewise.
953 (Word): Likewise.
954 (Dword): Likewise.
955 (QWord): Likewise.
956 (Xmmword): Likewise.
957 (FWait): Updated.
958 (i386_opcode_modifier): Add No_xSuf, CheckSize, Byte, Word,
959 Dword, QWord and Xmmword.
960
961 * i386-opc.tbl: Add CheckSize|QWord to movq if IgnoreSize is
962 used.
963 * i386-tbl.h: Regenerated.
964
3fe15143
MK		 9652008-01-02 Mark Kettenis <kettenis@gnu.org>
966
967 * m88k-dis.c (instructions): Fix fcvt.* instructions.
968 From Miod Vallat.
969
6c7ac64e 970For older changes see ChangeLog-2007
252b5132
RH		 971\f
972Local Variables:
2f6d2f85
NC		 973mode: change-log
974left-margin: 8
975fill-column: 74
252b5132
RH		 976version-control: never
977End:
GDB Binutils - Deliverables
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