x86: drop unused EXVexWdq / vex_w_dq_mode
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
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825bd36c
JB
12020-01-31 Jan Beulich <jbeulich@suse.com>
2
3 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
4 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
5 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
6 (intel_operand_size): Drop vex_w_dq_mode case label.
7
c3036ed0
RS
82020-01-31 Richard Sandiford <richard.sandiford@arm.com>
9
10 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
11 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
12
0c115f84
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132020-01-30 Alan Modra <amodra@gmail.com>
14
15 * m32c-ibld.c: Regenerate.
16
bd434cc4
JM
172020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
18
19 * bpf-opc.c: Regenerate.
20
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212020-01-30 Jan Beulich <jbeulich@suse.com>
22
23 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
24 (dis386): Use them to replace C2/C3 table entries.
25 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
26 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
27 ones. Use Size64 instead of DefaultSize on Intel64 ones.
28 * i386-tbl.h: Re-generate.
29
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JB
302020-01-30 Jan Beulich <jbeulich@suse.com>
31
32 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
33 forms.
34 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
35 DefaultSize.
36 * i386-tbl.h: Re-generate.
37
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382020-01-30 Alan Modra <amodra@gmail.com>
39
40 * tic4x-dis.c (tic4x_dp): Make unsigned.
41
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422020-01-27 H.J. Lu <hongjiu.lu@intel.com>
43 Jan Beulich <jbeulich@suse.com>
44
45 PR binutils/25445
46 * i386-dis.c (MOVSXD_Fixup): New function.
47 (movsxd_mode): New enum.
48 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
49 (intel_operand_size): Handle movsxd_mode.
50 (OP_E_register): Likewise.
51 (OP_G): Likewise.
52 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
53 register on movsxd. Add movsxd with 16-bit destination register
54 for AMD64 and Intel64 ISAs.
55 * i386-tbl.h: Regenerated.
56
7568c93b
TC
572020-01-27 Tamar Christina <tamar.christina@arm.com>
58
59 PR 25403
60 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
61 * aarch64-asm-2.c: Regenerate
62 * aarch64-dis-2.c: Likewise.
63 * aarch64-opc-2.c: Likewise.
64
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652020-01-21 Jan Beulich <jbeulich@suse.com>
66
67 * i386-opc.tbl (sysret): Drop DefaultSize.
68 * i386-tbl.h: Re-generate.
69
c906a69a
JB
702020-01-21 Jan Beulich <jbeulich@suse.com>
71
72 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
73 Dword.
74 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
75 * i386-tbl.h: Re-generate.
76
26916852
NC
772020-01-20 Nick Clifton <nickc@redhat.com>
78
79 * po/de.po: Updated German translation.
80 * po/pt_BR.po: Updated Brazilian Portuguese translation.
81 * po/uk.po: Updated Ukranian translation.
82
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832020-01-20 Alan Modra <amodra@gmail.com>
84
85 * hppa-dis.c (fput_const): Remove useless cast.
86
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872020-01-20 Alan Modra <amodra@gmail.com>
88
89 * arm-dis.c (print_insn_arm): Wrap 'T' value.
90
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912020-01-18 Nick Clifton <nickc@redhat.com>
92
93 * configure: Regenerate.
94 * po/opcodes.pot: Regenerate.
95
ae774686
NC
962020-01-18 Nick Clifton <nickc@redhat.com>
97
98 Binutils 2.34 branch created.
99
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1002020-01-17 Christian Biesinger <cbiesinger@google.com>
101
102 * opintl.h: Fix spelling error (seperate).
103
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1042020-01-17 H.J. Lu <hongjiu.lu@intel.com>
105
106 * i386-opc.tbl: Add {vex} pseudo prefix.
107 * i386-tbl.h: Regenerated.
108
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AV
1092020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
110
111 PR 25376
112 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
113 (neon_opcodes): Likewise.
114 (select_arm_features): Make sure we enable MVE bits when selecting
115 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
116 any architecture.
117
d0849eed
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1182020-01-16 Jan Beulich <jbeulich@suse.com>
119
120 * i386-opc.tbl: Drop stale comment from XOP section.
121
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1222020-01-16 Jan Beulich <jbeulich@suse.com>
123
124 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
125 (extractps): Add VexWIG to SSE2AVX forms.
126 * i386-tbl.h: Re-generate.
127
4814632e
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1282020-01-16 Jan Beulich <jbeulich@suse.com>
129
130 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
131 Size64 from and use VexW1 on SSE2AVX forms.
132 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
133 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
134 * i386-tbl.h: Re-generate.
135
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1362020-01-15 Alan Modra <amodra@gmail.com>
137
138 * tic4x-dis.c (tic4x_version): Make unsigned long.
139 (optab, optab_special, registernames): New file scope vars.
140 (tic4x_print_register): Set up registernames rather than
141 malloc'd registertable.
142 (tic4x_disassemble): Delete optable and optable_special. Use
143 optab and optab_special instead. Throw away old optab,
144 optab_special and registernames when info->mach changes.
145
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SB
1462020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
147
148 PR 25377
149 * z80-dis.c (suffix): Use .db instruction to generate double
150 prefix.
151
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1522020-01-14 Alan Modra <amodra@gmail.com>
153
154 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
155 values to unsigned before shifting.
156
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TT
1572020-01-13 Thomas Troeger <tstroege@gmx.de>
158
159 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
160 flow instructions.
161 (print_insn_thumb16, print_insn_thumb32): Likewise.
162 (print_insn): Initialize the insn info.
163 * i386-dis.c (print_insn): Initialize the insn info fields, and
164 detect jumps.
165
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CZ
1662012-01-13 Claudiu Zissulescu <claziss@gmail.com>
167
168 * arc-opc.c (C_NE): Make it required.
169
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CZ
1702012-01-13 Claudiu Zissulescu <claziss@gmail.com>
171
172 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
173 reserved register name.
174
90dee485
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1752020-01-13 Alan Modra <amodra@gmail.com>
176
177 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
178 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
179
febda64f
AM
1802020-01-13 Alan Modra <amodra@gmail.com>
181
182 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
183 result of wasm_read_leb128 in a uint64_t and check that bits
184 are not lost when copying to other locals. Use uint32_t for
185 most locals. Use PRId64 when printing int64_t.
186
df08b588
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1872020-01-13 Alan Modra <amodra@gmail.com>
188
189 * score-dis.c: Formatting.
190 * score7-dis.c: Formatting.
191
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1922020-01-13 Alan Modra <amodra@gmail.com>
193
194 * score-dis.c (print_insn_score48): Use unsigned variables for
195 unsigned values. Don't left shift negative values.
196 (print_insn_score32): Likewise.
197 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
198
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1992020-01-13 Alan Modra <amodra@gmail.com>
200
201 * tic4x-dis.c (tic4x_print_register): Remove dead code.
202
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AM
2032020-01-13 Alan Modra <amodra@gmail.com>
204
205 * fr30-ibld.c: Regenerate.
206
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2072020-01-13 Alan Modra <amodra@gmail.com>
208
209 * xgate-dis.c (print_insn): Don't left shift signed value.
210 (ripBits): Formatting, use 1u.
211
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AM
2122020-01-10 Alan Modra <amodra@gmail.com>
213
214 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
215 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
216
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2172020-01-10 Alan Modra <amodra@gmail.com>
218
219 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
220 and XRREG value earlier to avoid a shift with negative exponent.
221 * m10200-dis.c (disassemble): Similarly.
222
bce58db4
NC
2232020-01-09 Nick Clifton <nickc@redhat.com>
224
225 PR 25224
226 * z80-dis.c (ld_ii_ii): Use correct cast.
227
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SB
2282020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
229
230 PR 25224
231 * z80-dis.c (ld_ii_ii): Use character constant when checking
232 opcode byte value.
233
d835a58b
JB
2342020-01-09 Jan Beulich <jbeulich@suse.com>
235
236 * i386-dis.c (SEP_Fixup): New.
237 (SEP): Define.
238 (dis386_twobyte): Use it for sysenter/sysexit.
239 (enum x86_64_isa): Change amd64 enumerator to value 1.
240 (OP_J): Compare isa64 against intel64 instead of amd64.
241 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
242 forms.
243 * i386-tbl.h: Re-generate.
244
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2452020-01-08 Alan Modra <amodra@gmail.com>
246
247 * z8k-dis.c: Include libiberty.h
248 (instr_data_s): Make max_fetched unsigned.
249 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
250 Don't exceed byte_info bounds.
251 (output_instr): Make num_bytes unsigned.
252 (unpack_instr): Likewise for nibl_count and loop.
253 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
254 idx unsigned.
255 * z8k-opc.h: Regenerate.
256
bb82aefe
SV
2572020-01-07 Shahab Vahedi <shahab@synopsys.com>
258
259 * arc-tbl.h (llock): Use 'LLOCK' as class.
260 (llockd): Likewise.
261 (scond): Use 'SCOND' as class.
262 (scondd): Likewise.
263 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
264 (scondd): Likewise.
265
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2662020-01-06 Alan Modra <amodra@gmail.com>
267
268 * m32c-ibld.c: Regenerate.
269
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2702020-01-06 Alan Modra <amodra@gmail.com>
271
272 PR 25344
273 * z80-dis.c (suffix): Don't use a local struct buffer copy.
274 Peek at next byte to prevent recursion on repeated prefix bytes.
275 Ensure uninitialised "mybuf" is not accessed.
276 (print_insn_z80): Don't zero n_fetch and n_used here,..
277 (print_insn_z80_buf): ..do it here instead.
278
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2792020-01-04 Alan Modra <amodra@gmail.com>
280
281 * m32r-ibld.c: Regenerate.
282
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2832020-01-04 Alan Modra <amodra@gmail.com>
284
285 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
286
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2872020-01-04 Alan Modra <amodra@gmail.com>
288
289 * crx-dis.c (match_opcode): Avoid shift left of signed value.
290
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2912020-01-04 Alan Modra <amodra@gmail.com>
292
293 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
294
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2952020-01-03 Jan Beulich <jbeulich@suse.com>
296
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JB
297 * aarch64-tbl.h (aarch64_opcode_table): Use
298 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
299
3002020-01-03 Jan Beulich <jbeulich@suse.com>
301
302 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
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303 forms of SUDOT and USDOT.
304
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3052020-01-03 Jan Beulich <jbeulich@suse.com>
306
5437a02a 307 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
8c45011a
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308 uzip{1,2}.
309 * opcodes/aarch64-dis-2.c: Re-generate.
310
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3112020-01-03 Jan Beulich <jbeulich@suse.com>
312
5437a02a 313 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
f4950f76
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314 FMMLA encoding.
315 * opcodes/aarch64-dis-2.c: Re-generate.
316
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3172020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
318
319 * z80-dis.c: Add support for eZ80 and Z80 instructions.
320
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3212020-01-01 Alan Modra <amodra@gmail.com>
322
323 Update year range in copyright notice of all files.
324
0b114740 325For older changes see ChangeLog-2019
3499769a 326\f
0b114740 327Copyright (C) 2020 Free Software Foundation, Inc.
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328
329Copying and distribution of this file, with or without modification,
330are permitted in any medium without royalty provided the copyright
331notice and this notice are preserved.
332
333Local Variables:
334mode: change-log
335left-margin: 8
336fill-column: 74
337version-control: never
338End:
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