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Fix another memory access error triggered by attempting to parse a corrupt binary.
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
47826cdb
AK		 12017-07-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
2
3 * s390-mkopc.c (main): Enable z14 as CPU string in the opcode
4 table.
5
2d2dbad0
NC		 62017-07-20 Nick Clifton <nickc@redhat.com>
7
8 * po/de.po: Updated German translation.
9
70b448ba 102017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
11
12 * arc-regs.h (sec_stat): New aux register.
13 (aux_kernel_sp): Likewise.
14 (aux_sec_u_sp): Likewise.
15 (aux_sec_k_sp): Likewise.
16 (sec_vecbase_build): Likewise.
17 (nsc_table_top): Likewise.
18 (nsc_table_base): Likewise.
19 (ersec_stat): Likewise.
20 (aux_sec_except): Likewise.
21
7179e0e6
CZ		 222017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
23
24 * arc-opc.c (extract_uimm12_20): New function.
25 (UIMM12_20): New operand.
26 (SIMM3_5_S): Adjust.
27 * arc-tbl.h (sjli): Add new instruction.
28
684d5a10
JEM		 292017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
30 John Eric Martin <John.Martin@emmicro-us.com>
31
32 * arc-opc.c (UIMM10_6_S_JLIOFF): Define.
33 (UIMM3_23): Adjust accordingly.
34 * arc-regs.h: Add/correct jli_base register.
35 * arc-tbl.h (jli_s): Likewise.
36
de194d85
YC		 372017-07-18 Nick Clifton <nickc@redhat.com>
38
39 PR 21775
40 * aarch64-opc.c: Fix spelling typos.
41 * i386-dis.c: Likewise.
42
0f6329bd
RB		 432017-07-14 Ravi Bangoria <ravi.bangoria@linux.vnet.ibm.com>
44
45 * dis-buf.c (buffer_read_memory): Change type of end_addr_offset,
46 max_addr_offset and octets variables to size_t.
47
429d795d
AM		 482017-07-12 Alan Modra <amodra@gmail.com>
49
50 * po/da.po: Update from translationproject.org/latest/opcodes/.
51 * po/de.po: Likewise.
52 * po/es.po: Likewise.
53 * po/fi.po: Likewise.
54 * po/fr.po: Likewise.
55 * po/id.po: Likewise.
56 * po/it.po: Likewise.
57 * po/nl.po: Likewise.
58 * po/pt_BR.po: Likewise.
59 * po/ro.po: Likewise.
60 * po/sv.po: Likewise.
61 * po/tr.po: Likewise.
62 * po/uk.po: Likewise.
63 * po/vi.po: Likewise.
64 * po/zh_CN.po: Likewise.
65
4162bb66
AM		 662017-07-11 Yao Qi <yao.qi@linaro.org>
67 Alan Modra <amodra@gmail.com>
68
69 * cgen.sh: Mark generated files read-only.
70 * epiphany-asm.c: Regenerate.
71 * epiphany-desc.c: Regenerate.
72 * epiphany-desc.h: Regenerate.
73 * epiphany-dis.c: Regenerate.
74 * epiphany-ibld.c: Regenerate.
75 * epiphany-opc.c: Regenerate.
76 * epiphany-opc.h: Regenerate.
77 * fr30-asm.c: Regenerate.
78 * fr30-desc.c: Regenerate.
79 * fr30-desc.h: Regenerate.
80 * fr30-dis.c: Regenerate.
81 * fr30-ibld.c: Regenerate.
82 * fr30-opc.c: Regenerate.
83 * fr30-opc.h: Regenerate.
84 * frv-asm.c: Regenerate.
85 * frv-desc.c: Regenerate.
86 * frv-desc.h: Regenerate.
87 * frv-dis.c: Regenerate.
88 * frv-ibld.c: Regenerate.
89 * frv-opc.c: Regenerate.
90 * frv-opc.h: Regenerate.
91 * ip2k-asm.c: Regenerate.
92 * ip2k-desc.c: Regenerate.
93 * ip2k-desc.h: Regenerate.
94 * ip2k-dis.c: Regenerate.
95 * ip2k-ibld.c: Regenerate.
96 * ip2k-opc.c: Regenerate.
97 * ip2k-opc.h: Regenerate.
98 * iq2000-asm.c: Regenerate.
99 * iq2000-desc.c: Regenerate.
100 * iq2000-desc.h: Regenerate.
101 * iq2000-dis.c: Regenerate.
102 * iq2000-ibld.c: Regenerate.
103 * iq2000-opc.c: Regenerate.
104 * iq2000-opc.h: Regenerate.
105 * lm32-asm.c: Regenerate.
106 * lm32-desc.c: Regenerate.
107 * lm32-desc.h: Regenerate.
108 * lm32-dis.c: Regenerate.
109 * lm32-ibld.c: Regenerate.
110 * lm32-opc.c: Regenerate.
111 * lm32-opc.h: Regenerate.
112 * lm32-opinst.c: Regenerate.
113 * m32c-asm.c: Regenerate.
114 * m32c-desc.c: Regenerate.
115 * m32c-desc.h: Regenerate.
116 * m32c-dis.c: Regenerate.
117 * m32c-ibld.c: Regenerate.
118 * m32c-opc.c: Regenerate.
119 * m32c-opc.h: Regenerate.
120 * m32r-asm.c: Regenerate.
121 * m32r-desc.c: Regenerate.
122 * m32r-desc.h: Regenerate.
123 * m32r-dis.c: Regenerate.
124 * m32r-ibld.c: Regenerate.
125 * m32r-opc.c: Regenerate.
126 * m32r-opc.h: Regenerate.
127 * m32r-opinst.c: Regenerate.
128 * mep-asm.c: Regenerate.
129 * mep-desc.c: Regenerate.
130 * mep-desc.h: Regenerate.
131 * mep-dis.c: Regenerate.
132 * mep-ibld.c: Regenerate.
133 * mep-opc.c: Regenerate.
134 * mep-opc.h: Regenerate.
135 * mt-asm.c: Regenerate.
136 * mt-desc.c: Regenerate.
137 * mt-desc.h: Regenerate.
138 * mt-dis.c: Regenerate.
139 * mt-ibld.c: Regenerate.
140 * mt-opc.c: Regenerate.
141 * mt-opc.h: Regenerate.
142 * or1k-asm.c: Regenerate.
143 * or1k-desc.c: Regenerate.
144 * or1k-desc.h: Regenerate.
145 * or1k-dis.c: Regenerate.
146 * or1k-ibld.c: Regenerate.
147 * or1k-opc.c: Regenerate.
148 * or1k-opc.h: Regenerate.
149 * or1k-opinst.c: Regenerate.
150 * xc16x-asm.c: Regenerate.
151 * xc16x-desc.c: Regenerate.
152 * xc16x-desc.h: Regenerate.
153 * xc16x-dis.c: Regenerate.
154 * xc16x-ibld.c: Regenerate.
155 * xc16x-opc.c: Regenerate.
156 * xc16x-opc.h: Regenerate.
157 * xstormy16-asm.c: Regenerate.
158 * xstormy16-desc.c: Regenerate.
159 * xstormy16-desc.h: Regenerate.
160 * xstormy16-dis.c: Regenerate.
161 * xstormy16-ibld.c: Regenerate.
162 * xstormy16-opc.c: Regenerate.
163 * xstormy16-opc.h: Regenerate.
164
7639175c
AM		 1652017-07-07 Alan Modra <amodra@gmail.com>
166
167 * cgen-dis.in: Include disassemble.h, not dis-asm.h.
168 * m32c-dis.c: Regenerate.
169 * mep-dis.c: Regenerate.
170
e4bdd679
BP		 1712017-07-05 Borislav Petkov <bp@suse.de>
172
173 * i386-dis.c: Enable ModRM.reg /6 aliases.
174
60c96dbf
RR		 1752017-07-04 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
176
177 * opcodes/arm-dis.c: Support MVFR2 in disassembly
178 with vmrs and vmsr.
179
0d702cfe
TG		 1802017-07-04 Tristan Gingold <gingold@adacore.com>
181
182 * configure: Regenerate.
183
15e6ed8c
TG		 1842017-07-03 Tristan Gingold <gingold@adacore.com>
185
186 * po/opcodes.pot: Regenerate.
187
b1d3c886
MR		 1882017-06-30 Maciej W. Rozycki <macro@imgtec.com>
189
190 * mips-opc.c (mips_builtin_opcodes): Move "lsa" and "dlsa"
191 entries to the MSA ASE instruction block.
192
909b4e3d
MR		 1932017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
194 Maciej W. Rozycki <macro@imgtec.com>
195
196 * micromips-opc.c (XPA, XPAVZ): New macros.
197 (micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and
198 "mthgc0".
199
f5b2fd52
MR		 2002017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
201 Maciej W. Rozycki <macro@imgtec.com>
202
203 * micromips-opc.c (I36): New macro.
204 (micromips_opcodes): Add "eretnc".
205
9785fc2a
MR		 2062017-06-30 Maciej W. Rozycki <macro@imgtec.com>
207 Andrew Bennett <andrew.bennett@imgtec.com>
208
209 * mips-dis.c (mips_calculate_combination_ases): Handle the
210 ASE_XPA_VIRT flag.
211 (parse_mips_ase_option): New function.
212 (parse_mips_dis_option): Factor out ASE option handling to the
213 new function. Call `mips_calculate_combination_ases'.
214 * mips-opc.c (XPAVZ): New macro.
215 (mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0",
216 "mfhgc0", "mthc0" and "mthgc0".
217
60804c53
MR		 2182017-06-29 Maciej W. Rozycki <macro@imgtec.com>
219
220 * mips-dis.c (mips_calculate_combination_ases): New function.
221 (mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT
222 calculation to the new function.
223 (set_default_mips_dis_options): Call the new function.
224
2e74f9dd
AK		 2252017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
226
227 * arc-dis.c (parse_disassembler_options): Use
228 FOR_EACH_DISASSEMBLER_OPTION.
229
e1e94c49
AK		 2302017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
231
232 * arc-dis.c (parse_option): Use disassembler_options_cmp to compare
233 disassembler option strings.
234 (parse_cpu_option): Likewise.
235
65a55fbb
TC		 2362017-06-28 Tamar Christina <tamar.christina@arm.com>
237
238 * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod.
239 * aarch64-dis.c (aarch64_ext_reglane): Likewise.
240 * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New.
241 (aarch64_feature_dotprod, DOT_INSN): New.
242 (udot, sdot): New.
243 * aarch64-dis-2.c: Regenerated.
244
c604a79a
JW		 2452017-06-28 Jiong Wang <jiong.wang@arm.com>
246
247 * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
248
38bf472a
MR		 2492017-06-28 Maciej W. Rozycki <macro@imgtec.com>
250 Matthew Fortune <matthew.fortune@imgtec.com>
4151f684 251 Andrew Bennett <andrew.bennett@imgtec.com>
38bf472a
MR		 252
253 * mips-formats.h (INT_BIAS): New macro.
254 (INT_ADJ): Redefine in INT_BIAS terms.
255 * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
256 (mips_print_save_restore): New function.
257 (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
258 (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
259 call.
260 (print_insn_args): Handle OP_SAVE_RESTORE_LIST.
261 (print_mips16_insn_arg): Call `mips_print_save_restore' for
262 OP_SAVE_RESTORE_LIST handling, factored out from here.
263 * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
264 (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
265 (mips_builtin_opcodes): Add "restore" and "save" entries.
266 * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
267 (IAMR2): New macro.
268 (mips16_opcodes): Add "copyw" and "ucopyw" entries.
269
9bdfdbf9
AW		 2702017-06-23 Andrew Waterman <andrew@sifive.com>
271
272 * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
273 alias; do not mark SLTI instruction as an alias.
274
2234eee6
L		 2752017-06-21 H.J. Lu <hongjiu.lu@intel.com>
276
277 * i386-dis.c (RM_0FAE_REG_5): Removed.
278 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
279 (PREFIX_MOD_3_0F01_REG_5_RM_0): New.
280 (PREFIX_MOD_3_0FAE_REG_5): Likewise.
281 (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1. Add
282 PREFIX_MOD_3_0F01_REG_5_RM_0.
283 (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5. Add
284 PREFIX_MOD_3_0FAE_REG_5.
285 (mod_table): Update MOD_0FAE_REG_5.
286 (rm_table): Update RM_0F01_REG_5. Remove RM_0FAE_REG_5.
287 * i386-opc.tbl: Update incsspd, incsspq and setssbsy.
288 * i386-tbl.h: Regenerated.
289
c2f76402
L		 2902017-06-21 H.J. Lu <hongjiu.lu@intel.com>
291
292 * i386-dis.c (prefix_table): Replace savessp with saveprevssp.
293 * i386-opc.tbl: Likewise.
294 * i386-tbl.h: Regenerated.
295
9fef80d6
L		 2962017-06-21 H.J. Lu <hongjiu.lu@intel.com>
297
298 * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"
299 and "jmp{&|}".
300 (NOTRACK_Fixup): Support memory indirect branch with NOTRACK
301 prefix.
302
0f6d864d
NC		 3032017-06-19 Nick Clifton <nickc@redhat.com>
304
305 PR binutils/21614
306 * score-dis.c (score_opcodes): Add sentinel.
307
e197589b
AM		 3082017-06-16 Alan Modra <amodra@gmail.com>
309
310 * rx-decode.c: Regenerate.
311
0d96e4df
L		 3122017-06-15 H.J. Lu <hongjiu.lu@intel.com>
313
314 PR binutils/21594
315 * i386-dis.c (OP_E_register): Check valid bnd register.
316 (OP_G): Likewise.
317
cd3ea7c6
NC		 3182017-06-15 Nick Clifton <nickc@redhat.com>
319
320 PR binutils/21595
321 * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
322 range value.
323
63323b5b
NC		 3242017-06-15 Nick Clifton <nickc@redhat.com>
325
326 PR binutils/21588
327 * rl78-decode.opc (OP_BUF_LEN): Define.
328 (GETBYTE): Check for the index exceeding OP_BUF_LEN.
329 (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
330 array.
331 * rl78-decode.c: Regenerate.
332
08c7881b
NC		 3332017-06-15 Nick Clifton <nickc@redhat.com>
334
335 PR binutils/21586
336 * bfin-dis.c (gregs): Clip index to prevent overflow.
337 (regs): Likewise.
338 (regs_lo): Likewise.
339 (regs_hi): Likewise.
340
e64519d1
NC		 3412017-06-14 Nick Clifton <nickc@redhat.com>
342
343 PR binutils/21576
344 * score7-dis.c (score_opcodes): Add sentinel.
345
6394c606
YQ		 3462017-06-14 Yao Qi <yao.qi@linaro.org>
347
348 * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
349 * arm-dis.c: Likewise.
350 * ia64-dis.c: Likewise.
351 * mips-dis.c: Likewise.
352 * spu-dis.c: Likewise.
353 * disassemble.h (print_insn_aarch64): New declaration, moved from
354 include/dis-asm.h.
355 (print_insn_big_arm, print_insn_big_mips): Likewise.
356 (print_insn_i386, print_insn_ia64): Likewise.
357 (print_insn_little_arm, print_insn_little_mips): Likewise.
358
db5fa770
NC		 3592017-06-14 Nick Clifton <nickc@redhat.com>
360
361 PR binutils/21587
362 * rx-decode.opc: Include libiberty.h
363 (GET_SCALE): New macro - validates access to SCALE array.
364 (GET_PSCALE): New macro - validates access to PSCALE array.
365 (DIs, SIs, S2Is, rx_disp): Use new macros.
366 * rx-decode.c: Regenerate.
367
05c966f3
AV		 3682017-07-14 Andre Vieira <andre.simoesdiasvieira@arm.com>
369
370 * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
371
10045478
AK		 3722017-05-30 Anton Kolesov <anton.kolesov@synopsys.com>
373
374 * arc-dis.c (enforced_isa_mask): Declare.
375 (cpu_types): Likewise.
376 (parse_cpu_option): New function.
377 (parse_disassembler_options): Use it.
378 (print_insn_arc): Use enforced_isa_mask.
379 (print_arc_disassembler_options): Document new options.
380
88c1242d
YQ		 3812017-05-24 Yao Qi <yao.qi@linaro.org>
382
383 * alpha-dis.c: Include disassemble.h, don't include
384 dis-asm.h.
385 * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
386 * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
387 * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
388 * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
389 * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
390 * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
391 * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
392 * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
393 * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
394 * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
395 * moxie-dis.c, msp430-dis.c, mt-dis.c:
396 * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
397 * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
398 * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
399 * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
400 * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
401 * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
402 * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
403 * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
404 * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
405 * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
406 * z80-dis.c, z8k-dis.c: Likewise.
407 * disassemble.h: New file.
408
ab20fa4a
YQ		 4092017-05-24 Yao Qi <yao.qi@linaro.org>
410
411 * rl78-dis.c (rl78_get_disassembler): If parameter abfd
412 is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
413
003ca0fd
YQ		 4142017-05-24 Yao Qi <yao.qi@linaro.org>
415
416 * disassemble.c (disassembler): Add arguments a, big and mach.
417 Use them.
418
04ef582a
L		 4192017-05-22 H.J. Lu <hongjiu.lu@intel.com>
420
421 * i386-dis.c (NOTRACK_Fixup): New.
422 (NOTRACK): Likewise.
423 (NOTRACK_PREFIX): Likewise.
424 (last_active_prefix): Likewise.
425 (reg_table): Use NOTRACK on indirect call and jmp.
426 (ckprefix): Set last_active_prefix.
427 (prefix_name): Return "notrack" for NOTRACK_PREFIX.
428 * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
429 * i386-opc.h (NoTrackPrefixOk): New.
430 (i386_opcode_modifier): Add notrackprefixok.
431 * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
432 Add notrack.
433 * i386-tbl.h: Regenerated.
434
64517994
JM		 4352017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
436
437 * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
438 (X_IMM2): Define.
439 (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
440 bfd_mach_sparc_v9m8.
441 (print_insn_sparc): Handle new operand types.
442 * sparc-opc.c (MASK_M8): Define.
443 (v6): Add MASK_M8.
444 (v6notlet): Likewise.
445 (v7): Likewise.
446 (v8): Likewise.
447 (v9): Likewise.
448 (v9a): Likewise.
449 (v9b): Likewise.
450 (v9c): Likewise.
451 (v9d): Likewise.
452 (v9e): Likewise.
453 (v9v): Likewise.
454 (v9m): Likewise.
455 (v9andleon): Likewise.
456 (m8): Define.
457 (HWS_VM8): Define.
458 (HWS2_VM8): Likewise.
459 (sparc_opcode_archs): Add entry for "m8".
460 (sparc_opcodes): Add OSA2017 and M8 instructions
461 dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
462 fpx{ll,ra,rl}64x,
463 ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
464 ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
465 revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
466 stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
467 (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
468 ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
469 ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
470 ASI_CORE_SELECT_COMMIT_NHT.
471
535b785f
AM		 4722017-05-18 Alan Modra <amodra@gmail.com>
473
474 * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
475 * aarch64-dis.c: Likewise.
476 * aarch64-gen.c: Likewise.
477 * aarch64-opc.c: Likewise.
478
25499ac7
MR		 4792017-05-15 Maciej W. Rozycki <macro@imgtec.com>
480 Matthew Fortune <matthew.fortune@imgtec.com>
481
482 * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
483 ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
484 (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
485 (print_insn_arg) <OP_REG28>: Add handler.
486 (validate_insn_args) <OP_REG28>: Handle.
487 (print_mips16_insn_arg): Handle MIPS16 instructions that require
488 32-bit encoding and 9-bit immediates.
489 (print_insn_mips16): Handle MIPS16 instructions that require
490 32-bit encoding and MFC0/MTC0 operand decoding.
491 * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
492 <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
493 (RD_C0, WR_C0, E2, E2MT): New macros.
494 (mips16_opcodes): Add entries for MIPS16e2 instructions:
495 GP-relative "addiu" and its "addu" spelling, "andi", "cache",
496 "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
497 "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
498 "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
499 "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
500 instructions, "swl", "swr", "sync" and its "sync_acquire",
501 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
502 "xori", "dmt", "dvpe", "emt" and "evpe". Add split
503 regular/extended entries for original MIPS16 ISA revision
504 instructions whose extended forms are subdecoded in the MIPS16e2
505 ISA revision: "li", "sll" and "srl".
506
fdfb4752
MR		 5072017-05-15 Maciej W. Rozycki <macro@imgtec.com>
508
509 * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
510 reference in CP0 move operand decoding.
511
a4f89915
MR		 5122017-05-12 Maciej W. Rozycki <macro@imgtec.com>
513
514 * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
515 type to hexadecimal.
516 (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
517
99e2d67a
MR		 5182017-05-11 Maciej W. Rozycki <macro@imgtec.com>
519
520 * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
521 "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
522 "sync_rmb" and "sync_wmb" as aliases.
523 * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
524 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
525
53a346d8
CZ		 5262017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
527
528 * arc-dis.c (parse_option): Update quarkse_em option..
529 * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
530 QUARKSE1.
531 (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
532
f91d48de
KC		 5332017-05-03 Kito Cheng <kito.cheng@gmail.com>
534
535 * riscv-dis.c (print_insn_args): Handle 'Co' operands.
536
43e379d7
MC		 5372017-05-01 Michael Clark <michaeljclark@mac.com>
538
539 * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
540 register.
541
a4ddc54e
MR		 5422017-05-02 Maciej W. Rozycki <macro@imgtec.com>
543
544 * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
545 and branches and not synthetic data instructions.
546
fe50e98c
BE		 5472017-05-02 Bernd Edlinger <bernd.edlinger@hotmail.de>
548
549 * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
550
126124cc
CZ		 5512017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
552
553 * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
554 * arc-opc.c (insert_r13el): New function.
555 (R13_EL): Define.
556 * arc-tbl.h: Add new enter/leave variants.
557
be6a24d8
CZ		 5582017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
559
560 * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
561
0348fd79
MR		 5622017-04-25 Maciej W. Rozycki <macro@imgtec.com>
563
564 * mips-dis.c (print_mips_disassembler_options): Add
565 `no-aliases'.
566
6e3d1f07
MR		 5672017-04-25 Maciej W. Rozycki <macro@imgtec.com>
568
569 * mips16-opc.c (AL): New macro.
570 (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
571 of "ld" and "lw" as aliases.
572
957f6b39
TC		 5732017-04-24 Tamar Christina <tamar.christina@arm.com>
574
575 * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
576 arguments.
577
a8cc8a54
AM		 5782017-04-22 Alexander Fedotov <alfedotov@gmail.com>
579 Alan Modra <amodra@gmail.com>
580
581 * ppc-opc.c (ELEV): Define.
582 (vle_opcodes): Add se_rfgi and e_sc.
583 (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
584 for E200Z4.
585
3ab87b68
JM		 5862017-04-21 Jose E. Marchesi <jose.marchesi@oracle.com>
587
588 * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
589
792f174f
NC		 5902017-04-21 Nick Clifton <nickc@redhat.com>
591
592 PR binutils/21380
593 * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
594 LD3R and LD4R.
595
42742084
AM		 5962017-04-13 Alan Modra <amodra@gmail.com>
597
598 * epiphany-desc.c: Regenerate.
599 * fr30-desc.c: Regenerate.
600 * frv-desc.c: Regenerate.
601 * ip2k-desc.c: Regenerate.
602 * iq2000-desc.c: Regenerate.
603 * lm32-desc.c: Regenerate.
604 * m32c-desc.c: Regenerate.
605 * m32r-desc.c: Regenerate.
606 * mep-desc.c: Regenerate.
607 * mt-desc.c: Regenerate.
608 * or1k-desc.c: Regenerate.
609 * xc16x-desc.c: Regenerate.
610 * xstormy16-desc.c: Regenerate.
611
9a85b496
AM		 6122017-04-11 Alan Modra <amodra@gmail.com>
613
ef85eab0 614 * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
c03dc33b
AM		 615 PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm". Formatting. Set
616 PPC_OPCODE_TMR for e6500.
9a85b496
AM		 617 * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
618 (PPCVEC3): Define as PPC_OPCODE_POWER9.
9570835e
AM		 619 (PPCVSX2): Define as PPC_OPCODE_POWER8.
620 (PPCVSX3): Define as PPC_OPCODE_POWER9.
ef85eab0 621 (PPCHTM): Define as PPC_OPCODE_POWER8.
c03dc33b 622 (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
9a85b496 623
62adc510
AM		 6242017-04-10 Alan Modra <amodra@gmail.com>
625
626 * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
627 * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
628 (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
629 removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
630
aa808707
PC		 6312017-04-09 Pip Cet <pipcet@gmail.com>
632
633 * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
634 appropriate floating-point precision directly.
635
ac8f0f72
AM		 6362017-04-07 Alan Modra <amodra@gmail.com>
637
638 * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
639 lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
640 lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
641 lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
642 vector instructions with E6500 not PPCVEC2.
643
62ecb94c
PC		 6442017-04-06 Pip Cet <pipcet@gmail.com>
645
646 * Makefile.am: Add wasm32-dis.c.
647 * configure.ac: Add wasm32-dis.c to wasm32 target.
648 * disassemble.c: Add wasm32 disassembler code.
649 * wasm32-dis.c: New file.
650 * Makefile.in: Regenerate.
651 * configure: Regenerate.
652 * po/POTFILES.in: Regenerate.
653 * po/opcodes.pot: Regenerate.
654
f995bbe8
PA		 6552017-04-05 Pedro Alves <palves@redhat.com>
656
657 * arc-dis.c (parse_option, parse_disassembler_options): Constify.
658 * arm-dis.c (parse_arm_disassembler_options): Constify.
659 * ppc-dis.c (powerpc_init_dialect): Constify local.
660 * vax-dis.c (parse_disassembler_options): Constify.
661
b5292032
PD		 6622017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
663
664 * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
665 RISCV_GP_SYMBOL.
666
f96bd6c2
PC		 6672017-03-30 Pip Cet <pipcet@gmail.com>
668
669 * configure.ac: Add (empty) bfd_wasm32_arch target.
670 * configure: Regenerate
671 * po/opcodes.pot: Regenerate.
672
f7c514a3
JM		 6732017-03-29 Sheldon Lobo <sheldon.lobo@oracle.com>
674
675 Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
676 OSA2015.
677 * opcodes/sparc-opc.c (asi_table): New ASIs.
678
52be03fd
AM		 6792017-03-29 Alan Modra <amodra@gmail.com>
680
681 * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add
682 "raw" option.
683 (lookup_powerpc): Don't special case -1 dialect. Handle
684 PPC_OPCODE_RAW.
685 (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
686 lookup_powerpc call, pass it on second.
687
9b753937
AM		 6882017-03-27 Alan Modra <amodra@gmail.com>
689
690 PR 21303
691 * ppc-dis.c (struct ppc_mopt): Comment.
692 (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
693
c0c31e91
RZ		 6942017-03-27 Rinat Zelig <rinat@mellanox.com>
695
696 * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
697 * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
698 F_NPS_M, F_NPS_CORE, F_NPS_ALL.
699 (insert_nps_misc_imm_offset): New function.
700 (extract_nps_misc imm_offset): New function.
701 (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
702 (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
703
2253c8f0
AK		 7042017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
705
706 * s390-mkopc.c (main): Remove vx2 check.
707 * s390-opc.txt: Remove vx2 instruction flags.
708
645d3342
RZ		 7092017-03-21 Rinat Zelig <rinat@mellanox.com>
710
711 * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
712 * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
713 (insert_nps_imm_offset): New function.
714 (extract_nps_imm_offset): New function.
715 (insert_nps_imm_entry): New function.
716 (extract_nps_imm_entry): New function.
717
4b94dd2d
AM		 7182017-03-17 Alan Modra <amodra@gmail.com>
719
720 PR 21248
721 * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
722 mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after
723 those spr mnemonics they alias. Similarly for mtibatl, mtibatu.
724
b416fe87
KC		 7252017-03-14 Kito Cheng <kito.cheng@gmail.com>
726
727 * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
728 <c.andi>: Likewise.
729 <c.addiw> Likewise.
730
03b039a5
KC		 7312017-03-14 Kito Cheng <kito.cheng@gmail.com>
732
733 * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
734
2c232b83
AW		 7352017-03-13 Andrew Waterman <andrew@sifive.com>
736
737 * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
738 <srl> Likewise.
739 <srai> Likewise.
740 <sra> Likewise.
741
86fa6981
L		 7422017-03-09 H.J. Lu <hongjiu.lu@intel.com>
743
744 * i386-gen.c (opcode_modifiers): Replace S with Load.
745 * i386-opc.h (S): Removed.
746 (Load): New.
747 (i386_opcode_modifier): Replace s with load.
748 * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
749 and {evex}. Replace S with Load.
750 * i386-tbl.h: Regenerated.
751
c1fe188b
L		 7522017-03-09 H.J. Lu <hongjiu.lu@intel.com>
753
754 * i386-opc.tbl: Use CpuCET on rdsspq.
755 * i386-tbl.h: Regenerated.
756
4b8b687e
PB		 7572017-03-08 Peter Bergner <bergner@vnet.ibm.com>
758
759 * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
760 <vsx>: Do not use PPC_OPCODE_VSX3;
761
1437d063
PB		 7622017-03-08 Peter Bergner <bergner@vnet.ibm.com>
763
764 * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
765
603555e5
L		 7662017-03-06 H.J. Lu <hongjiu.lu@intel.com>
767
768 * i386-dis.c (REG_0F1E_MOD_3): New enum.
769 (MOD_0F1E_PREFIX_1): Likewise.
770 (MOD_0F38F5_PREFIX_2): Likewise.
771 (MOD_0F38F6_PREFIX_0): Likewise.
772 (RM_0F1E_MOD_3_REG_7): Likewise.
773 (PREFIX_MOD_0_0F01_REG_5): Likewise.
774 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
775 (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
776 (PREFIX_0F1E): Likewise.
777 (PREFIX_MOD_0_0FAE_REG_5): Likewise.
778 (PREFIX_0F38F5): Likewise.
779 (dis386_twobyte): Use PREFIX_0F1E.
780 (reg_table): Add REG_0F1E_MOD_3.
781 (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
782 PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
783 PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
784 PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
785 (three_byte_table): Use PREFIX_0F38F5.
786 (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
787 Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
788 (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
789 RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
790 PREFIX_MOD_3_0F01_REG_5_RM_2.
791 * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
792 (cpu_flags): Add CpuCET.
793 * i386-opc.h (CpuCET): New enum.
794 (CpuUnused): Commented out.
795 (i386_cpu_flags): Add cpucet.
796 * i386-opc.tbl: Add Intel CET instructions.
797 * i386-init.h: Regenerated.
798 * i386-tbl.h: Likewise.
799
73f07bff
AM		 8002017-03-06 Alan Modra <amodra@gmail.com>
801
802 PR 21124
803 * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
804 (extract_raq, extract_ras, extract_rbx): New functions.
805 (powerpc_operands): Use opposite corresponding insert function.
806 (Q_MASK): Define.
807 (powerpc_opcodes): Apply Q_MASK to all quad insns with even
808 register restriction.
809
65b48a81
PB		 8102017-02-28 Peter Bergner <bergner@vnet.ibm.com>
811
812 * disassemble.c Include "safe-ctype.h".
813 (disassemble_init_for_target): Handle s390 init.
814 (remove_whitespace_and_extra_commas): New function.
815 (disassembler_options_cmp): Likewise.
816 * arm-dis.c: Include "libiberty.h".
817 (NUM_ELEM): Delete.
818 (regnames): Use long disassembler style names.
819 Add force-thumb and no-force-thumb options.
820 (NUM_ARM_REGNAMES): Rename from this...
821 (NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE.
822 (get_arm_regname_num_options): Delete.
823 (set_arm_regname_option): Likewise.
824 (get_arm_regnames): Likewise.
825 (parse_disassembler_options): Likewise.
826 (parse_arm_disassembler_option): Rename from this...
827 (parse_arm_disassembler_options): ...to this. Make static.
828 Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
829 (print_insn): Use parse_arm_disassembler_options.
830 (disassembler_options_arm): New function.
831 (print_arm_disassembler_options): Handle updated regnames.
832 * ppc-dis.c: Include "libiberty.h".
833 (ppc_opts): Add "32" and "64" entries.
834 (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
835 (powerpc_init_dialect): Add break to switch statement.
836 Use new FOR_EACH_DISASSEMBLER_OPTION macro.
837 (disassembler_options_powerpc): New function.
838 (print_ppc_disassembler_options): Use ARRAY_SIZE.
839 Remove printing of "32" and "64".
840 * s390-dis.c: Include "libiberty.h".
841 (init_flag): Remove unneeded variable.
842 (struct s390_options_t): New structure type.
843 (options): New structure.
844 (init_disasm): Rename from this...
845 (disassemble_init_s390): ...to this. Add initializations for
846 current_arch_mask and option_use_insn_len_bits_p. Remove init_flag.
847 (print_insn_s390): Delete call to init_disasm.
848 (disassembler_options_s390): New function.
849 (print_s390_disassembler_options): Print using information from
850 struct 'options'.
851 * po/opcodes.pot: Regenerate.
852
15c7c1d8
JB		 8532017-02-28 Jan Beulich <jbeulich@suse.com>
854
855 * i386-dis.c (PCMPESTR_Fixup): New.
856 (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
857 (prefix_table): Use PCMPESTR_Fixup.
858 (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
859 PCMPESTR_Fixup.
860 (vex_w_table): Delete VPCMPESTR{I,M} entries.
861 * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
862 Split 64-bit and non-64-bit variants.
863 * opcodes/i386-tbl.h: Re-generate.
864
582e12bf
RS		 8652017-02-24 Richard Sandiford <richard.sandiford@arm.com>
866
867 * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
868 (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
869 (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
870 (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
871 (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
872 (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
873 (OP_SVE_V_HSD): New macros.
874 (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
875 (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
876 (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
877 (aarch64_opcode_table): Add new SVE instructions.
878 (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
879 for rotation operands. Add new SVE operands.
880 * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
881 (ins_sve_quad_index): Likewise.
882 (ins_imm_rotate): Split into...
883 (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
884 * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
885 (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
886 functions.
887 (aarch64_ins_sve_addr_ri_s4): New function.
888 (aarch64_ins_sve_quad_index): Likewise.
889 (do_misc_encoding): Handle "MOV Zn.Q, Qm".
890 * aarch64-asm-2.c: Regenerate.
891 * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
892 (ext_sve_quad_index): Likewise.
893 (ext_imm_rotate): Split into...
894 (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
895 * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
896 (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
897 functions.
898 (aarch64_ext_sve_addr_ri_s4): New function.
899 (aarch64_ext_sve_quad_index): Likewise.
900 (aarch64_ext_sve_index): Allow quad indices.
901 (do_misc_decoding): Likewise.
902 * aarch64-dis-2.c: Regenerate.
903 * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
904 aarch64_field_kinds.
905 (OPD_F_OD_MASK): Widen by one bit.
906 (OPD_F_NO_ZR): Bump accordingly.
907 (get_operand_field_width): New function.
908 * aarch64-opc.c (fields): Add new SVE fields.
909 (operand_general_constraint_met_p): Handle new SVE operands.
910 (aarch64_print_operand): Likewise.
911 * aarch64-opc-2.c: Regenerate.
912
f482d304
RS		 9132017-02-24 Richard Sandiford <richard.sandiford@arm.com>
914
915 * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
916 (aarch64_feature_compnum): ...this.
917 (SIMD_V8_3): Replace with...
918 (COMPNUM): ...this.
919 (CNUM_INSN): New macro.
920 (aarch64_opcode_table): Use it for the complex number instructions.
921
7db2c588
JB		 9222017-02-24 Jan Beulich <jbeulich@suse.com>
923
924 * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
925
1e9d41d4
SL		 9262017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
927
928 Add support for associating SPARC ASIs with an architecture level.
929 * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
930 * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
931 decoding of SPARC ASIs.
932
53c4d625
JB		 9332017-02-23 Jan Beulich <jbeulich@suse.com>
934
935 * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
936 82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
937
11648de5
JB		 9382017-02-21 Jan Beulich <jbeulich@suse.com>
939
940 * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
941 1 (instead of to itself). Correct typo.
942
f98d33be
AW		 9432017-02-14 Andrew Waterman <andrew@sifive.com>
944
945 * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
946 pseudoinstructions.
947
773fb663
RS		 9482017-02-15 Richard Sandiford <richard.sandiford@arm.com>
949
950 * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
951 (aarch64_sys_reg_supported_p): Handle them.
952
cc07cda6
CZ		 9532017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
954
955 * arc-opc.c (UIMM6_20R): Define.
956 (SIMM12_20): Use above.
957 (SIMM12_20R): Define.
958 (SIMM3_5_S): Use above.
959 (UIMM7_A32_11R_S): Define.
960 (UIMM7_9_S): Use above.
961 (UIMM3_13R_S): Define.
962 (SIMM11_A32_7_S): Use above.
963 (SIMM9_8R): Define.
964 (UIMM10_A32_8_S): Use above.
965 (UIMM8_8R_S): Define.
966 (W6): Use above.
967 (arc_relax_opcodes): Use all above defines.
968
66a5a740
VG		 9692017-02-15 Vineet Gupta <vgupta@synopsys.com>
970
971 * arc-regs.h: Distinguish some of the registers different on
972 ARC700 and HS38 cpus.
973
7e0de605
AM		 9742017-02-14 Alan Modra <amodra@gmail.com>
975
976 PR 21118
977 * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
978 with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
979
54064fdb
AM		 9802017-02-11 Stafford Horne <shorne@gmail.com>
981 Alan Modra <amodra@gmail.com>
982
983 * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
984 Use insn_bytes_value and insn_int_value directly instead. Don't
985 free allocated memory until function exit.
986
dce75bf9
NP		 9872017-02-10 Nicholas Piggin <npiggin@gmail.com>
988
989 * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
990
1b7e3d2f
NC		 9912017-02-03 Nick Clifton <nickc@redhat.com>
992
993 PR 21096
994 * aarch64-opc.c (print_register_list): Ensure that the register
995 list index will fir into the tb buffer.
996 (print_register_offset_address): Likewise.
997 * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
998
8ec5cf65
AD		 9992017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
1000
1001 PR 21056
1002 * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
1003 instructions when the previous fetch packet ends with a 32-bit
1004 instruction.
1005
a1aa5e81
DD		 10062017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
1007
1008 * pru-opc.c: Remove vague reference to a future GDB port.
1009
add3afb2
NC		 10102017-01-20 Nick Clifton <nickc@redhat.com>
1011
1012 * po/ga.po: Updated Irish translation.
1013
c13a63b0
SN		 10142017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
1015
1016 * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
1017
9608051a
YQ		 10182017-01-13 Yao Qi <yao.qi@linaro.org>
1019
1020 * m68k-dis.c (match_insn_m68k): Extend comments. Return -1
1021 if FETCH_DATA returns 0.
1022 (m68k_scan_mask): Likewise.
1023 (print_insn_m68k): Update code to handle -1 return value.
1024
f622ea96
YQ		 10252017-01-13 Yao Qi <yao.qi@linaro.org>
1026
1027 * m68k-dis.c (enum print_insn_arg_error): New.
1028 (NEXTBYTE): Replace -3 with
1029 PRINT_INSN_ARG_MEMORY_ERROR.
1030 (NEXTULONG): Likewise.
1031 (NEXTSINGLE): Likewise.
1032 (NEXTDOUBLE): Likewise.
1033 (NEXTDOUBLE): Likewise.
1034 (NEXTPACKED): Likewise.
1035 (FETCH_ARG): Likewise.
1036 (FETCH_DATA): Update comments.
1037 (print_insn_arg): Update comments. Replace magic numbers with
1038 enum.
1039 (match_insn_m68k): Likewise.
1040
620214f7
IT		 10412017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1042
1043 * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
1044 * i386-dis-evex.h (evex_table): Updated.
1045 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
1046 CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
1047 (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
1048 * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
1049 (i386_cpu_flags): Add cpuavx512_vpopcntdq.
1050 * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
1051 * i386-init.h: Regenerate.
1052 * i386-tbl.h: Ditto.
1053
d95014a2
YQ		 10542017-01-12 Yao Qi <yao.qi@linaro.org>
1055
1056 * msp430-dis.c (msp430_singleoperand): Return -1 if
1057 msp430dis_opcode_signed returns false.
1058 (msp430_doubleoperand): Likewise.
1059 (msp430_branchinstr): Return -1 if
1060 msp430dis_opcode_unsigned returns false.
1061 (msp430x_calla_instr): Likewise.
1062 (print_insn_msp430): Likewise.
1063
0ae60c3e
NC		 10642017-01-05 Nick Clifton <nickc@redhat.com>
1065
1066 PR 20946
1067 * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
1068 could not be matched.
1069 (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
1070 NULL.
1071
d74d4880
SN		 10722017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
1073
1074 * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
1075 (aarch64_opcode_table): Use RCPC_INSN.
1076
cc917fd9
KC		 10772017-01-03 Kito Cheng <kito.cheng@gmail.com>
1078
1079 * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
1080 extension.
1081 * riscv-opcodes/all-opcodes: Likewise.
1082
b52d3cfc
DP		 10832017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
1084
1085 * riscv-dis.c (print_insn_args): Add fall through comment.
1086
f90c58d5
NC		 10872017-01-03 Nick Clifton <nickc@redhat.com>
1088
1089 * po/sr.po: New Serbian translation.
1090 * configure.ac (ALL_LINGUAS): Add sr.
1091 * configure: Regenerate.
1092
f47b0d4a
AM		 10932017-01-02 Alan Modra <amodra@gmail.com>
1094
1095 * epiphany-desc.h: Regenerate.
1096 * epiphany-opc.h: Regenerate.
1097 * fr30-desc.h: Regenerate.
1098 * fr30-opc.h: Regenerate.
1099 * frv-desc.h: Regenerate.
1100 * frv-opc.h: Regenerate.
1101 * ip2k-desc.h: Regenerate.
1102 * ip2k-opc.h: Regenerate.
1103 * iq2000-desc.h: Regenerate.
1104 * iq2000-opc.h: Regenerate.
1105 * lm32-desc.h: Regenerate.
1106 * lm32-opc.h: Regenerate.
1107 * m32c-desc.h: Regenerate.
1108 * m32c-opc.h: Regenerate.
1109 * m32r-desc.h: Regenerate.
1110 * m32r-opc.h: Regenerate.
1111 * mep-desc.h: Regenerate.
1112 * mep-opc.h: Regenerate.
1113 * mt-desc.h: Regenerate.
1114 * mt-opc.h: Regenerate.
1115 * or1k-desc.h: Regenerate.
1116 * or1k-opc.h: Regenerate.
1117 * xc16x-desc.h: Regenerate.
1118 * xc16x-opc.h: Regenerate.
1119 * xstormy16-desc.h: Regenerate.
1120 * xstormy16-opc.h: Regenerate.
1121
2571583a
AM		 11222017-01-02 Alan Modra <amodra@gmail.com>
1123
1124 Update year range in copyright notice of all files.
1125
5c1ad6b5 1126For older changes see ChangeLog-2016
3499769a 1127\f
5c1ad6b5 1128Copyright (C) 2017 Free Software Foundation, Inc.
3499769a
AM		 1129
1130Copying and distribution of this file, with or without modification,
1131are permitted in any medium without royalty provided the copyright
1132notice and this notice are preserved.
1133
1134Local Variables:
1135mode: change-log
1136left-margin: 8
1137fill-column: 74
1138version-control: never
1139End:
GDB Binutils - Deliverables
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