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* gdb.base/consecutive.exp: Don't use global in gdb_expect.
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
03547503
L		 12008-12-08 H.J. Lu <hongjiu.lu@intel.com>
2
3 * i386-gen.c (opcode_modifiers): Move VexNDS before VexNDD.
4
efa7dee7
L		 52008-12-08 H.J. Lu <hongjiu.lu@intel.com>
6
7 * i386-dis.c (putop): Remove strayed comments.
8
2f3bb96a
BE		 92008-12-04 Ben Elliston <bje@au.ibm.com>
10
11 * ppc-dis.c (powerpc_init_dialect): Do not set PPC_OPCODE_BOOKE
12 for -Mbooke.
13 (print_ppc_disassembler_options): Update usage.
14 * ppc-opc.c (DE, DES, DEO, DE_MASK): Remove.
15 (BOOKE64): Remove.
16 (PPCCHLK64): Likewise.
17 (powerpc_opcodes): Remove all BOOKE64 instructions.
18
3aa3176b
TS		 192008-11-28 Joshua Kinard <kumba@gentoo.org>
20
21 * mips-dis.c (mips_arch_choices): Add r14000, r16000.
22
59b098c9
SR		 232008-11-27 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
24
25 * cr16-dis.c (match_opcode): Truncate mcode to 32 bit and
26 adjusted the mask for 32-bit branch instruction.
27
e1c93c69
AM		 282008-11-27 Alan Modra <amodra@bigpond.net.au>
29
30 * ppc-opc.c (extract_sprg): Correct operand range check.
31
9f7678f6
AS		 322008-11-26 Andreas Schwab <schwab@suse.de>
33
34 * m68k-dis.c (NEXTBYTE, NEXTWORD, NEXTLONG, NEXTULONG, NEXTSINGLE)
35 (NEXTDOUBLE, NEXTEXTEND, NEXTPACKED): Fix error handling.
36 (save_printer, save_print_address): Remove.
37 (fetch_data): Don't use them.
38 (match_insn_m68k): Always restore printing functions.
39 (print_insn_m68k): Don't save/restore printing functions.
40
62443ade
NC		 412008-11-25 Nick Clifton <nickc@redhat.com>
42
43 * m68k-dis.c: Rewrite to remove use of setjmp/longjmp.
44
8e79c3df
CM		 452008-11-18 Catherine Moore <clm@codesourcery.com>
46
47 * arm-dis.c (coprocessor_opcodes): Add half-precision vcvt
48 instructions.
49 (neon_opcodes): Likewise.
50 (print_insn_coprocessor): Print 't' or 'b' for vcvt
51 instructions.
52
d387240a
TG		 532008-11-14 Tristan Gingold <gingold@adacore.com>
54
55 * makefile.vms (OBJS): Update list of objects.
56 (DEFS): Update
57 (CFLAGS): Update.
58
4dc48ef6
CF		 592008-11-06 Chao-ying Fu <fu@mips.com>
60
61 * mips-opc.c (synciobdma, syncs, syncw, syncws): Move these
62 before sync.
63 (sync): New instruction with 5-bit sync type.
3c6528a8 64 * mips-dis.c (print_insn_args): Add case '1' to print 5-bit values.
4dc48ef6 65
c8941035
NC		 662008-11-06 Nick Clifton <nickc@redhat.com>
67
68 * avr-dis.c: Replace uses of sprintf without a format string with
69 calls to strcpy.
70
a7bea99d
L		 712008-11-03 H.J. Lu <hongjiu.lu@intel.com>
72
73 * i386-opc.tbl: Add cmovpe and cmovpo.
74 * i386-tbl.h: Regenerated.
75
4267b19f
NC		 762008-10-22 Nick Clifton <nickc@redhat.com>
77
78 PR 6937
79 * configure.in (SHARED_LIBADD): Revert previous change.
80 Add a comment explaining why.
81 (SHARED_DEPENDENCIES): Revert previous change.
82 * configure: Regenerate.
83
8a9629d0
NC		 842008-10-10 Nick Clifton <nickc@redhat.com>
85
86 PR 6937
87 * configure.in (SHARED_LIBADD): Add libiberty.a.
88 (SHARED_DEPENDENCIES): Add libiberty.a.
89
c587b3f9
L		 902008-09-30 H.J. Lu <hongjiu.lu@intel.com>
91
92 * i386-gen.c: Include "hashtab.h".
93 (next_field): Take a new argument, last. Check last.
94 (process_i386_cpu_flag): Updated.
95 (process_i386_opcode_modifier): Likewise.
96 (process_i386_operand_type): Likewise.
97 (process_i386_registers): Likewise.
98 (output_i386_opcode): New.
99 (opcode_hash_entry): Likewise.
100 (opcode_hash_table): Likewise.
101 (opcode_hash_hash): Likewise.
102 (opcode_hash_eq): Likewise.
103 (process_i386_opcodes): Use opcode hash table and opcode array.
104
34b23dab
AK		 1052008-09-30 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
106
107 * s390-opc.txt (stdy, stey): Fix description
108
782e11fd
AM		 1092008-09-30 Alan Modra <amodra@bigpond.net.au>
110
111 * Makefile.am: Run "make dep-am".
112 * Makefile.in: Regenerate.
113
1927a18f
L		 1142008-09-29 H.J. Lu <hongjiu.lu@intel.com>
115
116 * aclocal.m4: Regenerated.
117 * configure: Likewise.
118 * Makefile.in: Likewise.
119
afac680a
NC		 1202008-09-29 Nick Clifton <nickc@redhat.com>
121
122 * po/vi.po: Updated Vietnamese translation.
123 * po/fr.po: Updated French translation.
124
b40d5eb9
AK		 1252008-09-26 Florian Krohm <fkrohm@us.ibm.com>
126
127 * s390-opc.txt (thder, thdr): Change RRE_RR to RRE_FF.
128 (cfxr, cfdr, cfer, clclu): Add esa flag.
129 (sqd): Instruction added.
130 (qadtr, qaxtr): Change RRF_FFFU to RRF_FUFF.
131 * s390-opc.c: (INSTR_RRF_FFFU, MASK_RRF_FFFU): Removed.
132
d0411736
AM		 1332008-09-14 Arnold Metselaar <arnold.metselaar@planet.nl>
134
135 * z80-dis.c (prt_rr_nn): Fix register pair for two byte opcodes.
136 (tab_elt opc_ed): Add "ld r,a" and "ld r,a" instructions.
137
3e126784
L		 1382008-09-11 H.J. Lu <hongjiu.lu@intel.com>
139
140 * i386-opc.tbl: Fix memory operand size for cmpXXXs[sd].
141 * i386-tbl.h: Regenerated.
142
ddab3d59
JB		 1432008-08-28 Jan Beulich <jbeulich@novell.com>
144
145 * i386-dis.c (dis386): Adjust far return mnemonics.
146 * i386-opc.tbl: Add retf.
147 * i386-tbl.h: Re-generate.
148
b19d5385
JB		 1492008-08-28 Jan Beulich <jbeulich@novell.com>
150
151 * i386-dis.c (dis386_twobyte): Adjust cmovXX mnemonics.
152
1ca35711
L		 1532008-08-28 H.J. Lu <hongjiu.lu@intel.com>
154
155 * ia64-dis.c (print_insn_ia64): Handle cr.iib0 and cr.iib1.
156 * ia64-gen.c (lookup_specifier): Likewise.
157
158 * ia64-ic.tbl: Add support for cr.iib0 and cr.iib1.
159 * ia64-raw.tbl: Likewise.
160 * ia64-waw.tbl: Likewise.
161 * ia64-asmtab.c: Regenerated.
162
515c56e7
L		 1632008-08-27 H.J. Lu <hongjiu.lu@intel.com>
164
165 * i386-opc.tbl: Correct fidivr operand size.
166
167 * i386-tbl.h: Regenerated.
168
da594c4a
AM		 1692008-08-24 Alan Modra <amodra@bigpond.net.au>
170
171 * configure.in: Update a number of obsolete autoconf macros.
172 * aclocal.m4: Regenerate.
173
a5ff0eb2
L		 1742008-08-20 H.J. Lu <hongjiu.lu@intel.com>
175
176 AVX Programming Reference (August, 2008)
177 * i386-dis.c (PREFIX_VEX_38DB): New.
178 (PREFIX_VEX_38DC): Likewise.
179 (PREFIX_VEX_38DD): Likewise.
180 (PREFIX_VEX_38DE): Likewise.
181 (PREFIX_VEX_38DF): Likewise.
182 (PREFIX_VEX_3ADF): Likewise.
183 (VEX_LEN_38DB_P_2): Likewise.
184 (VEX_LEN_38DC_P_2): Likewise.
185 (VEX_LEN_38DD_P_2): Likewise.
186 (VEX_LEN_38DE_P_2): Likewise.
187 (VEX_LEN_38DF_P_2): Likewise.
188 (VEX_LEN_3ADF_P_2): Likewise.
189 (PREFIX_VEX_3A04): Updated.
190 (VEX_LEN_3A06_P_2): Likewise.
191 (prefix_table): Add PREFIX_VEX_38DB, PREFIX_VEX_38DC,
192 PREFIX_VEX_38DD, PREFIX_VEX_38DE and PREFIX_VEX_3ADF.
193 (x86_64_table): Likewise.
194 (vex_len_table): Add VEX_LEN_38DB_P_2, VEX_LEN_38DC_P_2,
195 VEX_LEN_38DD_P_2, VEX_LEN_38DE_P_2, VEX_LEN_38DF_P_2 and
196 VEX_LEN_3ADF_P_2.
197
198 * i386-opc.tbl: Add AES + AVX instructions.
199 * i386-init.h: Regenerated.
200 * i386-tbl.h: Likewise.
201
7dc6076f
AK		 2022008-08-15 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
203
204 * s390-opc.c (INSTR_RRF_FFRU, MASK_RRF_FFRU): New instruction format.
205 * s390-opc.txt (lxr, rrdtr, rrxtr): Fix instruction format.
206
7357c5b6
AM		 2072008-08-15 Alan Modra <amodra@bigpond.net.au>
208
209 PR 6526
210 * configure.in: Invoke AC_USE_SYSTEM_EXTENSIONS.
211 * Makefile.in: Regenerate.
212 * aclocal.m4: Regenerate.
213 * config.in: Regenerate.
214 * configure: Regenerate.
215
899d85be
AM		 2162008-08-14 Sebastian Huber <sebastian.huber@embedded-brains.de>
217
218 PR 6825
219 * ppc-opc.c (powerpc_opcodes): Enable rfci, mfpmr, mtpmr for e300.
220
dfb07592
L		 2212008-08-12 H.J. Lu <hongjiu.lu@intel.com>
222
223 * i386-opc.tbl: Add syscall and sysret for Cpu64.
224
225 * i386-tbl.h: Regenerated.
226
323ee3f4
AM		 2272008-08-04 Alan Modra <amodra@bigpond.net.au>
228
229 * Makefile.am (POTFILES.in): Set LC_ALL=C.
230 * Makefile.in: Regenerate.
231 * po/POTFILES.in: Regenerate.
232
9b4e5766
PB		 2332008-08-01 Peter Bergner <bergner@vnet.ibm.com>
234
235 * ppc-dis.c (powerpc_init_dialect): Handle power7 and vsx options.
236 (print_insn_powerpc): Prepend 'vs' when printing VSX registers.
237 (print_ppc_disassembler_options): Document -Mpower7 and -Mvsx.
238 * ppc-opc.c (insert_xt6): New static function.
239 (extract_xt6): Likewise.
240 (insert_xa6): Likewise.
241 (extract_xa6: Likewise.
242 (insert_xb6): Likewise.
243 (extract_xb6): Likewise.
244 (insert_xb6s): Likewise.
245 (extract_xb6s): Likewise.
246 (XS6, XT6, XA6, XB6, XB6S, DM, XX3, XX3DM, XX1_MASK, XX3_MASK,
247 XX3DM_MASK, PPCVSX): New.
248 (powerpc_opcodes): Add opcodes "lxvd2x", "lxvd2ux", "stxvd2x",
249 "stxvd2ux", "xxmrghd", "xxmrgld", "xxpermdi", "xvmovdp", "xvcpsgndp".
250
20fd6e2e
PA		 2512008-08-01 Pedro Alves <pedro@codesourcery.com>
252
253 * Makefile.am ($(srcdir)/ia64-asmtab.c): Remove line continuation.
254 * Makefile.in: Regenerate.
255
a656ed5b
L		 2562008-08-01 H.J. Lu <hongjiu.lu@intel.com>
257
258 * i386-reg.tbl: Use Dw2Inval on AVX registers.
259 * i386-tbl.h: Regenerated.
260
081ba1b3
AM		 2612008-07-30 Michael J. Eager <eager@eagercon.com>
262
263 * ppc-dis.c (print_insn_powerpc): Disassemble FSL/FCR/UDI fields.
264 * ppc-opc.c (powerpc_operands): Add Xilinx APU related operands.
265 (insert_sprg, PPC405): Use PPC_OPCODE_405.
266 (powerpc_opcodes): Add Xilinx APU related opcodes.
267
0af1713e
AM		 2682008-07-30 Alan Modra <amodra@bigpond.net.au>
269
270 * bfin-dis.c, cris-dis.c, i386-dis.c, or32-opc.c: Silence gcc warnings.
271
30c09090
RS		 2722008-07-10 Richard Sandiford <rdsandiford@googlemail.com>
273
274 * mips-dis.c (_print_insn_mips): Use ELF_ST_IS_MIPS16.
275
c27e721e
AN		 2762008-07-07 Adam Nemet <anemet@caviumnetworks.com>
277
278 * mips-opc.c (CP): New macro.
279 (mips_builtin_opcodes): Mark c0, c2 and c3 as CP. Add Octeon to the
280 membership of di, dmfc0, dmtc0, ei, mfc0 and mtc0. Add dmfc2 and
281 dmtc2 Octeon instructions.
282
bd2e2557
SS		 2832008-07-07 Stan Shebs <stan@codesourcery.com>
284
285 * dis-init.c (init_disassemble_info): Init endian_code field.
286 * arm-dis.c (print_insn): Disassemble code according to
287 setting of endian_code.
288 (print_insn_big_arm): Detect when BE8 extension flag has been set.
289
6ba2a415
RS		 2902008-06-30 Richard Sandiford <rdsandiford@googlemail.com>
291
292 * mips-dis.c (_print_insn_mips): Use bfd_asymbol_flavour to check
293 for ELF symbols.
294
c8187e15
PB		 2952008-06-25 Peter Bergner <bergner@vnet.ibm.com>
296
297 * ppc-dis.c (powerpc_init_dialect): Handle -M464.
298 (print_ppc_disassembler_options): Likewise.
299 * ppc-opc.c (PPC464): Define.
300 (powerpc_opcodes): Add mfdcrux and mtdcrux.
301
7a283e07
RW		 3022008-06-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
303
304 * configure: Regenerate.
305
fa452fa6
PB		 3062008-06-13 Peter Bergner <bergner@vnet.ibm.com>
307
308 * ppc-dis.c (print_insn_powerpc): Update prototye to use new
309 ppc_cpu_t typedef.
310 (struct dis_private): New.
311 (POWERPC_DIALECT): New define.
312 (powerpc_dialect): Renamed to...
313 (powerpc_init_dialect): This. Update to use ppc_cpu_t and
314 struct dis_private.
315 (print_insn_big_powerpc): Update for using structure in
316 info->private_data.
317 (print_insn_little_powerpc): Likewise.
318 (operand_value_powerpc): Change type of dialect param to ppc_cpu_t.
319 (skip_optional_operands): Likewise.
320 (print_insn_powerpc): Likewise. Remove initialization of dialect.
321 * ppc-opc.c (extract_bat, extract_bba, extract_bdm, extract_bdp,
322 extract_bo, extract_boe, extract_fxm, extract_mb6, extract_mbe,
323 extract_nb, extract_nsi, extract_rbs, extract_sh6, extract_spr,
324 extract_sprg, extract_tbr insert_bat, insert_bba, insert_bdm,
325 insert_bdp, insert_bo, insert_boe, insert_fxm, insert_mb6, insert_mbe,
326 insert_nsi, insert_ral, insert_ram, insert_raq, insert_ras, insert_rbs,
327 insert_sh6, insert_spr, insert_sprg, insert_tbr): Change the dialect
328 param to be of type ppc_cpu_t. Update prototype.
329
bb35fb24
NC		 3302008-06-12 Adam Nemet <anemet@caviumnetworks.com>
331
332 * mips-dis.c (print_insn_args): Handle field descriptors +x, +p,
333 +s, +S.
334 * mips-opc.c (mips_builtin_opcodes): Add Octeon instructions
335 baddu, bbit*, cins*, dmul, pop, dpop, exts*, mtm*, mtp*, syncs,
336 syncw, syncws, vm3mulu, vm0 and vmulu.
337
dd3cbb7e
NC		 338 * mips-dis.c (print_insn_args): Handle field descriptor +Q.
339 * mips-opc.c (mips_builtin_opcodes): Add Octeon instructions seq,
340 seqi, sne and snei.
341
a5dabbb0
L		 3422008-05-30 H.J. Lu <hongjiu.lu@intel.com>
343
344 * i386-opc.tbl: Add vmovd with 64bit operand.
345 * i386-tbl.h: Regenerated.
346
725a9891
MS		 3472008-05-27 Martin Schwidefsky <schwidefsky@de.ibm.com>
348
349 * s390-opc.c (INSTR_RRF_R0RR): Fix RRF_R0RR operand format.
350
cbc80391
L		 3512008-05-22 H.J. Lu <hongjiu.lu@intel.com>
352
353 * i386-opc.tbl: Add NoAVX to cvtpd2pi, cvtpi2pd and cvttpd2pi.
354 * i386-tbl.h: Regenerated.
355
116615c5
L		 3562008-05-22 H.J. Lu <hongjiu.lu@intel.com>
357
358 PR gas/6517
359 * i386-opc.tbl: Break cvtsi2ss/cvtsi2sd/vcvtsi2sd/vcvtsi2ss
3c6528a8 360 into 32bit and 64bit. Remove Reg64|Qword and add
116615c5
L		 361 IgnoreSize|No_qSuf on 32bit version.
362 * i386-tbl.h: Regenerated.
363
d9479f2d
L		 3642008-05-21 H.J. Lu <hongjiu.lu@intel.com>
365
366 * i386-opc.tbl: Add NoAVX to movdq2q and movq2dq.
367 * i386-tbl.h: Regenerated.
368
3ce6fddb
NC		 3692008-05-21 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
370
371 * cr16-dis.c (build_mask): Adjust the mask for 32-bit bcond.
372
8944f3c2
AM		 3732008-05-14 Alan Modra <amodra@bigpond.net.au>
374
375 * Makefile.am: Run "make dep-am".
376 * Makefile.in: Regenerate.
377
f1f8f695
L		 3782008-05-02 H.J. Lu <hongjiu.lu@intel.com>
379
380 * i386-dis.c (MOVBE_Fixup): New.
381 (Mo): Likewise.
382 (PREFIX_0F3880): Likewise.
383 (PREFIX_0F3881): Likewise.
384 (PREFIX_0F38F0): Updated.
385 (prefix_table): Add PREFIX_0F3880 and PREFIX_0F3881. Update
386 PREFIX_0F38F0 and PREFIX_0F38F1 for movbe.
387 (three_byte_table): Use PREFIX_0F3880 and PREFIX_0F3881.
388
389 * i386-gen.c (cpu_flag_init): Add CPU_MOVBE_FLAGS and
390 CPU_EPT_FLAGS.
391 (cpu_flags): Add CpuMovbe and CpuEPT.
392
393 * i386-opc.h (CpuMovbe): New.
394 (CpuEPT): Likewise.
395 (CpuLM): Updated.
396 (i386_cpu_flags): Add cpumovbe and cpuept.
397
398 * i386-opc.tbl: Add entries for movbe and EPT instructions.
399 * i386-init.h: Regenerated.
400 * i386-tbl.h: Likewise.
401
89aa3097
AN		 4022008-04-29 Adam Nemet <anemet@caviumnetworks.com>
403
404 * mips-opc.c (mips_builtin_opcodes): Set field `match' to 0 for
405 the two drem and the two dremu macros.
406
39c5c168
AN		 4072008-04-28 Adam Nemet <anemet@caviumnetworks.com>
408
409 * mips-opc.c (mips_builtin_opcodes): Mark prefx and c1
410 instructions FP_S. Mark l.s, li.s, lwc1, swc1, s.s, trunc.w.s and
411 cop1 macros INSN2_M_FP_S. Mark l.d, li.d, ldc1 and sdc1 macros
412 INSN2_M_FP_D. Mark trunc.w.d macro INSN2_M_FP_S and INSN2_M_FP_D.
413
f04d18b7
DM		 4142008-04-25 David S. Miller <davem@davemloft.net>
415
416 * sparc-dis.c: Emit %stick instead of %sys_tick, and %stick_cmpr
417 instead of %sys_tick_cmpr, as suggested in architecture manuals.
418
6194aaab
L		 4192008-04-23 Paolo Bonzini <bonzini@gnu.org>
420
421 * aclocal.m4: Regenerate.
422 * configure: Regenerate.
423
1a6b486f
DM		 4242008-04-23 David S. Miller <davem@davemloft.net>
425
426 * sparc-opc.c (asi_table): Add UltraSPARC and Niagara
427 extended values.
428 (prefetch_table): Add missing values.
429
81f8a913
L		 4302008-04-22 H.J. Lu <hongjiu.lu@intel.com>
431
432 * i386-gen.c (opcode_modifiers): Add NoAVX.
433
434 * i386-opc.h (NoAVX): New.
435 (OldGcc): Updated.
436 (i386_opcode_modifier): Add noavx.
437
438 * i386-opc.tbl: Add NoAVX to SSE, SSE2, SSE3 and SSSE3
439 instructions which don't have AVX equivalent.
440 * i386-tbl.h: Regenerated.
441
dae39acc
L		 4422008-04-18 H.J. Lu <hongjiu.lu@intel.com>
443
444 * i386-dis.c (OP_VEX_FMA): New.
445 (OP_EX_VexImmW): Likewise.
446 (VexFMA): Likewise.
447 (Vex128FMA): Likewise.
448 (EXVexImmW): Likewise.
449 (get_vex_imm8): Likewise.
450 (OP_EX_VexReg): Likewise.
451 (vex_i4_done): Renamed to ...
452 (vex_w_done): This.
453 (prefix_table): Replace EXVexW with EXVexImmW on vpermil2ps
454 and vpermil2pd. Replace Vex/Vex128 with VexFMA/Vex128FMA on
455 FMA instructions.
456 (print_insn): Updated.
457 (OP_EX_VexW): Rewrite to swap register in VEX with EX.
458 (OP_REG_VexI4): Check invalid high registers.
459
ce886ab1
DR		 4602008-04-16 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
461 Michael Meissner <michael.meissner@amd.com>
462
463 * i386-opc.tbl: Fix protX to allow memory in the middle operand.
464 * i386-tbl.h: Regenerate from i386-opc.tbl.
8944f3c2 465
19a6653c
AM		 4662008-04-14 Edmar Wienskoski <edmar@freescale.com>
467
468 * ppc-dis.c (powerpc_dialect): Handle "e500mc". Extend "e500" to
469 accept Power E500MC instructions.
470 (print_ppc_disassembler_options): Document -Me500mc.
471 * ppc-opc.c (DUIS, DUI, T): New.
472 (XRT, XRTRA): Likewise.
473 (E500MC): Likewise.
474 (powerpc_opcodes): Add new Power E500MC instructions.
475
112b7c50
AK		 4762008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
477
478 * s390-dis.c (init_disasm): Evaluate disassembler_options.
479 (print_s390_disassembler_options): New function.
480 * disassemble.c (disassembler_usage): Invoke
481 print_s390_disassembler_options.
482
7ff42648
AK		 4832008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
484
485 * s390-mkopc.c (insertExpandedMnemonic): Expand string sizes
486 of local variables used for mnemonic parsing: prefix, suffix and
487 number.
488
45a5551e
AK		 4892008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
490
491 * s390-mkopc.c (s390_cond_ext_format): Add back the mnemonic
492 extensions for conditional jumps (o, p, m, nz, z, nm, np, no).
493 (s390_crb_extensions): New extensions table.
494 (insertExpandedMnemonic): Handle '$' tag.
495 * s390-opc.txt: Remove conditional jump variants which can now
496 be expanded automatically.
497 Replace '*' tag with '$' in the compare and branch instructions.
498
06c8514a
L		 4992008-04-07 H.J. Lu <hongjiu.lu@intel.com>
500
501 * i386-dis.c (PREFIX_VEX_38XX): Add a tab.
502 (PREFIX_VEX_3AXX): Likewis.
503
b122c285
L		 5042008-04-07 H.J. Lu <hongjiu.lu@intel.com>
505
506 * i386-opc.tbl: Remove 4 extra blank lines.
507
594ab6a3
L		 5082008-04-04 H.J. Lu <hongjiu.lu@intel.com>
509
510 * i386-gen.c (cpu_flag_init): Replace CPU_CLMUL_FLAGS/CpuCLMUL
511 with CPU_PCLMUL_FLAGS/CpuPCLMUL.
512 (cpu_flags): Replace CpuCLMUL with CpuPCLMUL.
513 * i386-opc.tbl: Likewise.
514
515 * i386-opc.h (CpuCLMUL): Renamed to ...
516 (CpuPCLMUL): This.
517 (CpuFMA): Updated.
518 (i386_cpu_flags): Replace cpuclmul with cpupclmul.
519
520 * i386-init.h: Regenerated.
521
c0f3af97
L		 5222008-04-03 H.J. Lu <hongjiu.lu@intel.com>
523
524 * i386-dis.c (OP_E_register): New.
525 (OP_E_memory): Likewise.
526 (OP_VEX): Likewise.
527 (OP_EX_Vex): Likewise.
528 (OP_EX_VexW): Likewise.
529 (OP_XMM_Vex): Likewise.
530 (OP_XMM_VexW): Likewise.
531 (OP_REG_VexI4): Likewise.
532 (PCLMUL_Fixup): Likewise.
533 (VEXI4_Fixup): Likewise.
534 (VZERO_Fixup): Likewise.
535 (VCMP_Fixup): Likewise.
536 (VPERMIL2_Fixup): Likewise.
537 (rex_original): Likewise.
538 (rex_ignored): Likewise.
539 (Mxmm): Likewise.
540 (XMM): Likewise.
541 (EXxmm): Likewise.
542 (EXxmmq): Likewise.
543 (EXymmq): Likewise.
544 (Vex): Likewise.
545 (Vex128): Likewise.
546 (Vex256): Likewise.
547 (VexI4): Likewise.
548 (EXdVex): Likewise.
549 (EXqVex): Likewise.
550 (EXVexW): Likewise.
551 (EXdVexW): Likewise.
552 (EXqVexW): Likewise.
553 (XMVex): Likewise.
554 (XMVexW): Likewise.
555 (XMVexI4): Likewise.
556 (PCLMUL): Likewise.
557 (VZERO): Likewise.
558 (VCMP): Likewise.
559 (VPERMIL2): Likewise.
560 (xmm_mode): Likewise.
561 (xmmq_mode): Likewise.
562 (ymmq_mode): Likewise.
563 (vex_mode): Likewise.
564 (vex128_mode): Likewise.
565 (vex256_mode): Likewise.
566 (USE_VEX_C4_TABLE): Likewise.
567 (USE_VEX_C5_TABLE): Likewise.
568 (USE_VEX_LEN_TABLE): Likewise.
569 (VEX_C4_TABLE): Likewise.
570 (VEX_C5_TABLE): Likewise.
571 (VEX_LEN_TABLE): Likewise.
572 (REG_VEX_XX): Likewise.
573 (MOD_VEX_XXX): Likewise.
574 (PREFIX_0F38DB..PREFIX_0F38DF): Likewise.
575 (PREFIX_0F3A44): Likewise.
576 (PREFIX_0F3ADF): Likewise.
577 (PREFIX_VEX_XXX): Likewise.
578 (VEX_OF): Likewise.
579 (VEX_OF38): Likewise.
580 (VEX_OF3A): Likewise.
581 (VEX_LEN_XXX): Likewise.
582 (vex): Likewise.
583 (need_vex): Likewise.
584 (need_vex_reg): Likewise.
585 (vex_i4_done): Likewise.
586 (vex_table): Likewise.
587 (vex_len_table): Likewise.
588 (OP_REG_VexI4): Likewise.
589 (vex_cmp_op): Likewise.
590 (pclmul_op): Likewise.
591 (vpermil2_op): Likewise.
592 (m_mode): Updated.
593 (es_reg): Likewise.
594 (PREFIX_0F38F0): Likewise.
595 (PREFIX_0F3A60): Likewise.
596 (reg_table): Add REG_VEX_71...REG_VEX_73 and REG_VEX_AE.
597 (prefix_table): Add PREFIX_0F38DB..PREFIX_0F38DF, PREFIX_0F3ADF
598 and PREFIX_VEX_XXX entries.
599 (x86_64_table): Use VEX_C4_TABLE and VEX_C5_TABLE.
600 (three_byte_table): Use PREFIX_0F38DB..PREFIX_0F38DF and
601 PREFIX_0F3ADF.
602 (mod_table): Use VEX_C4_TABLE, VEX_C5_TABLE and VEX_LEN_TABLE.
603 Add MOD_VEX_XXX entries.
604 (ckprefix): Initialize rex_original and rex_ignored. Store the
605 REX byte in rex_original.
606 (get_valid_dis386): Handle the implicit prefix in VEX prefix
607 bytes and USE_VEX_LEN_TABLE/USE_VEX_C4_TABLE/USE_VEX_C5_TABLE.
608 (print_insn): Set need_vex/need_vex_reg/vex_i4_done to 0 before
609 calling get_valid_dis386. Use rex_original and rex_ignored when
610 printing out REX.
611 (putop): Handle "XY".
612 (intel_operand_size): Handle VEX, xmm_mode, xmmq_mode and
613 ymmq_mode.
614 (OP_E_extended): Updated to use OP_E_register and
615 OP_E_memory.
616 (OP_XMM): Handle VEX.
617 (OP_EX): Likewise.
618 (XMM_Fixup): Likewise.
619 (CMP_Fixup): Use ARRAY_SIZE.
620
621 * i386-gen.c (cpu_flag_init): Add CpuAES, CPU_CLMUL_FLAGS,
622 CPU_FMA_FLAGS and CPU_AVX_FLAGS.
623 (operand_type_init): Add OPERAND_TYPE_REGYMM and
624 OPERAND_TYPE_VEX_IMM4.
625 (cpu_flags): Add CpuAVX, CpuAES, CpuCLMUL and CpuFMA.
626 (opcode_modifiers): Add Implicit1stXmm0, Vex, Vex256, VexNDD,
627 VexNDS, VexW0, VexW1, Vex0F, Vex0F38, Vex0F3A, Vex3Sources,
628 VexImmExt and SSE2AVX.
629 (operand_types): Add RegYMM, Ymmword and Vex_Imm4.
630
631 * i386-opc.h (CpuAVX): New.
632 (CpuAES): Likewise.
633 (CpuCLMUL): Likewise.
634 (CpuFMA): Likewise.
635 (Vex): Likewise.
636 (Vex256): Likewise.
637 (VexNDS): Likewise.
638 (VexNDD): Likewise.
639 (VexW0): Likewise.
640 (VexW1): Likewise.
641 (Vex0F): Likewise.
642 (Vex0F38): Likewise.
643 (Vex0F3A): Likewise.
644 (Vex3Sources): Likewise.
645 (VexImmExt): Likewise.
646 (SSE2AVX): Likewise.
647 (RegYMM): Likewise.
648 (Ymmword): Likewise.
649 (Vex_Imm4): Likewise.
650 (Implicit1stXmm0): Likewise.
651 (CpuXsave): Updated.
652 (CpuLM): Likewise.
653 (ByteOkIntel): Likewise.
654 (OldGcc): Likewise.
655 (Control): Likewise.
656 (Unspecified): Likewise.
657 (OTMax): Likewise.
658 (i386_cpu_flags): Add cpuavx, cpuaes, cpuclmul and cpufma.
659 (i386_opcode_modifier): Add implicit1stxmm0, vex, vex256,
660 vexnds, vexndd, vexw0, vexw1, vex0f, vex0f38, vex0f3a,
661 vex3sources, veximmext and sse2avx.
662 (i386_operand_type): Add regymm, ymmword and vex_imm4.
663
664 * i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions.
665
666 * i386-reg.tbl: Add AVX registers, ymm0..ymm15.
667
668 * i386-init.h: Regenerated.
669 * i386-tbl.h: Likewise.
670
b21c9cb4
BS		 6712008-03-26 Bernd Schmidt <bernd.schmidt@analog.com>
672
673 From Robin Getz <robin.getz@analog.com>
674 * bfin-dis.c (bu32): Typedef.
675 (enum const_forms_t): Add c_uimm32 and c_huimm32.
676 (constant_formats[]): Add uimm32 and huimm16.
677 (fmtconst_val): New.
678 (uimm32): Define.
679 (huimm32): Define.
680 (imm16_val): Define.
681 (luimm16_val): Define.
682 (struct saved_state): Define.
683 (GREG, DPREG, DREG, PREG, SPREG, FPREG, IREG, MREG, BREG, LREG,
684 A0XREG, A0WREG, A1XREG, A1WREG,CCREG, LC0REG, LT0REG, LB0REG,
685 LC1REG, LT1REG, LB1REG, RETSREG, PCREG): Define.
686 (get_allreg): New.
687 (decode_LDIMMhalf_0): Print out the whole register value.
688
ee171c8f
BS		 689 From Jie Zhang <jie.zhang@analog.com>
690 * bfin-dis.c (decode_dsp32mac_0): Decode (IU) option for
691 multiply and multiply-accumulate to data register instruction.
692
086134ec
BS		 693 * bfin-dis.c: (c_uimm4s4d, c_imm5d, c_imm7d, c_imm16d, c_uimm16s4d,
694 c_imm32, c_huimm32e): Define.
695 (constant_formats): Add flags for printing decimal, leading spaces, and
696 exact symbols.
697 (comment, parallel): Add global flags in all disassembly.
698 (fmtconst): Take advantage of new flags, and print default in hex.
699 (fmtconst_val): Likewise.
700 (decode_macfunc): Be consistant with spaces, tabs, comments,
701 capitalization in disassembly, fix minor coding style issues.
702 (reg_names, amod0, amod1, amod0amod2, aligndir, get_allreg): Likewise.
703 (decode_ProgCtrl_0, decode_PushPopMultiple_0, decode_CCflag_0,
704 decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0,
705 decode_REGMV_0, decode_ALU2op_0, decode_PTR2op_0, decode_LOGI2op_0,
706 decode_COMP3op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
707 decode_LDSTpmod_0, decode_dagMODim_0, decode_dagMODik_0,
708 decode_dspLDST_0, decode_LDST_0, decode_LDSTiiFP_0, decode_LDSTii_0,
709 decode_LoopSetup_0, decode_LDIMMhalf_0, decode_CALLa_0,
710 decode_LDSTidxI_0, decode_linkage_0, decode_dsp32alu_0,
711 decode_dsp32shift_0, decode_dsp32shiftimm_0, decode_pseudodbg_assert_0,
712 _print_insn_bfin, print_insn_bfin): Likewise.
713
58c85be7
RW		 7142008-03-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
715
716 * aclocal.m4: Regenerate.
717 * configure: Likewise.
718 * Makefile.in: Likewise.
719
50e7d84b
AM		 7202008-03-13 Alan Modra <amodra@bigpond.net.au>
721
722 * Makefile.am: Run "make dep-am".
723 * Makefile.in: Regenerate.
724 * configure: Regenerate.
725
de866fcc
AM		 7262008-03-07 Alan Modra <amodra@bigpond.net.au>
727
728 * ppc-opc.c (powerpc_opcodes): Order and format.
729
28dbc079
L		 7302008-03-01 H.J. Lu <hongjiu.lu@intel.com>
731
732 * i386-opc.tbl: Allow 16-bit near indirect branches for x86-64.
733 * i386-tbl.h: Regenerated.
734
849830bd
L		 7352008-02-23 H.J. Lu <hongjiu.lu@intel.com>
736
737 * i386-opc.tbl: Disallow 16-bit near indirect branches for
738 x86-64.
739 * i386-tbl.h: Regenerated.
740
743ddb6b
JB		 7412008-02-21 Jan Beulich <jbeulich@novell.com>
742
743 * i386-opc.tbl: Allow Dword for far indirect call. Allow Dword
744 and Fword for far indirect jmp. Allow Reg16 and Word for near
745 indirect jmp on x86-64. Disallow Fword for lcall.
746 * i386-tbl.h: Re-generate.
747
796d5313
NC		 7482008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
749
750 * cr16-opc.c (cr16_num_optab): Defined
751
65da13b5
L		 7522008-02-16 H.J. Lu <hongjiu.lu@intel.com>
753
754 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_INOUTPORTREG.
755 * i386-init.h: Regenerated.
756
0e336180
NC		 7572008-02-14 Nick Clifton <nickc@redhat.com>
758
759 PR binutils/5524
760 * configure.in (SHARED_LIBADD): Select the correct host specific
761 file extension for shared libraries.
762 * configure: Regenerate.
763
b7240065
JB		 7642008-02-13 Jan Beulich <jbeulich@novell.com>
765
766 * i386-opc.h (RegFlat): New.
767 * i386-reg.tbl (flat): Add.
768 * i386-tbl.h: Re-generate.
769
34b772a6
JB		 7702008-02-13 Jan Beulich <jbeulich@novell.com>
771
772 * i386-dis.c (a_mode): New.
773 (cond_jump_mode): Adjust.
774 (Ma): Change to a_mode.
775 (intel_operand_size): Handle a_mode.
776 * i386-opc.tbl: Allow Dword and Qword for bound.
777 * i386-tbl.h: Re-generate.
778
a60de03c
JB		 7792008-02-13 Jan Beulich <jbeulich@novell.com>
780
781 * i386-gen.c (process_i386_registers): Process new fields.
782 * i386-opc.h (reg_entry): Shrink reg_flags and reg_num to
783 unsigned char. Add dw2_regnum and Dw2Inval.
784 * i386-reg.tbl: Provide initializers for dw2_regnum. Add pseudo
785 register names.
786 * i386-tbl.h: Re-generate.
787
f03fe4c1
L		 7882008-02-11 H.J. Lu <hongjiu.lu@intel.com>
789
4b6bc8eb 790 * i386-gen.c (cpu_flag_init): Add CPU_XSAVE_FLAGS.
f03fe4c1
L		 791 * i386-init.h: Updated.
792
475a2301
L		 7932008-02-11 H.J. Lu <hongjiu.lu@intel.com>
794
795 * i386-gen.c (cpu_flags): Add CpuXsave.
796
797 * i386-opc.h (CpuXsave): New.
4b6bc8eb 798 (CpuLM): Updated.
475a2301
L		 799 (i386_cpu_flags): Add cpuxsave.
800
801 * i386-dis.c (MOD_0FAE_REG_4): New.
802 (RM_0F01_REG_2): Likewise.
803 (MOD_0FAE_REG_5): Updated.
804 (RM_0F01_REG_3): Likewise.
805 (reg_table): Use MOD_0FAE_REG_4.
806 (mod_table): Use RM_0F01_REG_2. Add MOD_0FAE_REG_4. Updated
807 for xrstor.
808 (rm_table): Add RM_0F01_REG_2.
809
810 * i386-opc.tbl: Add xsave, xrstor, xgetbv and xsetbv.
811 * i386-init.h: Regenerated.
812 * i386-tbl.h: Likewise.
813
595785c6 8142008-02-11 Jan Beulich <jbeulich@novell.com>
041179fc 815
595785c6
JB		 816 * i386-opc.tbl: Remove Disp32S from CpuNo64 opcodes. Remove
817 Disp16 from Cpu64 non-jump opcodes (including loop and j?cxz).
818 * i386-tbl.h: Re-generate.
819
bb8541b9
L		 8202008-02-04 H.J. Lu <hongjiu.lu@intel.com>
821
822 PR 5715
823 * configure: Regenerated.
824
57b592a3
AN		 8252008-02-04 Adam Nemet <anemet@caviumnetworks.com>
826
827 * mips-dis.c: Update copyright.
828 (mips_arch_choices): Add Octeon.
829 * mips-opc.c: Update copyright.
830 (IOCT): New macro.
831 (mips_builtin_opcodes): Add Octeon instruction synciobdma.
832
930bb4cf
AM		 8332008-01-29 Alan Modra <amodra@bigpond.net.au>
834
835 * ppc-opc.c: Support optional L form mtmsr.
836
82c18208
L		 8372008-01-24 H.J. Lu <hongjiu.lu@intel.com>
838
839 * i386-dis.c (OP_E_extended): Handle r12 like rsp.
840
599121aa
L		 8412008-01-23 H.J. Lu <hongjiu.lu@intel.com>
842
843 * i386-gen.c (cpu_flag_init): Add CpuLM to CPU_GENERIC64_FLAGS.
844 * i386-init.h: Regenerated.
845
80098f51
TG		 8462008-01-23 Tristan Gingold <gingold@adacore.com>
847
848 * ia64-dis.c (print_insn_ia64): Display symbolic name of ar.fcr,
849 ar.eflag, ar.csd, ar.ssd, ar.cflg, ar.fsr, ar.fir and ar.fdr.
850
115c7c25
L		 8512008-01-22 H.J. Lu <hongjiu.lu@intel.com>
852
853 * i386-gen.c (cpu_flag_init): Remove CpuMMX2.
854 (cpu_flags): Likewise.
855
856 * i386-opc.h (CpuMMX2): Removed.
857 (CpuSSE): Updated.
858
859 * i386-opc.tbl: Replace CpuMMX2 with CpuSSE|Cpu3dnowA.
860 * i386-init.h: Regenerated.
861 * i386-tbl.h: Likewise.
862
6305a203
L		 8632008-01-22 H.J. Lu <hongjiu.lu@intel.com>
864
865 * i386-gen.c (cpu_flag_init): Add CPU_VMX_FLAGS and
866 CPU_SMX_FLAGS.
867 * i386-init.h: Regenerated.
868
fd07a1c8
L		 8692008-01-15 H.J. Lu <hongjiu.lu@intel.com>
870
871 * i386-opc.tbl: Use Qword on movddup.
872 * i386-tbl.h: Regenerated.
873
321fd21e
L		 8742008-01-15 H.J. Lu <hongjiu.lu@intel.com>
875
876 * i386-opc.tbl: Put back 16bit movsx/movzx for AT&T syntax.
877 * i386-tbl.h: Regenerated.
878
4ee52178
L		 8792008-01-15 H.J. Lu <hongjiu.lu@intel.com>
880
881 * i386-dis.c (Mx): New.
882 (PREFIX_0FC3): Likewise.
883 (PREFIX_0FC7_REG_6): Updated.
884 (dis386_twobyte): Use PREFIX_0FC3.
885 (prefix_table): Add PREFIX_0FC3. Use Mq on movntq and movntsd.
886 Use Mx on movntps, movntpd, movntdq and movntdqa. Use Md on
887 movntss.
888
5c07affc
L		 8892008-01-14 H.J. Lu <hongjiu.lu@intel.com>
890
891 * i386-gen.c (opcode_modifiers): Add IntelSyntax.
892 (operand_types): Add Mem.
893
894 * i386-opc.h (IntelSyntax): New.
895 * i386-opc.h (Mem): New.
896 (Byte): Updated.
897 (Opcode_Modifier_Max): Updated.
898 (i386_opcode_modifier): Add intelsyntax.
899 (i386_operand_type): Add mem.
900
901 * i386-opc.tbl: Remove Reg16 from movnti. Add sizes to more
902 instructions.
903
904 * i386-reg.tbl: Add size for accumulator.
905
906 * i386-init.h: Regenerated.
907 * i386-tbl.h: Likewise.
908
0d6a2f58
L		 9092008-01-13 H.J. Lu <hongjiu.lu@intel.com>
910
911 * i386-opc.h (Byte): Fix a typo.
912
7d5e4556
L		 9132008-01-12 H.J. Lu <hongjiu.lu@intel.com>
914
915 PR gas/5534
916 * i386-gen.c (operand_type_init): Add Dword to
917 OPERAND_TYPE_ACC32. Add Qword to OPERAND_TYPE_ACC64.
918 (opcode_modifiers): Remove CheckSize, Byte, Word, Dword,
919 Qword and Xmmword.
920 (operand_types): Add Byte, Word, Dword, Fword, Qword, Tbyte,
921 Xmmword, Unspecified and Anysize.
922 (set_bitfield): Make Mmword an alias of Qword. Make Oword
923 an alias of Xmmword.
924
925 * i386-opc.h (CheckSize): Removed.
926 (Byte): Updated.
927 (Word): Likewise.
928 (Dword): Likewise.
929 (Qword): Likewise.
930 (Xmmword): Likewise.
931 (FWait): Updated.
932 (OTMax): Likewise.
933 (i386_opcode_modifier): Remove checksize, byte, word, dword,
934 qword and xmmword.
935 (Fword): New.
936 (TBYTE): Likewise.
937 (Unspecified): Likewise.
938 (Anysize): Likewise.
939 (i386_operand_type): Add byte, word, dword, fword, qword,
940 tbyte xmmword, unspecified and anysize.
941
942 * i386-opc.tbl: Updated to use Byte, Word, Dword, Fword, Qword,
943 Tbyte, Xmmword, Unspecified and Anysize.
944
945 * i386-reg.tbl: Add size for accumulator.
946
947 * i386-init.h: Regenerated.
948 * i386-tbl.h: Likewise.
949
b5b1fc4f
L		 9502008-01-10 H.J. Lu <hongjiu.lu@intel.com>
951
952 * i386-dis.c (REG_0F0E): Renamed to REG_0F0D.
953 (REG_0F18): Updated.
954 (reg_table): Updated.
955 (dis386_twobyte): Updated. Use "nopQ" on 0x19 to 0x1e.
956 (twobyte_has_modrm): Set 1 for 0x19 to 0x1e.
957
50e8458f
L		 9582008-01-08 H.J. Lu <hongjiu.lu@intel.com>
959
960 * i386-gen.c (set_bitfield): Use fail () on error.
961
3d4d5afa
L		 9622008-01-08 H.J. Lu <hongjiu.lu@intel.com>
963
964 * i386-gen.c (lineno): New.
965 (filename): Likewise.
966 (set_bitfield): Report filename and line numer on error.
967 (process_i386_opcodes): Set filename and update lineno.
968 (process_i386_registers): Likewise.
969
e1d4d893
L		 9702008-01-05 H.J. Lu <hongjiu.lu@intel.com>
971
972 * i386-gen.c (opcode_modifiers): Rename IntelMnemonic to
973 ATTSyntax.
974
975 * i386-opc.h (IntelMnemonic): Renamed to ..
976 (ATTSyntax): This
977 (Opcode_Modifier_Max): Updated.
978 (i386_opcode_modifier): Remove intelmnemonic. Add attsyntax
979 and intelsyntax.
980
8944f3c2 981 * i386-opc.tbl: Remove IntelMnemonic and update with ATTSyntax
e1d4d893
L		 982 on fsub, fubp, fsubr, fsubrp, div, fdivp, fdivr and fdivrp.
983 * i386-tbl.h: Regenerated.
984
6f143e4d
L		 9852008-01-04 H.J. Lu <hongjiu.lu@intel.com>
986
987 * i386-gen.c: Update copyright to 2008.
988 * i386-opc.h: Likewise.
989 * i386-opc.tbl: Likewise.
990
991 * i386-init.h: Regenerated.
992 * i386-tbl.h: Likewise.
993
c6add537
L		 9942008-01-04 H.J. Lu <hongjiu.lu@intel.com>
995
996 * i386-opc.tbl: Add NoRex64 to extractps, movmskpd, movmskps,
997 pextrb, pextrw, pinsrb, pinsrw and pmovmskb.
998 * i386-tbl.h: Regenerated.
999
3629bb00
L		 10002008-01-03 H.J. Lu <hongjiu.lu@intel.com>
1001
1002 * i386-gen.c (cpu_flag_init): Remove CpuSSE4_1_Or_5 and
1003 CpuSSE4_2_Or_ABM.
1004 (cpu_flags): Likewise.
1005
1006 * i386-opc.h (CpuSSE4_1_Or_5): Removed.
1007 (CpuSSE4_2_Or_ABM): Likewise.
1008 (CpuLM): Updated.
1009 (i386_cpu_flags): Remove cpusse4_1_or_5 and cpusse4_2_or_abm.
1010
1011 * i386-opc.tbl: Replace CpuSSE4_1_Or_5, CpuSSE4_2_Or_ABM and
1012 Cpu686|CpuPadLock with CpuSSE4_1|CpuSSE5, CpuABM|CpuSSE4_2
1013 and CpuPadLock, respectively.
1014 * i386-init.h: Regenerated.
1015 * i386-tbl.h: Likewise.
1016
24995bd6
L		 10172008-01-03 H.J. Lu <hongjiu.lu@intel.com>
1018
1019 * i386-gen.c (opcode_modifiers): Remove No_xSuf.
1020
1021 * i386-opc.h (No_xSuf): Removed.
1022 (CheckSize): Updated.
1023
1024 * i386-tbl.h: Regenerated.
1025
e0329a22
L		 10262008-01-02 H.J. Lu <hongjiu.lu@intel.com>
1027
1028 * i386-gen.c (cpu_flag_init): Add CpuSSE4_2_Or_ABM to
1029 CPU_AMDFAM10_FLAGS, CPU_SSE4_2_FLAGS, CpuABM and
1030 CPU_SSE5_FLAGS.
1031 (cpu_flags): Add CpuSSE4_2_Or_ABM.
1032
1033 * i386-opc.h (CpuSSE4_2_Or_ABM): New.
1034 (CpuLM): Updated.
1035 (i386_cpu_flags): Add cpusse4_2_or_abm.
1036
1037 * i386-opc.tbl: Use CpuSSE4_2_Or_ABM instead of
1038 CpuABM|CpuSSE4_2 on popcnt.
1039 * i386-init.h: Regenerated.
1040 * i386-tbl.h: Likewise.
1041
f2a9c676
L		 10422008-01-02 H.J. Lu <hongjiu.lu@intel.com>
1043
1044 * i386-opc.h: Update comments.
1045
d978b5be
L		 10462008-01-02 H.J. Lu <hongjiu.lu@intel.com>
1047
1048 * i386-gen.c (opcode_modifiers): Use Qword instead of QWord.
1049 * i386-opc.h: Likewise.
1050 * i386-opc.tbl: Likewise.
1051
582d5edd
L		 10522008-01-02 H.J. Lu <hongjiu.lu@intel.com>
1053
1054 PR gas/5534
1055 * i386-gen.c (opcode_modifiers): Add No_xSuf, CheckSize,
1056 Byte, Word, Dword, QWord and Xmmword.
1057
1058 * i386-opc.h (No_xSuf): New.
1059 (CheckSize): Likewise.
1060 (Byte): Likewise.
1061 (Word): Likewise.
1062 (Dword): Likewise.
1063 (QWord): Likewise.
1064 (Xmmword): Likewise.
1065 (FWait): Updated.
1066 (i386_opcode_modifier): Add No_xSuf, CheckSize, Byte, Word,
1067 Dword, QWord and Xmmword.
1068
1069 * i386-opc.tbl: Add CheckSize|QWord to movq if IgnoreSize is
1070 used.
1071 * i386-tbl.h: Regenerated.
1072
3fe15143
MK		 10732008-01-02 Mark Kettenis <kettenis@gnu.org>
1074
1075 * m88k-dis.c (instructions): Fix fcvt.* instructions.
1076 From Miod Vallat.
1077
6c7ac64e 1078For older changes see ChangeLog-2007
252b5132
RH		 1079\f
1080Local Variables:
2f6d2f85
NC		 1081mode: change-log
1082left-margin: 8
1083fill-column: 74
252b5132
RH		 1084version-control: never
1085End:
GDB Binutils - Deliverables
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