[deliverable/binutils-gdb.git] / opcodes / ChangeLog

2008-04-07  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.tbl: Remove 4 extra blank lines.

2008-04-04  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (cpu_flag_init): Replace CPU_CLMUL_FLAGS/CpuCLMUL
	with CPU_PCLMUL_FLAGS/CpuPCLMUL.
	(cpu_flags): Replace CpuCLMUL with CpuPCLMUL.
	* i386-opc.tbl: Likewise.

	* i386-opc.h (CpuCLMUL): Renamed to ...
	(CpuPCLMUL): This.
	(CpuFMA): Updated.
	(i386_cpu_flags): Replace cpuclmul with cpupclmul.

	* i386-init.h: Regenerated.

2008-04-03  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (OP_E_register): New.
	(OP_E_memory): Likewise.
	(OP_VEX): Likewise.
	(OP_EX_Vex): Likewise.
	(OP_EX_VexW): Likewise.
	(OP_XMM_Vex): Likewise.
	(OP_XMM_VexW): Likewise.
	(OP_REG_VexI4): Likewise.
	(PCLMUL_Fixup): Likewise.
	(VEXI4_Fixup): Likewise.
	(VZERO_Fixup): Likewise.
	(VCMP_Fixup): Likewise.
	(VPERMIL2_Fixup): Likewise.
	(rex_original): Likewise.
	(rex_ignored): Likewise.
	(Mxmm): Likewise.
	(XMM): Likewise.
	(EXxmm): Likewise.
	(EXxmmq): Likewise.
	(EXymmq): Likewise.
	(Vex): Likewise.
	(Vex128): Likewise.
	(Vex256): Likewise.
	(VexI4): Likewise.
	(EXdVex): Likewise.
	(EXqVex): Likewise.
	(EXVexW): Likewise.
	(EXdVexW): Likewise.
	(EXqVexW): Likewise.
	(XMVex): Likewise.
	(XMVexW): Likewise.
	(XMVexI4): Likewise.
	(PCLMUL): Likewise.
	(VZERO): Likewise.
	(VCMP): Likewise.
	(VPERMIL2): Likewise.
	(xmm_mode): Likewise.
	(xmmq_mode): Likewise.
	(ymmq_mode): Likewise.
	(vex_mode): Likewise.
	(vex128_mode): Likewise.
	(vex256_mode): Likewise.
	(USE_VEX_C4_TABLE): Likewise.
	(USE_VEX_C5_TABLE): Likewise.
	(USE_VEX_LEN_TABLE): Likewise.
	(VEX_C4_TABLE): Likewise.
	(VEX_C5_TABLE): Likewise.
	(VEX_LEN_TABLE): Likewise.
	(REG_VEX_XX): Likewise.
	(MOD_VEX_XXX): Likewise.
	(PREFIX_0F38DB..PREFIX_0F38DF): Likewise.
	(PREFIX_0F3A44): Likewise.
	(PREFIX_0F3ADF): Likewise.
	(PREFIX_VEX_XXX): Likewise.
	(VEX_OF): Likewise.
	(VEX_OF38): Likewise.
	(VEX_OF3A): Likewise.
	(VEX_LEN_XXX): Likewise.
	(vex): Likewise.
	(need_vex): Likewise.
	(need_vex_reg): Likewise.
	(vex_i4_done): Likewise.
	(vex_table): Likewise.
	(vex_len_table): Likewise.
	(OP_REG_VexI4): Likewise.
	(vex_cmp_op): Likewise.
	(pclmul_op): Likewise.
	(vpermil2_op): Likewise.
	(m_mode): Updated.
	(es_reg): Likewise.
	(PREFIX_0F38F0): Likewise.
	(PREFIX_0F3A60): Likewise.
	(reg_table): Add REG_VEX_71...REG_VEX_73 and REG_VEX_AE.
	(prefix_table): Add PREFIX_0F38DB..PREFIX_0F38DF, PREFIX_0F3ADF
	and PREFIX_VEX_XXX entries.
	(x86_64_table): Use VEX_C4_TABLE and VEX_C5_TABLE.
	(three_byte_table): Use PREFIX_0F38DB..PREFIX_0F38DF and
	PREFIX_0F3ADF.
	(mod_table): Use VEX_C4_TABLE, VEX_C5_TABLE and VEX_LEN_TABLE.
	Add MOD_VEX_XXX entries.
	(ckprefix): Initialize rex_original and rex_ignored.  Store the
	REX byte in rex_original.
	(get_valid_dis386): Handle the implicit prefix in VEX prefix
	bytes and USE_VEX_LEN_TABLE/USE_VEX_C4_TABLE/USE_VEX_C5_TABLE.
	(print_insn): Set need_vex/need_vex_reg/vex_i4_done to 0 before
	calling get_valid_dis386.  Use rex_original and rex_ignored when
	printing out REX.
	(putop): Handle "XY".
	(intel_operand_size): Handle VEX, xmm_mode, xmmq_mode and
	ymmq_mode.
	(OP_E_extended): Updated to use OP_E_register and
	OP_E_memory.
	(OP_XMM): Handle VEX.
	(OP_EX): Likewise.
	(XMM_Fixup): Likewise.
	(CMP_Fixup): Use ARRAY_SIZE.

	* i386-gen.c (cpu_flag_init): Add CpuAES, CPU_CLMUL_FLAGS,
	CPU_FMA_FLAGS and CPU_AVX_FLAGS.
	(operand_type_init): Add OPERAND_TYPE_REGYMM and
	OPERAND_TYPE_VEX_IMM4.
	(cpu_flags): Add CpuAVX, CpuAES, CpuCLMUL and CpuFMA.
	(opcode_modifiers): Add Implicit1stXmm0, Vex, Vex256, VexNDD,
	VexNDS, VexW0, VexW1, Vex0F, Vex0F38, Vex0F3A, Vex3Sources,
	VexImmExt and SSE2AVX.
	(operand_types): Add RegYMM, Ymmword and Vex_Imm4.

	* i386-opc.h (CpuAVX): New.
	(CpuAES): Likewise.
	(CpuCLMUL): Likewise.
	(CpuFMA): Likewise.
	(Vex): Likewise.
	(Vex256): Likewise.
	(VexNDS): Likewise.
	(VexNDD): Likewise.
	(VexW0): Likewise.
	(VexW1): Likewise.
	(Vex0F): Likewise.
	(Vex0F38): Likewise.
	(Vex0F3A): Likewise.
	(Vex3Sources): Likewise.
	(VexImmExt): Likewise.
	(SSE2AVX): Likewise.
	(RegYMM): Likewise.
	(Ymmword): Likewise.
	(Vex_Imm4): Likewise.
	(Implicit1stXmm0): Likewise.
	(CpuXsave): Updated.
	(CpuLM): Likewise.
	(ByteOkIntel): Likewise.
	(OldGcc): Likewise.
	(Control): Likewise.
	(Unspecified): Likewise.
	(OTMax): Likewise.
	(i386_cpu_flags): Add cpuavx, cpuaes, cpuclmul and cpufma.
	(i386_opcode_modifier): Add implicit1stxmm0, vex, vex256,
	vexnds, vexndd, vexw0, vexw1, vex0f, vex0f38, vex0f3a,
	vex3sources, veximmext and sse2avx.
	(i386_operand_type): Add regymm, ymmword and vex_imm4.

	* i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions.

	* i386-reg.tbl: Add AVX registers, ymm0..ymm15.

	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2008-03-26  Bernd Schmidt  <bernd.schmidt@analog.com>

	From  Robin Getz  <robin.getz@analog.com>
	* bfin-dis.c (bu32): Typedef.
	(enum const_forms_t): Add c_uimm32 and c_huimm32.
	(constant_formats[]): Add uimm32 and huimm16.
	(fmtconst_val): New.
	(uimm32): Define.
	(huimm32): Define.
	(imm16_val): Define.
	(luimm16_val): Define.
	(struct saved_state): Define.
	(GREG, DPREG, DREG, PREG, SPREG, FPREG, IREG, MREG, BREG, LREG,
	A0XREG, A0WREG, A1XREG, A1WREG,CCREG, LC0REG, LT0REG, LB0REG,
	LC1REG, LT1REG, LB1REG, RETSREG, PCREG): Define.
	(get_allreg): New.
	(decode_LDIMMhalf_0): Print out the whole register value.

	From Jie Zhang  <jie.zhang@analog.com>
	* bfin-dis.c (decode_dsp32mac_0): Decode (IU) option for
	multiply and multiply-accumulate to data register instruction.

	* bfin-dis.c: (c_uimm4s4d, c_imm5d, c_imm7d, c_imm16d, c_uimm16s4d,
	c_imm32, c_huimm32e): Define.
	(constant_formats): Add flags for printing decimal, leading spaces, and
	exact symbols.
	(comment, parallel): Add global flags in all disassembly.
	(fmtconst): Take advantage of new flags, and print default in hex.
	(fmtconst_val): Likewise.
	(decode_macfunc): Be consistant with spaces, tabs, comments,
	capitalization in disassembly, fix minor coding style issues.
	(reg_names, amod0, amod1, amod0amod2, aligndir, get_allreg): Likewise.
	(decode_ProgCtrl_0, decode_PushPopMultiple_0, decode_CCflag_0,
	decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0,
	decode_REGMV_0, decode_ALU2op_0, decode_PTR2op_0, decode_LOGI2op_0,
	decode_COMP3op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
	decode_LDSTpmod_0, decode_dagMODim_0, decode_dagMODik_0,
	decode_dspLDST_0, decode_LDST_0, decode_LDSTiiFP_0, decode_LDSTii_0,
	decode_LoopSetup_0, decode_LDIMMhalf_0, decode_CALLa_0,
	decode_LDSTidxI_0, decode_linkage_0, decode_dsp32alu_0,
	decode_dsp32shift_0, decode_dsp32shiftimm_0, decode_pseudodbg_assert_0,
	_print_insn_bfin, print_insn_bfin): Likewise.

2008-03-17  Ralf Wildenhues  <Ralf.Wildenhues@gmx.de>

	* aclocal.m4: Regenerate.
	* configure: Likewise.
	* Makefile.in: Likewise.

2008-03-13  Alan Modra  <amodra@bigpond.net.au>

	* Makefile.am: Run "make dep-am".
	* Makefile.in: Regenerate.
	* configure: Regenerate.

2008-03-07  Alan Modra  <amodra@bigpond.net.au>

	* ppc-opc.c (powerpc_opcodes): Order and format.

2008-03-01  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.tbl: Allow 16-bit near indirect branches for x86-64.
	* i386-tbl.h: Regenerated.

2008-02-23  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.tbl: Disallow 16-bit near indirect branches for
	x86-64.
	* i386-tbl.h: Regenerated.

2008-02-21  Jan Beulich  <jbeulich@novell.com>

	* i386-opc.tbl: Allow Dword for far indirect call. Allow Dword
	and Fword for far indirect jmp. Allow Reg16 and Word for near
	indirect jmp on x86-64. Disallow Fword for lcall.
	* i386-tbl.h: Re-generate.

2008-02-18  M R Swami Reddy <MR.Swami.Reddy@nsc.com>

	* cr16-opc.c  (cr16_num_optab): Defined

2008-02-16  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c  (operand_type_init): Add OPERAND_TYPE_INOUTPORTREG.
	* i386-init.h: Regenerated.

2008-02-14  Nick Clifton  <nickc@redhat.com>

	PR binutils/5524
	* configure.in (SHARED_LIBADD): Select the correct host specific
	file extension for shared libraries.
	* configure: Regenerate.

2008-02-13  Jan Beulich  <jbeulich@novell.com>

	* i386-opc.h (RegFlat): New.
	* i386-reg.tbl (flat): Add.
	* i386-tbl.h: Re-generate.

2008-02-13  Jan Beulich  <jbeulich@novell.com>

	* i386-dis.c (a_mode): New.
	(cond_jump_mode): Adjust.
	(Ma): Change to a_mode.
	(intel_operand_size): Handle a_mode.
	* i386-opc.tbl: Allow Dword and Qword for bound.
	* i386-tbl.h: Re-generate.

2008-02-13  Jan Beulich  <jbeulich@novell.com>

	* i386-gen.c (process_i386_registers): Process new fields.
	* i386-opc.h (reg_entry): Shrink reg_flags and reg_num to
	unsigned char. Add dw2_regnum and Dw2Inval.
	* i386-reg.tbl: Provide initializers for dw2_regnum. Add pseudo
	register names.
	* i386-tbl.h: Re-generate.

2008-02-11  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (cpu_flag_init): Add CPU_XSAVE_FLAGS.
	* i386-init.h: Updated.

2008-02-11  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (cpu_flags): Add CpuXsave.

	* i386-opc.h (CpuXsave): New.
	(CpuLM): Updated.
	(i386_cpu_flags): Add cpuxsave.

	* i386-dis.c (MOD_0FAE_REG_4): New.
	(RM_0F01_REG_2): Likewise.
	(MOD_0FAE_REG_5): Updated.
	(RM_0F01_REG_3): Likewise.
	(reg_table): Use MOD_0FAE_REG_4.
	(mod_table): Use RM_0F01_REG_2.  Add MOD_0FAE_REG_4.  Updated
	for xrstor.
	(rm_table): Add RM_0F01_REG_2.

	* i386-opc.tbl: Add xsave, xrstor, xgetbv and xsetbv.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2008-02-11  Jan Beulich  <jbeulich@novell.com>

	* i386-opc.tbl: Remove Disp32S from CpuNo64 opcodes. Remove
	Disp16 from Cpu64 non-jump opcodes (including loop and j?cxz).
	* i386-tbl.h: Re-generate.

2008-02-04  H.J. Lu  <hongjiu.lu@intel.com>

	PR 5715
	* configure: Regenerated.

2008-02-04  Adam Nemet  <anemet@caviumnetworks.com>

	* mips-dis.c: Update copyright.
	(mips_arch_choices): Add Octeon.
	* mips-opc.c: Update copyright.
	(IOCT): New macro.
	(mips_builtin_opcodes): Add Octeon instruction synciobdma.

2008-01-29  Alan Modra  <amodra@bigpond.net.au>

	* ppc-opc.c: Support optional L form mtmsr.

2008-01-24  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (OP_E_extended): Handle r12 like rsp.

2008-01-23  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (cpu_flag_init): Add CpuLM to CPU_GENERIC64_FLAGS.
	* i386-init.h: Regenerated.

2008-01-23  Tristan Gingold  <gingold@adacore.com>

	* ia64-dis.c (print_insn_ia64): Display symbolic name of ar.fcr,
	ar.eflag, ar.csd, ar.ssd, ar.cflg, ar.fsr, ar.fir and ar.fdr.

2008-01-22  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (cpu_flag_init): Remove CpuMMX2.
	(cpu_flags): Likewise.

	* i386-opc.h (CpuMMX2): Removed.
	(CpuSSE): Updated.

	* i386-opc.tbl: Replace CpuMMX2 with CpuSSE|Cpu3dnowA.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2008-01-22  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (cpu_flag_init): Add CPU_VMX_FLAGS and
	CPU_SMX_FLAGS.
	* i386-init.h: Regenerated.

2008-01-15  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.tbl: Use Qword on movddup.
	* i386-tbl.h: Regenerated.

2008-01-15  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.tbl: Put back 16bit movsx/movzx for AT&T syntax.
	* i386-tbl.h: Regenerated.

2008-01-15  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (Mx): New.
	(PREFIX_0FC3): Likewise.
	(PREFIX_0FC7_REG_6): Updated.
	(dis386_twobyte): Use PREFIX_0FC3.
	(prefix_table): Add PREFIX_0FC3.  Use Mq on movntq and movntsd.
	Use Mx on movntps, movntpd, movntdq and movntdqa.  Use Md on
	movntss.

2008-01-14  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (opcode_modifiers): Add IntelSyntax.
	(operand_types): Add Mem.

	* i386-opc.h (IntelSyntax): New.
	* i386-opc.h (Mem): New.
	(Byte): Updated.
	(Opcode_Modifier_Max): Updated.
	(i386_opcode_modifier): Add intelsyntax.
	(i386_operand_type): Add mem.

	* i386-opc.tbl: Remove Reg16 from movnti.  Add sizes to more
	instructions.

	* i386-reg.tbl: Add size for accumulator.

	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2008-01-13  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.h (Byte): Fix a typo.

2008-01-12  H.J. Lu  <hongjiu.lu@intel.com>

	PR gas/5534
	* i386-gen.c (operand_type_init): Add Dword to
	OPERAND_TYPE_ACC32.  Add Qword to OPERAND_TYPE_ACC64.
	(opcode_modifiers): Remove CheckSize, Byte, Word, Dword,
	Qword and Xmmword.
	(operand_types): Add Byte, Word, Dword, Fword, Qword, Tbyte,
	Xmmword, Unspecified and Anysize.
	(set_bitfield): Make Mmword an alias of Qword.  Make Oword
	an alias of Xmmword.

	* i386-opc.h (CheckSize): Removed.
	(Byte): Updated.
	(Word): Likewise.
	(Dword): Likewise.
	(Qword): Likewise.
	(Xmmword): Likewise.
	(FWait): Updated.
	(OTMax): Likewise.
	(i386_opcode_modifier): Remove checksize, byte, word, dword,
	qword and xmmword.
	(Fword): New.
	(TBYTE): Likewise.
	(Unspecified): Likewise.
	(Anysize): Likewise.
	(i386_operand_type): Add byte, word, dword, fword, qword,
	tbyte xmmword, unspecified and anysize.

	* i386-opc.tbl: Updated to use Byte, Word, Dword, Fword, Qword,
	Tbyte, Xmmword, Unspecified and Anysize.

	* i386-reg.tbl: Add size for accumulator.

	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2008-01-10  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (REG_0F0E): Renamed to REG_0F0D.
	(REG_0F18): Updated.
	(reg_table): Updated.
	(dis386_twobyte): Updated.  Use "nopQ" on 0x19 to 0x1e.
	(twobyte_has_modrm): Set 1 for 0x19 to 0x1e.

2008-01-08  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (set_bitfield): Use fail () on error.

2008-01-08  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (lineno): New.
	(filename): Likewise.
	(set_bitfield): Report filename and line numer on error.
	(process_i386_opcodes): Set filename and update lineno.
	(process_i386_registers): Likewise.

2008-01-05  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (opcode_modifiers): Rename IntelMnemonic to
	ATTSyntax.

	* i386-opc.h (IntelMnemonic): Renamed to ..
	(ATTSyntax): This
	(Opcode_Modifier_Max): Updated.
	(i386_opcode_modifier): Remove intelmnemonic. Add attsyntax
	and intelsyntax.

	* i386-opc.tbl: Remove IntelMnemonic and update with ATTSyntax 
	on fsub, fubp, fsubr, fsubrp, div, fdivp, fdivr and fdivrp.
	* i386-tbl.h: Regenerated.

2008-01-04  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c: Update copyright to 2008.
	* i386-opc.h: Likewise.
	* i386-opc.tbl: Likewise.

	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2008-01-04  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.tbl: Add NoRex64 to extractps, movmskpd, movmskps,
	pextrb, pextrw, pinsrb, pinsrw and pmovmskb.
	* i386-tbl.h: Regenerated.

2008-01-03  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (cpu_flag_init): Remove CpuSSE4_1_Or_5 and
	CpuSSE4_2_Or_ABM.
	(cpu_flags): Likewise.

	* i386-opc.h (CpuSSE4_1_Or_5): Removed.
	(CpuSSE4_2_Or_ABM): Likewise.
	(CpuLM): Updated.
	(i386_cpu_flags): Remove cpusse4_1_or_5 and cpusse4_2_or_abm.

	* i386-opc.tbl: Replace CpuSSE4_1_Or_5, CpuSSE4_2_Or_ABM and
	Cpu686|CpuPadLock with CpuSSE4_1|CpuSSE5, CpuABM|CpuSSE4_2
	and CpuPadLock, respectively.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2008-01-03  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (opcode_modifiers): Remove No_xSuf.

	* i386-opc.h (No_xSuf): Removed.
	(CheckSize): Updated.

	* i386-tbl.h: Regenerated.

2008-01-02  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (cpu_flag_init): Add CpuSSE4_2_Or_ABM to
	CPU_AMDFAM10_FLAGS, CPU_SSE4_2_FLAGS, CpuABM and
	CPU_SSE5_FLAGS.
	(cpu_flags): Add CpuSSE4_2_Or_ABM.

	* i386-opc.h (CpuSSE4_2_Or_ABM): New.
	(CpuLM): Updated.
	(i386_cpu_flags): Add cpusse4_2_or_abm.

	* i386-opc.tbl: Use CpuSSE4_2_Or_ABM instead of
	CpuABM|CpuSSE4_2 on popcnt.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2008-01-02  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.h: Update comments.

2008-01-02  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (opcode_modifiers): Use Qword instead of QWord.
	* i386-opc.h: Likewise.
	* i386-opc.tbl: Likewise.

2008-01-02  H.J. Lu  <hongjiu.lu@intel.com>

	PR gas/5534
	* i386-gen.c (opcode_modifiers): Add No_xSuf, CheckSize,
	Byte, Word, Dword, QWord and Xmmword.

	* i386-opc.h (No_xSuf): New.
	(CheckSize): Likewise.
	(Byte): Likewise.
	(Word): Likewise.
	(Dword): Likewise.
	(QWord): Likewise.
	(Xmmword): Likewise.
	(FWait): Updated.
	(i386_opcode_modifier): Add No_xSuf, CheckSize, Byte, Word,
	Dword, QWord and Xmmword.

	* i386-opc.tbl: Add CheckSize|QWord to movq if IgnoreSize is
	used.
	* i386-tbl.h: Regenerated.

2008-01-02  Mark Kettenis  <kettenis@gnu.org>

	* m88k-dis.c (instructions): Fix fcvt.* instructions.
	From Miod Vallat.

For older changes see ChangeLog-2007
\f
Local Variables:
mode: change-log
left-margin: 8
fill-column: 74
version-control: never
End:
Commit	Line	Data
b122c285 L	1	2008-04-07 H.J. Lu <hongjiu.lu@intel.com>
	2
	3	* i386-opc.tbl: Remove 4 extra blank lines.
	4
594ab6a3 L	5	2008-04-04 H.J. Lu <hongjiu.lu@intel.com>
	6
	7	* i386-gen.c (cpu_flag_init): Replace CPU_CLMUL_FLAGS/CpuCLMUL
	8	with CPU_PCLMUL_FLAGS/CpuPCLMUL.
	9	(cpu_flags): Replace CpuCLMUL with CpuPCLMUL.
	10	* i386-opc.tbl: Likewise.
	11
	12	* i386-opc.h (CpuCLMUL): Renamed to ...
	13	(CpuPCLMUL): This.
	14	(CpuFMA): Updated.
	15	(i386_cpu_flags): Replace cpuclmul with cpupclmul.
	16
	17	* i386-init.h: Regenerated.
	18
c0f3af97 L	19	2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
	20
	21	* i386-dis.c (OP_E_register): New.
	22	(OP_E_memory): Likewise.
	23	(OP_VEX): Likewise.
	24	(OP_EX_Vex): Likewise.
	25	(OP_EX_VexW): Likewise.
	26	(OP_XMM_Vex): Likewise.
	27	(OP_XMM_VexW): Likewise.
	28	(OP_REG_VexI4): Likewise.
	29	(PCLMUL_Fixup): Likewise.
	30	(VEXI4_Fixup): Likewise.
	31	(VZERO_Fixup): Likewise.
	32	(VCMP_Fixup): Likewise.
	33	(VPERMIL2_Fixup): Likewise.
	34	(rex_original): Likewise.
	35	(rex_ignored): Likewise.
	36	(Mxmm): Likewise.
	37	(XMM): Likewise.
	38	(EXxmm): Likewise.
	39	(EXxmmq): Likewise.
	40	(EXymmq): Likewise.
	41	(Vex): Likewise.
	42	(Vex128): Likewise.
	43	(Vex256): Likewise.
	44	(VexI4): Likewise.
	45	(EXdVex): Likewise.
	46	(EXqVex): Likewise.
	47	(EXVexW): Likewise.
	48	(EXdVexW): Likewise.
	49	(EXqVexW): Likewise.
	50	(XMVex): Likewise.
	51	(XMVexW): Likewise.
	52	(XMVexI4): Likewise.
	53	(PCLMUL): Likewise.
	54	(VZERO): Likewise.
	55	(VCMP): Likewise.
	56	(VPERMIL2): Likewise.
	57	(xmm_mode): Likewise.
	58	(xmmq_mode): Likewise.
	59	(ymmq_mode): Likewise.
	60	(vex_mode): Likewise.
	61	(vex128_mode): Likewise.
	62	(vex256_mode): Likewise.
	63	(USE_VEX_C4_TABLE): Likewise.
	64	(USE_VEX_C5_TABLE): Likewise.
	65	(USE_VEX_LEN_TABLE): Likewise.
	66	(VEX_C4_TABLE): Likewise.
	67	(VEX_C5_TABLE): Likewise.
	68	(VEX_LEN_TABLE): Likewise.
	69	(REG_VEX_XX): Likewise.
	70	(MOD_VEX_XXX): Likewise.
	71	(PREFIX_0F38DB..PREFIX_0F38DF): Likewise.
	72	(PREFIX_0F3A44): Likewise.
	73	(PREFIX_0F3ADF): Likewise.
	74	(PREFIX_VEX_XXX): Likewise.
	75	(VEX_OF): Likewise.
	76	(VEX_OF38): Likewise.
	77	(VEX_OF3A): Likewise.
	78	(VEX_LEN_XXX): Likewise.
	79	(vex): Likewise.
	80	(need_vex): Likewise.
	81	(need_vex_reg): Likewise.
	82	(vex_i4_done): Likewise.
83	(vex_table): Likewise.
84	(vex_len_table): Likewise.
85	(OP_REG_VexI4): Likewise.
86	(vex_cmp_op): Likewise.
87	(pclmul_op): Likewise.
88	(vpermil2_op): Likewise.
89	(m_mode): Updated.
90	(es_reg): Likewise.
91	(PREFIX_0F38F0): Likewise.
92	(PREFIX_0F3A60): Likewise.
93	(reg_table): Add REG_VEX_71...REG_VEX_73 and REG_VEX_AE.
94	(prefix_table): Add PREFIX_0F38DB..PREFIX_0F38DF, PREFIX_0F3ADF
95	and PREFIX_VEX_XXX entries.
96	(x86_64_table): Use VEX_C4_TABLE and VEX_C5_TABLE.
97	(three_byte_table): Use PREFIX_0F38DB..PREFIX_0F38DF and
98	PREFIX_0F3ADF.
99	(mod_table): Use VEX_C4_TABLE, VEX_C5_TABLE and VEX_LEN_TABLE.
100	Add MOD_VEX_XXX entries.
101	(ckprefix): Initialize rex_original and rex_ignored. Store the
102	REX byte in rex_original.
103	(get_valid_dis386): Handle the implicit prefix in VEX prefix
104	bytes and USE_VEX_LEN_TABLE/USE_VEX_C4_TABLE/USE_VEX_C5_TABLE.
105	(print_insn): Set need_vex/need_vex_reg/vex_i4_done to 0 before
106	calling get_valid_dis386. Use rex_original and rex_ignored when
107	printing out REX.
108	(putop): Handle "XY".
109	(intel_operand_size): Handle VEX, xmm_mode, xmmq_mode and
110	ymmq_mode.
111	(OP_E_extended): Updated to use OP_E_register and
112	OP_E_memory.
113	(OP_XMM): Handle VEX.
114	(OP_EX): Likewise.
115	(XMM_Fixup): Likewise.
116	(CMP_Fixup): Use ARRAY_SIZE.
117
118	* i386-gen.c (cpu_flag_init): Add CpuAES, CPU_CLMUL_FLAGS,
119	CPU_FMA_FLAGS and CPU_AVX_FLAGS.
120	(operand_type_init): Add OPERAND_TYPE_REGYMM and
121	OPERAND_TYPE_VEX_IMM4.
122	(cpu_flags): Add CpuAVX, CpuAES, CpuCLMUL and CpuFMA.
123	(opcode_modifiers): Add Implicit1stXmm0, Vex, Vex256, VexNDD,
124	VexNDS, VexW0, VexW1, Vex0F, Vex0F38, Vex0F3A, Vex3Sources,
125	VexImmExt and SSE2AVX.
126	(operand_types): Add RegYMM, Ymmword and Vex_Imm4.
127
128	* i386-opc.h (CpuAVX): New.
129	(CpuAES): Likewise.
130	(CpuCLMUL): Likewise.
131	(CpuFMA): Likewise.
132	(Vex): Likewise.
133	(Vex256): Likewise.
134	(VexNDS): Likewise.
135	(VexNDD): Likewise.
136	(VexW0): Likewise.
137	(VexW1): Likewise.
138	(Vex0F): Likewise.
139	(Vex0F38): Likewise.
140	(Vex0F3A): Likewise.
141	(Vex3Sources): Likewise.
142	(VexImmExt): Likewise.
143	(SSE2AVX): Likewise.
144	(RegYMM): Likewise.
145	(Ymmword): Likewise.
146	(Vex_Imm4): Likewise.
147	(Implicit1stXmm0): Likewise.
148	(CpuXsave): Updated.
149	(CpuLM): Likewise.
150	(ByteOkIntel): Likewise.
151	(OldGcc): Likewise.
152	(Control): Likewise.
153	(Unspecified): Likewise.
154	(OTMax): Likewise.
155	(i386_cpu_flags): Add cpuavx, cpuaes, cpuclmul and cpufma.
156	(i386_opcode_modifier): Add implicit1stxmm0, vex, vex256,
157	vexnds, vexndd, vexw0, vexw1, vex0f, vex0f38, vex0f3a,
158	vex3sources, veximmext and sse2avx.
159	(i386_operand_type): Add regymm, ymmword and vex_imm4.
160
161	* i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions.
162
163	* i386-reg.tbl: Add AVX registers, ymm0..ymm15.
164
165	* i386-init.h: Regenerated.
166	* i386-tbl.h: Likewise.
167
b21c9cb4 BS	168	2008-03-26 Bernd Schmidt <bernd.schmidt@analog.com>
	169
	170	From Robin Getz <robin.getz@analog.com>
	171	* bfin-dis.c (bu32): Typedef.
	172	(enum const_forms_t): Add c_uimm32 and c_huimm32.
	173	(constant_formats[]): Add uimm32 and huimm16.
	174	(fmtconst_val): New.
	175	(uimm32): Define.
	176	(huimm32): Define.
	177	(imm16_val): Define.
	178	(luimm16_val): Define.
	179	(struct saved_state): Define.
	180	(GREG, DPREG, DREG, PREG, SPREG, FPREG, IREG, MREG, BREG, LREG,
	181	A0XREG, A0WREG, A1XREG, A1WREG,CCREG, LC0REG, LT0REG, LB0REG,
	182	LC1REG, LT1REG, LB1REG, RETSREG, PCREG): Define.
	183	(get_allreg): New.
	184	(decode_LDIMMhalf_0): Print out the whole register value.
	185
ee171c8f BS	186	From Jie Zhang <jie.zhang@analog.com>
	187	* bfin-dis.c (decode_dsp32mac_0): Decode (IU) option for
	188	multiply and multiply-accumulate to data register instruction.
	189
086134ec BS	190	* bfin-dis.c: (c_uimm4s4d, c_imm5d, c_imm7d, c_imm16d, c_uimm16s4d,
	191	c_imm32, c_huimm32e): Define.
	192	(constant_formats): Add flags for printing decimal, leading spaces, and
	193	exact symbols.
	194	(comment, parallel): Add global flags in all disassembly.
	195	(fmtconst): Take advantage of new flags, and print default in hex.
	196	(fmtconst_val): Likewise.
	197	(decode_macfunc): Be consistant with spaces, tabs, comments,
	198	capitalization in disassembly, fix minor coding style issues.
	199	(reg_names, amod0, amod1, amod0amod2, aligndir, get_allreg): Likewise.
	200	(decode_ProgCtrl_0, decode_PushPopMultiple_0, decode_CCflag_0,
	201	decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0,
	202	decode_REGMV_0, decode_ALU2op_0, decode_PTR2op_0, decode_LOGI2op_0,
	203	decode_COMP3op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
	204	decode_LDSTpmod_0, decode_dagMODim_0, decode_dagMODik_0,
	205	decode_dspLDST_0, decode_LDST_0, decode_LDSTiiFP_0, decode_LDSTii_0,
	206	decode_LoopSetup_0, decode_LDIMMhalf_0, decode_CALLa_0,
	207	decode_LDSTidxI_0, decode_linkage_0, decode_dsp32alu_0,
	208	decode_dsp32shift_0, decode_dsp32shiftimm_0, decode_pseudodbg_assert_0,
	209	_print_insn_bfin, print_insn_bfin): Likewise.
	210
58c85be7 RW	211	2008-03-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
	212
	213	* aclocal.m4: Regenerate.
	214	* configure: Likewise.
	215	* Makefile.in: Likewise.
	216
50e7d84b AM	217	2008-03-13 Alan Modra <amodra@bigpond.net.au>
	218
	219	* Makefile.am: Run "make dep-am".
	220	* Makefile.in: Regenerate.
	221	* configure: Regenerate.
	222
de866fcc AM	223	2008-03-07 Alan Modra <amodra@bigpond.net.au>
	224
	225	* ppc-opc.c (powerpc_opcodes): Order and format.
	226
28dbc079 L	227	2008-03-01 H.J. Lu <hongjiu.lu@intel.com>
	228
	229	* i386-opc.tbl: Allow 16-bit near indirect branches for x86-64.
	230	* i386-tbl.h: Regenerated.
	231
849830bd L	232	2008-02-23 H.J. Lu <hongjiu.lu@intel.com>
	233
	234	* i386-opc.tbl: Disallow 16-bit near indirect branches for
	235	x86-64.
	236	* i386-tbl.h: Regenerated.
	237
743ddb6b JB	238	2008-02-21 Jan Beulich <jbeulich@novell.com>
	239
	240	* i386-opc.tbl: Allow Dword for far indirect call. Allow Dword
	241	and Fword for far indirect jmp. Allow Reg16 and Word for near
	242	indirect jmp on x86-64. Disallow Fword for lcall.
	243	* i386-tbl.h: Re-generate.
	244
796d5313 NC	245	2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
	246
	247	* cr16-opc.c (cr16_num_optab): Defined
	248
65da13b5 L	249	2008-02-16 H.J. Lu <hongjiu.lu@intel.com>
	250
	251	* i386-gen.c (operand_type_init): Add OPERAND_TYPE_INOUTPORTREG.
	252	* i386-init.h: Regenerated.
	253
0e336180 NC	254	2008-02-14 Nick Clifton <nickc@redhat.com>
	255
	256	PR binutils/5524
	257	* configure.in (SHARED_LIBADD): Select the correct host specific
	258	file extension for shared libraries.
	259	* configure: Regenerate.
	260
b7240065 JB	261	2008-02-13 Jan Beulich <jbeulich@novell.com>
	262
	263	* i386-opc.h (RegFlat): New.
	264	* i386-reg.tbl (flat): Add.
	265	* i386-tbl.h: Re-generate.
	266
34b772a6 JB	267	2008-02-13 Jan Beulich <jbeulich@novell.com>
	268
	269	* i386-dis.c (a_mode): New.
	270	(cond_jump_mode): Adjust.
	271	(Ma): Change to a_mode.
	272	(intel_operand_size): Handle a_mode.
	273	* i386-opc.tbl: Allow Dword and Qword for bound.
	274	* i386-tbl.h: Re-generate.
	275
a60de03c JB	276	2008-02-13 Jan Beulich <jbeulich@novell.com>
	277
	278	* i386-gen.c (process_i386_registers): Process new fields.
	279	* i386-opc.h (reg_entry): Shrink reg_flags and reg_num to
	280	unsigned char. Add dw2_regnum and Dw2Inval.
	281	* i386-reg.tbl: Provide initializers for dw2_regnum. Add pseudo
	282	register names.
	283	* i386-tbl.h: Re-generate.
	284
f03fe4c1 L	285	2008-02-11 H.J. Lu <hongjiu.lu@intel.com>
f03fe4c1 L	286
4b6bc8eb	287	* i386-gen.c (cpu_flag_init): Add CPU_XSAVE_FLAGS.
f03fe4c1 L	288	* i386-init.h: Updated.
f03fe4c1 L	289
475a2301 L	290	2008-02-11 H.J. Lu <hongjiu.lu@intel.com>
	291
	292	* i386-gen.c (cpu_flags): Add CpuXsave.
	293
	294	* i386-opc.h (CpuXsave): New.
4b6bc8eb	295	(CpuLM): Updated.
475a2301 L	296	(i386_cpu_flags): Add cpuxsave.
	297
	298	* i386-dis.c (MOD_0FAE_REG_4): New.
	299	(RM_0F01_REG_2): Likewise.
	300	(MOD_0FAE_REG_5): Updated.
	301	(RM_0F01_REG_3): Likewise.
	302	(reg_table): Use MOD_0FAE_REG_4.
	303	(mod_table): Use RM_0F01_REG_2. Add MOD_0FAE_REG_4. Updated
	304	for xrstor.
	305	(rm_table): Add RM_0F01_REG_2.
	306
	307	* i386-opc.tbl: Add xsave, xrstor, xgetbv and xsetbv.
	308	* i386-init.h: Regenerated.
	309	* i386-tbl.h: Likewise.
	310
595785c6	311	2008-02-11 Jan Beulich <jbeulich@novell.com>
041179fc	312
595785c6 JB	313	* i386-opc.tbl: Remove Disp32S from CpuNo64 opcodes. Remove
	314	Disp16 from Cpu64 non-jump opcodes (including loop and j?cxz).
	315	* i386-tbl.h: Re-generate.
	316
bb8541b9 L	317	2008-02-04 H.J. Lu <hongjiu.lu@intel.com>
	318
	319	PR 5715
	320	* configure: Regenerated.
	321
57b592a3 AN	322	2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
	323
	324	* mips-dis.c: Update copyright.
	325	(mips_arch_choices): Add Octeon.
	326	* mips-opc.c: Update copyright.
	327	(IOCT): New macro.
	328	(mips_builtin_opcodes): Add Octeon instruction synciobdma.
	329
930bb4cf AM	330	2008-01-29 Alan Modra <amodra@bigpond.net.au>
	331
	332	* ppc-opc.c: Support optional L form mtmsr.
	333
82c18208 L	334	2008-01-24 H.J. Lu <hongjiu.lu@intel.com>
	335
	336	* i386-dis.c (OP_E_extended): Handle r12 like rsp.
	337
599121aa L	338	2008-01-23 H.J. Lu <hongjiu.lu@intel.com>
	339
	340	* i386-gen.c (cpu_flag_init): Add CpuLM to CPU_GENERIC64_FLAGS.
	341	* i386-init.h: Regenerated.
	342
80098f51 TG	343	2008-01-23 Tristan Gingold <gingold@adacore.com>
	344
	345	* ia64-dis.c (print_insn_ia64): Display symbolic name of ar.fcr,
	346	ar.eflag, ar.csd, ar.ssd, ar.cflg, ar.fsr, ar.fir and ar.fdr.
	347
115c7c25 L	348	2008-01-22 H.J. Lu <hongjiu.lu@intel.com>
	349
	350	* i386-gen.c (cpu_flag_init): Remove CpuMMX2.
	351	(cpu_flags): Likewise.
	352
	353	* i386-opc.h (CpuMMX2): Removed.
	354	(CpuSSE): Updated.
	355
	356	* i386-opc.tbl: Replace CpuMMX2 with CpuSSE\|Cpu3dnowA.
	357	* i386-init.h: Regenerated.
	358	* i386-tbl.h: Likewise.
	359
6305a203 L	360	2008-01-22 H.J. Lu <hongjiu.lu@intel.com>
	361
	362	* i386-gen.c (cpu_flag_init): Add CPU_VMX_FLAGS and
	363	CPU_SMX_FLAGS.
	364	* i386-init.h: Regenerated.
	365
fd07a1c8 L	366	2008-01-15 H.J. Lu <hongjiu.lu@intel.com>
	367
	368	* i386-opc.tbl: Use Qword on movddup.
	369	* i386-tbl.h: Regenerated.
	370
321fd21e L	371	2008-01-15 H.J. Lu <hongjiu.lu@intel.com>
	372
	373	* i386-opc.tbl: Put back 16bit movsx/movzx for AT&T syntax.
	374	* i386-tbl.h: Regenerated.
	375
4ee52178 L	376	2008-01-15 H.J. Lu <hongjiu.lu@intel.com>
	377
	378	* i386-dis.c (Mx): New.
	379	(PREFIX_0FC3): Likewise.
	380	(PREFIX_0FC7_REG_6): Updated.
	381	(dis386_twobyte): Use PREFIX_0FC3.
	382	(prefix_table): Add PREFIX_0FC3. Use Mq on movntq and movntsd.
	383	Use Mx on movntps, movntpd, movntdq and movntdqa. Use Md on
	384	movntss.
	385
5c07affc L	386	2008-01-14 H.J. Lu <hongjiu.lu@intel.com>
	387
	388	* i386-gen.c (opcode_modifiers): Add IntelSyntax.
	389	(operand_types): Add Mem.
	390
	391	* i386-opc.h (IntelSyntax): New.
	392	* i386-opc.h (Mem): New.
	393	(Byte): Updated.
	394	(Opcode_Modifier_Max): Updated.
	395	(i386_opcode_modifier): Add intelsyntax.
	396	(i386_operand_type): Add mem.
	397
	398	* i386-opc.tbl: Remove Reg16 from movnti. Add sizes to more
	399	instructions.
	400
	401	* i386-reg.tbl: Add size for accumulator.
	402
	403	* i386-init.h: Regenerated.
	404	* i386-tbl.h: Likewise.
	405
0d6a2f58 L	406	2008-01-13 H.J. Lu <hongjiu.lu@intel.com>
	407
	408	* i386-opc.h (Byte): Fix a typo.
	409
7d5e4556 L	410	2008-01-12 H.J. Lu <hongjiu.lu@intel.com>
	411
	412	PR gas/5534
	413	* i386-gen.c (operand_type_init): Add Dword to
	414	OPERAND_TYPE_ACC32. Add Qword to OPERAND_TYPE_ACC64.
	415	(opcode_modifiers): Remove CheckSize, Byte, Word, Dword,
	416	Qword and Xmmword.
	417	(operand_types): Add Byte, Word, Dword, Fword, Qword, Tbyte,
	418	Xmmword, Unspecified and Anysize.
	419	(set_bitfield): Make Mmword an alias of Qword. Make Oword
	420	an alias of Xmmword.
	421
	422	* i386-opc.h (CheckSize): Removed.
	423	(Byte): Updated.
	424	(Word): Likewise.
	425	(Dword): Likewise.
	426	(Qword): Likewise.
	427	(Xmmword): Likewise.
	428	(FWait): Updated.
	429	(OTMax): Likewise.
	430	(i386_opcode_modifier): Remove checksize, byte, word, dword,
	431	qword and xmmword.
	432	(Fword): New.
	433	(TBYTE): Likewise.
	434	(Unspecified): Likewise.
	435	(Anysize): Likewise.
	436	(i386_operand_type): Add byte, word, dword, fword, qword,
	437	tbyte xmmword, unspecified and anysize.
	438
	439	* i386-opc.tbl: Updated to use Byte, Word, Dword, Fword, Qword,
	440	Tbyte, Xmmword, Unspecified and Anysize.
	441
	442	* i386-reg.tbl: Add size for accumulator.
	443
	444	* i386-init.h: Regenerated.
	445	* i386-tbl.h: Likewise.
	446
b5b1fc4f L	447	2008-01-10 H.J. Lu <hongjiu.lu@intel.com>
	448
	449	* i386-dis.c (REG_0F0E): Renamed to REG_0F0D.
	450	(REG_0F18): Updated.
	451	(reg_table): Updated.
	452	(dis386_twobyte): Updated. Use "nopQ" on 0x19 to 0x1e.
	453	(twobyte_has_modrm): Set 1 for 0x19 to 0x1e.
	454
50e8458f L	455	2008-01-08 H.J. Lu <hongjiu.lu@intel.com>
	456
	457	* i386-gen.c (set_bitfield): Use fail () on error.
	458
3d4d5afa L	459	2008-01-08 H.J. Lu <hongjiu.lu@intel.com>
	460
	461	* i386-gen.c (lineno): New.
	462	(filename): Likewise.
	463	(set_bitfield): Report filename and line numer on error.
	464	(process_i386_opcodes): Set filename and update lineno.
	465	(process_i386_registers): Likewise.
	466
e1d4d893 L	467	2008-01-05 H.J. Lu <hongjiu.lu@intel.com>
	468
	469	* i386-gen.c (opcode_modifiers): Rename IntelMnemonic to
	470	ATTSyntax.
	471
	472	* i386-opc.h (IntelMnemonic): Renamed to ..
	473	(ATTSyntax): This
	474	(Opcode_Modifier_Max): Updated.
	475	(i386_opcode_modifier): Remove intelmnemonic. Add attsyntax
	476	and intelsyntax.
	477
	478	* i386-opc.tbl: Remove IntelMnemonic and update with ATTSyntax
	479	on fsub, fubp, fsubr, fsubrp, div, fdivp, fdivr and fdivrp.
	480	* i386-tbl.h: Regenerated.
	481
6f143e4d L	482	2008-01-04 H.J. Lu <hongjiu.lu@intel.com>
	483
	484	* i386-gen.c: Update copyright to 2008.
	485	* i386-opc.h: Likewise.
	486	* i386-opc.tbl: Likewise.
	487
	488	* i386-init.h: Regenerated.
	489	* i386-tbl.h: Likewise.
	490
c6add537 L	491	2008-01-04 H.J. Lu <hongjiu.lu@intel.com>
	492
	493	* i386-opc.tbl: Add NoRex64 to extractps, movmskpd, movmskps,
	494	pextrb, pextrw, pinsrb, pinsrw and pmovmskb.
	495	* i386-tbl.h: Regenerated.
	496
3629bb00 L	497	2008-01-03 H.J. Lu <hongjiu.lu@intel.com>
	498
	499	* i386-gen.c (cpu_flag_init): Remove CpuSSE4_1_Or_5 and
	500	CpuSSE4_2_Or_ABM.
	501	(cpu_flags): Likewise.
	502
	503	* i386-opc.h (CpuSSE4_1_Or_5): Removed.
	504	(CpuSSE4_2_Or_ABM): Likewise.
	505	(CpuLM): Updated.
	506	(i386_cpu_flags): Remove cpusse4_1_or_5 and cpusse4_2_or_abm.
	507
	508	* i386-opc.tbl: Replace CpuSSE4_1_Or_5, CpuSSE4_2_Or_ABM and
	509	Cpu686\|CpuPadLock with CpuSSE4_1\|CpuSSE5, CpuABM\|CpuSSE4_2
	510	and CpuPadLock, respectively.
	511	* i386-init.h: Regenerated.
	512	* i386-tbl.h: Likewise.
	513
24995bd6 L	514	2008-01-03 H.J. Lu <hongjiu.lu@intel.com>
	515
	516	* i386-gen.c (opcode_modifiers): Remove No_xSuf.
	517
	518	* i386-opc.h (No_xSuf): Removed.
	519	(CheckSize): Updated.
	520
	521	* i386-tbl.h: Regenerated.
	522
e0329a22 L	523	2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
	524
	525	* i386-gen.c (cpu_flag_init): Add CpuSSE4_2_Or_ABM to
	526	CPU_AMDFAM10_FLAGS, CPU_SSE4_2_FLAGS, CpuABM and
	527	CPU_SSE5_FLAGS.
	528	(cpu_flags): Add CpuSSE4_2_Or_ABM.
	529
	530	* i386-opc.h (CpuSSE4_2_Or_ABM): New.
	531	(CpuLM): Updated.
	532	(i386_cpu_flags): Add cpusse4_2_or_abm.
	533
	534	* i386-opc.tbl: Use CpuSSE4_2_Or_ABM instead of
	535	CpuABM\|CpuSSE4_2 on popcnt.
	536	* i386-init.h: Regenerated.
	537	* i386-tbl.h: Likewise.
	538
f2a9c676 L	539	2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
	540
	541	* i386-opc.h: Update comments.
	542
d978b5be L	543	2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
	544
	545	* i386-gen.c (opcode_modifiers): Use Qword instead of QWord.
	546	* i386-opc.h: Likewise.
	547	* i386-opc.tbl: Likewise.
	548
582d5edd L	549	2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
	550
	551	PR gas/5534
	552	* i386-gen.c (opcode_modifiers): Add No_xSuf, CheckSize,
	553	Byte, Word, Dword, QWord and Xmmword.
	554
	555	* i386-opc.h (No_xSuf): New.
	556	(CheckSize): Likewise.
	557	(Byte): Likewise.
	558	(Word): Likewise.
	559	(Dword): Likewise.
	560	(QWord): Likewise.
	561	(Xmmword): Likewise.
	562	(FWait): Updated.
	563	(i386_opcode_modifier): Add No_xSuf, CheckSize, Byte, Word,
	564	Dword, QWord and Xmmword.
	565
	566	* i386-opc.tbl: Add CheckSize\|QWord to movq if IgnoreSize is
	567	used.
	568	* i386-tbl.h: Regenerated.
	569
3fe15143 MK	570	2008-01-02 Mark Kettenis <kettenis@gnu.org>
	571
	572	* m88k-dis.c (instructions): Fix fcvt.* instructions.
	573	From Miod Vallat.
	574
6c7ac64e	575	For older changes see ChangeLog-2007
252b5132 RH	576	\f
252b5132 RH	577	Local Variables:
2f6d2f85 NC	578	mode: change-log
	579	left-margin: 8
	580	fill-column: 74
252b5132 RH	581	version-control: never
252b5132 RH	582	End: