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CommitLineData
6194aaab
L		 12008-04-23 Paolo Bonzini <bonzini@gnu.org>
2
3 * aclocal.m4: Regenerate.
4 * configure: Regenerate.
5
1a6b486f
DM		 62008-04-23 David S. Miller <davem@davemloft.net>
7
8 * sparc-opc.c (asi_table): Add UltraSPARC and Niagara
9 extended values.
10 (prefetch_table): Add missing values.
11
81f8a913
L		 122008-04-22 H.J. Lu <hongjiu.lu@intel.com>
13
14 * i386-gen.c (opcode_modifiers): Add NoAVX.
15
16 * i386-opc.h (NoAVX): New.
17 (OldGcc): Updated.
18 (i386_opcode_modifier): Add noavx.
19
20 * i386-opc.tbl: Add NoAVX to SSE, SSE2, SSE3 and SSSE3
21 instructions which don't have AVX equivalent.
22 * i386-tbl.h: Regenerated.
23
dae39acc
L		 242008-04-18 H.J. Lu <hongjiu.lu@intel.com>
25
26 * i386-dis.c (OP_VEX_FMA): New.
27 (OP_EX_VexImmW): Likewise.
28 (VexFMA): Likewise.
29 (Vex128FMA): Likewise.
30 (EXVexImmW): Likewise.
31 (get_vex_imm8): Likewise.
32 (OP_EX_VexReg): Likewise.
33 (vex_i4_done): Renamed to ...
34 (vex_w_done): This.
35 (prefix_table): Replace EXVexW with EXVexImmW on vpermil2ps
36 and vpermil2pd. Replace Vex/Vex128 with VexFMA/Vex128FMA on
37 FMA instructions.
38 (print_insn): Updated.
39 (OP_EX_VexW): Rewrite to swap register in VEX with EX.
40 (OP_REG_VexI4): Check invalid high registers.
41
ce886ab1
DR		 422008-04-16 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
43 Michael Meissner <michael.meissner@amd.com>
44
45 * i386-opc.tbl: Fix protX to allow memory in the middle operand.
46 * i386-tbl.h: Regenerate from i386-opc.tbl.
47
19a6653c
AM		 482008-04-14 Edmar Wienskoski <edmar@freescale.com>
49
50 * ppc-dis.c (powerpc_dialect): Handle "e500mc". Extend "e500" to
51 accept Power E500MC instructions.
52 (print_ppc_disassembler_options): Document -Me500mc.
53 * ppc-opc.c (DUIS, DUI, T): New.
54 (XRT, XRTRA): Likewise.
55 (E500MC): Likewise.
56 (powerpc_opcodes): Add new Power E500MC instructions.
57
112b7c50
AK		 582008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
59
60 * s390-dis.c (init_disasm): Evaluate disassembler_options.
61 (print_s390_disassembler_options): New function.
62 * disassemble.c (disassembler_usage): Invoke
63 print_s390_disassembler_options.
64
7ff42648
AK		 652008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
66
67 * s390-mkopc.c (insertExpandedMnemonic): Expand string sizes
68 of local variables used for mnemonic parsing: prefix, suffix and
69 number.
70
45a5551e
AK		 712008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
72
73 * s390-mkopc.c (s390_cond_ext_format): Add back the mnemonic
74 extensions for conditional jumps (o, p, m, nz, z, nm, np, no).
75 (s390_crb_extensions): New extensions table.
76 (insertExpandedMnemonic): Handle '$' tag.
77 * s390-opc.txt: Remove conditional jump variants which can now
78 be expanded automatically.
79 Replace '*' tag with '$' in the compare and branch instructions.
80
06c8514a
L		 812008-04-07 H.J. Lu <hongjiu.lu@intel.com>
82
83 * i386-dis.c (PREFIX_VEX_38XX): Add a tab.
84 (PREFIX_VEX_3AXX): Likewis.
85
b122c285
L		 862008-04-07 H.J. Lu <hongjiu.lu@intel.com>
87
88 * i386-opc.tbl: Remove 4 extra blank lines.
89
594ab6a3
L		 902008-04-04 H.J. Lu <hongjiu.lu@intel.com>
91
92 * i386-gen.c (cpu_flag_init): Replace CPU_CLMUL_FLAGS/CpuCLMUL
93 with CPU_PCLMUL_FLAGS/CpuPCLMUL.
94 (cpu_flags): Replace CpuCLMUL with CpuPCLMUL.
95 * i386-opc.tbl: Likewise.
96
97 * i386-opc.h (CpuCLMUL): Renamed to ...
98 (CpuPCLMUL): This.
99 (CpuFMA): Updated.
100 (i386_cpu_flags): Replace cpuclmul with cpupclmul.
101
102 * i386-init.h: Regenerated.
103
c0f3af97
L		 1042008-04-03 H.J. Lu <hongjiu.lu@intel.com>
105
106 * i386-dis.c (OP_E_register): New.
107 (OP_E_memory): Likewise.
108 (OP_VEX): Likewise.
109 (OP_EX_Vex): Likewise.
110 (OP_EX_VexW): Likewise.
111 (OP_XMM_Vex): Likewise.
112 (OP_XMM_VexW): Likewise.
113 (OP_REG_VexI4): Likewise.
114 (PCLMUL_Fixup): Likewise.
115 (VEXI4_Fixup): Likewise.
116 (VZERO_Fixup): Likewise.
117 (VCMP_Fixup): Likewise.
118 (VPERMIL2_Fixup): Likewise.
119 (rex_original): Likewise.
120 (rex_ignored): Likewise.
121 (Mxmm): Likewise.
122 (XMM): Likewise.
123 (EXxmm): Likewise.
124 (EXxmmq): Likewise.
125 (EXymmq): Likewise.
126 (Vex): Likewise.
127 (Vex128): Likewise.
128 (Vex256): Likewise.
129 (VexI4): Likewise.
130 (EXdVex): Likewise.
131 (EXqVex): Likewise.
132 (EXVexW): Likewise.
133 (EXdVexW): Likewise.
134 (EXqVexW): Likewise.
135 (XMVex): Likewise.
136 (XMVexW): Likewise.
137 (XMVexI4): Likewise.
138 (PCLMUL): Likewise.
139 (VZERO): Likewise.
140 (VCMP): Likewise.
141 (VPERMIL2): Likewise.
142 (xmm_mode): Likewise.
143 (xmmq_mode): Likewise.
144 (ymmq_mode): Likewise.
145 (vex_mode): Likewise.
146 (vex128_mode): Likewise.
147 (vex256_mode): Likewise.
148 (USE_VEX_C4_TABLE): Likewise.
149 (USE_VEX_C5_TABLE): Likewise.
150 (USE_VEX_LEN_TABLE): Likewise.
151 (VEX_C4_TABLE): Likewise.
152 (VEX_C5_TABLE): Likewise.
153 (VEX_LEN_TABLE): Likewise.
154 (REG_VEX_XX): Likewise.
155 (MOD_VEX_XXX): Likewise.
156 (PREFIX_0F38DB..PREFIX_0F38DF): Likewise.
157 (PREFIX_0F3A44): Likewise.
158 (PREFIX_0F3ADF): Likewise.
159 (PREFIX_VEX_XXX): Likewise.
160 (VEX_OF): Likewise.
161 (VEX_OF38): Likewise.
162 (VEX_OF3A): Likewise.
163 (VEX_LEN_XXX): Likewise.
164 (vex): Likewise.
165 (need_vex): Likewise.
166 (need_vex_reg): Likewise.
167 (vex_i4_done): Likewise.
168 (vex_table): Likewise.
169 (vex_len_table): Likewise.
170 (OP_REG_VexI4): Likewise.
171 (vex_cmp_op): Likewise.
172 (pclmul_op): Likewise.
173 (vpermil2_op): Likewise.
174 (m_mode): Updated.
175 (es_reg): Likewise.
176 (PREFIX_0F38F0): Likewise.
177 (PREFIX_0F3A60): Likewise.
178 (reg_table): Add REG_VEX_71...REG_VEX_73 and REG_VEX_AE.
179 (prefix_table): Add PREFIX_0F38DB..PREFIX_0F38DF, PREFIX_0F3ADF
180 and PREFIX_VEX_XXX entries.
181 (x86_64_table): Use VEX_C4_TABLE and VEX_C5_TABLE.
182 (three_byte_table): Use PREFIX_0F38DB..PREFIX_0F38DF and
183 PREFIX_0F3ADF.
184 (mod_table): Use VEX_C4_TABLE, VEX_C5_TABLE and VEX_LEN_TABLE.
185 Add MOD_VEX_XXX entries.
186 (ckprefix): Initialize rex_original and rex_ignored. Store the
187 REX byte in rex_original.
188 (get_valid_dis386): Handle the implicit prefix in VEX prefix
189 bytes and USE_VEX_LEN_TABLE/USE_VEX_C4_TABLE/USE_VEX_C5_TABLE.
190 (print_insn): Set need_vex/need_vex_reg/vex_i4_done to 0 before
191 calling get_valid_dis386. Use rex_original and rex_ignored when
192 printing out REX.
193 (putop): Handle "XY".
194 (intel_operand_size): Handle VEX, xmm_mode, xmmq_mode and
195 ymmq_mode.
196 (OP_E_extended): Updated to use OP_E_register and
197 OP_E_memory.
198 (OP_XMM): Handle VEX.
199 (OP_EX): Likewise.
200 (XMM_Fixup): Likewise.
201 (CMP_Fixup): Use ARRAY_SIZE.
202
203 * i386-gen.c (cpu_flag_init): Add CpuAES, CPU_CLMUL_FLAGS,
204 CPU_FMA_FLAGS and CPU_AVX_FLAGS.
205 (operand_type_init): Add OPERAND_TYPE_REGYMM and
206 OPERAND_TYPE_VEX_IMM4.
207 (cpu_flags): Add CpuAVX, CpuAES, CpuCLMUL and CpuFMA.
208 (opcode_modifiers): Add Implicit1stXmm0, Vex, Vex256, VexNDD,
209 VexNDS, VexW0, VexW1, Vex0F, Vex0F38, Vex0F3A, Vex3Sources,
210 VexImmExt and SSE2AVX.
211 (operand_types): Add RegYMM, Ymmword and Vex_Imm4.
212
213 * i386-opc.h (CpuAVX): New.
214 (CpuAES): Likewise.
215 (CpuCLMUL): Likewise.
216 (CpuFMA): Likewise.
217 (Vex): Likewise.
218 (Vex256): Likewise.
219 (VexNDS): Likewise.
220 (VexNDD): Likewise.
221 (VexW0): Likewise.
222 (VexW1): Likewise.
223 (Vex0F): Likewise.
224 (Vex0F38): Likewise.
225 (Vex0F3A): Likewise.
226 (Vex3Sources): Likewise.
227 (VexImmExt): Likewise.
228 (SSE2AVX): Likewise.
229 (RegYMM): Likewise.
230 (Ymmword): Likewise.
231 (Vex_Imm4): Likewise.
232 (Implicit1stXmm0): Likewise.
233 (CpuXsave): Updated.
234 (CpuLM): Likewise.
235 (ByteOkIntel): Likewise.
236 (OldGcc): Likewise.
237 (Control): Likewise.
238 (Unspecified): Likewise.
239 (OTMax): Likewise.
240 (i386_cpu_flags): Add cpuavx, cpuaes, cpuclmul and cpufma.
241 (i386_opcode_modifier): Add implicit1stxmm0, vex, vex256,
242 vexnds, vexndd, vexw0, vexw1, vex0f, vex0f38, vex0f3a,
243 vex3sources, veximmext and sse2avx.
244 (i386_operand_type): Add regymm, ymmword and vex_imm4.
245
246 * i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions.
247
248 * i386-reg.tbl: Add AVX registers, ymm0..ymm15.
249
250 * i386-init.h: Regenerated.
251 * i386-tbl.h: Likewise.
252
b21c9cb4
BS		 2532008-03-26 Bernd Schmidt <bernd.schmidt@analog.com>
254
255 From Robin Getz <robin.getz@analog.com>
256 * bfin-dis.c (bu32): Typedef.
257 (enum const_forms_t): Add c_uimm32 and c_huimm32.
258 (constant_formats[]): Add uimm32 and huimm16.
259 (fmtconst_val): New.
260 (uimm32): Define.
261 (huimm32): Define.
262 (imm16_val): Define.
263 (luimm16_val): Define.
264 (struct saved_state): Define.
265 (GREG, DPREG, DREG, PREG, SPREG, FPREG, IREG, MREG, BREG, LREG,
266 A0XREG, A0WREG, A1XREG, A1WREG,CCREG, LC0REG, LT0REG, LB0REG,
267 LC1REG, LT1REG, LB1REG, RETSREG, PCREG): Define.
268 (get_allreg): New.
269 (decode_LDIMMhalf_0): Print out the whole register value.
270
ee171c8f
BS		 271 From Jie Zhang <jie.zhang@analog.com>
272 * bfin-dis.c (decode_dsp32mac_0): Decode (IU) option for
273 multiply and multiply-accumulate to data register instruction.
274
086134ec
BS		 275 * bfin-dis.c: (c_uimm4s4d, c_imm5d, c_imm7d, c_imm16d, c_uimm16s4d,
276 c_imm32, c_huimm32e): Define.
277 (constant_formats): Add flags for printing decimal, leading spaces, and
278 exact symbols.
279 (comment, parallel): Add global flags in all disassembly.
280 (fmtconst): Take advantage of new flags, and print default in hex.
281 (fmtconst_val): Likewise.
282 (decode_macfunc): Be consistant with spaces, tabs, comments,
283 capitalization in disassembly, fix minor coding style issues.
284 (reg_names, amod0, amod1, amod0amod2, aligndir, get_allreg): Likewise.
285 (decode_ProgCtrl_0, decode_PushPopMultiple_0, decode_CCflag_0,
286 decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0,
287 decode_REGMV_0, decode_ALU2op_0, decode_PTR2op_0, decode_LOGI2op_0,
288 decode_COMP3op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
289 decode_LDSTpmod_0, decode_dagMODim_0, decode_dagMODik_0,
290 decode_dspLDST_0, decode_LDST_0, decode_LDSTiiFP_0, decode_LDSTii_0,
291 decode_LoopSetup_0, decode_LDIMMhalf_0, decode_CALLa_0,
292 decode_LDSTidxI_0, decode_linkage_0, decode_dsp32alu_0,
293 decode_dsp32shift_0, decode_dsp32shiftimm_0, decode_pseudodbg_assert_0,
294 _print_insn_bfin, print_insn_bfin): Likewise.
295
58c85be7
RW		 2962008-03-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
297
298 * aclocal.m4: Regenerate.
299 * configure: Likewise.
300 * Makefile.in: Likewise.
301
50e7d84b
AM		 3022008-03-13 Alan Modra <amodra@bigpond.net.au>
303
304 * Makefile.am: Run "make dep-am".
305 * Makefile.in: Regenerate.
306 * configure: Regenerate.
307
de866fcc
AM		 3082008-03-07 Alan Modra <amodra@bigpond.net.au>
309
310 * ppc-opc.c (powerpc_opcodes): Order and format.
311
28dbc079
L		 3122008-03-01 H.J. Lu <hongjiu.lu@intel.com>
313
314 * i386-opc.tbl: Allow 16-bit near indirect branches for x86-64.
315 * i386-tbl.h: Regenerated.
316
849830bd
L		 3172008-02-23 H.J. Lu <hongjiu.lu@intel.com>
318
319 * i386-opc.tbl: Disallow 16-bit near indirect branches for
320 x86-64.
321 * i386-tbl.h: Regenerated.
322
743ddb6b
JB		 3232008-02-21 Jan Beulich <jbeulich@novell.com>
324
325 * i386-opc.tbl: Allow Dword for far indirect call. Allow Dword
326 and Fword for far indirect jmp. Allow Reg16 and Word for near
327 indirect jmp on x86-64. Disallow Fword for lcall.
328 * i386-tbl.h: Re-generate.
329
796d5313
NC		 3302008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
331
332 * cr16-opc.c (cr16_num_optab): Defined
333
65da13b5
L		 3342008-02-16 H.J. Lu <hongjiu.lu@intel.com>
335
336 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_INOUTPORTREG.
337 * i386-init.h: Regenerated.
338
0e336180
NC		 3392008-02-14 Nick Clifton <nickc@redhat.com>
340
341 PR binutils/5524
342 * configure.in (SHARED_LIBADD): Select the correct host specific
343 file extension for shared libraries.
344 * configure: Regenerate.
345
b7240065
JB		 3462008-02-13 Jan Beulich <jbeulich@novell.com>
347
348 * i386-opc.h (RegFlat): New.
349 * i386-reg.tbl (flat): Add.
350 * i386-tbl.h: Re-generate.
351
34b772a6
JB		 3522008-02-13 Jan Beulich <jbeulich@novell.com>
353
354 * i386-dis.c (a_mode): New.
355 (cond_jump_mode): Adjust.
356 (Ma): Change to a_mode.
357 (intel_operand_size): Handle a_mode.
358 * i386-opc.tbl: Allow Dword and Qword for bound.
359 * i386-tbl.h: Re-generate.
360
a60de03c
JB		 3612008-02-13 Jan Beulich <jbeulich@novell.com>
362
363 * i386-gen.c (process_i386_registers): Process new fields.
364 * i386-opc.h (reg_entry): Shrink reg_flags and reg_num to
365 unsigned char. Add dw2_regnum and Dw2Inval.
366 * i386-reg.tbl: Provide initializers for dw2_regnum. Add pseudo
367 register names.
368 * i386-tbl.h: Re-generate.
369
f03fe4c1
L		 3702008-02-11 H.J. Lu <hongjiu.lu@intel.com>
371
4b6bc8eb 372 * i386-gen.c (cpu_flag_init): Add CPU_XSAVE_FLAGS.
f03fe4c1
L		 373 * i386-init.h: Updated.
374
475a2301
L		 3752008-02-11 H.J. Lu <hongjiu.lu@intel.com>
376
377 * i386-gen.c (cpu_flags): Add CpuXsave.
378
379 * i386-opc.h (CpuXsave): New.
4b6bc8eb 380 (CpuLM): Updated.
475a2301
L		 381 (i386_cpu_flags): Add cpuxsave.
382
383 * i386-dis.c (MOD_0FAE_REG_4): New.
384 (RM_0F01_REG_2): Likewise.
385 (MOD_0FAE_REG_5): Updated.
386 (RM_0F01_REG_3): Likewise.
387 (reg_table): Use MOD_0FAE_REG_4.
388 (mod_table): Use RM_0F01_REG_2. Add MOD_0FAE_REG_4. Updated
389 for xrstor.
390 (rm_table): Add RM_0F01_REG_2.
391
392 * i386-opc.tbl: Add xsave, xrstor, xgetbv and xsetbv.
393 * i386-init.h: Regenerated.
394 * i386-tbl.h: Likewise.
395
595785c6 3962008-02-11 Jan Beulich <jbeulich@novell.com>
041179fc 397
595785c6
JB		 398 * i386-opc.tbl: Remove Disp32S from CpuNo64 opcodes. Remove
399 Disp16 from Cpu64 non-jump opcodes (including loop and j?cxz).
400 * i386-tbl.h: Re-generate.
401
bb8541b9
L		 4022008-02-04 H.J. Lu <hongjiu.lu@intel.com>
403
404 PR 5715
405 * configure: Regenerated.
406
57b592a3
AN		 4072008-02-04 Adam Nemet <anemet@caviumnetworks.com>
408
409 * mips-dis.c: Update copyright.
410 (mips_arch_choices): Add Octeon.
411 * mips-opc.c: Update copyright.
412 (IOCT): New macro.
413 (mips_builtin_opcodes): Add Octeon instruction synciobdma.
414
930bb4cf
AM		 4152008-01-29 Alan Modra <amodra@bigpond.net.au>
416
417 * ppc-opc.c: Support optional L form mtmsr.
418
82c18208
L		 4192008-01-24 H.J. Lu <hongjiu.lu@intel.com>
420
421 * i386-dis.c (OP_E_extended): Handle r12 like rsp.
422
599121aa
L		 4232008-01-23 H.J. Lu <hongjiu.lu@intel.com>
424
425 * i386-gen.c (cpu_flag_init): Add CpuLM to CPU_GENERIC64_FLAGS.
426 * i386-init.h: Regenerated.
427
80098f51
TG		 4282008-01-23 Tristan Gingold <gingold@adacore.com>
429
430 * ia64-dis.c (print_insn_ia64): Display symbolic name of ar.fcr,
431 ar.eflag, ar.csd, ar.ssd, ar.cflg, ar.fsr, ar.fir and ar.fdr.
432
115c7c25
L		 4332008-01-22 H.J. Lu <hongjiu.lu@intel.com>
434
435 * i386-gen.c (cpu_flag_init): Remove CpuMMX2.
436 (cpu_flags): Likewise.
437
438 * i386-opc.h (CpuMMX2): Removed.
439 (CpuSSE): Updated.
440
441 * i386-opc.tbl: Replace CpuMMX2 with CpuSSE|Cpu3dnowA.
442 * i386-init.h: Regenerated.
443 * i386-tbl.h: Likewise.
444
6305a203
L		 4452008-01-22 H.J. Lu <hongjiu.lu@intel.com>
446
447 * i386-gen.c (cpu_flag_init): Add CPU_VMX_FLAGS and
448 CPU_SMX_FLAGS.
449 * i386-init.h: Regenerated.
450
fd07a1c8
L		 4512008-01-15 H.J. Lu <hongjiu.lu@intel.com>
452
453 * i386-opc.tbl: Use Qword on movddup.
454 * i386-tbl.h: Regenerated.
455
321fd21e
L		 4562008-01-15 H.J. Lu <hongjiu.lu@intel.com>
457
458 * i386-opc.tbl: Put back 16bit movsx/movzx for AT&T syntax.
459 * i386-tbl.h: Regenerated.
460
4ee52178
L		 4612008-01-15 H.J. Lu <hongjiu.lu@intel.com>
462
463 * i386-dis.c (Mx): New.
464 (PREFIX_0FC3): Likewise.
465 (PREFIX_0FC7_REG_6): Updated.
466 (dis386_twobyte): Use PREFIX_0FC3.
467 (prefix_table): Add PREFIX_0FC3. Use Mq on movntq and movntsd.
468 Use Mx on movntps, movntpd, movntdq and movntdqa. Use Md on
469 movntss.
470
5c07affc
L		 4712008-01-14 H.J. Lu <hongjiu.lu@intel.com>
472
473 * i386-gen.c (opcode_modifiers): Add IntelSyntax.
474 (operand_types): Add Mem.
475
476 * i386-opc.h (IntelSyntax): New.
477 * i386-opc.h (Mem): New.
478 (Byte): Updated.
479 (Opcode_Modifier_Max): Updated.
480 (i386_opcode_modifier): Add intelsyntax.
481 (i386_operand_type): Add mem.
482
483 * i386-opc.tbl: Remove Reg16 from movnti. Add sizes to more
484 instructions.
485
486 * i386-reg.tbl: Add size for accumulator.
487
488 * i386-init.h: Regenerated.
489 * i386-tbl.h: Likewise.
490
0d6a2f58
L		 4912008-01-13 H.J. Lu <hongjiu.lu@intel.com>
492
493 * i386-opc.h (Byte): Fix a typo.
494
7d5e4556
L		 4952008-01-12 H.J. Lu <hongjiu.lu@intel.com>
496
497 PR gas/5534
498 * i386-gen.c (operand_type_init): Add Dword to
499 OPERAND_TYPE_ACC32. Add Qword to OPERAND_TYPE_ACC64.
500 (opcode_modifiers): Remove CheckSize, Byte, Word, Dword,
501 Qword and Xmmword.
502 (operand_types): Add Byte, Word, Dword, Fword, Qword, Tbyte,
503 Xmmword, Unspecified and Anysize.
504 (set_bitfield): Make Mmword an alias of Qword. Make Oword
505 an alias of Xmmword.
506
507 * i386-opc.h (CheckSize): Removed.
508 (Byte): Updated.
509 (Word): Likewise.
510 (Dword): Likewise.
511 (Qword): Likewise.
512 (Xmmword): Likewise.
513 (FWait): Updated.
514 (OTMax): Likewise.
515 (i386_opcode_modifier): Remove checksize, byte, word, dword,
516 qword and xmmword.
517 (Fword): New.
518 (TBYTE): Likewise.
519 (Unspecified): Likewise.
520 (Anysize): Likewise.
521 (i386_operand_type): Add byte, word, dword, fword, qword,
522 tbyte xmmword, unspecified and anysize.
523
524 * i386-opc.tbl: Updated to use Byte, Word, Dword, Fword, Qword,
525 Tbyte, Xmmword, Unspecified and Anysize.
526
527 * i386-reg.tbl: Add size for accumulator.
528
529 * i386-init.h: Regenerated.
530 * i386-tbl.h: Likewise.
531
b5b1fc4f
L		 5322008-01-10 H.J. Lu <hongjiu.lu@intel.com>
533
534 * i386-dis.c (REG_0F0E): Renamed to REG_0F0D.
535 (REG_0F18): Updated.
536 (reg_table): Updated.
537 (dis386_twobyte): Updated. Use "nopQ" on 0x19 to 0x1e.
538 (twobyte_has_modrm): Set 1 for 0x19 to 0x1e.
539
50e8458f
L		 5402008-01-08 H.J. Lu <hongjiu.lu@intel.com>
541
542 * i386-gen.c (set_bitfield): Use fail () on error.
543
3d4d5afa
L		 5442008-01-08 H.J. Lu <hongjiu.lu@intel.com>
545
546 * i386-gen.c (lineno): New.
547 (filename): Likewise.
548 (set_bitfield): Report filename and line numer on error.
549 (process_i386_opcodes): Set filename and update lineno.
550 (process_i386_registers): Likewise.
551
e1d4d893
L		 5522008-01-05 H.J. Lu <hongjiu.lu@intel.com>
553
554 * i386-gen.c (opcode_modifiers): Rename IntelMnemonic to
555 ATTSyntax.
556
557 * i386-opc.h (IntelMnemonic): Renamed to ..
558 (ATTSyntax): This
559 (Opcode_Modifier_Max): Updated.
560 (i386_opcode_modifier): Remove intelmnemonic. Add attsyntax
561 and intelsyntax.
562
563 * i386-opc.tbl: Remove IntelMnemonic and update with ATTSyntax
564 on fsub, fubp, fsubr, fsubrp, div, fdivp, fdivr and fdivrp.
565 * i386-tbl.h: Regenerated.
566
6f143e4d
L		 5672008-01-04 H.J. Lu <hongjiu.lu@intel.com>
568
569 * i386-gen.c: Update copyright to 2008.
570 * i386-opc.h: Likewise.
571 * i386-opc.tbl: Likewise.
572
573 * i386-init.h: Regenerated.
574 * i386-tbl.h: Likewise.
575
c6add537
L		 5762008-01-04 H.J. Lu <hongjiu.lu@intel.com>
577
578 * i386-opc.tbl: Add NoRex64 to extractps, movmskpd, movmskps,
579 pextrb, pextrw, pinsrb, pinsrw and pmovmskb.
580 * i386-tbl.h: Regenerated.
581
3629bb00
L		 5822008-01-03 H.J. Lu <hongjiu.lu@intel.com>
583
584 * i386-gen.c (cpu_flag_init): Remove CpuSSE4_1_Or_5 and
585 CpuSSE4_2_Or_ABM.
586 (cpu_flags): Likewise.
587
588 * i386-opc.h (CpuSSE4_1_Or_5): Removed.
589 (CpuSSE4_2_Or_ABM): Likewise.
590 (CpuLM): Updated.
591 (i386_cpu_flags): Remove cpusse4_1_or_5 and cpusse4_2_or_abm.
592
593 * i386-opc.tbl: Replace CpuSSE4_1_Or_5, CpuSSE4_2_Or_ABM and
594 Cpu686|CpuPadLock with CpuSSE4_1|CpuSSE5, CpuABM|CpuSSE4_2
595 and CpuPadLock, respectively.
596 * i386-init.h: Regenerated.
597 * i386-tbl.h: Likewise.
598
24995bd6
L		 5992008-01-03 H.J. Lu <hongjiu.lu@intel.com>
600
601 * i386-gen.c (opcode_modifiers): Remove No_xSuf.
602
603 * i386-opc.h (No_xSuf): Removed.
604 (CheckSize): Updated.
605
606 * i386-tbl.h: Regenerated.
607
e0329a22
L		 6082008-01-02 H.J. Lu <hongjiu.lu@intel.com>
609
610 * i386-gen.c (cpu_flag_init): Add CpuSSE4_2_Or_ABM to
611 CPU_AMDFAM10_FLAGS, CPU_SSE4_2_FLAGS, CpuABM and
612 CPU_SSE5_FLAGS.
613 (cpu_flags): Add CpuSSE4_2_Or_ABM.
614
615 * i386-opc.h (CpuSSE4_2_Or_ABM): New.
616 (CpuLM): Updated.
617 (i386_cpu_flags): Add cpusse4_2_or_abm.
618
619 * i386-opc.tbl: Use CpuSSE4_2_Or_ABM instead of
620 CpuABM|CpuSSE4_2 on popcnt.
621 * i386-init.h: Regenerated.
622 * i386-tbl.h: Likewise.
623
f2a9c676
L		 6242008-01-02 H.J. Lu <hongjiu.lu@intel.com>
625
626 * i386-opc.h: Update comments.
627
d978b5be
L		 6282008-01-02 H.J. Lu <hongjiu.lu@intel.com>
629
630 * i386-gen.c (opcode_modifiers): Use Qword instead of QWord.
631 * i386-opc.h: Likewise.
632 * i386-opc.tbl: Likewise.
633
582d5edd
L		 6342008-01-02 H.J. Lu <hongjiu.lu@intel.com>
635
636 PR gas/5534
637 * i386-gen.c (opcode_modifiers): Add No_xSuf, CheckSize,
638 Byte, Word, Dword, QWord and Xmmword.
639
640 * i386-opc.h (No_xSuf): New.
641 (CheckSize): Likewise.
642 (Byte): Likewise.
643 (Word): Likewise.
644 (Dword): Likewise.
645 (QWord): Likewise.
646 (Xmmword): Likewise.
647 (FWait): Updated.
648 (i386_opcode_modifier): Add No_xSuf, CheckSize, Byte, Word,
649 Dword, QWord and Xmmword.
650
651 * i386-opc.tbl: Add CheckSize|QWord to movq if IgnoreSize is
652 used.
653 * i386-tbl.h: Regenerated.
654
3fe15143
MK		 6552008-01-02 Mark Kettenis <kettenis@gnu.org>
656
657 * m88k-dis.c (instructions): Fix fcvt.* instructions.
658 From Miod Vallat.
659
6c7ac64e 660For older changes see ChangeLog-2007
252b5132
RH		 661\f
662Local Variables:
2f6d2f85
NC		 663mode: change-log
664left-margin: 8
665fill-column: 74
252b5132
RH		 666version-control: never
667End:
GDB Binutils - Deliverables
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