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Bye Bye PPC_OPCODE_VSX3
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
9a85b496
AM		 12017-04-11 Alan Modra <amodra@gmail.com>
2
9570835e
AM		 3 * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2 and
4 PPC_OPCODE_VSX3.
9a85b496
AM		 5 * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
6 (PPCVEC3): Define as PPC_OPCODE_POWER9.
9570835e
AM		 7 (PPCVSX2): Define as PPC_OPCODE_POWER8.
8 (PPCVSX3): Define as PPC_OPCODE_POWER9.
9a85b496 9
62adc510
AM		 102017-04-10 Alan Modra <amodra@gmail.com>
11
12 * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
13 * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
14 (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
15 removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
16
aa808707
PC		 172017-04-09 Pip Cet <pipcet@gmail.com>
18
19 * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
20 appropriate floating-point precision directly.
21
ac8f0f72
AM		 222017-04-07 Alan Modra <amodra@gmail.com>
23
24 * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
25 lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
26 lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
27 lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
28 vector instructions with E6500 not PPCVEC2.
29
62ecb94c
PC		 302017-04-06 Pip Cet <pipcet@gmail.com>
31
32 * Makefile.am: Add wasm32-dis.c.
33 * configure.ac: Add wasm32-dis.c to wasm32 target.
34 * disassemble.c: Add wasm32 disassembler code.
35 * wasm32-dis.c: New file.
36 * Makefile.in: Regenerate.
37 * configure: Regenerate.
38 * po/POTFILES.in: Regenerate.
39 * po/opcodes.pot: Regenerate.
40
f995bbe8
PA		 412017-04-05 Pedro Alves <palves@redhat.com>
42
43 * arc-dis.c (parse_option, parse_disassembler_options): Constify.
44 * arm-dis.c (parse_arm_disassembler_options): Constify.
45 * ppc-dis.c (powerpc_init_dialect): Constify local.
46 * vax-dis.c (parse_disassembler_options): Constify.
47
b5292032
PD		 482017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
49
50 * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
51 RISCV_GP_SYMBOL.
52
f96bd6c2
PC		 532017-03-30 Pip Cet <pipcet@gmail.com>
54
55 * configure.ac: Add (empty) bfd_wasm32_arch target.
56 * configure: Regenerate
57 * po/opcodes.pot: Regenerate.
58
f7c514a3
JM		 592017-03-29 Sheldon Lobo <sheldon.lobo@oracle.com>
60
61 Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
62 OSA2015.
63 * opcodes/sparc-opc.c (asi_table): New ASIs.
64
52be03fd
AM		 652017-03-29 Alan Modra <amodra@gmail.com>
66
67 * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add
68 "raw" option.
69 (lookup_powerpc): Don't special case -1 dialect. Handle
70 PPC_OPCODE_RAW.
71 (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
72 lookup_powerpc call, pass it on second.
73
9b753937
AM		 742017-03-27 Alan Modra <amodra@gmail.com>
75
76 PR 21303
77 * ppc-dis.c (struct ppc_mopt): Comment.
78 (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
79
c0c31e91
RZ		 802017-03-27 Rinat Zelig <rinat@mellanox.com>
81
82 * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
83 * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
84 F_NPS_M, F_NPS_CORE, F_NPS_ALL.
85 (insert_nps_misc_imm_offset): New function.
86 (extract_nps_misc imm_offset): New function.
87 (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
88 (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
89
2253c8f0
AK		 902017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
91
92 * s390-mkopc.c (main): Remove vx2 check.
93 * s390-opc.txt: Remove vx2 instruction flags.
94
645d3342
RZ		 952017-03-21 Rinat Zelig <rinat@mellanox.com>
96
97 * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
98 * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
99 (insert_nps_imm_offset): New function.
100 (extract_nps_imm_offset): New function.
101 (insert_nps_imm_entry): New function.
102 (extract_nps_imm_entry): New function.
103
4b94dd2d
AM		 1042017-03-17 Alan Modra <amodra@gmail.com>
105
106 PR 21248
107 * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
108 mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after
109 those spr mnemonics they alias. Similarly for mtibatl, mtibatu.
110
b416fe87
KC		 1112017-03-14 Kito Cheng <kito.cheng@gmail.com>
112
113 * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
114 <c.andi>: Likewise.
115 <c.addiw> Likewise.
116
03b039a5
KC		 1172017-03-14 Kito Cheng <kito.cheng@gmail.com>
118
119 * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
120
2c232b83
AW		 1212017-03-13 Andrew Waterman <andrew@sifive.com>
122
123 * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
124 <srl> Likewise.
125 <srai> Likewise.
126 <sra> Likewise.
127
86fa6981
L		 1282017-03-09 H.J. Lu <hongjiu.lu@intel.com>
129
130 * i386-gen.c (opcode_modifiers): Replace S with Load.
131 * i386-opc.h (S): Removed.
132 (Load): New.
133 (i386_opcode_modifier): Replace s with load.
134 * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
135 and {evex}. Replace S with Load.
136 * i386-tbl.h: Regenerated.
137
c1fe188b
L		 1382017-03-09 H.J. Lu <hongjiu.lu@intel.com>
139
140 * i386-opc.tbl: Use CpuCET on rdsspq.
141 * i386-tbl.h: Regenerated.
142
4b8b687e
PB		 1432017-03-08 Peter Bergner <bergner@vnet.ibm.com>
144
145 * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
146 <vsx>: Do not use PPC_OPCODE_VSX3;
147
1437d063
PB		 1482017-03-08 Peter Bergner <bergner@vnet.ibm.com>
149
150 * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
151
603555e5
L		 1522017-03-06 H.J. Lu <hongjiu.lu@intel.com>
153
154 * i386-dis.c (REG_0F1E_MOD_3): New enum.
155 (MOD_0F1E_PREFIX_1): Likewise.
156 (MOD_0F38F5_PREFIX_2): Likewise.
157 (MOD_0F38F6_PREFIX_0): Likewise.
158 (RM_0F1E_MOD_3_REG_7): Likewise.
159 (PREFIX_MOD_0_0F01_REG_5): Likewise.
160 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
161 (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
162 (PREFIX_0F1E): Likewise.
163 (PREFIX_MOD_0_0FAE_REG_5): Likewise.
164 (PREFIX_0F38F5): Likewise.
165 (dis386_twobyte): Use PREFIX_0F1E.
166 (reg_table): Add REG_0F1E_MOD_3.
167 (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
168 PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
169 PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
170 PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
171 (three_byte_table): Use PREFIX_0F38F5.
172 (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
173 Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
174 (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
175 RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
176 PREFIX_MOD_3_0F01_REG_5_RM_2.
177 * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
178 (cpu_flags): Add CpuCET.
179 * i386-opc.h (CpuCET): New enum.
180 (CpuUnused): Commented out.
181 (i386_cpu_flags): Add cpucet.
182 * i386-opc.tbl: Add Intel CET instructions.
183 * i386-init.h: Regenerated.
184 * i386-tbl.h: Likewise.
185
73f07bff
AM		 1862017-03-06 Alan Modra <amodra@gmail.com>
187
188 PR 21124
189 * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
190 (extract_raq, extract_ras, extract_rbx): New functions.
191 (powerpc_operands): Use opposite corresponding insert function.
192 (Q_MASK): Define.
193 (powerpc_opcodes): Apply Q_MASK to all quad insns with even
194 register restriction.
195
65b48a81
PB		 1962017-02-28 Peter Bergner <bergner@vnet.ibm.com>
197
198 * disassemble.c Include "safe-ctype.h".
199 (disassemble_init_for_target): Handle s390 init.
200 (remove_whitespace_and_extra_commas): New function.
201 (disassembler_options_cmp): Likewise.
202 * arm-dis.c: Include "libiberty.h".
203 (NUM_ELEM): Delete.
204 (regnames): Use long disassembler style names.
205 Add force-thumb and no-force-thumb options.
206 (NUM_ARM_REGNAMES): Rename from this...
207 (NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE.
208 (get_arm_regname_num_options): Delete.
209 (set_arm_regname_option): Likewise.
210 (get_arm_regnames): Likewise.
211 (parse_disassembler_options): Likewise.
212 (parse_arm_disassembler_option): Rename from this...
213 (parse_arm_disassembler_options): ...to this. Make static.
214 Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
215 (print_insn): Use parse_arm_disassembler_options.
216 (disassembler_options_arm): New function.
217 (print_arm_disassembler_options): Handle updated regnames.
218 * ppc-dis.c: Include "libiberty.h".
219 (ppc_opts): Add "32" and "64" entries.
220 (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
221 (powerpc_init_dialect): Add break to switch statement.
222 Use new FOR_EACH_DISASSEMBLER_OPTION macro.
223 (disassembler_options_powerpc): New function.
224 (print_ppc_disassembler_options): Use ARRAY_SIZE.
225 Remove printing of "32" and "64".
226 * s390-dis.c: Include "libiberty.h".
227 (init_flag): Remove unneeded variable.
228 (struct s390_options_t): New structure type.
229 (options): New structure.
230 (init_disasm): Rename from this...
231 (disassemble_init_s390): ...to this. Add initializations for
232 current_arch_mask and option_use_insn_len_bits_p. Remove init_flag.
233 (print_insn_s390): Delete call to init_disasm.
234 (disassembler_options_s390): New function.
235 (print_s390_disassembler_options): Print using information from
236 struct 'options'.
237 * po/opcodes.pot: Regenerate.
238
15c7c1d8
JB		 2392017-02-28 Jan Beulich <jbeulich@suse.com>
240
241 * i386-dis.c (PCMPESTR_Fixup): New.
242 (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
243 (prefix_table): Use PCMPESTR_Fixup.
244 (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
245 PCMPESTR_Fixup.
246 (vex_w_table): Delete VPCMPESTR{I,M} entries.
247 * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
248 Split 64-bit and non-64-bit variants.
249 * opcodes/i386-tbl.h: Re-generate.
250
582e12bf
RS		 2512017-02-24 Richard Sandiford <richard.sandiford@arm.com>
252
253 * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
254 (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
255 (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
256 (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
257 (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
258 (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
259 (OP_SVE_V_HSD): New macros.
260 (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
261 (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
262 (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
263 (aarch64_opcode_table): Add new SVE instructions.
264 (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
265 for rotation operands. Add new SVE operands.
266 * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
267 (ins_sve_quad_index): Likewise.
268 (ins_imm_rotate): Split into...
269 (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
270 * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
271 (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
272 functions.
273 (aarch64_ins_sve_addr_ri_s4): New function.
274 (aarch64_ins_sve_quad_index): Likewise.
275 (do_misc_encoding): Handle "MOV Zn.Q, Qm".
276 * aarch64-asm-2.c: Regenerate.
277 * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
278 (ext_sve_quad_index): Likewise.
279 (ext_imm_rotate): Split into...
280 (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
281 * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
282 (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
283 functions.
284 (aarch64_ext_sve_addr_ri_s4): New function.
285 (aarch64_ext_sve_quad_index): Likewise.
286 (aarch64_ext_sve_index): Allow quad indices.
287 (do_misc_decoding): Likewise.
288 * aarch64-dis-2.c: Regenerate.
289 * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
290 aarch64_field_kinds.
291 (OPD_F_OD_MASK): Widen by one bit.
292 (OPD_F_NO_ZR): Bump accordingly.
293 (get_operand_field_width): New function.
294 * aarch64-opc.c (fields): Add new SVE fields.
295 (operand_general_constraint_met_p): Handle new SVE operands.
296 (aarch64_print_operand): Likewise.
297 * aarch64-opc-2.c: Regenerate.
298
f482d304
RS		 2992017-02-24 Richard Sandiford <richard.sandiford@arm.com>
300
301 * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
302 (aarch64_feature_compnum): ...this.
303 (SIMD_V8_3): Replace with...
304 (COMPNUM): ...this.
305 (CNUM_INSN): New macro.
306 (aarch64_opcode_table): Use it for the complex number instructions.
307
7db2c588
JB		 3082017-02-24 Jan Beulich <jbeulich@suse.com>
309
310 * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
311
1e9d41d4
SL		 3122017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
313
314 Add support for associating SPARC ASIs with an architecture level.
315 * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
316 * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
317 decoding of SPARC ASIs.
318
53c4d625
JB		 3192017-02-23 Jan Beulich <jbeulich@suse.com>
320
321 * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
322 82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
323
11648de5
JB		 3242017-02-21 Jan Beulich <jbeulich@suse.com>
325
326 * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
327 1 (instead of to itself). Correct typo.
328
f98d33be
AW		 3292017-02-14 Andrew Waterman <andrew@sifive.com>
330
331 * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
332 pseudoinstructions.
333
773fb663
RS		 3342017-02-15 Richard Sandiford <richard.sandiford@arm.com>
335
336 * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
337 (aarch64_sys_reg_supported_p): Handle them.
338
cc07cda6
CZ		 3392017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
340
341 * arc-opc.c (UIMM6_20R): Define.
342 (SIMM12_20): Use above.
343 (SIMM12_20R): Define.
344 (SIMM3_5_S): Use above.
345 (UIMM7_A32_11R_S): Define.
346 (UIMM7_9_S): Use above.
347 (UIMM3_13R_S): Define.
348 (SIMM11_A32_7_S): Use above.
349 (SIMM9_8R): Define.
350 (UIMM10_A32_8_S): Use above.
351 (UIMM8_8R_S): Define.
352 (W6): Use above.
353 (arc_relax_opcodes): Use all above defines.
354
66a5a740
VG		 3552017-02-15 Vineet Gupta <vgupta@synopsys.com>
356
357 * arc-regs.h: Distinguish some of the registers different on
358 ARC700 and HS38 cpus.
359
7e0de605
AM		 3602017-02-14 Alan Modra <amodra@gmail.com>
361
362 PR 21118
363 * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
364 with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
365
54064fdb
AM		 3662017-02-11 Stafford Horne <shorne@gmail.com>
367 Alan Modra <amodra@gmail.com>
368
369 * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
370 Use insn_bytes_value and insn_int_value directly instead. Don't
371 free allocated memory until function exit.
372
dce75bf9
NP		 3732017-02-10 Nicholas Piggin <npiggin@gmail.com>
374
375 * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
376
1b7e3d2f
NC		 3772017-02-03 Nick Clifton <nickc@redhat.com>
378
379 PR 21096
380 * aarch64-opc.c (print_register_list): Ensure that the register
381 list index will fir into the tb buffer.
382 (print_register_offset_address): Likewise.
383 * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
384
8ec5cf65
AD		 3852017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
386
387 PR 21056
388 * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
389 instructions when the previous fetch packet ends with a 32-bit
390 instruction.
391
a1aa5e81
DD		 3922017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
393
394 * pru-opc.c: Remove vague reference to a future GDB port.
395
add3afb2
NC		 3962017-01-20 Nick Clifton <nickc@redhat.com>
397
398 * po/ga.po: Updated Irish translation.
399
c13a63b0
SN		 4002017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
401
402 * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
403
9608051a
YQ		 4042017-01-13 Yao Qi <yao.qi@linaro.org>
405
406 * m68k-dis.c (match_insn_m68k): Extend comments. Return -1
407 if FETCH_DATA returns 0.
408 (m68k_scan_mask): Likewise.
409 (print_insn_m68k): Update code to handle -1 return value.
410
f622ea96
YQ		 4112017-01-13 Yao Qi <yao.qi@linaro.org>
412
413 * m68k-dis.c (enum print_insn_arg_error): New.
414 (NEXTBYTE): Replace -3 with
415 PRINT_INSN_ARG_MEMORY_ERROR.
416 (NEXTULONG): Likewise.
417 (NEXTSINGLE): Likewise.
418 (NEXTDOUBLE): Likewise.
419 (NEXTDOUBLE): Likewise.
420 (NEXTPACKED): Likewise.
421 (FETCH_ARG): Likewise.
422 (FETCH_DATA): Update comments.
423 (print_insn_arg): Update comments. Replace magic numbers with
424 enum.
425 (match_insn_m68k): Likewise.
426
620214f7
IT		 4272017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
428
429 * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
430 * i386-dis-evex.h (evex_table): Updated.
431 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
432 CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
433 (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
434 * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
435 (i386_cpu_flags): Add cpuavx512_vpopcntdq.
436 * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
437 * i386-init.h: Regenerate.
438 * i386-tbl.h: Ditto.
439
d95014a2
YQ		 4402017-01-12 Yao Qi <yao.qi@linaro.org>
441
442 * msp430-dis.c (msp430_singleoperand): Return -1 if
443 msp430dis_opcode_signed returns false.
444 (msp430_doubleoperand): Likewise.
445 (msp430_branchinstr): Return -1 if
446 msp430dis_opcode_unsigned returns false.
447 (msp430x_calla_instr): Likewise.
448 (print_insn_msp430): Likewise.
449
0ae60c3e
NC		 4502017-01-05 Nick Clifton <nickc@redhat.com>
451
452 PR 20946
453 * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
454 could not be matched.
455 (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
456 NULL.
457
d74d4880
SN		 4582017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
459
460 * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
461 (aarch64_opcode_table): Use RCPC_INSN.
462
cc917fd9
KC		 4632017-01-03 Kito Cheng <kito.cheng@gmail.com>
464
465 * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
466 extension.
467 * riscv-opcodes/all-opcodes: Likewise.
468
b52d3cfc
DP		 4692017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
470
471 * riscv-dis.c (print_insn_args): Add fall through comment.
472
f90c58d5
NC		 4732017-01-03 Nick Clifton <nickc@redhat.com>
474
475 * po/sr.po: New Serbian translation.
476 * configure.ac (ALL_LINGUAS): Add sr.
477 * configure: Regenerate.
478
f47b0d4a
AM		 4792017-01-02 Alan Modra <amodra@gmail.com>
480
481 * epiphany-desc.h: Regenerate.
482 * epiphany-opc.h: Regenerate.
483 * fr30-desc.h: Regenerate.
484 * fr30-opc.h: Regenerate.
485 * frv-desc.h: Regenerate.
486 * frv-opc.h: Regenerate.
487 * ip2k-desc.h: Regenerate.
488 * ip2k-opc.h: Regenerate.
489 * iq2000-desc.h: Regenerate.
490 * iq2000-opc.h: Regenerate.
491 * lm32-desc.h: Regenerate.
492 * lm32-opc.h: Regenerate.
493 * m32c-desc.h: Regenerate.
494 * m32c-opc.h: Regenerate.
495 * m32r-desc.h: Regenerate.
496 * m32r-opc.h: Regenerate.
497 * mep-desc.h: Regenerate.
498 * mep-opc.h: Regenerate.
499 * mt-desc.h: Regenerate.
500 * mt-opc.h: Regenerate.
501 * or1k-desc.h: Regenerate.
502 * or1k-opc.h: Regenerate.
503 * xc16x-desc.h: Regenerate.
504 * xc16x-opc.h: Regenerate.
505 * xstormy16-desc.h: Regenerate.
506 * xstormy16-opc.h: Regenerate.
507
2571583a
AM		 5082017-01-02 Alan Modra <amodra@gmail.com>
509
510 Update year range in copyright notice of all files.
511
5c1ad6b5 512For older changes see ChangeLog-2016
3499769a 513\f
5c1ad6b5 514Copyright (C) 2017 Free Software Foundation, Inc.
3499769a
AM		 515
516Copying and distribution of this file, with or without modification,
517are permitted in any medium without royalty provided the copyright
518notice and this notice are preserved.
519
520Local Variables:
521mode: change-log
522left-margin: 8
523fill-column: 74
524version-control: never
525End:
GDB Binutils - Deliverables
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