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PR27676, PowerPC missing extended dcbt, dcbtst mnemonics
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
97bf40d8
AM		 12021-04-08 Alan Modra <amodra@gmail.com>
2
3 PR 27676
4 * ppc-opc.c (DCBT_EO): Move earlier.
5 (insert_thct, extract_thct, insert_thds, extract_thds): New functions.
6 (powerpc_operands): Add THCT and THDS entries.
7 (powerpc_opcodes): Add dcbtstct, dcbtstds, dcbna, dcbtct, dcbtds.
8
a2e66773
AM		 92021-04-06 Alan Modra <amodra@gmail.com>
10
11 * dis-buf.c (generic_symbol_at_address): Return symbol* NULL.
12 * s12z-dis.c (decode_possible_symbol): Use symbol returned from
13 symbol_at_address_func.
14
ab2af25e
AM		 152021-04-05 Alan Modra <amodra@gmail.com>
16
17 * configure.ac: Don't check for limits.h, string.h, strings.h or
18 stdlib.h.
19 (AC_ISC_POSIX): Don't invoke.
20 * sysdep.h: Include stdlib.h and string.h unconditionally.
21 * i386-opc.h: Include limits.h unconditionally.
22 * wasm32-dis.c: Likewise.
23 * cgen-opc.c: Don't include alloca-conf.h.
24 * config.in: Regenerate.
25 * configure: Regenerate.
26
e9b095a5
ML		 272021-04-01 Martin Liska <mliska@suse.cz>
28
29 * arm-dis.c (strneq): Remove strneq and use startswith.
30 * cr16-dis.c (print_insn_cr16): Likewise.
31 * score-dis.c (streq): Likewise.
32 (strneq): Likewise.
33 * score7-dis.c (strneq): Likewise.
34
1cb108e4
AM		 352021-04-01 Alan Modra <amodra@gmail.com>
36
37 PR 27675
38 * ppc-opc.c (powerpc_opcodes): Add mfummcr2 and mfmmcr2.
39
78933a4a
AM		 402021-03-31 Alan Modra <amodra@gmail.com>
41
42 * sysdep.h (POISON_BFD_BOOLEAN): Define.
43 * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h,
44 * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h,
45 * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c,
46 * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c,
47 * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c,
48 * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c,
49 * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c,
50 * microblaze-dis.h, * micromips-opc.c, * mips-dis.c,
51 * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c,
52 * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c,
53 * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c,
54 * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c,
55 * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false,
56 and TRUE with true throughout.
57
3dfb1b6d
AM		 582021-03-31 Alan Modra <amodra@gmail.com>
59
60 * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h.
61 * aarch64-dis.h: Likewise.
62 * aarch64-opc.c: Likewise.
63 * avr-dis.c: Likewise.
64 * csky-dis.c: Likewise.
65 * nds32-asm.c: Likewise.
66 * nds32-dis.c: Likewise.
67 * nfp-dis.c: Likewise.
68 * riscv-dis.c: Likewise.
69 * s12z-dis.c: Likewise.
70 * wasm32-dis.c: Likewise.
71
5e042380
JB		 722021-03-30 Jan Beulich <jbeulich@suse.com>
73
74 * i386-opc.c (cs, ds, ss, es, fs, gs): Delete.
75 (i386_seg_prefixes): New.
76 * i386-opc.h (cs, ds, ss, es, fs, gs): Delete.
77 (i386_seg_prefixes): Declare.
78
34684862
JB		 792021-03-30 Jan Beulich <jbeulich@suse.com>
80
81 * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Delete.
82
6288d05f
JB		 832021-03-30 Jan Beulich <jbeulich@suse.com>
84
85 * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Adjust values.
86 * i386-reg.tbl (st): Move down.
87 (st(0)): Delete. Extend comment.
88 * i386-tbl.h: Re-generate.
89
bbe1eca6
JB		 902021-03-29 Jan Beulich <jbeulich@suse.com>
91
92 * i386-opc.tbl (movq, movabs): Move next to mov counterparts.
93 (cmpsd): Move next to cmps.
94 (movsd): Move next to movs.
95 (cmpxchg16b): Move to separate section.
96 (fisttp, fisttpll): Likewise.
97 (monitor, mwait): Likewise.
98 * i386-tbl.h: Re-generate.
99
c8cad9d3
JB		 1002021-03-29 Jan Beulich <jbeulich@suse.com>
101
102 * i386-opc.tbl (psadbw): Add <sse2:comm>.
103 (vpsadbw): Add C.
104 * i386-tbl.h: Re-generate.
105
5cdaf100
JB		 1062021-03-29 Jan Beulich <jbeulich@suse.com>
107
108 * i386-opc.tbl (mmx, sse, sse2, sse3, ssse3, sse41, sse42, aes,
109 pclmul, gfni): New templates. Use them wherever possible. Move
110 SSE4.1 pextrw into respective section.
111 * i386-tbl.h: Re-generate.
112
73e45eb2
JB		 1132021-03-29 Jan Beulich <jbeulich@suse.com>
114
115 * i386-gen.c (output_i386_opcode): Widen type of "opcode". Use
116 strtoull(). Bump upper loop bound. Widen masks. Sanity check
117 "length".
118 * i386-opc.tbl (Prefix_0X66, Prefix_0XF2, Prefix_0XF3): Delete.
119 Convert all of their uses to representation in opcode.
120
9df6f676
JB		 1212021-03-29 Jan Beulich <jbeulich@suse.com>
122
123 * i386-opc.h (struct insn_template): Shrink base_opcode to 16
124 bits. Shrink extension_opcode to 9 bits. Make it signed. Change
125 value of None. Shrink operands to 3 bits.
126
389d00a5
JB		 1272021-03-29 Jan Beulich <jbeulich@suse.com>
128
129 * i386-gen.c (process_i386_opcode_modifier): New parameter
130 "space".
131 (output_i386_opcode): New local variable "space". Adjust
132 process_i386_opcode_modifier() invocation.
133 (process_i386_opcodes): Adjust process_i386_opcode_modifier()
134 invocation.
135 * i386-tbl.h: Re-generate.
136
63b4cc53
AM		 1372021-03-29 Alan Modra <amodra@gmail.com>
138
139 * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
140 (fp_qualifier_p, get_data_pattern): Likewise.
141 (aarch64_get_operand_modifier_from_value): Likewise.
142 (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
143 (operand_variant_qualifier_p): Likewise.
144 (qualifier_value_in_range_constraint_p): Likewise.
145 (aarch64_get_qualifier_esize): Likewise.
146 (aarch64_get_qualifier_nelem): Likewise.
147 (aarch64_get_qualifier_standard_value): Likewise.
148 (get_lower_bound, get_upper_bound): Likewise.
149 (aarch64_find_best_match, match_operands_qualifier): Likewise.
150 (aarch64_print_operand): Likewise.
151 * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
152 (operand_need_sign_extension, operand_need_shift_by_two): Likewise.
153 (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
154 * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
155 * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
156 (print_insn_tic6x): Likewise.
157
3d7d6c1b
AM		 1582021-03-29 Alan Modra <amodra@gmail.com>
159
160 * arc-dis.c (extract_operand_value): Correct NULL cast.
161 * frv-opc.h: Regenerate.
162
c3344b62
JB		 1632021-03-26 Jan Beulich <jbeulich@suse.com>
164
165 * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to
166 MMX form.
167 * i386-tbl.h: Re-generate.
168
efa30ac3
HAQ		 1692021-03-25 Abid Qadeer <abidh@codesourcery.com>
170
171 * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
172 immediate in br.n instruction.
173
596a02ff
JB		 1742021-03-25 Jan Beulich <jbeulich@suse.com>
175
176 * i386-dis.c (XMGatherD, VexGatherD): New.
177 (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
178 (print_insn): Check masking for S/G insns.
179 (OP_E_memory): New local variable check_gather. Extend mandatory
180 SIB check. Check register conflicts for (EVEX-encoded) gathers.
181 Extend check for disallowed 16-bit addressing.
182 (OP_VEX): New local variables modrm_reg and sib_index. Convert
183 if()s to switch(). Check register conflicts for (VEX-encoded)
184 gathers. Drop no longer reachable cases.
185 * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
186 vgatherdp*.
187
53642852
JB		 1882021-03-25 Jan Beulich <jbeulich@suse.com>
189
190 * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
191 zeroing-masking without masking.
192
c0e54661
JB		 1932021-03-25 Jan Beulich <jbeulich@suse.com>
194
195 * i386-opc.tbl (invlpgb): Fix multi-operand form.
196 (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
197 single-operand forms as deprecated.
198 * i386-tbl.h: Re-generate.
199
5a403766
AM		 2002021-03-25 Alan Modra <amodra@gmail.com>
201
202 PR 27647
203 * ppc-opc.c (XLOCB_MASK): Delete.
204 (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
205 XLBH_MASK.
206 (powerpc_opcodes): Accept a BH field on all extended forms of
207 bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
208
9a182d04
JB		 2092021-03-24 Jan Beulich <jbeulich@suse.com>
210
211 * i386-gen.c (output_i386_opcode): Drop processing of
212 opcode_length. Calculate length from base_opcode. Adjust prefix
213 encoding determination.
214 (process_i386_opcodes): Drop output of fake opcode_length.
215 * i386-opc.h (struct insn_template): Drop opcode_length field.
216 * i386-opc.tbl: Drop opcode length field from all templates.
217 * i386-tbl.h: Re-generate.
218
35648716
JB		 2192021-03-24 Jan Beulich <jbeulich@suse.com>
220
221 * i386-gen.c (process_i386_opcode_modifier): Return void. New
222 parameter "prefix". Drop local variable "regular_encoding".
223 Record prefix setting / check for consistency.
224 (output_i386_opcode): Parse opcode_length and base_opcode
225 earlier. Derive prefix encoding. Drop no longer applicable
226 consistency checking. Adjust process_i386_opcode_modifier()
227 invocation.
228 (process_i386_opcodes): Adjust process_i386_opcode_modifier()
229 invocation.
230 * i386-tbl.h: Re-generate.
231
31184569
JB		 2322021-03-24 Jan Beulich <jbeulich@suse.com>
233
234 * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
235 check.
236 * i386-opc.h (Prefix_*): Move #define-s.
237 * i386-opc.tbl: Move pseudo prefix enumerator values to
238 extension opcode field. Introduce pseudopfx template.
239 * i386-tbl.h: Re-generate.
240
b933fa4b
JB		 2412021-03-23 Jan Beulich <jbeulich@suse.com>
242
243 * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
244 comment.
245 * i386-tbl.h: Re-generate.
246
dac10fb0
JB		 2472021-03-23 Jan Beulich <jbeulich@suse.com>
248
249 * i386-opc.h (struct insn_template): Move cpu_flags field past
250 opcode_modifier one.
251 * i386-tbl.h: Re-generate.
252
441f6aca
JB		 2532021-03-23 Jan Beulich <jbeulich@suse.com>
254
255 * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
256 * i386-opc.h (OpcodeSpace): New enumerator.
257 (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
258 (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
259 SPACE_XOP09, SPACE_XOP0A): ... respectively.
260 (struct i386_opcode_modifier): New field opcodespace. Shrink
261 opcodeprefix field.
262 i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
263 SpaceXOP09, SpaceXOP0A): Define. Use them to replace
264 OpcodePrefix uses.
265 * i386-tbl.h: Re-generate.
266
08dedd66
ML		 2672021-03-22 Martin Liska <mliska@suse.cz>
268
269 * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
270 * arc-dis.c (parse_option): Likewise.
271 * arm-dis.c (parse_arm_disassembler_options): Likewise.
272 * cris-dis.c (print_with_operands): Likewise.
273 * h8300-dis.c (bfd_h8_disassemble): Likewise.
274 * i386-dis.c (print_insn): Likewise.
275 * ia64-gen.c (fetch_insn_class): Likewise.
276 (parse_resource_users): Likewise.
277 (in_iclass): Likewise.
278 (lookup_specifier): Likewise.
279 (insert_opcode_dependencies): Likewise.
280 * mips-dis.c (parse_mips_ase_option): Likewise.
281 (parse_mips_dis_option): Likewise.
282 * s390-dis.c (disassemble_init_s390): Likewise.
283 * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
284
80d49d6a
KLC		 2852021-03-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
286
287 * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
288
7fce7ea9
PW		 2892021-03-12 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
290
291 * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
292 icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
293
78c84bf9
AM		 2942021-03-12 Alan Modra <amodra@gmail.com>
295
296 * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
297
fd1fd061
JB		 2982021-03-11 Jan Beulich <jbeulich@suse.com>
299
300 * i386-dis.c (OP_XMM): Re-order checks.
301
ac7a2311
JB		 3022021-03-11 Jan Beulich <jbeulich@suse.com>
303
304 * i386-dis.c (putop): Drop need_vex check when also checking
305 vex.evex.
306 (intel_operand_size, OP_E_memory): Drop vex.evex check when also
307 checking vex.b.
308
da944c8a
JB		 3092021-03-11 Jan Beulich <jbeulich@suse.com>
310
311 * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
312 checks. Move case label past broadcast check.
313
b763d508
JB		 3142021-03-10 Jan Beulich <jbeulich@suse.com>
315
316 * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
317 vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
318 REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
319 EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
320 EVEX_W_0F38C7_M_0_L_2): Delete.
321 (REG_EVEX_0F38C7_M_0_L_2): New.
322 (intel_operand_size): Handle VEX and EVEX the same for
323 vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
324 vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
325 (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
326 vex_vsib_q_w_d_mode uses.
327 * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
328 0F38A1, and 0F38A3 entries.
329 * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
330 entry.
331 * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
332 * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
333 0F38A3 entries.
334
32e31ad7
JB		 3352021-03-10 Jan Beulich <jbeulich@suse.com>
336
337 * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
338 REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
339 MOD_VEX_0FXOP_09_12): Rename to ...
340 (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
341 REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
342 (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
343 RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
344 X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
345 X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
346 (reg_table): Adjust comments.
347 (x86_64_table): Move X86_64_0F24, X86_64_0F26,
348 X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
349 X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
350 (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
351 (vex_len_table): Adjust opcode 0A_12 entry.
352 (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
353 MOD_C5_32BIT, and MOD_XOP_09_12 entries.
354 (rm_table): Move hreset entry.
355
85ba7507
JB		 3562021-03-10 Jan Beulich <jbeulich@suse.com>
357
358 * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
359 EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
360 EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
361 EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
362 EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
363 (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
364 (get_valid_dis386): Also handle 512-bit vector length when
365 vectoring into vex_len_table[].
366 * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
367 0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
368 entries.
369 * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
370 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
371 * i386-dis-evex-prefix.h: Adjust 0F7E entry.
372 * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
373 entries.
374
066f82b9
JB		 3752021-03-10 Jan Beulich <jbeulich@suse.com>
376
377 * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
378 Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
379 EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
380 * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
381 entries.
382 * i386-dis-evex-len.h (evex_len_table): Likewise.
383 * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
384
fc681dd6
JB		 3852021-03-10 Jan Beulich <jbeulich@suse.com>
386
387 * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
388 MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
389 MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
390 MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
391 MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
392 MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
393 MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
394 MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
395 EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
396 EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
397 EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
398 EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
399 EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
400 EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
401 EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
402 EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
403 EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
404 EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
405 EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
406 EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
407 EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
408 EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
409 EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
410 EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
411 EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
412 EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
413 EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
414 EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
415 EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
416 EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
417 EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
418 EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
419 REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
420 REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
421 MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
422 MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
423 EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
424 EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
425 EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
426 EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
427 EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
428 EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
429 EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
430 EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
431 EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
432 EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
433 EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
434 EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
435 EVEX_W_0F3A43_L_n): New.
436 * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
437 0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
438 0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
439 * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
440 for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
441 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
442 0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
443 * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
444 0F385B, 0F38C6, and 0F38C7 entries.
445 * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
446 0F38C6 and 0F38C7.
447 * i386-dis-evex-w.h: No longer link to evex_len_table[] for
448 opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
449 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
450 evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
451
13954a31
JB		 4522021-03-10 Jan Beulich <jbeulich@suse.com>
453
454 * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
455 MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
456 MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
457 MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
458 MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
459 MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
460 MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
461 MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
462 MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
463 MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
464 MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
465 MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
466 MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
467 MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
468 MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
469 MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
470 MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
471 MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
472 MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
473 MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
474 MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
475 MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
476 MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
477 MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
478 MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
479 PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
480 PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
481 PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
482 PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
483 PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
484 VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
485 VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
486 VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
487 VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
488 VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
489 VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
490 VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
491 VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
492 VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
493 VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
494 VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
495 VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
496 VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
497 VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
498 VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
499 VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
500 VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
501 VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
502 VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
503 VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
504 VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
505 VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
506 VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
507 VEX_W_0F99_P_2_LEN_0): Delete.
508 MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
509 MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
510 MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
511 MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
512 MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
513 PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
514 PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
515 PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
516 PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
517 PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
518 PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
519 PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
520 PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
521 PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
522 PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
523 PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
524 PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
525 PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
526 PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
527 VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
528 VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
529 VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
530 VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
531 VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
532 VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
533 VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
534 VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
535 (prefix_table): No longer link to vex_len_table[] for opcodes
536 0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
537 0F92, 0F93, 0F98, and 0F99.
538 (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
539 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
540 0F98, and 0F99.
541 (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
542 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
543 0F98, and 0F99.
544 (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
545 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
546 0F98, and 0F99.
547 (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
548 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
549 0F98, and 0F99.
550
14d10c6c
JB		 5512021-03-10 Jan Beulich <jbeulich@suse.com>
552
553 * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
554 Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
555 REG_VEX_0F73_M_0 respectively.
556 (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
557 MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
558 MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
559 MOD_VEX_0F73_REG_7): Delete.
560 (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
561 (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
562 PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
563 PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
564 PREFIX_VEX_0F3AF0_L_0 respectively.
565 (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
566 VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
567 VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
568 VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
569 (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
570 VEX_LEN_0F38F7): New.
571 (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
572 (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
573 0F72, and 0F73. No longer link to vex_len_table[] for opcode
574 0F38F3.
575 (prefix_table): No longer link to vex_len_table[] for opcodes
576 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
577 (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
578 0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
579 0F38F6, 0F38F7, and 0F3AF0.
580 (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
581 prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
582 (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
583 0F73.
584
00ec1875
JB		 5852021-03-10 Jan Beulich <jbeulich@suse.com>
586
587 * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
588 REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
589 (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
590 MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
591 MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
592 (MOD_0F71, MOD_0F72, MOD_0F73): New.
593 (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
594 73.
595 (reg_table): No longer link to mod_table[] for opcodes 0F71,
596 0F72, and 0F73.
597 (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
598 0F73.
599
31941983
JB		 6002021-03-10 Jan Beulich <jbeulich@suse.com>
601
602 * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
603 MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
604 (reg_table): Don't link to mod_table[] where not needed. Add
605 PREFIX_IGNORED to nop entries.
606 (prefix_table): Replace PREFIX_OPCODE in nop entries.
607 (mod_table): Add nop entries next to prefetch ones. Drop
608 MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
609 MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
610 (rm_table): Add PREFIX_IGNORED to nop entries. Drop
611 PREFIX_OPCODE from endbr* entries.
612 (get_valid_dis386): Also consider entry's name when zapping
613 vindex.
614 (print_insn): Handle PREFIX_IGNORED.
615
742732c7
JB		 6162021-03-09 Jan Beulich <jbeulich@suse.com>
617
618 * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
619 IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
620 element.
621 * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
622 HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
623 (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
624 PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
625 (struct i386_opcode_modifier): Delete notrackprefixok,
626 islockable, hleprefixok, and repprefixok fields. Add prefixok
627 field.
628 * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
629 HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
630 (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
631 not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
632 Replace HLEPrefixOk.
633 * opcodes/i386-tbl.h: Re-generate.
634
e93a3b27
JB		 6352021-03-09 Jan Beulich <jbeulich@suse.com>
636
637 * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
638 * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
639 64-bit form.
640 * opcodes/i386-tbl.h: Re-generate.
641
75363b6d
JB		 6422021-03-03 Jan Beulich <jbeulich@suse.com>
643
644 * i386-gen.c (output_i386_opcode): Don't get operand count. Look
645 for {} instead of {0}. Don't look for '0'.
646 * i386-opc.tbl: Drop operand count field. Drop redundant operand
647 size specifiers.
648
5a9f5403
NC		 6492021-02-19 Nelson Chu <nelson.chu@sifive.com>
650
651 PR 27158
652 * riscv-dis.c (print_insn_args): Updated encoding macros.
653 * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
654 (match_c_addi16sp): Updated encoding macros.
655 (match_c_lui): Likewise.
656 (match_c_lui_with_hint): Likewise.
657 (match_c_addi4spn): Likewise.
658 (match_c_slli): Likewise.
659 (match_slli_as_c_slli): Likewise.
660 (match_c_slli64): Likewise.
661 (match_srxi_as_c_srxi): Likewise.
662 (riscv_insn_types): Added .insn css/cl/cs.
663
3d73d29e
NC		 6642021-02-18 Nelson Chu <nelson.chu@sifive.com>
665
666 * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
667 (default_priv_spec): Updated type to riscv_spec_class.
668 (parse_riscv_dis_option): Updated.
669 * riscv-opc.c: Moved stuff and make the file tidy.
670
b9b204b3
AM		 6712021-02-17 Alan Modra <amodra@gmail.com>
672
673 * wasm32-dis.c: Include limits.h.
674 (CHAR_BIT): Provide backup define.
675 (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
676 Correct signed overflow checking.
677
394ae71f
JB		 6782021-02-16 Jan Beulich <jbeulich@suse.com>
679
680 * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
681 * i386-tbl.h: Re-generate.
682
b818b220
JB		 6832021-02-16 Jan Beulich <jbeulich@suse.com>
684
685 * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
686 Oword.
687 * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
688
ba2b480f
AK		 6892021-02-15 Andreas Krebbel <krebbel@linux.ibm.com>
690
691 * s390-mkopc.c (main): Accept arch14 as cpu string.
692 * s390-opc.txt: Add new arch14 instructions.
693
95148614
NA		 6942021-02-04 Nick Alcock <nick.alcock@oracle.com>
695
696 * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
697 favour of LIBINTL.
698 * configure: Regenerated.
699
bfd428bc
MF		 7002021-02-08 Mike Frysinger <vapier@gentoo.org>
701
702 * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
703 * tic54x-opc.c (regs): Rename to ...
704 (tic54x_regs): ... this.
705 (mmregs): Rename to ...
706 (tic54x_mmregs): ... this.
707 (condition_codes): Rename to ...
708 (tic54x_condition_codes): ... this.
709 (cc2_codes): Rename to ...
710 (tic54x_cc2_codes): ... this.
711 (cc3_codes): Rename to ...
712 (tic54x_cc3_codes): ... this.
713 (status_bits): Rename to ...
714 (tic54x_status_bits): ... this.
715 (misc_symbols): Rename to ...
716 (tic54x_misc_symbols): ... this.
717
24075dcc
NC		 7182021-02-04 Nelson Chu <nelson.chu@sifive.com>
719
720 * riscv-opc.c (MASK_RVB_IMM): Removed.
721 (riscv_opcodes): Removed zb* instructions.
722 (riscv_ext_version_table): Removed versions for zb*.
723
c3ffb8f3
AM		 7242021-01-26 Alan Modra <amodra@gmail.com>
725
726 * i386-gen.c (parse_template): Ensure entire template_instance
727 is initialised.
728
1942a048
NC		 7292021-01-15 Nelson Chu <nelson.chu@sifive.com>
730
731 * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
732 (riscv_fpr_names_abi): Likewise.
733 (riscv_opcodes): Likewise.
734 (riscv_insn_types): Likewise.
735
b800637e
NC		 7362021-01-15 Nelson Chu <nelson.chu@sifive.com>
737
738 * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
739
dcd709e0
NC		 7402021-01-15 Nelson Chu <nelson.chu@sifive.com>
741
742 * riscv-dis.c: Comments tidy and improvement.
743 * riscv-opc.c: Likewise.
744
5347ed60
AM		 7452021-01-13 Alan Modra <amodra@gmail.com>
746
747 * Makefile.in: Regenerate.
748
d546b610
L		 7492021-01-12 H.J. Lu <hongjiu.lu@intel.com>
750
751 PR binutils/26792
752 * configure.ac: Use GNU_MAKE_JOBSERVER.
753 * aclocal.m4: Regenerated.
754 * configure: Likewise.
755
6d104cac
NC		 7562021-01-12 Nick Clifton <nickc@redhat.com>
757
758 * po/sr.po: Updated Serbian translation.
759
83b33c6c
L		 7602021-01-11 H.J. Lu <hongjiu.lu@intel.com>
761
762 PR ld/27173
763 * configure: Regenerated.
764
82c70b08
KT		 7652021-01-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
766
767 * aarch64-asm-2.c: Regenerate.
768 * aarch64-dis-2.c: Likewise.
769 * aarch64-opc-2.c: Likewise.
770 * aarch64-opc.c (aarch64_print_operand):
771 Delete handling of AARCH64_OPND_CSRE_CSR.
772 * aarch64-tbl.h (aarch64_feature_csre): Delete.
773 (CSRE): Likewise.
774 (_CSRE_INSN): Likewise.
775 (aarch64_opcode_table): Delete csr.
776
a8aa72b9
NC		 7772021-01-11 Nick Clifton <nickc@redhat.com>
778
779 * po/de.po: Updated German translation.
780 * po/fr.po: Updated French translation.
781 * po/pt_BR.po: Updated Brazilian Portuguese translation.
782 * po/sv.po: Updated Swedish translation.
783 * po/uk.po: Updated Ukranian translation.
784
a4966cd9
L		 7852021-01-09 H.J. Lu <hongjiu.lu@intel.com>
786
787 * configure: Regenerated.
788
573fe3fb
NC		 7892021-01-09 Nick Clifton <nickc@redhat.com>
790
791 * configure: Regenerate.
792 * po/opcodes.pot: Regenerate.
793
055bc77a
NC		 7942021-01-09 Nick Clifton <nickc@redhat.com>
795
796 * 2.36 release branch crated.
797
aae7fcb8
PB		 7982021-01-08 Peter Bergner <bergner@linux.ibm.com>
799
800 * ppc-opc.c (insert_dw, (extract_dw): New functions.
801 (DW, (XRC_MASK): Define.
802 (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
803
64307045
AM		 8042021-01-09 Alan Modra <amodra@gmail.com>
805
806 * configure: Regenerate.
807
ed205222
NC		 8082021-01-08 Nick Clifton <nickc@redhat.com>
809
810 * po/sv.po: Updated Swedish translation.
811
fb932b57
NC		 8122021-01-08 Nick Clifton <nickc@redhat.com>
813
e84c8716
NC		 814 PR 27129
815 * aarch64-dis.c (determine_disassembling_preference): Move call to
816 aarch64_match_operands_constraint outside of the assertion.
817 * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
818 Replace with a return of FALSE.
819
fb932b57
NC		 820 PR 27139
821 * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
822 core system register.
823
f4782128
ST		 8242021-01-07 Samuel Thibault <samuel.thibault@gnu.org>
825
826 * configure: Regenerate.
827
1b0927db
NC		 8282021-01-07 Nick Clifton <nickc@redhat.com>
829
830 * po/fr.po: Updated French translation.
831
3b288c8e
FN		 8322021-01-07 Fredrik Noring <noring@nocrew.org>
833
834 * m68k-opc.c (chkl): Change minimum architecture requirement to
835 m68020.
836
aa881ecd
PT		 8372021-01-07 Philipp Tomsich <prt@gnu.org>
838
839 * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
840
2652cfad
CXW		 8412021-01-07 Claire Xenia Wolf <claire@symbioticeda.com>
842 Jim Wilson <jimw@sifive.com>
843 Andrew Waterman <andrew@sifive.com>
844 Maxim Blinov <maxim.blinov@embecosm.com>
845 Kito Cheng <kito.cheng@sifive.com>
846 Nelson Chu <nelson.chu@sifive.com>
847
848 * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
849 (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
850
250d07de
AM		 8512021-01-01 Alan Modra <amodra@gmail.com>
852
853 Update year range in copyright notice of all files.
854
c2795844 855For older changes see ChangeLog-2020
3499769a 856\f
c2795844 857Copyright (C) 2021 Free Software Foundation, Inc.
3499769a
AM		 858
859Copying and distribution of this file, with or without modification,
860are permitted in any medium without royalty provided the copyright
861notice and this notice are preserved.
862
863Local Variables:
864mode: change-log
865left-margin: 8
866fill-column: 74
867version-control: never
868End:
GDB Binutils - Deliverables
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