projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
xfail pr20022.d on targets without dynamic relocs in .text
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
db5fa770
NC		 12017-06-14 Nick Clifton <nickc@redhat.com>
2
3 PR binutils/21587
4 * rx-decode.opc: Include libiberty.h
5 (GET_SCALE): New macro - validates access to SCALE array.
6 (GET_PSCALE): New macro - validates access to PSCALE array.
7 (DIs, SIs, S2Is, rx_disp): Use new macros.
8 * rx-decode.c: Regenerate.
9
05c966f3
AV		 102017-07-14 Andre Vieira <andre.simoesdiasvieira@arm.com>
11
12 * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
13
10045478
AK		 142017-05-30 Anton Kolesov <anton.kolesov@synopsys.com>
15
16 * arc-dis.c (enforced_isa_mask): Declare.
17 (cpu_types): Likewise.
18 (parse_cpu_option): New function.
19 (parse_disassembler_options): Use it.
20 (print_insn_arc): Use enforced_isa_mask.
21 (print_arc_disassembler_options): Document new options.
22
88c1242d
YQ		 232017-05-24 Yao Qi <yao.qi@linaro.org>
24
25 * alpha-dis.c: Include disassemble.h, don't include
26 dis-asm.h.
27 * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
28 * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
29 * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
30 * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
31 * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
32 * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
33 * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
34 * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
35 * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
36 * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
37 * moxie-dis.c, msp430-dis.c, mt-dis.c:
38 * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
39 * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
40 * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
41 * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
42 * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
43 * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
44 * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
45 * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
46 * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
47 * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
48 * z80-dis.c, z8k-dis.c: Likewise.
49 * disassemble.h: New file.
50
ab20fa4a
YQ		 512017-05-24 Yao Qi <yao.qi@linaro.org>
52
53 * rl78-dis.c (rl78_get_disassembler): If parameter abfd
54 is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
55
003ca0fd
YQ		 562017-05-24 Yao Qi <yao.qi@linaro.org>
57
58 * disassemble.c (disassembler): Add arguments a, big and mach.
59 Use them.
60
04ef582a
L		 612017-05-22 H.J. Lu <hongjiu.lu@intel.com>
62
63 * i386-dis.c (NOTRACK_Fixup): New.
64 (NOTRACK): Likewise.
65 (NOTRACK_PREFIX): Likewise.
66 (last_active_prefix): Likewise.
67 (reg_table): Use NOTRACK on indirect call and jmp.
68 (ckprefix): Set last_active_prefix.
69 (prefix_name): Return "notrack" for NOTRACK_PREFIX.
70 * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
71 * i386-opc.h (NoTrackPrefixOk): New.
72 (i386_opcode_modifier): Add notrackprefixok.
73 * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
74 Add notrack.
75 * i386-tbl.h: Regenerated.
76
64517994
JM		 772017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
78
79 * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
80 (X_IMM2): Define.
81 (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
82 bfd_mach_sparc_v9m8.
83 (print_insn_sparc): Handle new operand types.
84 * sparc-opc.c (MASK_M8): Define.
85 (v6): Add MASK_M8.
86 (v6notlet): Likewise.
87 (v7): Likewise.
88 (v8): Likewise.
89 (v9): Likewise.
90 (v9a): Likewise.
91 (v9b): Likewise.
92 (v9c): Likewise.
93 (v9d): Likewise.
94 (v9e): Likewise.
95 (v9v): Likewise.
96 (v9m): Likewise.
97 (v9andleon): Likewise.
98 (m8): Define.
99 (HWS_VM8): Define.
100 (HWS2_VM8): Likewise.
101 (sparc_opcode_archs): Add entry for "m8".
102 (sparc_opcodes): Add OSA2017 and M8 instructions
103 dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
104 fpx{ll,ra,rl}64x,
105 ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
106 ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
107 revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
108 stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
109 (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
110 ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
111 ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
112 ASI_CORE_SELECT_COMMIT_NHT.
113
535b785f
AM		 1142017-05-18 Alan Modra <amodra@gmail.com>
115
116 * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
117 * aarch64-dis.c: Likewise.
118 * aarch64-gen.c: Likewise.
119 * aarch64-opc.c: Likewise.
120
25499ac7
MR		 1212017-05-15 Maciej W. Rozycki <macro@imgtec.com>
122 Matthew Fortune <matthew.fortune@imgtec.com>
123
124 * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
125 ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
126 (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
127 (print_insn_arg) <OP_REG28>: Add handler.
128 (validate_insn_args) <OP_REG28>: Handle.
129 (print_mips16_insn_arg): Handle MIPS16 instructions that require
130 32-bit encoding and 9-bit immediates.
131 (print_insn_mips16): Handle MIPS16 instructions that require
132 32-bit encoding and MFC0/MTC0 operand decoding.
133 * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
134 <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
135 (RD_C0, WR_C0, E2, E2MT): New macros.
136 (mips16_opcodes): Add entries for MIPS16e2 instructions:
137 GP-relative "addiu" and its "addu" spelling, "andi", "cache",
138 "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
139 "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
140 "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
141 "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
142 instructions, "swl", "swr", "sync" and its "sync_acquire",
143 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
144 "xori", "dmt", "dvpe", "emt" and "evpe". Add split
145 regular/extended entries for original MIPS16 ISA revision
146 instructions whose extended forms are subdecoded in the MIPS16e2
147 ISA revision: "li", "sll" and "srl".
148
fdfb4752
MR		 1492017-05-15 Maciej W. Rozycki <macro@imgtec.com>
150
151 * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
152 reference in CP0 move operand decoding.
153
a4f89915
MR		 1542017-05-12 Maciej W. Rozycki <macro@imgtec.com>
155
156 * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
157 type to hexadecimal.
158 (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
159
99e2d67a
MR		 1602017-05-11 Maciej W. Rozycki <macro@imgtec.com>
161
162 * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
163 "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
164 "sync_rmb" and "sync_wmb" as aliases.
165 * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
166 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
167
53a346d8
CZ		 1682017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
169
170 * arc-dis.c (parse_option): Update quarkse_em option..
171 * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
172 QUARKSE1.
173 (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
174
f91d48de
KC		 1752017-05-03 Kito Cheng <kito.cheng@gmail.com>
176
177 * riscv-dis.c (print_insn_args): Handle 'Co' operands.
178
43e379d7
MC		 1792017-05-01 Michael Clark <michaeljclark@mac.com>
180
181 * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
182 register.
183
a4ddc54e
MR		 1842017-05-02 Maciej W. Rozycki <macro@imgtec.com>
185
186 * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
187 and branches and not synthetic data instructions.
188
fe50e98c
BE		 1892017-05-02 Bernd Edlinger <bernd.edlinger@hotmail.de>
190
191 * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
192
126124cc
CZ		 1932017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
194
195 * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
196 * arc-opc.c (insert_r13el): New function.
197 (R13_EL): Define.
198 * arc-tbl.h: Add new enter/leave variants.
199
be6a24d8
CZ		 2002017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
201
202 * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
203
0348fd79
MR		 2042017-04-25 Maciej W. Rozycki <macro@imgtec.com>
205
206 * mips-dis.c (print_mips_disassembler_options): Add
207 `no-aliases'.
208
6e3d1f07
MR		 2092017-04-25 Maciej W. Rozycki <macro@imgtec.com>
210
211 * mips16-opc.c (AL): New macro.
212 (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
213 of "ld" and "lw" as aliases.
214
957f6b39
TC		 2152017-04-24 Tamar Christina <tamar.christina@arm.com>
216
217 * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
218 arguments.
219
a8cc8a54
AM		 2202017-04-22 Alexander Fedotov <alfedotov@gmail.com>
221 Alan Modra <amodra@gmail.com>
222
223 * ppc-opc.c (ELEV): Define.
224 (vle_opcodes): Add se_rfgi and e_sc.
225 (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
226 for E200Z4.
227
3ab87b68
JM		 2282017-04-21 Jose E. Marchesi <jose.marchesi@oracle.com>
229
230 * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
231
792f174f
NC		 2322017-04-21 Nick Clifton <nickc@redhat.com>
233
234 PR binutils/21380
235 * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
236 LD3R and LD4R.
237
42742084
AM		 2382017-04-13 Alan Modra <amodra@gmail.com>
239
240 * epiphany-desc.c: Regenerate.
241 * fr30-desc.c: Regenerate.
242 * frv-desc.c: Regenerate.
243 * ip2k-desc.c: Regenerate.
244 * iq2000-desc.c: Regenerate.
245 * lm32-desc.c: Regenerate.
246 * m32c-desc.c: Regenerate.
247 * m32r-desc.c: Regenerate.
248 * mep-desc.c: Regenerate.
249 * mt-desc.c: Regenerate.
250 * or1k-desc.c: Regenerate.
251 * xc16x-desc.c: Regenerate.
252 * xstormy16-desc.c: Regenerate.
253
9a85b496
AM		 2542017-04-11 Alan Modra <amodra@gmail.com>
255
ef85eab0 256 * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
c03dc33b
AM		 257 PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm". Formatting. Set
258 PPC_OPCODE_TMR for e6500.
9a85b496
AM		 259 * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
260 (PPCVEC3): Define as PPC_OPCODE_POWER9.
9570835e
AM		 261 (PPCVSX2): Define as PPC_OPCODE_POWER8.
262 (PPCVSX3): Define as PPC_OPCODE_POWER9.
ef85eab0 263 (PPCHTM): Define as PPC_OPCODE_POWER8.
c03dc33b 264 (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
9a85b496 265
62adc510
AM		 2662017-04-10 Alan Modra <amodra@gmail.com>
267
268 * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
269 * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
270 (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
271 removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
272
aa808707
PC		 2732017-04-09 Pip Cet <pipcet@gmail.com>
274
275 * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
276 appropriate floating-point precision directly.
277
ac8f0f72
AM		 2782017-04-07 Alan Modra <amodra@gmail.com>
279
280 * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
281 lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
282 lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
283 lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
284 vector instructions with E6500 not PPCVEC2.
285
62ecb94c
PC		 2862017-04-06 Pip Cet <pipcet@gmail.com>
287
288 * Makefile.am: Add wasm32-dis.c.
289 * configure.ac: Add wasm32-dis.c to wasm32 target.
290 * disassemble.c: Add wasm32 disassembler code.
291 * wasm32-dis.c: New file.
292 * Makefile.in: Regenerate.
293 * configure: Regenerate.
294 * po/POTFILES.in: Regenerate.
295 * po/opcodes.pot: Regenerate.
296
f995bbe8
PA		 2972017-04-05 Pedro Alves <palves@redhat.com>
298
299 * arc-dis.c (parse_option, parse_disassembler_options): Constify.
300 * arm-dis.c (parse_arm_disassembler_options): Constify.
301 * ppc-dis.c (powerpc_init_dialect): Constify local.
302 * vax-dis.c (parse_disassembler_options): Constify.
303
b5292032
PD		 3042017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
305
306 * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
307 RISCV_GP_SYMBOL.
308
f96bd6c2
PC		 3092017-03-30 Pip Cet <pipcet@gmail.com>
310
311 * configure.ac: Add (empty) bfd_wasm32_arch target.
312 * configure: Regenerate
313 * po/opcodes.pot: Regenerate.
314
f7c514a3
JM		 3152017-03-29 Sheldon Lobo <sheldon.lobo@oracle.com>
316
317 Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
318 OSA2015.
319 * opcodes/sparc-opc.c (asi_table): New ASIs.
320
52be03fd
AM		 3212017-03-29 Alan Modra <amodra@gmail.com>
322
323 * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add
324 "raw" option.
325 (lookup_powerpc): Don't special case -1 dialect. Handle
326 PPC_OPCODE_RAW.
327 (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
328 lookup_powerpc call, pass it on second.
329
9b753937
AM		 3302017-03-27 Alan Modra <amodra@gmail.com>
331
332 PR 21303
333 * ppc-dis.c (struct ppc_mopt): Comment.
334 (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
335
c0c31e91
RZ		 3362017-03-27 Rinat Zelig <rinat@mellanox.com>
337
338 * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
339 * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
340 F_NPS_M, F_NPS_CORE, F_NPS_ALL.
341 (insert_nps_misc_imm_offset): New function.
342 (extract_nps_misc imm_offset): New function.
343 (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
344 (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
345
2253c8f0
AK		 3462017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
347
348 * s390-mkopc.c (main): Remove vx2 check.
349 * s390-opc.txt: Remove vx2 instruction flags.
350
645d3342
RZ		 3512017-03-21 Rinat Zelig <rinat@mellanox.com>
352
353 * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
354 * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
355 (insert_nps_imm_offset): New function.
356 (extract_nps_imm_offset): New function.
357 (insert_nps_imm_entry): New function.
358 (extract_nps_imm_entry): New function.
359
4b94dd2d
AM		 3602017-03-17 Alan Modra <amodra@gmail.com>
361
362 PR 21248
363 * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
364 mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after
365 those spr mnemonics they alias. Similarly for mtibatl, mtibatu.
366
b416fe87
KC		 3672017-03-14 Kito Cheng <kito.cheng@gmail.com>
368
369 * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
370 <c.andi>: Likewise.
371 <c.addiw> Likewise.
372
03b039a5
KC		 3732017-03-14 Kito Cheng <kito.cheng@gmail.com>
374
375 * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
376
2c232b83
AW		 3772017-03-13 Andrew Waterman <andrew@sifive.com>
378
379 * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
380 <srl> Likewise.
381 <srai> Likewise.
382 <sra> Likewise.
383
86fa6981
L		 3842017-03-09 H.J. Lu <hongjiu.lu@intel.com>
385
386 * i386-gen.c (opcode_modifiers): Replace S with Load.
387 * i386-opc.h (S): Removed.
388 (Load): New.
389 (i386_opcode_modifier): Replace s with load.
390 * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
391 and {evex}. Replace S with Load.
392 * i386-tbl.h: Regenerated.
393
c1fe188b
L		 3942017-03-09 H.J. Lu <hongjiu.lu@intel.com>
395
396 * i386-opc.tbl: Use CpuCET on rdsspq.
397 * i386-tbl.h: Regenerated.
398
4b8b687e
PB		 3992017-03-08 Peter Bergner <bergner@vnet.ibm.com>
400
401 * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
402 <vsx>: Do not use PPC_OPCODE_VSX3;
403
1437d063
PB		 4042017-03-08 Peter Bergner <bergner@vnet.ibm.com>
405
406 * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
407
603555e5
L		 4082017-03-06 H.J. Lu <hongjiu.lu@intel.com>
409
410 * i386-dis.c (REG_0F1E_MOD_3): New enum.
411 (MOD_0F1E_PREFIX_1): Likewise.
412 (MOD_0F38F5_PREFIX_2): Likewise.
413 (MOD_0F38F6_PREFIX_0): Likewise.
414 (RM_0F1E_MOD_3_REG_7): Likewise.
415 (PREFIX_MOD_0_0F01_REG_5): Likewise.
416 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
417 (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
418 (PREFIX_0F1E): Likewise.
419 (PREFIX_MOD_0_0FAE_REG_5): Likewise.
420 (PREFIX_0F38F5): Likewise.
421 (dis386_twobyte): Use PREFIX_0F1E.
422 (reg_table): Add REG_0F1E_MOD_3.
423 (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
424 PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
425 PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
426 PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
427 (three_byte_table): Use PREFIX_0F38F5.
428 (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
429 Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
430 (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
431 RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
432 PREFIX_MOD_3_0F01_REG_5_RM_2.
433 * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
434 (cpu_flags): Add CpuCET.
435 * i386-opc.h (CpuCET): New enum.
436 (CpuUnused): Commented out.
437 (i386_cpu_flags): Add cpucet.
438 * i386-opc.tbl: Add Intel CET instructions.
439 * i386-init.h: Regenerated.
440 * i386-tbl.h: Likewise.
441
73f07bff
AM		 4422017-03-06 Alan Modra <amodra@gmail.com>
443
444 PR 21124
445 * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
446 (extract_raq, extract_ras, extract_rbx): New functions.
447 (powerpc_operands): Use opposite corresponding insert function.
448 (Q_MASK): Define.
449 (powerpc_opcodes): Apply Q_MASK to all quad insns with even
450 register restriction.
451
65b48a81
PB		 4522017-02-28 Peter Bergner <bergner@vnet.ibm.com>
453
454 * disassemble.c Include "safe-ctype.h".
455 (disassemble_init_for_target): Handle s390 init.
456 (remove_whitespace_and_extra_commas): New function.
457 (disassembler_options_cmp): Likewise.
458 * arm-dis.c: Include "libiberty.h".
459 (NUM_ELEM): Delete.
460 (regnames): Use long disassembler style names.
461 Add force-thumb and no-force-thumb options.
462 (NUM_ARM_REGNAMES): Rename from this...
463 (NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE.
464 (get_arm_regname_num_options): Delete.
465 (set_arm_regname_option): Likewise.
466 (get_arm_regnames): Likewise.
467 (parse_disassembler_options): Likewise.
468 (parse_arm_disassembler_option): Rename from this...
469 (parse_arm_disassembler_options): ...to this. Make static.
470 Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
471 (print_insn): Use parse_arm_disassembler_options.
472 (disassembler_options_arm): New function.
473 (print_arm_disassembler_options): Handle updated regnames.
474 * ppc-dis.c: Include "libiberty.h".
475 (ppc_opts): Add "32" and "64" entries.
476 (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
477 (powerpc_init_dialect): Add break to switch statement.
478 Use new FOR_EACH_DISASSEMBLER_OPTION macro.
479 (disassembler_options_powerpc): New function.
480 (print_ppc_disassembler_options): Use ARRAY_SIZE.
481 Remove printing of "32" and "64".
482 * s390-dis.c: Include "libiberty.h".
483 (init_flag): Remove unneeded variable.
484 (struct s390_options_t): New structure type.
485 (options): New structure.
486 (init_disasm): Rename from this...
487 (disassemble_init_s390): ...to this. Add initializations for
488 current_arch_mask and option_use_insn_len_bits_p. Remove init_flag.
489 (print_insn_s390): Delete call to init_disasm.
490 (disassembler_options_s390): New function.
491 (print_s390_disassembler_options): Print using information from
492 struct 'options'.
493 * po/opcodes.pot: Regenerate.
494
15c7c1d8
JB		 4952017-02-28 Jan Beulich <jbeulich@suse.com>
496
497 * i386-dis.c (PCMPESTR_Fixup): New.
498 (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
499 (prefix_table): Use PCMPESTR_Fixup.
500 (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
501 PCMPESTR_Fixup.
502 (vex_w_table): Delete VPCMPESTR{I,M} entries.
503 * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
504 Split 64-bit and non-64-bit variants.
505 * opcodes/i386-tbl.h: Re-generate.
506
582e12bf
RS		 5072017-02-24 Richard Sandiford <richard.sandiford@arm.com>
508
509 * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
510 (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
511 (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
512 (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
513 (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
514 (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
515 (OP_SVE_V_HSD): New macros.
516 (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
517 (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
518 (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
519 (aarch64_opcode_table): Add new SVE instructions.
520 (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
521 for rotation operands. Add new SVE operands.
522 * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
523 (ins_sve_quad_index): Likewise.
524 (ins_imm_rotate): Split into...
525 (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
526 * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
527 (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
528 functions.
529 (aarch64_ins_sve_addr_ri_s4): New function.
530 (aarch64_ins_sve_quad_index): Likewise.
531 (do_misc_encoding): Handle "MOV Zn.Q, Qm".
532 * aarch64-asm-2.c: Regenerate.
533 * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
534 (ext_sve_quad_index): Likewise.
535 (ext_imm_rotate): Split into...
536 (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
537 * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
538 (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
539 functions.
540 (aarch64_ext_sve_addr_ri_s4): New function.
541 (aarch64_ext_sve_quad_index): Likewise.
542 (aarch64_ext_sve_index): Allow quad indices.
543 (do_misc_decoding): Likewise.
544 * aarch64-dis-2.c: Regenerate.
545 * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
546 aarch64_field_kinds.
547 (OPD_F_OD_MASK): Widen by one bit.
548 (OPD_F_NO_ZR): Bump accordingly.
549 (get_operand_field_width): New function.
550 * aarch64-opc.c (fields): Add new SVE fields.
551 (operand_general_constraint_met_p): Handle new SVE operands.
552 (aarch64_print_operand): Likewise.
553 * aarch64-opc-2.c: Regenerate.
554
f482d304
RS		 5552017-02-24 Richard Sandiford <richard.sandiford@arm.com>
556
557 * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
558 (aarch64_feature_compnum): ...this.
559 (SIMD_V8_3): Replace with...
560 (COMPNUM): ...this.
561 (CNUM_INSN): New macro.
562 (aarch64_opcode_table): Use it for the complex number instructions.
563
7db2c588
JB		 5642017-02-24 Jan Beulich <jbeulich@suse.com>
565
566 * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
567
1e9d41d4
SL		 5682017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
569
570 Add support for associating SPARC ASIs with an architecture level.
571 * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
572 * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
573 decoding of SPARC ASIs.
574
53c4d625
JB		 5752017-02-23 Jan Beulich <jbeulich@suse.com>
576
577 * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
578 82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
579
11648de5
JB		 5802017-02-21 Jan Beulich <jbeulich@suse.com>
581
582 * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
583 1 (instead of to itself). Correct typo.
584
f98d33be
AW		 5852017-02-14 Andrew Waterman <andrew@sifive.com>
586
587 * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
588 pseudoinstructions.
589
773fb663
RS		 5902017-02-15 Richard Sandiford <richard.sandiford@arm.com>
591
592 * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
593 (aarch64_sys_reg_supported_p): Handle them.
594
cc07cda6
CZ		 5952017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
596
597 * arc-opc.c (UIMM6_20R): Define.
598 (SIMM12_20): Use above.
599 (SIMM12_20R): Define.
600 (SIMM3_5_S): Use above.
601 (UIMM7_A32_11R_S): Define.
602 (UIMM7_9_S): Use above.
603 (UIMM3_13R_S): Define.
604 (SIMM11_A32_7_S): Use above.
605 (SIMM9_8R): Define.
606 (UIMM10_A32_8_S): Use above.
607 (UIMM8_8R_S): Define.
608 (W6): Use above.
609 (arc_relax_opcodes): Use all above defines.
610
66a5a740
VG		 6112017-02-15 Vineet Gupta <vgupta@synopsys.com>
612
613 * arc-regs.h: Distinguish some of the registers different on
614 ARC700 and HS38 cpus.
615
7e0de605
AM		 6162017-02-14 Alan Modra <amodra@gmail.com>
617
618 PR 21118
619 * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
620 with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
621
54064fdb
AM		 6222017-02-11 Stafford Horne <shorne@gmail.com>
623 Alan Modra <amodra@gmail.com>
624
625 * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
626 Use insn_bytes_value and insn_int_value directly instead. Don't
627 free allocated memory until function exit.
628
dce75bf9
NP		 6292017-02-10 Nicholas Piggin <npiggin@gmail.com>
630
631 * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
632
1b7e3d2f
NC		 6332017-02-03 Nick Clifton <nickc@redhat.com>
634
635 PR 21096
636 * aarch64-opc.c (print_register_list): Ensure that the register
637 list index will fir into the tb buffer.
638 (print_register_offset_address): Likewise.
639 * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
640
8ec5cf65
AD		 6412017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
642
643 PR 21056
644 * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
645 instructions when the previous fetch packet ends with a 32-bit
646 instruction.
647
a1aa5e81
DD		 6482017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
649
650 * pru-opc.c: Remove vague reference to a future GDB port.
651
add3afb2
NC		 6522017-01-20 Nick Clifton <nickc@redhat.com>
653
654 * po/ga.po: Updated Irish translation.
655
c13a63b0
SN		 6562017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
657
658 * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
659
9608051a
YQ		 6602017-01-13 Yao Qi <yao.qi@linaro.org>
661
662 * m68k-dis.c (match_insn_m68k): Extend comments. Return -1
663 if FETCH_DATA returns 0.
664 (m68k_scan_mask): Likewise.
665 (print_insn_m68k): Update code to handle -1 return value.
666
f622ea96
YQ		 6672017-01-13 Yao Qi <yao.qi@linaro.org>
668
669 * m68k-dis.c (enum print_insn_arg_error): New.
670 (NEXTBYTE): Replace -3 with
671 PRINT_INSN_ARG_MEMORY_ERROR.
672 (NEXTULONG): Likewise.
673 (NEXTSINGLE): Likewise.
674 (NEXTDOUBLE): Likewise.
675 (NEXTDOUBLE): Likewise.
676 (NEXTPACKED): Likewise.
677 (FETCH_ARG): Likewise.
678 (FETCH_DATA): Update comments.
679 (print_insn_arg): Update comments. Replace magic numbers with
680 enum.
681 (match_insn_m68k): Likewise.
682
620214f7
IT		 6832017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
684
685 * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
686 * i386-dis-evex.h (evex_table): Updated.
687 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
688 CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
689 (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
690 * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
691 (i386_cpu_flags): Add cpuavx512_vpopcntdq.
692 * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
693 * i386-init.h: Regenerate.
694 * i386-tbl.h: Ditto.
695
d95014a2
YQ		 6962017-01-12 Yao Qi <yao.qi@linaro.org>
697
698 * msp430-dis.c (msp430_singleoperand): Return -1 if
699 msp430dis_opcode_signed returns false.
700 (msp430_doubleoperand): Likewise.
701 (msp430_branchinstr): Return -1 if
702 msp430dis_opcode_unsigned returns false.
703 (msp430x_calla_instr): Likewise.
704 (print_insn_msp430): Likewise.
705
0ae60c3e
NC		 7062017-01-05 Nick Clifton <nickc@redhat.com>
707
708 PR 20946
709 * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
710 could not be matched.
711 (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
712 NULL.
713
d74d4880
SN		 7142017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
715
716 * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
717 (aarch64_opcode_table): Use RCPC_INSN.
718
cc917fd9
KC		 7192017-01-03 Kito Cheng <kito.cheng@gmail.com>
720
721 * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
722 extension.
723 * riscv-opcodes/all-opcodes: Likewise.
724
b52d3cfc
DP		 7252017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
726
727 * riscv-dis.c (print_insn_args): Add fall through comment.
728
f90c58d5
NC		 7292017-01-03 Nick Clifton <nickc@redhat.com>
730
731 * po/sr.po: New Serbian translation.
732 * configure.ac (ALL_LINGUAS): Add sr.
733 * configure: Regenerate.
734
f47b0d4a
AM		 7352017-01-02 Alan Modra <amodra@gmail.com>
736
737 * epiphany-desc.h: Regenerate.
738 * epiphany-opc.h: Regenerate.
739 * fr30-desc.h: Regenerate.
740 * fr30-opc.h: Regenerate.
741 * frv-desc.h: Regenerate.
742 * frv-opc.h: Regenerate.
743 * ip2k-desc.h: Regenerate.
744 * ip2k-opc.h: Regenerate.
745 * iq2000-desc.h: Regenerate.
746 * iq2000-opc.h: Regenerate.
747 * lm32-desc.h: Regenerate.
748 * lm32-opc.h: Regenerate.
749 * m32c-desc.h: Regenerate.
750 * m32c-opc.h: Regenerate.
751 * m32r-desc.h: Regenerate.
752 * m32r-opc.h: Regenerate.
753 * mep-desc.h: Regenerate.
754 * mep-opc.h: Regenerate.
755 * mt-desc.h: Regenerate.
756 * mt-opc.h: Regenerate.
757 * or1k-desc.h: Regenerate.
758 * or1k-opc.h: Regenerate.
759 * xc16x-desc.h: Regenerate.
760 * xc16x-opc.h: Regenerate.
761 * xstormy16-desc.h: Regenerate.
762 * xstormy16-opc.h: Regenerate.
763
2571583a
AM		 7642017-01-02 Alan Modra <amodra@gmail.com>
765
766 Update year range in copyright notice of all files.
767
5c1ad6b5 768For older changes see ChangeLog-2016
3499769a 769\f
5c1ad6b5 770Copyright (C) 2017 Free Software Foundation, Inc.
3499769a
AM		 771
772Copying and distribution of this file, with or without modification,
773are permitted in any medium without royalty provided the copyright
774notice and this notice are preserved.
775
776Local Variables:
777mode: change-log
778left-margin: 8
779fill-column: 74
780version-control: never
781End:
GDB Binutils - Deliverables
This page took 0.137218 seconds and 4 git commands to generate.