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2008-04-23 H.J. Lu <hongjiu.lu@intel.com>
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
1a6b486f
DM		 12008-04-23 David S. Miller <davem@davemloft.net>
2
3 * sparc-opc.c (asi_table): Add UltraSPARC and Niagara
4 extended values.
5 (prefetch_table): Add missing values.
6
81f8a913
L		 72008-04-22 H.J. Lu <hongjiu.lu@intel.com>
8
9 * i386-gen.c (opcode_modifiers): Add NoAVX.
10
11 * i386-opc.h (NoAVX): New.
12 (OldGcc): Updated.
13 (i386_opcode_modifier): Add noavx.
14
15 * i386-opc.tbl: Add NoAVX to SSE, SSE2, SSE3 and SSSE3
16 instructions which don't have AVX equivalent.
17 * i386-tbl.h: Regenerated.
18
dae39acc
L		 192008-04-18 H.J. Lu <hongjiu.lu@intel.com>
20
21 * i386-dis.c (OP_VEX_FMA): New.
22 (OP_EX_VexImmW): Likewise.
23 (VexFMA): Likewise.
24 (Vex128FMA): Likewise.
25 (EXVexImmW): Likewise.
26 (get_vex_imm8): Likewise.
27 (OP_EX_VexReg): Likewise.
28 (vex_i4_done): Renamed to ...
29 (vex_w_done): This.
30 (prefix_table): Replace EXVexW with EXVexImmW on vpermil2ps
31 and vpermil2pd. Replace Vex/Vex128 with VexFMA/Vex128FMA on
32 FMA instructions.
33 (print_insn): Updated.
34 (OP_EX_VexW): Rewrite to swap register in VEX with EX.
35 (OP_REG_VexI4): Check invalid high registers.
36
ce886ab1
DR		 372008-04-16 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
38 Michael Meissner <michael.meissner@amd.com>
39
40 * i386-opc.tbl: Fix protX to allow memory in the middle operand.
41 * i386-tbl.h: Regenerate from i386-opc.tbl.
42
19a6653c
AM		 432008-04-14 Edmar Wienskoski <edmar@freescale.com>
44
45 * ppc-dis.c (powerpc_dialect): Handle "e500mc". Extend "e500" to
46 accept Power E500MC instructions.
47 (print_ppc_disassembler_options): Document -Me500mc.
48 * ppc-opc.c (DUIS, DUI, T): New.
49 (XRT, XRTRA): Likewise.
50 (E500MC): Likewise.
51 (powerpc_opcodes): Add new Power E500MC instructions.
52
112b7c50
AK		 532008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
54
55 * s390-dis.c (init_disasm): Evaluate disassembler_options.
56 (print_s390_disassembler_options): New function.
57 * disassemble.c (disassembler_usage): Invoke
58 print_s390_disassembler_options.
59
7ff42648
AK		 602008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
61
62 * s390-mkopc.c (insertExpandedMnemonic): Expand string sizes
63 of local variables used for mnemonic parsing: prefix, suffix and
64 number.
65
45a5551e
AK		 662008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
67
68 * s390-mkopc.c (s390_cond_ext_format): Add back the mnemonic
69 extensions for conditional jumps (o, p, m, nz, z, nm, np, no).
70 (s390_crb_extensions): New extensions table.
71 (insertExpandedMnemonic): Handle '$' tag.
72 * s390-opc.txt: Remove conditional jump variants which can now
73 be expanded automatically.
74 Replace '*' tag with '$' in the compare and branch instructions.
75
06c8514a
L		 762008-04-07 H.J. Lu <hongjiu.lu@intel.com>
77
78 * i386-dis.c (PREFIX_VEX_38XX): Add a tab.
79 (PREFIX_VEX_3AXX): Likewis.
80
b122c285
L		 812008-04-07 H.J. Lu <hongjiu.lu@intel.com>
82
83 * i386-opc.tbl: Remove 4 extra blank lines.
84
594ab6a3
L		 852008-04-04 H.J. Lu <hongjiu.lu@intel.com>
86
87 * i386-gen.c (cpu_flag_init): Replace CPU_CLMUL_FLAGS/CpuCLMUL
88 with CPU_PCLMUL_FLAGS/CpuPCLMUL.
89 (cpu_flags): Replace CpuCLMUL with CpuPCLMUL.
90 * i386-opc.tbl: Likewise.
91
92 * i386-opc.h (CpuCLMUL): Renamed to ...
93 (CpuPCLMUL): This.
94 (CpuFMA): Updated.
95 (i386_cpu_flags): Replace cpuclmul with cpupclmul.
96
97 * i386-init.h: Regenerated.
98
c0f3af97
L		 992008-04-03 H.J. Lu <hongjiu.lu@intel.com>
100
101 * i386-dis.c (OP_E_register): New.
102 (OP_E_memory): Likewise.
103 (OP_VEX): Likewise.
104 (OP_EX_Vex): Likewise.
105 (OP_EX_VexW): Likewise.
106 (OP_XMM_Vex): Likewise.
107 (OP_XMM_VexW): Likewise.
108 (OP_REG_VexI4): Likewise.
109 (PCLMUL_Fixup): Likewise.
110 (VEXI4_Fixup): Likewise.
111 (VZERO_Fixup): Likewise.
112 (VCMP_Fixup): Likewise.
113 (VPERMIL2_Fixup): Likewise.
114 (rex_original): Likewise.
115 (rex_ignored): Likewise.
116 (Mxmm): Likewise.
117 (XMM): Likewise.
118 (EXxmm): Likewise.
119 (EXxmmq): Likewise.
120 (EXymmq): Likewise.
121 (Vex): Likewise.
122 (Vex128): Likewise.
123 (Vex256): Likewise.
124 (VexI4): Likewise.
125 (EXdVex): Likewise.
126 (EXqVex): Likewise.
127 (EXVexW): Likewise.
128 (EXdVexW): Likewise.
129 (EXqVexW): Likewise.
130 (XMVex): Likewise.
131 (XMVexW): Likewise.
132 (XMVexI4): Likewise.
133 (PCLMUL): Likewise.
134 (VZERO): Likewise.
135 (VCMP): Likewise.
136 (VPERMIL2): Likewise.
137 (xmm_mode): Likewise.
138 (xmmq_mode): Likewise.
139 (ymmq_mode): Likewise.
140 (vex_mode): Likewise.
141 (vex128_mode): Likewise.
142 (vex256_mode): Likewise.
143 (USE_VEX_C4_TABLE): Likewise.
144 (USE_VEX_C5_TABLE): Likewise.
145 (USE_VEX_LEN_TABLE): Likewise.
146 (VEX_C4_TABLE): Likewise.
147 (VEX_C5_TABLE): Likewise.
148 (VEX_LEN_TABLE): Likewise.
149 (REG_VEX_XX): Likewise.
150 (MOD_VEX_XXX): Likewise.
151 (PREFIX_0F38DB..PREFIX_0F38DF): Likewise.
152 (PREFIX_0F3A44): Likewise.
153 (PREFIX_0F3ADF): Likewise.
154 (PREFIX_VEX_XXX): Likewise.
155 (VEX_OF): Likewise.
156 (VEX_OF38): Likewise.
157 (VEX_OF3A): Likewise.
158 (VEX_LEN_XXX): Likewise.
159 (vex): Likewise.
160 (need_vex): Likewise.
161 (need_vex_reg): Likewise.
162 (vex_i4_done): Likewise.
163 (vex_table): Likewise.
164 (vex_len_table): Likewise.
165 (OP_REG_VexI4): Likewise.
166 (vex_cmp_op): Likewise.
167 (pclmul_op): Likewise.
168 (vpermil2_op): Likewise.
169 (m_mode): Updated.
170 (es_reg): Likewise.
171 (PREFIX_0F38F0): Likewise.
172 (PREFIX_0F3A60): Likewise.
173 (reg_table): Add REG_VEX_71...REG_VEX_73 and REG_VEX_AE.
174 (prefix_table): Add PREFIX_0F38DB..PREFIX_0F38DF, PREFIX_0F3ADF
175 and PREFIX_VEX_XXX entries.
176 (x86_64_table): Use VEX_C4_TABLE and VEX_C5_TABLE.
177 (three_byte_table): Use PREFIX_0F38DB..PREFIX_0F38DF and
178 PREFIX_0F3ADF.
179 (mod_table): Use VEX_C4_TABLE, VEX_C5_TABLE and VEX_LEN_TABLE.
180 Add MOD_VEX_XXX entries.
181 (ckprefix): Initialize rex_original and rex_ignored. Store the
182 REX byte in rex_original.
183 (get_valid_dis386): Handle the implicit prefix in VEX prefix
184 bytes and USE_VEX_LEN_TABLE/USE_VEX_C4_TABLE/USE_VEX_C5_TABLE.
185 (print_insn): Set need_vex/need_vex_reg/vex_i4_done to 0 before
186 calling get_valid_dis386. Use rex_original and rex_ignored when
187 printing out REX.
188 (putop): Handle "XY".
189 (intel_operand_size): Handle VEX, xmm_mode, xmmq_mode and
190 ymmq_mode.
191 (OP_E_extended): Updated to use OP_E_register and
192 OP_E_memory.
193 (OP_XMM): Handle VEX.
194 (OP_EX): Likewise.
195 (XMM_Fixup): Likewise.
196 (CMP_Fixup): Use ARRAY_SIZE.
197
198 * i386-gen.c (cpu_flag_init): Add CpuAES, CPU_CLMUL_FLAGS,
199 CPU_FMA_FLAGS and CPU_AVX_FLAGS.
200 (operand_type_init): Add OPERAND_TYPE_REGYMM and
201 OPERAND_TYPE_VEX_IMM4.
202 (cpu_flags): Add CpuAVX, CpuAES, CpuCLMUL and CpuFMA.
203 (opcode_modifiers): Add Implicit1stXmm0, Vex, Vex256, VexNDD,
204 VexNDS, VexW0, VexW1, Vex0F, Vex0F38, Vex0F3A, Vex3Sources,
205 VexImmExt and SSE2AVX.
206 (operand_types): Add RegYMM, Ymmword and Vex_Imm4.
207
208 * i386-opc.h (CpuAVX): New.
209 (CpuAES): Likewise.
210 (CpuCLMUL): Likewise.
211 (CpuFMA): Likewise.
212 (Vex): Likewise.
213 (Vex256): Likewise.
214 (VexNDS): Likewise.
215 (VexNDD): Likewise.
216 (VexW0): Likewise.
217 (VexW1): Likewise.
218 (Vex0F): Likewise.
219 (Vex0F38): Likewise.
220 (Vex0F3A): Likewise.
221 (Vex3Sources): Likewise.
222 (VexImmExt): Likewise.
223 (SSE2AVX): Likewise.
224 (RegYMM): Likewise.
225 (Ymmword): Likewise.
226 (Vex_Imm4): Likewise.
227 (Implicit1stXmm0): Likewise.
228 (CpuXsave): Updated.
229 (CpuLM): Likewise.
230 (ByteOkIntel): Likewise.
231 (OldGcc): Likewise.
232 (Control): Likewise.
233 (Unspecified): Likewise.
234 (OTMax): Likewise.
235 (i386_cpu_flags): Add cpuavx, cpuaes, cpuclmul and cpufma.
236 (i386_opcode_modifier): Add implicit1stxmm0, vex, vex256,
237 vexnds, vexndd, vexw0, vexw1, vex0f, vex0f38, vex0f3a,
238 vex3sources, veximmext and sse2avx.
239 (i386_operand_type): Add regymm, ymmword and vex_imm4.
240
241 * i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions.
242
243 * i386-reg.tbl: Add AVX registers, ymm0..ymm15.
244
245 * i386-init.h: Regenerated.
246 * i386-tbl.h: Likewise.
247
b21c9cb4
BS		 2482008-03-26 Bernd Schmidt <bernd.schmidt@analog.com>
249
250 From Robin Getz <robin.getz@analog.com>
251 * bfin-dis.c (bu32): Typedef.
252 (enum const_forms_t): Add c_uimm32 and c_huimm32.
253 (constant_formats[]): Add uimm32 and huimm16.
254 (fmtconst_val): New.
255 (uimm32): Define.
256 (huimm32): Define.
257 (imm16_val): Define.
258 (luimm16_val): Define.
259 (struct saved_state): Define.
260 (GREG, DPREG, DREG, PREG, SPREG, FPREG, IREG, MREG, BREG, LREG,
261 A0XREG, A0WREG, A1XREG, A1WREG,CCREG, LC0REG, LT0REG, LB0REG,
262 LC1REG, LT1REG, LB1REG, RETSREG, PCREG): Define.
263 (get_allreg): New.
264 (decode_LDIMMhalf_0): Print out the whole register value.
265
ee171c8f
BS		 266 From Jie Zhang <jie.zhang@analog.com>
267 * bfin-dis.c (decode_dsp32mac_0): Decode (IU) option for
268 multiply and multiply-accumulate to data register instruction.
269
086134ec
BS		 270 * bfin-dis.c: (c_uimm4s4d, c_imm5d, c_imm7d, c_imm16d, c_uimm16s4d,
271 c_imm32, c_huimm32e): Define.
272 (constant_formats): Add flags for printing decimal, leading spaces, and
273 exact symbols.
274 (comment, parallel): Add global flags in all disassembly.
275 (fmtconst): Take advantage of new flags, and print default in hex.
276 (fmtconst_val): Likewise.
277 (decode_macfunc): Be consistant with spaces, tabs, comments,
278 capitalization in disassembly, fix minor coding style issues.
279 (reg_names, amod0, amod1, amod0amod2, aligndir, get_allreg): Likewise.
280 (decode_ProgCtrl_0, decode_PushPopMultiple_0, decode_CCflag_0,
281 decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0,
282 decode_REGMV_0, decode_ALU2op_0, decode_PTR2op_0, decode_LOGI2op_0,
283 decode_COMP3op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
284 decode_LDSTpmod_0, decode_dagMODim_0, decode_dagMODik_0,
285 decode_dspLDST_0, decode_LDST_0, decode_LDSTiiFP_0, decode_LDSTii_0,
286 decode_LoopSetup_0, decode_LDIMMhalf_0, decode_CALLa_0,
287 decode_LDSTidxI_0, decode_linkage_0, decode_dsp32alu_0,
288 decode_dsp32shift_0, decode_dsp32shiftimm_0, decode_pseudodbg_assert_0,
289 _print_insn_bfin, print_insn_bfin): Likewise.
290
58c85be7
RW		 2912008-03-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
292
293 * aclocal.m4: Regenerate.
294 * configure: Likewise.
295 * Makefile.in: Likewise.
296
50e7d84b
AM		 2972008-03-13 Alan Modra <amodra@bigpond.net.au>
298
299 * Makefile.am: Run "make dep-am".
300 * Makefile.in: Regenerate.
301 * configure: Regenerate.
302
de866fcc
AM		 3032008-03-07 Alan Modra <amodra@bigpond.net.au>
304
305 * ppc-opc.c (powerpc_opcodes): Order and format.
306
28dbc079
L		 3072008-03-01 H.J. Lu <hongjiu.lu@intel.com>
308
309 * i386-opc.tbl: Allow 16-bit near indirect branches for x86-64.
310 * i386-tbl.h: Regenerated.
311
849830bd
L		 3122008-02-23 H.J. Lu <hongjiu.lu@intel.com>
313
314 * i386-opc.tbl: Disallow 16-bit near indirect branches for
315 x86-64.
316 * i386-tbl.h: Regenerated.
317
743ddb6b
JB		 3182008-02-21 Jan Beulich <jbeulich@novell.com>
319
320 * i386-opc.tbl: Allow Dword for far indirect call. Allow Dword
321 and Fword for far indirect jmp. Allow Reg16 and Word for near
322 indirect jmp on x86-64. Disallow Fword for lcall.
323 * i386-tbl.h: Re-generate.
324
796d5313
NC		 3252008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
326
327 * cr16-opc.c (cr16_num_optab): Defined
328
65da13b5
L		 3292008-02-16 H.J. Lu <hongjiu.lu@intel.com>
330
331 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_INOUTPORTREG.
332 * i386-init.h: Regenerated.
333
0e336180
NC		 3342008-02-14 Nick Clifton <nickc@redhat.com>
335
336 PR binutils/5524
337 * configure.in (SHARED_LIBADD): Select the correct host specific
338 file extension for shared libraries.
339 * configure: Regenerate.
340
b7240065
JB		 3412008-02-13 Jan Beulich <jbeulich@novell.com>
342
343 * i386-opc.h (RegFlat): New.
344 * i386-reg.tbl (flat): Add.
345 * i386-tbl.h: Re-generate.
346
34b772a6
JB		 3472008-02-13 Jan Beulich <jbeulich@novell.com>
348
349 * i386-dis.c (a_mode): New.
350 (cond_jump_mode): Adjust.
351 (Ma): Change to a_mode.
352 (intel_operand_size): Handle a_mode.
353 * i386-opc.tbl: Allow Dword and Qword for bound.
354 * i386-tbl.h: Re-generate.
355
a60de03c
JB		 3562008-02-13 Jan Beulich <jbeulich@novell.com>
357
358 * i386-gen.c (process_i386_registers): Process new fields.
359 * i386-opc.h (reg_entry): Shrink reg_flags and reg_num to
360 unsigned char. Add dw2_regnum and Dw2Inval.
361 * i386-reg.tbl: Provide initializers for dw2_regnum. Add pseudo
362 register names.
363 * i386-tbl.h: Re-generate.
364
f03fe4c1
L		 3652008-02-11 H.J. Lu <hongjiu.lu@intel.com>
366
4b6bc8eb 367 * i386-gen.c (cpu_flag_init): Add CPU_XSAVE_FLAGS.
f03fe4c1
L		 368 * i386-init.h: Updated.
369
475a2301
L		 3702008-02-11 H.J. Lu <hongjiu.lu@intel.com>
371
372 * i386-gen.c (cpu_flags): Add CpuXsave.
373
374 * i386-opc.h (CpuXsave): New.
4b6bc8eb 375 (CpuLM): Updated.
475a2301
L		 376 (i386_cpu_flags): Add cpuxsave.
377
378 * i386-dis.c (MOD_0FAE_REG_4): New.
379 (RM_0F01_REG_2): Likewise.
380 (MOD_0FAE_REG_5): Updated.
381 (RM_0F01_REG_3): Likewise.
382 (reg_table): Use MOD_0FAE_REG_4.
383 (mod_table): Use RM_0F01_REG_2. Add MOD_0FAE_REG_4. Updated
384 for xrstor.
385 (rm_table): Add RM_0F01_REG_2.
386
387 * i386-opc.tbl: Add xsave, xrstor, xgetbv and xsetbv.
388 * i386-init.h: Regenerated.
389 * i386-tbl.h: Likewise.
390
595785c6 3912008-02-11 Jan Beulich <jbeulich@novell.com>
041179fc 392
595785c6
JB		 393 * i386-opc.tbl: Remove Disp32S from CpuNo64 opcodes. Remove
394 Disp16 from Cpu64 non-jump opcodes (including loop and j?cxz).
395 * i386-tbl.h: Re-generate.
396
bb8541b9
L		 3972008-02-04 H.J. Lu <hongjiu.lu@intel.com>
398
399 PR 5715
400 * configure: Regenerated.
401
57b592a3
AN		 4022008-02-04 Adam Nemet <anemet@caviumnetworks.com>
403
404 * mips-dis.c: Update copyright.
405 (mips_arch_choices): Add Octeon.
406 * mips-opc.c: Update copyright.
407 (IOCT): New macro.
408 (mips_builtin_opcodes): Add Octeon instruction synciobdma.
409
930bb4cf
AM		 4102008-01-29 Alan Modra <amodra@bigpond.net.au>
411
412 * ppc-opc.c: Support optional L form mtmsr.
413
82c18208
L		 4142008-01-24 H.J. Lu <hongjiu.lu@intel.com>
415
416 * i386-dis.c (OP_E_extended): Handle r12 like rsp.
417
599121aa
L		 4182008-01-23 H.J. Lu <hongjiu.lu@intel.com>
419
420 * i386-gen.c (cpu_flag_init): Add CpuLM to CPU_GENERIC64_FLAGS.
421 * i386-init.h: Regenerated.
422
80098f51
TG		 4232008-01-23 Tristan Gingold <gingold@adacore.com>
424
425 * ia64-dis.c (print_insn_ia64): Display symbolic name of ar.fcr,
426 ar.eflag, ar.csd, ar.ssd, ar.cflg, ar.fsr, ar.fir and ar.fdr.
427
115c7c25
L		 4282008-01-22 H.J. Lu <hongjiu.lu@intel.com>
429
430 * i386-gen.c (cpu_flag_init): Remove CpuMMX2.
431 (cpu_flags): Likewise.
432
433 * i386-opc.h (CpuMMX2): Removed.
434 (CpuSSE): Updated.
435
436 * i386-opc.tbl: Replace CpuMMX2 with CpuSSE|Cpu3dnowA.
437 * i386-init.h: Regenerated.
438 * i386-tbl.h: Likewise.
439
6305a203
L		 4402008-01-22 H.J. Lu <hongjiu.lu@intel.com>
441
442 * i386-gen.c (cpu_flag_init): Add CPU_VMX_FLAGS and
443 CPU_SMX_FLAGS.
444 * i386-init.h: Regenerated.
445
fd07a1c8
L		 4462008-01-15 H.J. Lu <hongjiu.lu@intel.com>
447
448 * i386-opc.tbl: Use Qword on movddup.
449 * i386-tbl.h: Regenerated.
450
321fd21e
L		 4512008-01-15 H.J. Lu <hongjiu.lu@intel.com>
452
453 * i386-opc.tbl: Put back 16bit movsx/movzx for AT&T syntax.
454 * i386-tbl.h: Regenerated.
455
4ee52178
L		 4562008-01-15 H.J. Lu <hongjiu.lu@intel.com>
457
458 * i386-dis.c (Mx): New.
459 (PREFIX_0FC3): Likewise.
460 (PREFIX_0FC7_REG_6): Updated.
461 (dis386_twobyte): Use PREFIX_0FC3.
462 (prefix_table): Add PREFIX_0FC3. Use Mq on movntq and movntsd.
463 Use Mx on movntps, movntpd, movntdq and movntdqa. Use Md on
464 movntss.
465
5c07affc
L		 4662008-01-14 H.J. Lu <hongjiu.lu@intel.com>
467
468 * i386-gen.c (opcode_modifiers): Add IntelSyntax.
469 (operand_types): Add Mem.
470
471 * i386-opc.h (IntelSyntax): New.
472 * i386-opc.h (Mem): New.
473 (Byte): Updated.
474 (Opcode_Modifier_Max): Updated.
475 (i386_opcode_modifier): Add intelsyntax.
476 (i386_operand_type): Add mem.
477
478 * i386-opc.tbl: Remove Reg16 from movnti. Add sizes to more
479 instructions.
480
481 * i386-reg.tbl: Add size for accumulator.
482
483 * i386-init.h: Regenerated.
484 * i386-tbl.h: Likewise.
485
0d6a2f58
L		 4862008-01-13 H.J. Lu <hongjiu.lu@intel.com>
487
488 * i386-opc.h (Byte): Fix a typo.
489
7d5e4556
L		 4902008-01-12 H.J. Lu <hongjiu.lu@intel.com>
491
492 PR gas/5534
493 * i386-gen.c (operand_type_init): Add Dword to
494 OPERAND_TYPE_ACC32. Add Qword to OPERAND_TYPE_ACC64.
495 (opcode_modifiers): Remove CheckSize, Byte, Word, Dword,
496 Qword and Xmmword.
497 (operand_types): Add Byte, Word, Dword, Fword, Qword, Tbyte,
498 Xmmword, Unspecified and Anysize.
499 (set_bitfield): Make Mmword an alias of Qword. Make Oword
500 an alias of Xmmword.
501
502 * i386-opc.h (CheckSize): Removed.
503 (Byte): Updated.
504 (Word): Likewise.
505 (Dword): Likewise.
506 (Qword): Likewise.
507 (Xmmword): Likewise.
508 (FWait): Updated.
509 (OTMax): Likewise.
510 (i386_opcode_modifier): Remove checksize, byte, word, dword,
511 qword and xmmword.
512 (Fword): New.
513 (TBYTE): Likewise.
514 (Unspecified): Likewise.
515 (Anysize): Likewise.
516 (i386_operand_type): Add byte, word, dword, fword, qword,
517 tbyte xmmword, unspecified and anysize.
518
519 * i386-opc.tbl: Updated to use Byte, Word, Dword, Fword, Qword,
520 Tbyte, Xmmword, Unspecified and Anysize.
521
522 * i386-reg.tbl: Add size for accumulator.
523
524 * i386-init.h: Regenerated.
525 * i386-tbl.h: Likewise.
526
b5b1fc4f
L		 5272008-01-10 H.J. Lu <hongjiu.lu@intel.com>
528
529 * i386-dis.c (REG_0F0E): Renamed to REG_0F0D.
530 (REG_0F18): Updated.
531 (reg_table): Updated.
532 (dis386_twobyte): Updated. Use "nopQ" on 0x19 to 0x1e.
533 (twobyte_has_modrm): Set 1 for 0x19 to 0x1e.
534
50e8458f
L		 5352008-01-08 H.J. Lu <hongjiu.lu@intel.com>
536
537 * i386-gen.c (set_bitfield): Use fail () on error.
538
3d4d5afa
L		 5392008-01-08 H.J. Lu <hongjiu.lu@intel.com>
540
541 * i386-gen.c (lineno): New.
542 (filename): Likewise.
543 (set_bitfield): Report filename and line numer on error.
544 (process_i386_opcodes): Set filename and update lineno.
545 (process_i386_registers): Likewise.
546
e1d4d893
L		 5472008-01-05 H.J. Lu <hongjiu.lu@intel.com>
548
549 * i386-gen.c (opcode_modifiers): Rename IntelMnemonic to
550 ATTSyntax.
551
552 * i386-opc.h (IntelMnemonic): Renamed to ..
553 (ATTSyntax): This
554 (Opcode_Modifier_Max): Updated.
555 (i386_opcode_modifier): Remove intelmnemonic. Add attsyntax
556 and intelsyntax.
557
558 * i386-opc.tbl: Remove IntelMnemonic and update with ATTSyntax
559 on fsub, fubp, fsubr, fsubrp, div, fdivp, fdivr and fdivrp.
560 * i386-tbl.h: Regenerated.
561
6f143e4d
L		 5622008-01-04 H.J. Lu <hongjiu.lu@intel.com>
563
564 * i386-gen.c: Update copyright to 2008.
565 * i386-opc.h: Likewise.
566 * i386-opc.tbl: Likewise.
567
568 * i386-init.h: Regenerated.
569 * i386-tbl.h: Likewise.
570
c6add537
L		 5712008-01-04 H.J. Lu <hongjiu.lu@intel.com>
572
573 * i386-opc.tbl: Add NoRex64 to extractps, movmskpd, movmskps,
574 pextrb, pextrw, pinsrb, pinsrw and pmovmskb.
575 * i386-tbl.h: Regenerated.
576
3629bb00
L		 5772008-01-03 H.J. Lu <hongjiu.lu@intel.com>
578
579 * i386-gen.c (cpu_flag_init): Remove CpuSSE4_1_Or_5 and
580 CpuSSE4_2_Or_ABM.
581 (cpu_flags): Likewise.
582
583 * i386-opc.h (CpuSSE4_1_Or_5): Removed.
584 (CpuSSE4_2_Or_ABM): Likewise.
585 (CpuLM): Updated.
586 (i386_cpu_flags): Remove cpusse4_1_or_5 and cpusse4_2_or_abm.
587
588 * i386-opc.tbl: Replace CpuSSE4_1_Or_5, CpuSSE4_2_Or_ABM and
589 Cpu686|CpuPadLock with CpuSSE4_1|CpuSSE5, CpuABM|CpuSSE4_2
590 and CpuPadLock, respectively.
591 * i386-init.h: Regenerated.
592 * i386-tbl.h: Likewise.
593
24995bd6
L		 5942008-01-03 H.J. Lu <hongjiu.lu@intel.com>
595
596 * i386-gen.c (opcode_modifiers): Remove No_xSuf.
597
598 * i386-opc.h (No_xSuf): Removed.
599 (CheckSize): Updated.
600
601 * i386-tbl.h: Regenerated.
602
e0329a22
L		 6032008-01-02 H.J. Lu <hongjiu.lu@intel.com>
604
605 * i386-gen.c (cpu_flag_init): Add CpuSSE4_2_Or_ABM to
606 CPU_AMDFAM10_FLAGS, CPU_SSE4_2_FLAGS, CpuABM and
607 CPU_SSE5_FLAGS.
608 (cpu_flags): Add CpuSSE4_2_Or_ABM.
609
610 * i386-opc.h (CpuSSE4_2_Or_ABM): New.
611 (CpuLM): Updated.
612 (i386_cpu_flags): Add cpusse4_2_or_abm.
613
614 * i386-opc.tbl: Use CpuSSE4_2_Or_ABM instead of
615 CpuABM|CpuSSE4_2 on popcnt.
616 * i386-init.h: Regenerated.
617 * i386-tbl.h: Likewise.
618
f2a9c676
L		 6192008-01-02 H.J. Lu <hongjiu.lu@intel.com>
620
621 * i386-opc.h: Update comments.
622
d978b5be
L		 6232008-01-02 H.J. Lu <hongjiu.lu@intel.com>
624
625 * i386-gen.c (opcode_modifiers): Use Qword instead of QWord.
626 * i386-opc.h: Likewise.
627 * i386-opc.tbl: Likewise.
628
582d5edd
L		 6292008-01-02 H.J. Lu <hongjiu.lu@intel.com>
630
631 PR gas/5534
632 * i386-gen.c (opcode_modifiers): Add No_xSuf, CheckSize,
633 Byte, Word, Dword, QWord and Xmmword.
634
635 * i386-opc.h (No_xSuf): New.
636 (CheckSize): Likewise.
637 (Byte): Likewise.
638 (Word): Likewise.
639 (Dword): Likewise.
640 (QWord): Likewise.
641 (Xmmword): Likewise.
642 (FWait): Updated.
643 (i386_opcode_modifier): Add No_xSuf, CheckSize, Byte, Word,
644 Dword, QWord and Xmmword.
645
646 * i386-opc.tbl: Add CheckSize|QWord to movq if IgnoreSize is
647 used.
648 * i386-tbl.h: Regenerated.
649
3fe15143
MK		 6502008-01-02 Mark Kettenis <kettenis@gnu.org>
651
652 * m88k-dis.c (instructions): Fix fcvt.* instructions.
653 From Miod Vallat.
654
6c7ac64e 655For older changes see ChangeLog-2007
252b5132
RH		 656\f
657Local Variables:
2f6d2f85
NC		 658mode: change-log
659left-margin: 8
660fill-column: 74
252b5132
RH		 661version-control: never
662End:
GDB Binutils - Deliverables
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