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2008-12-08 H.J. Lu <hongjiu.lu@intel.com>
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
efa7dee7
L		 12008-12-08 H.J. Lu <hongjiu.lu@intel.com>
2
3 * i386-dis.c (putop): Remove strayed comments.
4
2f3bb96a
BE		 52008-12-04 Ben Elliston <bje@au.ibm.com>
6
7 * ppc-dis.c (powerpc_init_dialect): Do not set PPC_OPCODE_BOOKE
8 for -Mbooke.
9 (print_ppc_disassembler_options): Update usage.
10 * ppc-opc.c (DE, DES, DEO, DE_MASK): Remove.
11 (BOOKE64): Remove.
12 (PPCCHLK64): Likewise.
13 (powerpc_opcodes): Remove all BOOKE64 instructions.
14
3aa3176b
TS		 152008-11-28 Joshua Kinard <kumba@gentoo.org>
16
17 * mips-dis.c (mips_arch_choices): Add r14000, r16000.
18
59b098c9
SR		 192008-11-27 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
20
21 * cr16-dis.c (match_opcode): Truncate mcode to 32 bit and
22 adjusted the mask for 32-bit branch instruction.
23
e1c93c69
AM		 242008-11-27 Alan Modra <amodra@bigpond.net.au>
25
26 * ppc-opc.c (extract_sprg): Correct operand range check.
27
9f7678f6
AS		 282008-11-26 Andreas Schwab <schwab@suse.de>
29
30 * m68k-dis.c (NEXTBYTE, NEXTWORD, NEXTLONG, NEXTULONG, NEXTSINGLE)
31 (NEXTDOUBLE, NEXTEXTEND, NEXTPACKED): Fix error handling.
32 (save_printer, save_print_address): Remove.
33 (fetch_data): Don't use them.
34 (match_insn_m68k): Always restore printing functions.
35 (print_insn_m68k): Don't save/restore printing functions.
36
62443ade
NC		 372008-11-25 Nick Clifton <nickc@redhat.com>
38
39 * m68k-dis.c: Rewrite to remove use of setjmp/longjmp.
40
8e79c3df
CM		 412008-11-18 Catherine Moore <clm@codesourcery.com>
42
43 * arm-dis.c (coprocessor_opcodes): Add half-precision vcvt
44 instructions.
45 (neon_opcodes): Likewise.
46 (print_insn_coprocessor): Print 't' or 'b' for vcvt
47 instructions.
48
d387240a
TG		 492008-11-14 Tristan Gingold <gingold@adacore.com>
50
51 * makefile.vms (OBJS): Update list of objects.
52 (DEFS): Update
53 (CFLAGS): Update.
54
4dc48ef6
CF		 552008-11-06 Chao-ying Fu <fu@mips.com>
56
57 * mips-opc.c (synciobdma, syncs, syncw, syncws): Move these
58 before sync.
59 (sync): New instruction with 5-bit sync type.
3c6528a8 60 * mips-dis.c (print_insn_args): Add case '1' to print 5-bit values.
4dc48ef6 61
c8941035
NC		 622008-11-06 Nick Clifton <nickc@redhat.com>
63
64 * avr-dis.c: Replace uses of sprintf without a format string with
65 calls to strcpy.
66
a7bea99d
L		 672008-11-03 H.J. Lu <hongjiu.lu@intel.com>
68
69 * i386-opc.tbl: Add cmovpe and cmovpo.
70 * i386-tbl.h: Regenerated.
71
4267b19f
NC		 722008-10-22 Nick Clifton <nickc@redhat.com>
73
74 PR 6937
75 * configure.in (SHARED_LIBADD): Revert previous change.
76 Add a comment explaining why.
77 (SHARED_DEPENDENCIES): Revert previous change.
78 * configure: Regenerate.
79
8a9629d0
NC		 802008-10-10 Nick Clifton <nickc@redhat.com>
81
82 PR 6937
83 * configure.in (SHARED_LIBADD): Add libiberty.a.
84 (SHARED_DEPENDENCIES): Add libiberty.a.
85
c587b3f9
L		 862008-09-30 H.J. Lu <hongjiu.lu@intel.com>
87
88 * i386-gen.c: Include "hashtab.h".
89 (next_field): Take a new argument, last. Check last.
90 (process_i386_cpu_flag): Updated.
91 (process_i386_opcode_modifier): Likewise.
92 (process_i386_operand_type): Likewise.
93 (process_i386_registers): Likewise.
94 (output_i386_opcode): New.
95 (opcode_hash_entry): Likewise.
96 (opcode_hash_table): Likewise.
97 (opcode_hash_hash): Likewise.
98 (opcode_hash_eq): Likewise.
99 (process_i386_opcodes): Use opcode hash table and opcode array.
100
34b23dab
AK		 1012008-09-30 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
102
103 * s390-opc.txt (stdy, stey): Fix description
104
782e11fd
AM		 1052008-09-30 Alan Modra <amodra@bigpond.net.au>
106
107 * Makefile.am: Run "make dep-am".
108 * Makefile.in: Regenerate.
109
1927a18f
L		 1102008-09-29 H.J. Lu <hongjiu.lu@intel.com>
111
112 * aclocal.m4: Regenerated.
113 * configure: Likewise.
114 * Makefile.in: Likewise.
115
afac680a
NC		 1162008-09-29 Nick Clifton <nickc@redhat.com>
117
118 * po/vi.po: Updated Vietnamese translation.
119 * po/fr.po: Updated French translation.
120
b40d5eb9
AK		 1212008-09-26 Florian Krohm <fkrohm@us.ibm.com>
122
123 * s390-opc.txt (thder, thdr): Change RRE_RR to RRE_FF.
124 (cfxr, cfdr, cfer, clclu): Add esa flag.
125 (sqd): Instruction added.
126 (qadtr, qaxtr): Change RRF_FFFU to RRF_FUFF.
127 * s390-opc.c: (INSTR_RRF_FFFU, MASK_RRF_FFFU): Removed.
128
d0411736
AM		 1292008-09-14 Arnold Metselaar <arnold.metselaar@planet.nl>
130
131 * z80-dis.c (prt_rr_nn): Fix register pair for two byte opcodes.
132 (tab_elt opc_ed): Add "ld r,a" and "ld r,a" instructions.
133
3e126784
L		 1342008-09-11 H.J. Lu <hongjiu.lu@intel.com>
135
136 * i386-opc.tbl: Fix memory operand size for cmpXXXs[sd].
137 * i386-tbl.h: Regenerated.
138
ddab3d59
JB		 1392008-08-28 Jan Beulich <jbeulich@novell.com>
140
141 * i386-dis.c (dis386): Adjust far return mnemonics.
142 * i386-opc.tbl: Add retf.
143 * i386-tbl.h: Re-generate.
144
b19d5385
JB		 1452008-08-28 Jan Beulich <jbeulich@novell.com>
146
147 * i386-dis.c (dis386_twobyte): Adjust cmovXX mnemonics.
148
1ca35711
L		 1492008-08-28 H.J. Lu <hongjiu.lu@intel.com>
150
151 * ia64-dis.c (print_insn_ia64): Handle cr.iib0 and cr.iib1.
152 * ia64-gen.c (lookup_specifier): Likewise.
153
154 * ia64-ic.tbl: Add support for cr.iib0 and cr.iib1.
155 * ia64-raw.tbl: Likewise.
156 * ia64-waw.tbl: Likewise.
157 * ia64-asmtab.c: Regenerated.
158
515c56e7
L		 1592008-08-27 H.J. Lu <hongjiu.lu@intel.com>
160
161 * i386-opc.tbl: Correct fidivr operand size.
162
163 * i386-tbl.h: Regenerated.
164
da594c4a
AM		 1652008-08-24 Alan Modra <amodra@bigpond.net.au>
166
167 * configure.in: Update a number of obsolete autoconf macros.
168 * aclocal.m4: Regenerate.
169
a5ff0eb2
L		 1702008-08-20 H.J. Lu <hongjiu.lu@intel.com>
171
172 AVX Programming Reference (August, 2008)
173 * i386-dis.c (PREFIX_VEX_38DB): New.
174 (PREFIX_VEX_38DC): Likewise.
175 (PREFIX_VEX_38DD): Likewise.
176 (PREFIX_VEX_38DE): Likewise.
177 (PREFIX_VEX_38DF): Likewise.
178 (PREFIX_VEX_3ADF): Likewise.
179 (VEX_LEN_38DB_P_2): Likewise.
180 (VEX_LEN_38DC_P_2): Likewise.
181 (VEX_LEN_38DD_P_2): Likewise.
182 (VEX_LEN_38DE_P_2): Likewise.
183 (VEX_LEN_38DF_P_2): Likewise.
184 (VEX_LEN_3ADF_P_2): Likewise.
185 (PREFIX_VEX_3A04): Updated.
186 (VEX_LEN_3A06_P_2): Likewise.
187 (prefix_table): Add PREFIX_VEX_38DB, PREFIX_VEX_38DC,
188 PREFIX_VEX_38DD, PREFIX_VEX_38DE and PREFIX_VEX_3ADF.
189 (x86_64_table): Likewise.
190 (vex_len_table): Add VEX_LEN_38DB_P_2, VEX_LEN_38DC_P_2,
191 VEX_LEN_38DD_P_2, VEX_LEN_38DE_P_2, VEX_LEN_38DF_P_2 and
192 VEX_LEN_3ADF_P_2.
193
194 * i386-opc.tbl: Add AES + AVX instructions.
195 * i386-init.h: Regenerated.
196 * i386-tbl.h: Likewise.
197
7dc6076f
AK		 1982008-08-15 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
199
200 * s390-opc.c (INSTR_RRF_FFRU, MASK_RRF_FFRU): New instruction format.
201 * s390-opc.txt (lxr, rrdtr, rrxtr): Fix instruction format.
202
7357c5b6
AM		 2032008-08-15 Alan Modra <amodra@bigpond.net.au>
204
205 PR 6526
206 * configure.in: Invoke AC_USE_SYSTEM_EXTENSIONS.
207 * Makefile.in: Regenerate.
208 * aclocal.m4: Regenerate.
209 * config.in: Regenerate.
210 * configure: Regenerate.
211
899d85be
AM		 2122008-08-14 Sebastian Huber <sebastian.huber@embedded-brains.de>
213
214 PR 6825
215 * ppc-opc.c (powerpc_opcodes): Enable rfci, mfpmr, mtpmr for e300.
216
dfb07592
L		 2172008-08-12 H.J. Lu <hongjiu.lu@intel.com>
218
219 * i386-opc.tbl: Add syscall and sysret for Cpu64.
220
221 * i386-tbl.h: Regenerated.
222
323ee3f4
AM		 2232008-08-04 Alan Modra <amodra@bigpond.net.au>
224
225 * Makefile.am (POTFILES.in): Set LC_ALL=C.
226 * Makefile.in: Regenerate.
227 * po/POTFILES.in: Regenerate.
228
9b4e5766
PB		 2292008-08-01 Peter Bergner <bergner@vnet.ibm.com>
230
231 * ppc-dis.c (powerpc_init_dialect): Handle power7 and vsx options.
232 (print_insn_powerpc): Prepend 'vs' when printing VSX registers.
233 (print_ppc_disassembler_options): Document -Mpower7 and -Mvsx.
234 * ppc-opc.c (insert_xt6): New static function.
235 (extract_xt6): Likewise.
236 (insert_xa6): Likewise.
237 (extract_xa6: Likewise.
238 (insert_xb6): Likewise.
239 (extract_xb6): Likewise.
240 (insert_xb6s): Likewise.
241 (extract_xb6s): Likewise.
242 (XS6, XT6, XA6, XB6, XB6S, DM, XX3, XX3DM, XX1_MASK, XX3_MASK,
243 XX3DM_MASK, PPCVSX): New.
244 (powerpc_opcodes): Add opcodes "lxvd2x", "lxvd2ux", "stxvd2x",
245 "stxvd2ux", "xxmrghd", "xxmrgld", "xxpermdi", "xvmovdp", "xvcpsgndp".
246
20fd6e2e
PA		 2472008-08-01 Pedro Alves <pedro@codesourcery.com>
248
249 * Makefile.am ($(srcdir)/ia64-asmtab.c): Remove line continuation.
250 * Makefile.in: Regenerate.
251
a656ed5b
L		 2522008-08-01 H.J. Lu <hongjiu.lu@intel.com>
253
254 * i386-reg.tbl: Use Dw2Inval on AVX registers.
255 * i386-tbl.h: Regenerated.
256
081ba1b3
AM		 2572008-07-30 Michael J. Eager <eager@eagercon.com>
258
259 * ppc-dis.c (print_insn_powerpc): Disassemble FSL/FCR/UDI fields.
260 * ppc-opc.c (powerpc_operands): Add Xilinx APU related operands.
261 (insert_sprg, PPC405): Use PPC_OPCODE_405.
262 (powerpc_opcodes): Add Xilinx APU related opcodes.
263
0af1713e
AM		 2642008-07-30 Alan Modra <amodra@bigpond.net.au>
265
266 * bfin-dis.c, cris-dis.c, i386-dis.c, or32-opc.c: Silence gcc warnings.
267
30c09090
RS		 2682008-07-10 Richard Sandiford <rdsandiford@googlemail.com>
269
270 * mips-dis.c (_print_insn_mips): Use ELF_ST_IS_MIPS16.
271
c27e721e
AN		 2722008-07-07 Adam Nemet <anemet@caviumnetworks.com>
273
274 * mips-opc.c (CP): New macro.
275 (mips_builtin_opcodes): Mark c0, c2 and c3 as CP. Add Octeon to the
276 membership of di, dmfc0, dmtc0, ei, mfc0 and mtc0. Add dmfc2 and
277 dmtc2 Octeon instructions.
278
bd2e2557
SS		 2792008-07-07 Stan Shebs <stan@codesourcery.com>
280
281 * dis-init.c (init_disassemble_info): Init endian_code field.
282 * arm-dis.c (print_insn): Disassemble code according to
283 setting of endian_code.
284 (print_insn_big_arm): Detect when BE8 extension flag has been set.
285
6ba2a415
RS		 2862008-06-30 Richard Sandiford <rdsandiford@googlemail.com>
287
288 * mips-dis.c (_print_insn_mips): Use bfd_asymbol_flavour to check
289 for ELF symbols.
290
c8187e15
PB		 2912008-06-25 Peter Bergner <bergner@vnet.ibm.com>
292
293 * ppc-dis.c (powerpc_init_dialect): Handle -M464.
294 (print_ppc_disassembler_options): Likewise.
295 * ppc-opc.c (PPC464): Define.
296 (powerpc_opcodes): Add mfdcrux and mtdcrux.
297
7a283e07
RW		 2982008-06-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
299
300 * configure: Regenerate.
301
fa452fa6
PB		 3022008-06-13 Peter Bergner <bergner@vnet.ibm.com>
303
304 * ppc-dis.c (print_insn_powerpc): Update prototye to use new
305 ppc_cpu_t typedef.
306 (struct dis_private): New.
307 (POWERPC_DIALECT): New define.
308 (powerpc_dialect): Renamed to...
309 (powerpc_init_dialect): This. Update to use ppc_cpu_t and
310 struct dis_private.
311 (print_insn_big_powerpc): Update for using structure in
312 info->private_data.
313 (print_insn_little_powerpc): Likewise.
314 (operand_value_powerpc): Change type of dialect param to ppc_cpu_t.
315 (skip_optional_operands): Likewise.
316 (print_insn_powerpc): Likewise. Remove initialization of dialect.
317 * ppc-opc.c (extract_bat, extract_bba, extract_bdm, extract_bdp,
318 extract_bo, extract_boe, extract_fxm, extract_mb6, extract_mbe,
319 extract_nb, extract_nsi, extract_rbs, extract_sh6, extract_spr,
320 extract_sprg, extract_tbr insert_bat, insert_bba, insert_bdm,
321 insert_bdp, insert_bo, insert_boe, insert_fxm, insert_mb6, insert_mbe,
322 insert_nsi, insert_ral, insert_ram, insert_raq, insert_ras, insert_rbs,
323 insert_sh6, insert_spr, insert_sprg, insert_tbr): Change the dialect
324 param to be of type ppc_cpu_t. Update prototype.
325
bb35fb24
NC		 3262008-06-12 Adam Nemet <anemet@caviumnetworks.com>
327
328 * mips-dis.c (print_insn_args): Handle field descriptors +x, +p,
329 +s, +S.
330 * mips-opc.c (mips_builtin_opcodes): Add Octeon instructions
331 baddu, bbit*, cins*, dmul, pop, dpop, exts*, mtm*, mtp*, syncs,
332 syncw, syncws, vm3mulu, vm0 and vmulu.
333
dd3cbb7e
NC		 334 * mips-dis.c (print_insn_args): Handle field descriptor +Q.
335 * mips-opc.c (mips_builtin_opcodes): Add Octeon instructions seq,
336 seqi, sne and snei.
337
a5dabbb0
L		 3382008-05-30 H.J. Lu <hongjiu.lu@intel.com>
339
340 * i386-opc.tbl: Add vmovd with 64bit operand.
341 * i386-tbl.h: Regenerated.
342
725a9891
MS		 3432008-05-27 Martin Schwidefsky <schwidefsky@de.ibm.com>
344
345 * s390-opc.c (INSTR_RRF_R0RR): Fix RRF_R0RR operand format.
346
cbc80391
L		 3472008-05-22 H.J. Lu <hongjiu.lu@intel.com>
348
349 * i386-opc.tbl: Add NoAVX to cvtpd2pi, cvtpi2pd and cvttpd2pi.
350 * i386-tbl.h: Regenerated.
351
116615c5
L		 3522008-05-22 H.J. Lu <hongjiu.lu@intel.com>
353
354 PR gas/6517
355 * i386-opc.tbl: Break cvtsi2ss/cvtsi2sd/vcvtsi2sd/vcvtsi2ss
3c6528a8 356 into 32bit and 64bit. Remove Reg64|Qword and add
116615c5
L		 357 IgnoreSize|No_qSuf on 32bit version.
358 * i386-tbl.h: Regenerated.
359
d9479f2d
L		 3602008-05-21 H.J. Lu <hongjiu.lu@intel.com>
361
362 * i386-opc.tbl: Add NoAVX to movdq2q and movq2dq.
363 * i386-tbl.h: Regenerated.
364
3ce6fddb
NC		 3652008-05-21 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
366
367 * cr16-dis.c (build_mask): Adjust the mask for 32-bit bcond.
368
8944f3c2
AM		 3692008-05-14 Alan Modra <amodra@bigpond.net.au>
370
371 * Makefile.am: Run "make dep-am".
372 * Makefile.in: Regenerate.
373
f1f8f695
L		 3742008-05-02 H.J. Lu <hongjiu.lu@intel.com>
375
376 * i386-dis.c (MOVBE_Fixup): New.
377 (Mo): Likewise.
378 (PREFIX_0F3880): Likewise.
379 (PREFIX_0F3881): Likewise.
380 (PREFIX_0F38F0): Updated.
381 (prefix_table): Add PREFIX_0F3880 and PREFIX_0F3881. Update
382 PREFIX_0F38F0 and PREFIX_0F38F1 for movbe.
383 (three_byte_table): Use PREFIX_0F3880 and PREFIX_0F3881.
384
385 * i386-gen.c (cpu_flag_init): Add CPU_MOVBE_FLAGS and
386 CPU_EPT_FLAGS.
387 (cpu_flags): Add CpuMovbe and CpuEPT.
388
389 * i386-opc.h (CpuMovbe): New.
390 (CpuEPT): Likewise.
391 (CpuLM): Updated.
392 (i386_cpu_flags): Add cpumovbe and cpuept.
393
394 * i386-opc.tbl: Add entries for movbe and EPT instructions.
395 * i386-init.h: Regenerated.
396 * i386-tbl.h: Likewise.
397
89aa3097
AN		 3982008-04-29 Adam Nemet <anemet@caviumnetworks.com>
399
400 * mips-opc.c (mips_builtin_opcodes): Set field `match' to 0 for
401 the two drem and the two dremu macros.
402
39c5c168
AN		 4032008-04-28 Adam Nemet <anemet@caviumnetworks.com>
404
405 * mips-opc.c (mips_builtin_opcodes): Mark prefx and c1
406 instructions FP_S. Mark l.s, li.s, lwc1, swc1, s.s, trunc.w.s and
407 cop1 macros INSN2_M_FP_S. Mark l.d, li.d, ldc1 and sdc1 macros
408 INSN2_M_FP_D. Mark trunc.w.d macro INSN2_M_FP_S and INSN2_M_FP_D.
409
f04d18b7
DM		 4102008-04-25 David S. Miller <davem@davemloft.net>
411
412 * sparc-dis.c: Emit %stick instead of %sys_tick, and %stick_cmpr
413 instead of %sys_tick_cmpr, as suggested in architecture manuals.
414
6194aaab
L		 4152008-04-23 Paolo Bonzini <bonzini@gnu.org>
416
417 * aclocal.m4: Regenerate.
418 * configure: Regenerate.
419
1a6b486f
DM		 4202008-04-23 David S. Miller <davem@davemloft.net>
421
422 * sparc-opc.c (asi_table): Add UltraSPARC and Niagara
423 extended values.
424 (prefetch_table): Add missing values.
425
81f8a913
L		 4262008-04-22 H.J. Lu <hongjiu.lu@intel.com>
427
428 * i386-gen.c (opcode_modifiers): Add NoAVX.
429
430 * i386-opc.h (NoAVX): New.
431 (OldGcc): Updated.
432 (i386_opcode_modifier): Add noavx.
433
434 * i386-opc.tbl: Add NoAVX to SSE, SSE2, SSE3 and SSSE3
435 instructions which don't have AVX equivalent.
436 * i386-tbl.h: Regenerated.
437
dae39acc
L		 4382008-04-18 H.J. Lu <hongjiu.lu@intel.com>
439
440 * i386-dis.c (OP_VEX_FMA): New.
441 (OP_EX_VexImmW): Likewise.
442 (VexFMA): Likewise.
443 (Vex128FMA): Likewise.
444 (EXVexImmW): Likewise.
445 (get_vex_imm8): Likewise.
446 (OP_EX_VexReg): Likewise.
447 (vex_i4_done): Renamed to ...
448 (vex_w_done): This.
449 (prefix_table): Replace EXVexW with EXVexImmW on vpermil2ps
450 and vpermil2pd. Replace Vex/Vex128 with VexFMA/Vex128FMA on
451 FMA instructions.
452 (print_insn): Updated.
453 (OP_EX_VexW): Rewrite to swap register in VEX with EX.
454 (OP_REG_VexI4): Check invalid high registers.
455
ce886ab1
DR		 4562008-04-16 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
457 Michael Meissner <michael.meissner@amd.com>
458
459 * i386-opc.tbl: Fix protX to allow memory in the middle operand.
460 * i386-tbl.h: Regenerate from i386-opc.tbl.
8944f3c2 461
19a6653c
AM		 4622008-04-14 Edmar Wienskoski <edmar@freescale.com>
463
464 * ppc-dis.c (powerpc_dialect): Handle "e500mc". Extend "e500" to
465 accept Power E500MC instructions.
466 (print_ppc_disassembler_options): Document -Me500mc.
467 * ppc-opc.c (DUIS, DUI, T): New.
468 (XRT, XRTRA): Likewise.
469 (E500MC): Likewise.
470 (powerpc_opcodes): Add new Power E500MC instructions.
471
112b7c50
AK		 4722008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
473
474 * s390-dis.c (init_disasm): Evaluate disassembler_options.
475 (print_s390_disassembler_options): New function.
476 * disassemble.c (disassembler_usage): Invoke
477 print_s390_disassembler_options.
478
7ff42648
AK		 4792008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
480
481 * s390-mkopc.c (insertExpandedMnemonic): Expand string sizes
482 of local variables used for mnemonic parsing: prefix, suffix and
483 number.
484
45a5551e
AK		 4852008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
486
487 * s390-mkopc.c (s390_cond_ext_format): Add back the mnemonic
488 extensions for conditional jumps (o, p, m, nz, z, nm, np, no).
489 (s390_crb_extensions): New extensions table.
490 (insertExpandedMnemonic): Handle '$' tag.
491 * s390-opc.txt: Remove conditional jump variants which can now
492 be expanded automatically.
493 Replace '*' tag with '$' in the compare and branch instructions.
494
06c8514a
L		 4952008-04-07 H.J. Lu <hongjiu.lu@intel.com>
496
497 * i386-dis.c (PREFIX_VEX_38XX): Add a tab.
498 (PREFIX_VEX_3AXX): Likewis.
499
b122c285
L		 5002008-04-07 H.J. Lu <hongjiu.lu@intel.com>
501
502 * i386-opc.tbl: Remove 4 extra blank lines.
503
594ab6a3
L		 5042008-04-04 H.J. Lu <hongjiu.lu@intel.com>
505
506 * i386-gen.c (cpu_flag_init): Replace CPU_CLMUL_FLAGS/CpuCLMUL
507 with CPU_PCLMUL_FLAGS/CpuPCLMUL.
508 (cpu_flags): Replace CpuCLMUL with CpuPCLMUL.
509 * i386-opc.tbl: Likewise.
510
511 * i386-opc.h (CpuCLMUL): Renamed to ...
512 (CpuPCLMUL): This.
513 (CpuFMA): Updated.
514 (i386_cpu_flags): Replace cpuclmul with cpupclmul.
515
516 * i386-init.h: Regenerated.
517
c0f3af97
L		 5182008-04-03 H.J. Lu <hongjiu.lu@intel.com>
519
520 * i386-dis.c (OP_E_register): New.
521 (OP_E_memory): Likewise.
522 (OP_VEX): Likewise.
523 (OP_EX_Vex): Likewise.
524 (OP_EX_VexW): Likewise.
525 (OP_XMM_Vex): Likewise.
526 (OP_XMM_VexW): Likewise.
527 (OP_REG_VexI4): Likewise.
528 (PCLMUL_Fixup): Likewise.
529 (VEXI4_Fixup): Likewise.
530 (VZERO_Fixup): Likewise.
531 (VCMP_Fixup): Likewise.
532 (VPERMIL2_Fixup): Likewise.
533 (rex_original): Likewise.
534 (rex_ignored): Likewise.
535 (Mxmm): Likewise.
536 (XMM): Likewise.
537 (EXxmm): Likewise.
538 (EXxmmq): Likewise.
539 (EXymmq): Likewise.
540 (Vex): Likewise.
541 (Vex128): Likewise.
542 (Vex256): Likewise.
543 (VexI4): Likewise.
544 (EXdVex): Likewise.
545 (EXqVex): Likewise.
546 (EXVexW): Likewise.
547 (EXdVexW): Likewise.
548 (EXqVexW): Likewise.
549 (XMVex): Likewise.
550 (XMVexW): Likewise.
551 (XMVexI4): Likewise.
552 (PCLMUL): Likewise.
553 (VZERO): Likewise.
554 (VCMP): Likewise.
555 (VPERMIL2): Likewise.
556 (xmm_mode): Likewise.
557 (xmmq_mode): Likewise.
558 (ymmq_mode): Likewise.
559 (vex_mode): Likewise.
560 (vex128_mode): Likewise.
561 (vex256_mode): Likewise.
562 (USE_VEX_C4_TABLE): Likewise.
563 (USE_VEX_C5_TABLE): Likewise.
564 (USE_VEX_LEN_TABLE): Likewise.
565 (VEX_C4_TABLE): Likewise.
566 (VEX_C5_TABLE): Likewise.
567 (VEX_LEN_TABLE): Likewise.
568 (REG_VEX_XX): Likewise.
569 (MOD_VEX_XXX): Likewise.
570 (PREFIX_0F38DB..PREFIX_0F38DF): Likewise.
571 (PREFIX_0F3A44): Likewise.
572 (PREFIX_0F3ADF): Likewise.
573 (PREFIX_VEX_XXX): Likewise.
574 (VEX_OF): Likewise.
575 (VEX_OF38): Likewise.
576 (VEX_OF3A): Likewise.
577 (VEX_LEN_XXX): Likewise.
578 (vex): Likewise.
579 (need_vex): Likewise.
580 (need_vex_reg): Likewise.
581 (vex_i4_done): Likewise.
582 (vex_table): Likewise.
583 (vex_len_table): Likewise.
584 (OP_REG_VexI4): Likewise.
585 (vex_cmp_op): Likewise.
586 (pclmul_op): Likewise.
587 (vpermil2_op): Likewise.
588 (m_mode): Updated.
589 (es_reg): Likewise.
590 (PREFIX_0F38F0): Likewise.
591 (PREFIX_0F3A60): Likewise.
592 (reg_table): Add REG_VEX_71...REG_VEX_73 and REG_VEX_AE.
593 (prefix_table): Add PREFIX_0F38DB..PREFIX_0F38DF, PREFIX_0F3ADF
594 and PREFIX_VEX_XXX entries.
595 (x86_64_table): Use VEX_C4_TABLE and VEX_C5_TABLE.
596 (three_byte_table): Use PREFIX_0F38DB..PREFIX_0F38DF and
597 PREFIX_0F3ADF.
598 (mod_table): Use VEX_C4_TABLE, VEX_C5_TABLE and VEX_LEN_TABLE.
599 Add MOD_VEX_XXX entries.
600 (ckprefix): Initialize rex_original and rex_ignored. Store the
601 REX byte in rex_original.
602 (get_valid_dis386): Handle the implicit prefix in VEX prefix
603 bytes and USE_VEX_LEN_TABLE/USE_VEX_C4_TABLE/USE_VEX_C5_TABLE.
604 (print_insn): Set need_vex/need_vex_reg/vex_i4_done to 0 before
605 calling get_valid_dis386. Use rex_original and rex_ignored when
606 printing out REX.
607 (putop): Handle "XY".
608 (intel_operand_size): Handle VEX, xmm_mode, xmmq_mode and
609 ymmq_mode.
610 (OP_E_extended): Updated to use OP_E_register and
611 OP_E_memory.
612 (OP_XMM): Handle VEX.
613 (OP_EX): Likewise.
614 (XMM_Fixup): Likewise.
615 (CMP_Fixup): Use ARRAY_SIZE.
616
617 * i386-gen.c (cpu_flag_init): Add CpuAES, CPU_CLMUL_FLAGS,
618 CPU_FMA_FLAGS and CPU_AVX_FLAGS.
619 (operand_type_init): Add OPERAND_TYPE_REGYMM and
620 OPERAND_TYPE_VEX_IMM4.
621 (cpu_flags): Add CpuAVX, CpuAES, CpuCLMUL and CpuFMA.
622 (opcode_modifiers): Add Implicit1stXmm0, Vex, Vex256, VexNDD,
623 VexNDS, VexW0, VexW1, Vex0F, Vex0F38, Vex0F3A, Vex3Sources,
624 VexImmExt and SSE2AVX.
625 (operand_types): Add RegYMM, Ymmword and Vex_Imm4.
626
627 * i386-opc.h (CpuAVX): New.
628 (CpuAES): Likewise.
629 (CpuCLMUL): Likewise.
630 (CpuFMA): Likewise.
631 (Vex): Likewise.
632 (Vex256): Likewise.
633 (VexNDS): Likewise.
634 (VexNDD): Likewise.
635 (VexW0): Likewise.
636 (VexW1): Likewise.
637 (Vex0F): Likewise.
638 (Vex0F38): Likewise.
639 (Vex0F3A): Likewise.
640 (Vex3Sources): Likewise.
641 (VexImmExt): Likewise.
642 (SSE2AVX): Likewise.
643 (RegYMM): Likewise.
644 (Ymmword): Likewise.
645 (Vex_Imm4): Likewise.
646 (Implicit1stXmm0): Likewise.
647 (CpuXsave): Updated.
648 (CpuLM): Likewise.
649 (ByteOkIntel): Likewise.
650 (OldGcc): Likewise.
651 (Control): Likewise.
652 (Unspecified): Likewise.
653 (OTMax): Likewise.
654 (i386_cpu_flags): Add cpuavx, cpuaes, cpuclmul and cpufma.
655 (i386_opcode_modifier): Add implicit1stxmm0, vex, vex256,
656 vexnds, vexndd, vexw0, vexw1, vex0f, vex0f38, vex0f3a,
657 vex3sources, veximmext and sse2avx.
658 (i386_operand_type): Add regymm, ymmword and vex_imm4.
659
660 * i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions.
661
662 * i386-reg.tbl: Add AVX registers, ymm0..ymm15.
663
664 * i386-init.h: Regenerated.
665 * i386-tbl.h: Likewise.
666
b21c9cb4
BS		 6672008-03-26 Bernd Schmidt <bernd.schmidt@analog.com>
668
669 From Robin Getz <robin.getz@analog.com>
670 * bfin-dis.c (bu32): Typedef.
671 (enum const_forms_t): Add c_uimm32 and c_huimm32.
672 (constant_formats[]): Add uimm32 and huimm16.
673 (fmtconst_val): New.
674 (uimm32): Define.
675 (huimm32): Define.
676 (imm16_val): Define.
677 (luimm16_val): Define.
678 (struct saved_state): Define.
679 (GREG, DPREG, DREG, PREG, SPREG, FPREG, IREG, MREG, BREG, LREG,
680 A0XREG, A0WREG, A1XREG, A1WREG,CCREG, LC0REG, LT0REG, LB0REG,
681 LC1REG, LT1REG, LB1REG, RETSREG, PCREG): Define.
682 (get_allreg): New.
683 (decode_LDIMMhalf_0): Print out the whole register value.
684
ee171c8f
BS		 685 From Jie Zhang <jie.zhang@analog.com>
686 * bfin-dis.c (decode_dsp32mac_0): Decode (IU) option for
687 multiply and multiply-accumulate to data register instruction.
688
086134ec
BS		 689 * bfin-dis.c: (c_uimm4s4d, c_imm5d, c_imm7d, c_imm16d, c_uimm16s4d,
690 c_imm32, c_huimm32e): Define.
691 (constant_formats): Add flags for printing decimal, leading spaces, and
692 exact symbols.
693 (comment, parallel): Add global flags in all disassembly.
694 (fmtconst): Take advantage of new flags, and print default in hex.
695 (fmtconst_val): Likewise.
696 (decode_macfunc): Be consistant with spaces, tabs, comments,
697 capitalization in disassembly, fix minor coding style issues.
698 (reg_names, amod0, amod1, amod0amod2, aligndir, get_allreg): Likewise.
699 (decode_ProgCtrl_0, decode_PushPopMultiple_0, decode_CCflag_0,
700 decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0,
701 decode_REGMV_0, decode_ALU2op_0, decode_PTR2op_0, decode_LOGI2op_0,
702 decode_COMP3op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
703 decode_LDSTpmod_0, decode_dagMODim_0, decode_dagMODik_0,
704 decode_dspLDST_0, decode_LDST_0, decode_LDSTiiFP_0, decode_LDSTii_0,
705 decode_LoopSetup_0, decode_LDIMMhalf_0, decode_CALLa_0,
706 decode_LDSTidxI_0, decode_linkage_0, decode_dsp32alu_0,
707 decode_dsp32shift_0, decode_dsp32shiftimm_0, decode_pseudodbg_assert_0,
708 _print_insn_bfin, print_insn_bfin): Likewise.
709
58c85be7
RW		 7102008-03-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
711
712 * aclocal.m4: Regenerate.
713 * configure: Likewise.
714 * Makefile.in: Likewise.
715
50e7d84b
AM		 7162008-03-13 Alan Modra <amodra@bigpond.net.au>
717
718 * Makefile.am: Run "make dep-am".
719 * Makefile.in: Regenerate.
720 * configure: Regenerate.
721
de866fcc
AM		 7222008-03-07 Alan Modra <amodra@bigpond.net.au>
723
724 * ppc-opc.c (powerpc_opcodes): Order and format.
725
28dbc079
L		 7262008-03-01 H.J. Lu <hongjiu.lu@intel.com>
727
728 * i386-opc.tbl: Allow 16-bit near indirect branches for x86-64.
729 * i386-tbl.h: Regenerated.
730
849830bd
L		 7312008-02-23 H.J. Lu <hongjiu.lu@intel.com>
732
733 * i386-opc.tbl: Disallow 16-bit near indirect branches for
734 x86-64.
735 * i386-tbl.h: Regenerated.
736
743ddb6b
JB		 7372008-02-21 Jan Beulich <jbeulich@novell.com>
738
739 * i386-opc.tbl: Allow Dword for far indirect call. Allow Dword
740 and Fword for far indirect jmp. Allow Reg16 and Word for near
741 indirect jmp on x86-64. Disallow Fword for lcall.
742 * i386-tbl.h: Re-generate.
743
796d5313
NC		 7442008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
745
746 * cr16-opc.c (cr16_num_optab): Defined
747
65da13b5
L		 7482008-02-16 H.J. Lu <hongjiu.lu@intel.com>
749
750 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_INOUTPORTREG.
751 * i386-init.h: Regenerated.
752
0e336180
NC		 7532008-02-14 Nick Clifton <nickc@redhat.com>
754
755 PR binutils/5524
756 * configure.in (SHARED_LIBADD): Select the correct host specific
757 file extension for shared libraries.
758 * configure: Regenerate.
759
b7240065
JB		 7602008-02-13 Jan Beulich <jbeulich@novell.com>
761
762 * i386-opc.h (RegFlat): New.
763 * i386-reg.tbl (flat): Add.
764 * i386-tbl.h: Re-generate.
765
34b772a6
JB		 7662008-02-13 Jan Beulich <jbeulich@novell.com>
767
768 * i386-dis.c (a_mode): New.
769 (cond_jump_mode): Adjust.
770 (Ma): Change to a_mode.
771 (intel_operand_size): Handle a_mode.
772 * i386-opc.tbl: Allow Dword and Qword for bound.
773 * i386-tbl.h: Re-generate.
774
a60de03c
JB		 7752008-02-13 Jan Beulich <jbeulich@novell.com>
776
777 * i386-gen.c (process_i386_registers): Process new fields.
778 * i386-opc.h (reg_entry): Shrink reg_flags and reg_num to
779 unsigned char. Add dw2_regnum and Dw2Inval.
780 * i386-reg.tbl: Provide initializers for dw2_regnum. Add pseudo
781 register names.
782 * i386-tbl.h: Re-generate.
783
f03fe4c1
L		 7842008-02-11 H.J. Lu <hongjiu.lu@intel.com>
785
4b6bc8eb 786 * i386-gen.c (cpu_flag_init): Add CPU_XSAVE_FLAGS.
f03fe4c1
L		 787 * i386-init.h: Updated.
788
475a2301
L		 7892008-02-11 H.J. Lu <hongjiu.lu@intel.com>
790
791 * i386-gen.c (cpu_flags): Add CpuXsave.
792
793 * i386-opc.h (CpuXsave): New.
4b6bc8eb 794 (CpuLM): Updated.
475a2301
L		 795 (i386_cpu_flags): Add cpuxsave.
796
797 * i386-dis.c (MOD_0FAE_REG_4): New.
798 (RM_0F01_REG_2): Likewise.
799 (MOD_0FAE_REG_5): Updated.
800 (RM_0F01_REG_3): Likewise.
801 (reg_table): Use MOD_0FAE_REG_4.
802 (mod_table): Use RM_0F01_REG_2. Add MOD_0FAE_REG_4. Updated
803 for xrstor.
804 (rm_table): Add RM_0F01_REG_2.
805
806 * i386-opc.tbl: Add xsave, xrstor, xgetbv and xsetbv.
807 * i386-init.h: Regenerated.
808 * i386-tbl.h: Likewise.
809
595785c6 8102008-02-11 Jan Beulich <jbeulich@novell.com>
041179fc 811
595785c6
JB		 812 * i386-opc.tbl: Remove Disp32S from CpuNo64 opcodes. Remove
813 Disp16 from Cpu64 non-jump opcodes (including loop and j?cxz).
814 * i386-tbl.h: Re-generate.
815
bb8541b9
L		 8162008-02-04 H.J. Lu <hongjiu.lu@intel.com>
817
818 PR 5715
819 * configure: Regenerated.
820
57b592a3
AN		 8212008-02-04 Adam Nemet <anemet@caviumnetworks.com>
822
823 * mips-dis.c: Update copyright.
824 (mips_arch_choices): Add Octeon.
825 * mips-opc.c: Update copyright.
826 (IOCT): New macro.
827 (mips_builtin_opcodes): Add Octeon instruction synciobdma.
828
930bb4cf
AM		 8292008-01-29 Alan Modra <amodra@bigpond.net.au>
830
831 * ppc-opc.c: Support optional L form mtmsr.
832
82c18208
L		 8332008-01-24 H.J. Lu <hongjiu.lu@intel.com>
834
835 * i386-dis.c (OP_E_extended): Handle r12 like rsp.
836
599121aa
L		 8372008-01-23 H.J. Lu <hongjiu.lu@intel.com>
838
839 * i386-gen.c (cpu_flag_init): Add CpuLM to CPU_GENERIC64_FLAGS.
840 * i386-init.h: Regenerated.
841
80098f51
TG		 8422008-01-23 Tristan Gingold <gingold@adacore.com>
843
844 * ia64-dis.c (print_insn_ia64): Display symbolic name of ar.fcr,
845 ar.eflag, ar.csd, ar.ssd, ar.cflg, ar.fsr, ar.fir and ar.fdr.
846
115c7c25
L		 8472008-01-22 H.J. Lu <hongjiu.lu@intel.com>
848
849 * i386-gen.c (cpu_flag_init): Remove CpuMMX2.
850 (cpu_flags): Likewise.
851
852 * i386-opc.h (CpuMMX2): Removed.
853 (CpuSSE): Updated.
854
855 * i386-opc.tbl: Replace CpuMMX2 with CpuSSE|Cpu3dnowA.
856 * i386-init.h: Regenerated.
857 * i386-tbl.h: Likewise.
858
6305a203
L		 8592008-01-22 H.J. Lu <hongjiu.lu@intel.com>
860
861 * i386-gen.c (cpu_flag_init): Add CPU_VMX_FLAGS and
862 CPU_SMX_FLAGS.
863 * i386-init.h: Regenerated.
864
fd07a1c8
L		 8652008-01-15 H.J. Lu <hongjiu.lu@intel.com>
866
867 * i386-opc.tbl: Use Qword on movddup.
868 * i386-tbl.h: Regenerated.
869
321fd21e
L		 8702008-01-15 H.J. Lu <hongjiu.lu@intel.com>
871
872 * i386-opc.tbl: Put back 16bit movsx/movzx for AT&T syntax.
873 * i386-tbl.h: Regenerated.
874
4ee52178
L		 8752008-01-15 H.J. Lu <hongjiu.lu@intel.com>
876
877 * i386-dis.c (Mx): New.
878 (PREFIX_0FC3): Likewise.
879 (PREFIX_0FC7_REG_6): Updated.
880 (dis386_twobyte): Use PREFIX_0FC3.
881 (prefix_table): Add PREFIX_0FC3. Use Mq on movntq and movntsd.
882 Use Mx on movntps, movntpd, movntdq and movntdqa. Use Md on
883 movntss.
884
5c07affc
L		 8852008-01-14 H.J. Lu <hongjiu.lu@intel.com>
886
887 * i386-gen.c (opcode_modifiers): Add IntelSyntax.
888 (operand_types): Add Mem.
889
890 * i386-opc.h (IntelSyntax): New.
891 * i386-opc.h (Mem): New.
892 (Byte): Updated.
893 (Opcode_Modifier_Max): Updated.
894 (i386_opcode_modifier): Add intelsyntax.
895 (i386_operand_type): Add mem.
896
897 * i386-opc.tbl: Remove Reg16 from movnti. Add sizes to more
898 instructions.
899
900 * i386-reg.tbl: Add size for accumulator.
901
902 * i386-init.h: Regenerated.
903 * i386-tbl.h: Likewise.
904
0d6a2f58
L		 9052008-01-13 H.J. Lu <hongjiu.lu@intel.com>
906
907 * i386-opc.h (Byte): Fix a typo.
908
7d5e4556
L		 9092008-01-12 H.J. Lu <hongjiu.lu@intel.com>
910
911 PR gas/5534
912 * i386-gen.c (operand_type_init): Add Dword to
913 OPERAND_TYPE_ACC32. Add Qword to OPERAND_TYPE_ACC64.
914 (opcode_modifiers): Remove CheckSize, Byte, Word, Dword,
915 Qword and Xmmword.
916 (operand_types): Add Byte, Word, Dword, Fword, Qword, Tbyte,
917 Xmmword, Unspecified and Anysize.
918 (set_bitfield): Make Mmword an alias of Qword. Make Oword
919 an alias of Xmmword.
920
921 * i386-opc.h (CheckSize): Removed.
922 (Byte): Updated.
923 (Word): Likewise.
924 (Dword): Likewise.
925 (Qword): Likewise.
926 (Xmmword): Likewise.
927 (FWait): Updated.
928 (OTMax): Likewise.
929 (i386_opcode_modifier): Remove checksize, byte, word, dword,
930 qword and xmmword.
931 (Fword): New.
932 (TBYTE): Likewise.
933 (Unspecified): Likewise.
934 (Anysize): Likewise.
935 (i386_operand_type): Add byte, word, dword, fword, qword,
936 tbyte xmmword, unspecified and anysize.
937
938 * i386-opc.tbl: Updated to use Byte, Word, Dword, Fword, Qword,
939 Tbyte, Xmmword, Unspecified and Anysize.
940
941 * i386-reg.tbl: Add size for accumulator.
942
943 * i386-init.h: Regenerated.
944 * i386-tbl.h: Likewise.
945
b5b1fc4f
L		 9462008-01-10 H.J. Lu <hongjiu.lu@intel.com>
947
948 * i386-dis.c (REG_0F0E): Renamed to REG_0F0D.
949 (REG_0F18): Updated.
950 (reg_table): Updated.
951 (dis386_twobyte): Updated. Use "nopQ" on 0x19 to 0x1e.
952 (twobyte_has_modrm): Set 1 for 0x19 to 0x1e.
953
50e8458f
L		 9542008-01-08 H.J. Lu <hongjiu.lu@intel.com>
955
956 * i386-gen.c (set_bitfield): Use fail () on error.
957
3d4d5afa
L		 9582008-01-08 H.J. Lu <hongjiu.lu@intel.com>
959
960 * i386-gen.c (lineno): New.
961 (filename): Likewise.
962 (set_bitfield): Report filename and line numer on error.
963 (process_i386_opcodes): Set filename and update lineno.
964 (process_i386_registers): Likewise.
965
e1d4d893
L		 9662008-01-05 H.J. Lu <hongjiu.lu@intel.com>
967
968 * i386-gen.c (opcode_modifiers): Rename IntelMnemonic to
969 ATTSyntax.
970
971 * i386-opc.h (IntelMnemonic): Renamed to ..
972 (ATTSyntax): This
973 (Opcode_Modifier_Max): Updated.
974 (i386_opcode_modifier): Remove intelmnemonic. Add attsyntax
975 and intelsyntax.
976
8944f3c2 977 * i386-opc.tbl: Remove IntelMnemonic and update with ATTSyntax
e1d4d893
L		 978 on fsub, fubp, fsubr, fsubrp, div, fdivp, fdivr and fdivrp.
979 * i386-tbl.h: Regenerated.
980
6f143e4d
L		 9812008-01-04 H.J. Lu <hongjiu.lu@intel.com>
982
983 * i386-gen.c: Update copyright to 2008.
984 * i386-opc.h: Likewise.
985 * i386-opc.tbl: Likewise.
986
987 * i386-init.h: Regenerated.
988 * i386-tbl.h: Likewise.
989
c6add537
L		 9902008-01-04 H.J. Lu <hongjiu.lu@intel.com>
991
992 * i386-opc.tbl: Add NoRex64 to extractps, movmskpd, movmskps,
993 pextrb, pextrw, pinsrb, pinsrw and pmovmskb.
994 * i386-tbl.h: Regenerated.
995
3629bb00
L		 9962008-01-03 H.J. Lu <hongjiu.lu@intel.com>
997
998 * i386-gen.c (cpu_flag_init): Remove CpuSSE4_1_Or_5 and
999 CpuSSE4_2_Or_ABM.
1000 (cpu_flags): Likewise.
1001
1002 * i386-opc.h (CpuSSE4_1_Or_5): Removed.
1003 (CpuSSE4_2_Or_ABM): Likewise.
1004 (CpuLM): Updated.
1005 (i386_cpu_flags): Remove cpusse4_1_or_5 and cpusse4_2_or_abm.
1006
1007 * i386-opc.tbl: Replace CpuSSE4_1_Or_5, CpuSSE4_2_Or_ABM and
1008 Cpu686|CpuPadLock with CpuSSE4_1|CpuSSE5, CpuABM|CpuSSE4_2
1009 and CpuPadLock, respectively.
1010 * i386-init.h: Regenerated.
1011 * i386-tbl.h: Likewise.
1012
24995bd6
L		 10132008-01-03 H.J. Lu <hongjiu.lu@intel.com>
1014
1015 * i386-gen.c (opcode_modifiers): Remove No_xSuf.
1016
1017 * i386-opc.h (No_xSuf): Removed.
1018 (CheckSize): Updated.
1019
1020 * i386-tbl.h: Regenerated.
1021
e0329a22
L		 10222008-01-02 H.J. Lu <hongjiu.lu@intel.com>
1023
1024 * i386-gen.c (cpu_flag_init): Add CpuSSE4_2_Or_ABM to
1025 CPU_AMDFAM10_FLAGS, CPU_SSE4_2_FLAGS, CpuABM and
1026 CPU_SSE5_FLAGS.
1027 (cpu_flags): Add CpuSSE4_2_Or_ABM.
1028
1029 * i386-opc.h (CpuSSE4_2_Or_ABM): New.
1030 (CpuLM): Updated.
1031 (i386_cpu_flags): Add cpusse4_2_or_abm.
1032
1033 * i386-opc.tbl: Use CpuSSE4_2_Or_ABM instead of
1034 CpuABM|CpuSSE4_2 on popcnt.
1035 * i386-init.h: Regenerated.
1036 * i386-tbl.h: Likewise.
1037
f2a9c676
L		 10382008-01-02 H.J. Lu <hongjiu.lu@intel.com>
1039
1040 * i386-opc.h: Update comments.
1041
d978b5be
L		 10422008-01-02 H.J. Lu <hongjiu.lu@intel.com>
1043
1044 * i386-gen.c (opcode_modifiers): Use Qword instead of QWord.
1045 * i386-opc.h: Likewise.
1046 * i386-opc.tbl: Likewise.
1047
582d5edd
L		 10482008-01-02 H.J. Lu <hongjiu.lu@intel.com>
1049
1050 PR gas/5534
1051 * i386-gen.c (opcode_modifiers): Add No_xSuf, CheckSize,
1052 Byte, Word, Dword, QWord and Xmmword.
1053
1054 * i386-opc.h (No_xSuf): New.
1055 (CheckSize): Likewise.
1056 (Byte): Likewise.
1057 (Word): Likewise.
1058 (Dword): Likewise.
1059 (QWord): Likewise.
1060 (Xmmword): Likewise.
1061 (FWait): Updated.
1062 (i386_opcode_modifier): Add No_xSuf, CheckSize, Byte, Word,
1063 Dword, QWord and Xmmword.
1064
1065 * i386-opc.tbl: Add CheckSize|QWord to movq if IgnoreSize is
1066 used.
1067 * i386-tbl.h: Regenerated.
1068
3fe15143
MK		 10692008-01-02 Mark Kettenis <kettenis@gnu.org>
1070
1071 * m88k-dis.c (instructions): Fix fcvt.* instructions.
1072 From Miod Vallat.
1073
6c7ac64e 1074For older changes see ChangeLog-2007
252b5132
RH		 1075\f
1076Local Variables:
2f6d2f85
NC		 1077mode: change-log
1078left-margin: 8
1079fill-column: 74
252b5132
RH		 1080version-control: never
1081End:
GDB Binutils - Deliverables
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