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[AArch64] Add ARMv8.3 single source PAC instructions
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
a2cfc830
SN		 12016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
2
3 * aarch64-tbl.h (arch64_opcode_table): Add pacia, pacib, pacda, pacdb, autia,
4 autib, autda, autdb, paciza, pacizb, pacdza, pacdzb, autiza, autizb, autdza,
5 autdzb, xpaci, xpacd.
6 * aarch64-asm-2.c: Regenerate.
7 * aarch64-dis-2.c: Regenerate.
8 * aarch64-opc-2.c: Regenerate.
9
b0bfa7b5
SN		 102016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
11
12 * aarch64-opc.c (aarch64_sys_regs): Add apiakeylo_el1, apiakeyhi_el1,
13 apibkeylo_el1, apibkeyhi_el1, apdakeylo_el1, apdakeyhi_el1,
14 apdbkeylo_el1, apdbkeyhi_el1, apgakeylo_el1 and apgakeyhi_el1.
15 (aarch64_sys_reg_supported_p): Add feature test for new registers.
16
8787d804
SN		 172016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
18
19 * aarch64-tbl.h (aarch64_feature_v8_3, ARMV8_3, V8_3_INSN): New.
20 (arch64_opcode_table): Add xpaclri, pacia1716, pacib1716, autia1716,
21 autib1716, paciaz, paciasp, pacibz, pacibsp, autiaz, autiasp, autibz,
22 autibsp.
23 * aarch64-asm-2.c: Regenerate.
24 * aarch64-dis-2.c: Regenerate.
25
3d731f69
SN		 262016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
27
28 * aarch64-gen.c (find_alias_opcode): Increase max_num_aliases to 32.
29
60227d64
L		 302016-11-09 H.J. Lu <hongjiu.lu@intel.com>
31
32 PR binutils/20799
33 * i386-dis-evex.h (evex_table): Replace EdqwS with Edqw.
34 * i386-dis.c (EdqwS): Removed.
35 (dqw_swap_mode): Likewise.
36 (intel_operand_size): Don't check dqw_swap_mode.
37 (OP_E_register): Likewise.
38 (OP_E_memory): Likewise.
39 (OP_G): Likewise.
40 (OP_EX): Likewise.
41 * i386-opc.tbl: Remove "S" from EVEX vpextrw.
42 * i386-tbl.h: Regerated.
43
7efeed17
L		 442016-11-09 H.J. Lu <hongjiu.lu@intel.com>
45
46 * i386-opc.tbl: Merge AVX512F vmovq.
1032d6eb 47 * i386-tbl.h: Regerated.
7efeed17 48
1f334aeb
L		 492016-11-08 H.J. Lu <hongjiu.lu@intel.com>
50
51 PR binutils/20701
52 * i386-dis.c (THREE_BYTE_0F7A): Removed.
53 (dis386_twobyte): Don't use THREE_BYTE_0F7A.
54 (three_byte_table): Remove THREE_BYTE_0F7A.
55
48c97fa1
L		 562016-11-07 H.J. Lu <hongjiu.lu@intel.com>
57
58 PR binutils/20775
59 * i386-dis.c (FGRPd9_2): Replace 0 with 1.
60 (FGRPd9_4): Replace 1 with 2.
61 (FGRPd9_5): Replace 2 with 3.
62 (FGRPd9_6): Replace 3 with 4.
63 (FGRPd9_7): Replace 4 with 5.
64 (FGRPda_5): Replace 5 with 6.
65 (FGRPdb_4): Replace 6 with 7.
66 (FGRPde_3): Replace 7 with 8.
67 (FGRPdf_4): Replace 8 with 9.
68 (fgrps): Add an entry for Bad_Opcode.
69
b437d035
AB		 702016-11-04 Andrew Burgess <andrew.burgess@embecosm.com>
71
72 * arc-opc.c (arc_flag_operands): Add F_DI14.
73 (arc_flag_classes): Add C_DI14.
74 * arc-nps400-tbl.h: Add new exc instructions.
75
5a736821
GM		 762016-11-03 Graham Markall <graham.markall@embecosm.com>
77
78 * arc-dis.c (arc_insn_length): Return length 8 for instructions with
79 major opcode 0xa.
80 * arc-nps-400-tbl.h: Add dcmac instruction.
81 * arc-opc.c (arc_operands): Added operands for dcmac instruction.
82 (insert_nps_rbdouble_64): Added.
83 (extract_nps_rbdouble_64): Added.
84 (insert_nps_proto_size): Added.
85 (extract_nps_proto_size): Added.
86
bdfe53e3
AB		 872016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
88
89 * arc-dis.c (struct arc_operand_iterator): Remove all fields
90 relating to long instruction processing, add new limm field.
91 (OPCODE): Rename to...
92 (OPCODE_32BIT_INSN): ...this.
93 (OPCODE_AC): Delete.
94 (skip_this_opcode): Handle different instruction lengths, update
95 macro name.
96 (special_flag_p): Update parameter type.
97 (find_format_from_table): Update for more instruction lengths.
98 (find_format_long_instructions): Delete.
99 (find_format): Update for more instruction lengths.
100 (arc_insn_length): Likewise.
101 (extract_operand_value): Update for more instruction lengths.
102 (operand_iterator_next): Remove code relating to long
103 instructions.
104 (arc_opcode_to_insn_type): New function.
105 (print_insn_arc):Update for more instructions lengths.
106 * arc-ext.c (extInstruction_t): Change argument type.
107 * arc-ext.h (extInstruction_t): Change argument type.
108 * arc-fxi.h: Change type unsigned to unsigned long long
109 extensively throughout.
110 * arc-nps400-tbl.h: Add long instructions taken from
111 arc_long_opcodes table in arc-opc.c.
112 * arc-opc.c: Update parameter types on insert/extract handlers.
113 (arc_long_opcodes): Delete.
114 (arc_num_long_opcodes): Delete.
115 (arc_opcode_len): Update for more instruction lengths.
116
90f61cce
GM		 1172016-11-03 Graham Markall <graham.markall@embecosm.com>
118
119 * arc-dis.c (print_insn_arc): Swap highbyte and lowbyte.
120
06fe285f
GM		 1212016-11-03 Graham Markall <graham.markall@embecosm.com>
122
123 * arc-dis.c (find_format_from_table): Replace use of ARC_SHORT
124 with arc_opcode_len.
125 (find_format_long_instructions): Likewise.
126 * arc-opc.c (arc_opcode_len): New function.
127
ecf64ec6
AB		 1282016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
129
130 * arc-nps400-tbl.h: Fix some instruction masks.
131
d039fef3
L		 1322016-11-03 H.J. Lu <hongjiu.lu@intel.com>
133
134 * i386-dis.c (REG_82): Removed.
135 (X86_64_82_REG_0): Likewise.
136 (X86_64_82_REG_1): Likewise.
137 (X86_64_82_REG_2): Likewise.
138 (X86_64_82_REG_3): Likewise.
139 (X86_64_82_REG_4): Likewise.
140 (X86_64_82_REG_5): Likewise.
141 (X86_64_82_REG_6): Likewise.
142 (X86_64_82_REG_7): Likewise.
143 (X86_64_82): New.
144 (dis386): Use X86_64_82 instead of REG_82.
145 (reg_table): Remove REG_82.
146 (x86_64_table): Add X86_64_82. Remove X86_64_82_REG_0,
147 X86_64_82_REG_1, X86_64_82_REG_2, X86_64_82_REG_3,
148 X86_64_82_REG_4, X86_64_82_REG_5, X86_64_82_REG_6 and
149 X86_64_82_REG_7.
150
8b89fe14
L		 1512016-11-03 H.J. Lu <hongjiu.lu@intel.com>
152
153 PR binutils/20754
154 * i386-dis.c (REG_82): New.
155 (X86_64_82_REG_0): Likewise.
156 (X86_64_82_REG_1): Likewise.
157 (X86_64_82_REG_2): Likewise.
158 (X86_64_82_REG_3): Likewise.
159 (X86_64_82_REG_4): Likewise.
160 (X86_64_82_REG_5): Likewise.
161 (X86_64_82_REG_6): Likewise.
162 (X86_64_82_REG_7): Likewise.
163 (dis386): Use REG_82.
164 (reg_table): Add REG_82.
165 (x86_64_table): Add X86_64_82_REG_0, X86_64_82_REG_1,
166 X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4,
167 X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7.
168
7148c369
L		 1692016-11-03 H.J. Lu <hongjiu.lu@intel.com>
170
171 * i386-dis.c (REG_82): Renamed to ...
172 (REG_83): This.
173 (dis386): Updated.
174 (reg_table): Likewise.
175
47acf0bd
IT		 1762016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
177
178 * i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853.
179 * i386-dis-evex.h (evex_table): Updated.
180 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS,
181 CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
182 (cpu_flags): Add CpuAVX512_4VNNIW.
183 * i386-opc.h (enum): (AVX512_4VNNIW): New.
184 (i386_cpu_flags): Add cpuavx512_4vnniw.
185 * i386-opc.tbl: Add Intel AVX512_4VNNIW instructions.
186 * i386-init.h: Regenerate.
187 * i386-tbl.h: Ditto.
188
920d2ddc
IT		 1892016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
190
191 * i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,
192 PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.
193 * i386-dis-evex.h (evex_table): Updated.
194 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,
195 CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
196 (cpu_flags): Add CpuAVX512_4FMAPS.
197 (opcode_modifiers): Add ImplicitQuadGroup modifier.
198 * i386-opc.h (AVX512_4FMAP): New.
199 (i386_cpu_flags): Add cpuavx512_4fmaps.
200 (ImplicitQuadGroup): New.
201 (i386_opcode_modifier): Add implicitquadgroup.
202 * i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.
203 * i386-init.h: Regenerate.
204 * i386-tbl.h: Ditto.
205
e23eba97
NC		 2062016-11-01 Palmer Dabbelt <palmer@dabbelt.com>
207 Andrew Waterman <andrew@sifive.com>
208
209 Add support for RISC-V architecture.
210 * configure.ac: Add entry for bfd_riscv_arch.
211 * configure: Regenerate.
212 * disassemble.c (disassembler): Add support for riscv.
213 (disassembler_usage): Likewise.
214 * riscv-dis.c: New file.
215 * riscv-opc.c: New file.
216
b5cefcca
L		 2172016-10-21 H.J. Lu <hongjiu.lu@intel.com>
218
219 * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
220 (prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
221 (rm_table): Update the RM_0FAE_REG_7 entry.
222 * i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
223 (cpu_flags): Remove CpuPCOMMIT.
224 * i386-opc.h (CpuPCOMMIT): Removed.
225 (i386_cpu_flags): Remove cpupcommit.
226 * i386-opc.tbl: Remove pcommit.
227 * i386-init.h: Regenerated.
228 * i386-tbl.h: Likewise.
229
9889cbb1
L		 2302016-10-20 H.J. Lu <hongjiu.lu@intel.com>
231
232 PR binutis/20705
233 * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
234 the highest bit in VEX.vvvv for the 3-byte VEX prefix in
235 32-bit mode. Don't check vex.register_specifier in 32-bit
236 mode.
237 (OP_VEX): Check for invalid mask registers.
238
28596323
L		 2392016-10-18 H.J. Lu <hongjiu.lu@intel.com>
240
241 PR binutis/20699
242 * i386-dis.c (OP_E_memory): Check addr32flag in stead of
243 sizeflag.
244
da8d7d66
L		 2452016-10-18 H.J. Lu <hongjiu.lu@intel.com>
246
247 PR binutis/20704
248 * i386-dis.c (three_byte_table): Remove the remaining SSE5 support.
249
eaf02703
MR		 2502016-10-18 Maciej W. Rozycki <macro@imgtec.com>
251
252 * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'
253 local variable to `index_regno'.
254
decf5bd1
CM		 2552016-10-17 Cupertino Miranda <cmiranda@synopsys.com>
256
257 * arc-tbl.h: Removed any "inv.+" instructions from the table.
258
e5b06ef0
CZ		 2592016-10-14 Claudiu Zissulescu <claziss@synopsys.com>
260
261 * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
262 usage on ISA basis.
263
93562a34
JW		 2642016-10-11 Jiong Wang <jiong.wang@arm.com>
265
266 PR target/20666
267 * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
268
362c0c4d
JW		 2692016-10-07 Jiong Wang <jiong.wang@arm.com>
270
271 PR target/20667
272 * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
273 available.
274
1047201f
AM		 2752016-10-07 Alan Modra <amodra@gmail.com>
276
277 * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
278
1a0670f3
AM		 2792016-10-06 Alan Modra <amodra@gmail.com>
280
281 * aarch64-opc.c: Spell fall through comments consistently.
282 * i386-dis.c: Likewise.
283 * aarch64-dis.c: Add missing fall through comments.
284 * aarch64-opc.c: Likewise.
285 * arc-dis.c: Likewise.
286 * arm-dis.c: Likewise.
287 * i386-dis.c: Likewise.
288 * m68k-dis.c: Likewise.
289 * mep-asm.c: Likewise.
290 * ns32k-dis.c: Likewise.
291 * sh-dis.c: Likewise.
292 * tic4x-dis.c: Likewise.
293 * tic6x-dis.c: Likewise.
294 * vax-dis.c: Likewise.
295
2b804145
AM		 2962016-10-06 Alan Modra <amodra@gmail.com>
297
298 * arc-ext.c (create_map): Add missing break.
299 * msp430-decode.opc (encode_as): Likewise.
300 * msp430-decode.c: Regenerate.
301
616ec358
AM		 3022016-10-06 Alan Modra <amodra@gmail.com>
303
304 * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
305 * crx-dis.c (print_insn_crx): Likewise.
306
72da393d
L		 3072016-09-30 H.J. Lu <hongjiu.lu@intel.com>
308
309 PR binutils/20657
310 * i386-dis.c (putop): Don't assign alt twice.
311
744ce302
JW		 3122016-09-29 Jiong Wang <jiong.wang@arm.com>
313
314 PR target/20553
315 * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
316
a5721ba2
AM		 3172016-09-29 Alan Modra <amodra@gmail.com>
318
319 * ppc-opc.c (L): Make compulsory.
320 (LOPT): New, optional form of L.
321 (HTM_R): Define as LOPT.
322 (L0, L1): Delete.
323 (L32OPT): New, optional for 32-bit L.
324 (L2OPT): New, 2-bit L for dcbf.
325 (SVC_LEC): Update.
326 (L2): Define.
327 (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
328 (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
329 <dcbf>: Use L2OPT.
330 <tlbiel, tlbie>: Use LOPT.
331 <wclr, wclrall>: Use L2.
332
c5da1932
VZ		 3332016-09-26 Vlad Zakharov <vzakhar@synopsys.com>
334
335 * Makefile.in: Regenerate.
336 * configure: Likewise.
337
2b848ebd
CZ		 3382016-09-26 Claudiu Zissulescu <claziss@synopsys.com>
339
340 * arc-ext-tbl.h (EXTINSN2OPF): Define.
341 (EXTINSN2OP): Use EXTINSN2OPF.
342 (bspeekm, bspop, modapp): New extension instructions.
343 * arc-opc.c (F_DNZ_ND): Define.
344 (F_DNZ_D): Likewise.
345 (F_SIZEB1): Changed.
346 (C_DNZ_D): Define.
347 (C_HARD): Changed.
348 * arc-tbl.h (dbnz): New instruction.
349 (prealloc): Allow it for ARC EM.
350 (xbfu): Likewise.
351
ad43e107
RS		 3522016-09-21 Richard Sandiford <richard.sandiford@arm.com>
353
354 * aarch64-opc.c (print_immediate_offset_address): Print spaces
355 after commas in addresses.
356 (aarch64_print_operand): Likewise.
357
ab3b8fcf
RS		 3582016-09-21 Richard Sandiford <richard.sandiford@arm.com>
359
360 * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
361 rather than "should be" or "expected to be" in error messages.
362
bb7eff52
RS		 3632016-09-21 Richard Sandiford <richard.sandiford@arm.com>
364
365 * aarch64-dis.c (remove_dot_suffix): New function, split out from...
366 (print_mnemonic_name): ...here.
367 (print_comment): New function.
368 (print_aarch64_insn): Call it.
369 * aarch64-opc.c (aarch64_conds): Add SVE names.
370 (aarch64_print_operand): Print alternative condition names in
371 a comment.
372
c0890d26
RS		 3732016-09-21 Richard Sandiford <richard.sandiford@arm.com>
374
375 * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
376 (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
377 (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
378 (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
379 (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
380 (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
381 (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
382 (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
383 (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
384 (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
385 (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
386 (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
387 (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
388 (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
389 (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
390 (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
391 (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
392 (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
393 (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
394 (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
395 (OP_SVE_XWU, OP_SVE_XXU): New macros.
396 (aarch64_feature_sve): New variable.
397 (SVE): New macro.
398 (_SVE_INSN): Likewise.
399 (aarch64_opcode_table): Add SVE instructions.
400 * aarch64-opc.h (extract_fields): Declare.
401 * aarch64-opc-2.c: Regenerate.
402 * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
403 * aarch64-asm-2.c: Regenerate.
404 * aarch64-dis.c (extract_fields): Make global.
405 (do_misc_decoding): Handle the new SVE aarch64_ops.
406 * aarch64-dis-2.c: Regenerate.
407
116b6019
RS		 4082016-09-21 Richard Sandiford <richard.sandiford@arm.com>
409
410 * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
411 (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
412 aarch64_field_kinds.
413 * aarch64-opc.c (fields): Add corresponding entries.
414 * aarch64-asm.c (aarch64_get_variant): New function.
415 (aarch64_encode_variant_using_iclass): Likewise.
416 (aarch64_opcode_encode): Call it.
417 * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
418 (aarch64_opcode_decode): Call it.
419
047cd301
RS		 4202016-09-21 Richard Sandiford <richard.sandiford@arm.com>
421
422 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
423 and FP register operands.
424 * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
425 (FLD_SVE_Vn): New aarch64_field_kinds.
426 * aarch64-opc.c (fields): Add corresponding entries.
427 (aarch64_print_operand): Handle the new SVE core and FP register
428 operands.
429 * aarch64-opc-2.c: Regenerate.
430 * aarch64-asm-2.c: Likewise.
431 * aarch64-dis-2.c: Likewise.
432
165d4950
RS		 4332016-09-21 Richard Sandiford <richard.sandiford@arm.com>
434
435 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
436 immediate operands.
437 * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
438 * aarch64-opc.c (fields): Add corresponding entry.
439 (operand_general_constraint_met_p): Handle the new SVE FP immediate
440 operands.
441 (aarch64_print_operand): Likewise.
442 * aarch64-opc-2.c: Regenerate.
443 * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
444 (ins_sve_float_zero_one): New inserters.
445 * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
446 (aarch64_ins_sve_float_half_two): Likewise.
447 (aarch64_ins_sve_float_zero_one): Likewise.
448 * aarch64-asm-2.c: Regenerate.
449 * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
450 (ext_sve_float_zero_one): New extractors.
451 * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
452 (aarch64_ext_sve_float_half_two): Likewise.
453 (aarch64_ext_sve_float_zero_one): Likewise.
454 * aarch64-dis-2.c: Regenerate.
455
e950b345
RS		 4562016-09-21 Richard Sandiford <richard.sandiford@arm.com>
457
458 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
459 integer immediate operands.
460 * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
461 (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
462 (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
463 * aarch64-opc.c (fields): Add corresponding entries.
464 (operand_general_constraint_met_p): Handle the new SVE integer
465 immediate operands.
466 (aarch64_print_operand): Likewise.
467 (aarch64_sve_dupm_mov_immediate_p): New function.
468 * aarch64-opc-2.c: Regenerate.
469 * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
470 (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
471 * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
472 (aarch64_ins_limm): ...here.
473 (aarch64_ins_inv_limm): New function.
474 (aarch64_ins_sve_aimm): Likewise.
475 (aarch64_ins_sve_asimm): Likewise.
476 (aarch64_ins_sve_limm_mov): Likewise.
477 (aarch64_ins_sve_shlimm): Likewise.
478 (aarch64_ins_sve_shrimm): Likewise.
479 * aarch64-asm-2.c: Regenerate.
480 * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
481 (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
482 * aarch64-dis.c (decode_limm): New function, split out from...
483 (aarch64_ext_limm): ...here.
484 (aarch64_ext_inv_limm): New function.
485 (decode_sve_aimm): Likewise.
486 (aarch64_ext_sve_aimm): Likewise.
487 (aarch64_ext_sve_asimm): Likewise.
488 (aarch64_ext_sve_limm_mov): Likewise.
489 (aarch64_top_bit): Likewise.
490 (aarch64_ext_sve_shlimm): Likewise.
491 (aarch64_ext_sve_shrimm): Likewise.
492 * aarch64-dis-2.c: Regenerate.
493
98907a70
RS		 4942016-09-21 Richard Sandiford <richard.sandiford@arm.com>
495
496 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
497 operands.
498 * aarch64-opc.c (aarch64_operand_modifiers): Initialize
499 the AARCH64_MOD_MUL_VL entry.
500 (value_aligned_p): Cope with non-power-of-two alignments.
501 (operand_general_constraint_met_p): Handle the new MUL VL addresses.
502 (print_immediate_offset_address): Likewise.
503 (aarch64_print_operand): Likewise.
504 * aarch64-opc-2.c: Regenerate.
505 * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
506 (ins_sve_addr_ri_s9xvl): New inserters.
507 * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
508 (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
509 (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
510 * aarch64-asm-2.c: Regenerate.
511 * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
512 (ext_sve_addr_ri_s9xvl): New extractors.
513 * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
514 (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
515 (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
516 (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
517 * aarch64-dis-2.c: Regenerate.
518
4df068de
RS		 5192016-09-21 Richard Sandiford <richard.sandiford@arm.com>
520
521 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
522 address operands.
523 * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
524 (FLD_SVE_xs_22): New aarch64_field_kinds.
525 (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
526 (get_operand_specific_data): New function.
527 * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
528 FLD_SVE_xs_14 and FLD_SVE_xs_22.
529 (operand_general_constraint_met_p): Handle the new SVE address
530 operands.
531 (sve_reg): New array.
532 (get_addr_sve_reg_name): New function.
533 (aarch64_print_operand): Handle the new SVE address operands.
534 * aarch64-opc-2.c: Regenerate.
535 * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
536 (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
537 (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
538 * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
539 (aarch64_ins_sve_addr_rr_lsl): Likewise.
540 (aarch64_ins_sve_addr_rz_xtw): Likewise.
541 (aarch64_ins_sve_addr_zi_u5): Likewise.
542 (aarch64_ins_sve_addr_zz): Likewise.
543 (aarch64_ins_sve_addr_zz_lsl): Likewise.
544 (aarch64_ins_sve_addr_zz_sxtw): Likewise.
545 (aarch64_ins_sve_addr_zz_uxtw): Likewise.
546 * aarch64-asm-2.c: Regenerate.
547 * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
548 (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
549 (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
550 * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
551 (aarch64_ext_sve_addr_ri_u6): Likewise.
552 (aarch64_ext_sve_addr_rr_lsl): Likewise.
553 (aarch64_ext_sve_addr_rz_xtw): Likewise.
554 (aarch64_ext_sve_addr_zi_u5): Likewise.
555 (aarch64_ext_sve_addr_zz): Likewise.
556 (aarch64_ext_sve_addr_zz_lsl): Likewise.
557 (aarch64_ext_sve_addr_zz_sxtw): Likewise.
558 (aarch64_ext_sve_addr_zz_uxtw): Likewise.
559 * aarch64-dis-2.c: Regenerate.
560
2442d846
RS		 5612016-09-21 Richard Sandiford <richard.sandiford@arm.com>
562
563 * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
564 AARCH64_OPND_SVE_PATTERN_SCALED.
565 * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
566 * aarch64-opc.c (fields): Add a corresponding entry.
567 (set_multiplier_out_of_range_error): New function.
568 (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
569 (operand_general_constraint_met_p): Handle
570 AARCH64_OPND_SVE_PATTERN_SCALED.
571 (print_register_offset_address): Use PRIi64 to print the
572 shift amount.
573 (aarch64_print_operand): Likewise. Handle
574 AARCH64_OPND_SVE_PATTERN_SCALED.
575 * aarch64-opc-2.c: Regenerate.
576 * aarch64-asm.h (ins_sve_scale): New inserter.
577 * aarch64-asm.c (aarch64_ins_sve_scale): New function.
578 * aarch64-asm-2.c: Regenerate.
579 * aarch64-dis.h (ext_sve_scale): New inserter.
580 * aarch64-dis.c (aarch64_ext_sve_scale): New function.
581 * aarch64-dis-2.c: Regenerate.
582
245d2e3f
RS		 5832016-09-21 Richard Sandiford <richard.sandiford@arm.com>
584
585 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
586 AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
587 * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
588 (FLD_SVE_prfop): Likewise.
589 * aarch64-opc.c: Include libiberty.h.
590 (aarch64_sve_pattern_array): New variable.
591 (aarch64_sve_prfop_array): Likewise.
592 (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
593 (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
594 AARCH64_OPND_SVE_PRFOP.
595 * aarch64-asm-2.c: Regenerate.
596 * aarch64-dis-2.c: Likewise.
597 * aarch64-opc-2.c: Likewise.
598
d50c751e
RS		 5992016-09-21 Richard Sandiford <richard.sandiford@arm.com>
600
601 * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
602 AARCH64_OPND_QLF_P_[ZM].
603 (aarch64_print_operand): Print /z and /m where appropriate.
604
f11ad6bc
RS		 6052016-09-21 Richard Sandiford <richard.sandiford@arm.com>
606
607 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
608 * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
609 (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
610 (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
611 (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
612 * aarch64-opc.c (fields): Add corresponding entries here.
613 (operand_general_constraint_met_p): Check that SVE register lists
614 have the correct length. Check the ranges of SVE index registers.
615 Check for cases where p8-p15 are used in 3-bit predicate fields.
616 (aarch64_print_operand): Handle the new SVE operands.
617 * aarch64-opc-2.c: Regenerate.
618 * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
619 * aarch64-asm.c (aarch64_ins_sve_index): New function.
620 (aarch64_ins_sve_reglist): Likewise.
621 * aarch64-asm-2.c: Regenerate.
622 * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
623 * aarch64-dis.c (aarch64_ext_sve_index): New function.
624 (aarch64_ext_sve_reglist): Likewise.
625 * aarch64-dis-2.c: Regenerate.
626
0c608d6b
RS		 6272016-09-21 Richard Sandiford <richard.sandiford@arm.com>
628
629 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
630 (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
631 (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
632 * aarch64-opc.c (aarch64_match_operands_constraint): Check for
633 tied operands.
634
01dbfe4c
RS		 6352016-09-21 Richard Sandiford <richard.sandiford@arm.com>
636
637 * aarch64-opc.c (get_offset_int_reg_name): New function.
638 (print_immediate_offset_address): Likewise.
639 (print_register_offset_address): Take the base and offset
640 registers as parameters.
641 (aarch64_print_operand): Update caller accordingly. Use
642 print_immediate_offset_address.
643
72e9f319
RS		 6442016-09-21 Richard Sandiford <richard.sandiford@arm.com>
645
646 * aarch64-opc.c (BANK): New macro.
647 (R32, R64): Take a register number as argument
648 (int_reg): Use BANK.
649
8a7f0c1b
RS		 6502016-09-21 Richard Sandiford <richard.sandiford@arm.com>
651
652 * aarch64-opc.c (print_register_list): Add a prefix parameter.
653 (aarch64_print_operand): Update accordingly.
654
aa2aa4c6
RS		 6552016-09-21 Richard Sandiford <richard.sandiford@arm.com>
656
657 * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
658 for FPIMM.
659 * aarch64-asm.h (ins_fpimm): New inserter.
660 * aarch64-asm.c (aarch64_ins_fpimm): New function.
661 * aarch64-asm-2.c: Regenerate.
662 * aarch64-dis.h (ext_fpimm): New extractor.
663 * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
664 (aarch64_ext_fpimm): New function.
665 * aarch64-dis-2.c: Regenerate.
666
b5464a68
RS		 6672016-09-21 Richard Sandiford <richard.sandiford@arm.com>
668
669 * aarch64-asm.c: Include libiberty.h.
670 (insert_fields): New function.
671 (aarch64_ins_imm): Use it.
672 * aarch64-dis.c (extract_fields): New function.
673 (aarch64_ext_imm): Use it.
674
42408347
RS		 6752016-09-21 Richard Sandiford <richard.sandiford@arm.com>
676
677 * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
678 with an esize parameter.
679 (operand_general_constraint_met_p): Update accordingly.
680 Fix misindented code.
681 * aarch64-asm.c (aarch64_ins_limm): Update call to
682 aarch64_logical_immediate_p.
683
4989adac
RS		 6842016-09-21 Richard Sandiford <richard.sandiford@arm.com>
685
686 * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
687
bd11d5d8
RS		 6882016-09-21 Richard Sandiford <richard.sandiford@arm.com>
689
690 * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
691
f807f43d
CZ		 6922016-09-15 Claudiu Zissulescu <claziss@synopsys.com>
693
694 * arc-dis.c (find_format): Walk the linked list pointed by einsn.
695
fd486b63
PB		 6962016-09-14 Peter Bergner <bergner@vnet.ibm.com>
697
698 * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
699 <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
700 xor3>: Delete mnemonics.
701 <cp_abort>: Rename mnemonic from ...
702 <cpabort>: ...to this.
703 <setb>: Change to a X form instruction.
704 <sync>: Change to 1 operand form.
705 <copy>: Delete mnemonic.
706 <copy_first>: Rename mnemonic from ...
707 <copy>: ...to this.
708 <paste, paste.>: Delete mnemonics.
709 <paste_last>: Rename mnemonic from ...
710 <paste.>: ...to this.
711
dce08442
AK		 7122016-09-14 Anton Kolesov <Anton.Kolesov@synopsys.com>
713
714 * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
715
952c3f51
AK		 7162016-09-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
717
718 * s390-mkopc.c (main): Support alternate arch strings.
719
8b71537b
PS		 7202016-09-12 Patrick Steuer <steuer@linux.vnet.ibm.com>
721
722 * s390-opc.txt: Fix kmctr instruction type.
723
5b64d091
L		 7242016-09-07 H.J. Lu <hongjiu.lu@intel.com>
725
726 * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
727 * i386-init.h: Regenerated.
728
7763838e
CM		 7292016-08-30 Cupertino Miranda <cmiranda@synopsys.com>
730
731 * opcodes/arc-dis.c (print_insn_arc): Changed.
732
1b8b6532
JM		 7332016-08-26 Jose E. Marchesi <jose.marchesi@oracle.com>
734
735 * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
736 camellia_fl.
737
1a336194
TP		 7382016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
739
740 * arm-dis.c (psr_name): Use hex as case labels. Add detection for
741 MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
742 FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
743
6b40c462
L		 7442016-08-24 H.J. Lu <hongjiu.lu@intel.com>
745
746 * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
747 (PREFIX_MOD_3_0FAE_REG_4): Likewise.
748 (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
749 PREFIX_MOD_3_0FAE_REG_4.
750 (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
751 PREFIX_MOD_3_0FAE_REG_4.
752 * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
753 (cpu_flags): Add CpuPTWRITE.
754 * i386-opc.h (CpuPTWRITE): New.
755 (i386_cpu_flags): Add cpuptwrite.
756 * i386-opc.tbl: Add ptwrite instruction.
757 * i386-init.h: Regenerated.
758 * i386-tbl.h: Likewise.
759
ab548d2d
AK		 7602016-08-24 Anton Kolesov <Anton.Kolesov@synopsys.com>
761
762 * arc-dis.h: Wrap around in extern "C".
763
344bde0a
RS		 7642016-08-23 Richard Sandiford <richard.sandiford@arm.com>
765
766 * aarch64-tbl.h (V8_2_INSN): New macro.
767 (aarch64_opcode_table): Use it.
768
5ce912d8
RS		 7692016-08-23 Richard Sandiford <richard.sandiford@arm.com>
770
771 * aarch64-tbl.h (aarch64_opcode_table): Make more use of
772 CORE_INSN, __FP_INSN and SIMD_INSN.
773
9d30b0bd
RS		 7742016-08-23 Richard Sandiford <richard.sandiford@arm.com>
775
776 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
777 (aarch64_opcode_table): Update uses accordingly.
778
dfdaec14
AJ		 7792016-07-25 Andrew Jenner <andrew@codesourcery.com>
780 Kwok Cheung Yeung <kcy@codesourcery.com>
781
782 opcodes/
783 * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
784 'e_cmplwi' to 'e_cmpli' instead.
785 (OPVUPRT, OPVUPRT_MASK): Define.
786 (powerpc_opcodes): Add E200Z4 insns.
787 (vle_opcodes): Add context save/restore insns.
788
7bd374a4
MR		 7892016-07-27 Maciej W. Rozycki <macro@imgtec.com>
790
791 * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
792 "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
793 "j".
794
db18dbab
GM		 7952016-07-27 Graham Markall <graham.markall@embecosm.com>
796
797 * arc-nps400-tbl.h: Change block comments to GNU format.
798 * arc-dis.c: Add new globals addrtypenames,
799 addrtypenames_max, and addtypeunknown.
800 (get_addrtype): New function.
801 (print_insn_arc): Print colons and address types when
802 required.
803 * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
804 define insert and extract functions for all address types.
805 (arc_operands): Add operands for colon and all address
806 types.
807 * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
808 * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
809 insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
810 * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
811 * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
812 insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
813
fecd57f9
L		 8142016-07-21 H.J. Lu <hongjiu.lu@intel.com>
815
816 * configure: Regenerated.
817
37fd5ef3
CZ		 8182016-07-20 Claudiu Zissulescu <claziss@synopsys.com>
819
820 * arc-dis.c (skipclass): New structure.
821 (decodelist): New variable.
822 (is_compatible_p): New function.
823 (new_element): Likewise.
824 (skip_class_p): Likewise.
825 (find_format_from_table): Use skip_class_p function.
826 (find_format): Decode first the extension instructions.
827 (print_insn_arc): Select either ARCEM or ARCHS based on elf
828 e_flags.
829 (parse_option): New function.
830 (parse_disassembler_options): Likewise.
831 (print_arc_disassembler_options): Likewise.
832 (print_insn_arc): Use parse_disassembler_options function. Proper
833 select ARCv2 cpu variant.
834 * disassemble.c (disassembler_usage): Add ARC disassembler
835 options.
836
92281a5b
MR		 8372016-07-13 Maciej W. Rozycki <macro@imgtec.com>
838
839 * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
840 annotation from the "nal" entry and reorder it beyond "bltzal".
841
6e7ced37
JM		 8422016-07-12 Jose E. Marchesi <jose.marchesi@oracle.com>
843
844 * sparc-opc.c (ldtxa): New macro.
845 (sparc_opcodes): Use the macro defined above to add entries for
846 the LDTXA instructions.
847 (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
848 instruction.
849
2f831b9a 8502016-07-07 James Bowman <james.bowman@ftdichip.com>
851
852 * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
853 and "jmpc".
854
c07315e0
JB		 8552016-07-01 Jan Beulich <jbeulich@suse.com>
856
857 * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
858 (movzb): Adjust to cover all permitted suffixes.
859 (movzw): New.
860 * i386-tbl.h: Re-generate.
861
9243100a
JB		 8622016-07-01 Jan Beulich <jbeulich@suse.com>
863
864 * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
865 (lgdt): Remove Tbyte from non-64-bit variant.
866 (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
867 xsaves64, xsavec64): Remove Disp16.
868 (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
869 Remove Disp32S from non-64-bit variants. Remove Disp16 from
870 64-bit variants.
871 (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
872 vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
873 vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
874 64-bit variants.
875 * i386-tbl.h: Re-generate.
876
8325cc63
JB		 8772016-07-01 Jan Beulich <jbeulich@suse.com>
878
879 * i386-opc.tbl (xlat): Remove RepPrefixOk.
880 * i386-tbl.h: Re-generate.
881
838441e4
YQ		 8822016-06-30 Yao Qi <yao.qi@linaro.org>
883
884 * arm-dis.c (print_insn): Fix typo in comment.
885
dab26bf4
RS		 8862016-06-28 Richard Sandiford <richard.sandiford@arm.com>
887
888 * aarch64-opc.c (operand_general_constraint_met_p): Check the
889 range of ldst_elemlist operands.
890 (print_register_list): Use PRIi64 to print the index.
891 (aarch64_print_operand): Likewise.
892
5703197e
TS		 8932016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
894
895 * mcore-opc.h: Remove sentinal.
896 * mcore-dis.c (print_insn_mcore): Adjust.
897
ce440d63
GM		 8982016-06-23 Graham Markall <graham.markall@embecosm.com>
899
900 * arc-opc.c: Correct description of availability of NPS400
901 features.
902
6fd3a02d
PB		 9032016-06-22 Peter Bergner <bergner@vnet.ibm.com>
904
905 * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
906 (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
907 mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
908 xor3>: New mnemonics.
909 <setb>: Change to a VX form instruction.
910 (insert_sh6): Add support for rldixor.
911 (extract_sh6): Likewise.
912
6b477896
TS		 9132016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
914
915 * arc-ext.h: Wrap in extern C.
916
bdd582db
GM		 9172016-06-21 Graham Markall <graham.markall@embecosm.com>
918
919 * arc-dis.c (arc_insn_length): Add comment on instruction length.
920 Use same method for determining instruction length on ARC700 and
921 NPS-400.
922 (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
923 * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
924 with the NPS400 subclass.
925 * arc-opc.c: Likewise.
926
96074adc
JM		 9272016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
928
929 * sparc-opc.c (rdasr): New macro.
930 (wrasr): Likewise.
931 (rdpr): Likewise.
932 (wrpr): Likewise.
933 (rdhpr): Likewise.
934 (wrhpr): Likewise.
935 (sparc_opcodes): Use the macros above to fix and expand the
936 definition of read/write instructions from/to
937 asr/privileged/hyperprivileged instructions.
938 * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
939 %hva_mask_nz. Prefer softint_set and softint_clear over
940 set_softint and clear_softint.
941 (print_insn_sparc): Support %ver in Rd.
942
7a10c22f
JM		 9432016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
944
945 * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
946 architecture according to the hardware capabilities they require.
947
4f26fb3a
JM		 9482016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
949
950 * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
951 (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
952 bfd_mach_sparc_v9{c,d,e,v,m}.
953 * sparc-opc.c (MASK_V9C): Define.
954 (MASK_V9D): Likewise.
955 (MASK_V9E): Likewise.
956 (MASK_V9V): Likewise.
957 (MASK_V9M): Likewise.
958 (v6): Add MASK_V9{C,D,E,V,M}.
959 (v6notlet): Likewise.
960 (v7): Likewise.
961 (v8): Likewise.
962 (v9): Likewise.
963 (v9andleon): Likewise.
964 (v9a): Likewise.
965 (v9b): Likewise.
966 (v9c): Define.
967 (v9d): Likewise.
968 (v9e): Likewise.
969 (v9v): Likewise.
970 (v9m): Likewise.
971 (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
972
3ee6e4fb
NC		 9732016-06-15 Nick Clifton <nickc@redhat.com>
974
975 * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
976 constants to match expected behaviour.
977 (nds32_parse_opcode): Likewise. Also for whitespace.
978
02f3be19
AB		 9792016-06-15 Andrew Burgess <andrew.burgess@embecosm.com>
980
981 * arc-opc.c (extract_rhv1): Extract value from insn.
982
6f9f37ed 9832016-06-14 Graham Markall <graham.markall@embecosm.com>
28215275
GM		 984
985 * arc-nps400-tbl.h: Add ldbit instruction.
986 * arc-opc.c: Add flag classes required for ldbit.
987
6f9f37ed 9882016-06-14 Graham Markall <graham.markall@embecosm.com>
9ba75c88
GM		 989
990 * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
991 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
992 support the above instructions.
993
6f9f37ed 9942016-06-14 Graham Markall <graham.markall@embecosm.com>
14053c19
GM		 995
996 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
997 imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
998 csma, cbba, zncv, and hofs.
999 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1000 support the above instructions.
1001
10022016-06-06 Graham Markall <graham.markall@embecosm.com>
1003
1004 * arc-nps400-tbl.h: Add andab and orab instructions.
1005
10062016-06-06 Graham Markall <graham.markall@embecosm.com>
1007
1008 * arc-nps400-tbl.h: Add addl-like instructions.
1009
10102016-06-06 Graham Markall <graham.markall@embecosm.com>
1011
1012 * arc-nps400-tbl.h: Add mxb and imxb instructions.
1013
10142016-06-06 Graham Markall <graham.markall@embecosm.com>
1015
1016 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
1017 instructions.
1018
b2cc3f6f
AK		 10192016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1020
1021 * s390-dis.c (option_use_insn_len_bits_p): New file scope
1022 variable.
1023 (init_disasm): Handle new command line option "insnlength".
1024 (print_s390_disassembler_options): Mention new option in help
1025 output.
1026 (print_insn_s390): Use the encoded insn length when dumping
1027 unknown instructions.
1028
1857fe72
DC		 10292016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
1030
1031 * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
1032 to the address and set as symbol address for LDS/ STS immediate operands.
1033
14b57c7c
AM		 10342016-06-07 Alan Modra <amodra@gmail.com>
1035
1036 * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
1037 cpu for "vle" to e500.
1038 * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
1039 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
1040 (PPCNONE): Delete, substitute throughout.
1041 (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
1042 except for major opcode 4 and 31.
1043 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
1044
4d1464f2
MW		 10452016-06-07 Matthew Wahab <matthew.wahab@arm.com>
1046
1047 * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
1048 ARM_EXT_RAS in relevant entries.
1049
026122a6
PB		 10502016-06-03 Peter Bergner <bergner@vnet.ibm.com>
1051
1052 PR binutils/20196
1053 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
1054 opcodes for E6500.
1055
07f5af7d
L		 10562016-06-03 H.J. Lu <hongjiu.lu@intel.com>
1057
1058 PR binutis/18386
1059 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
1060 (indir_v_mode): New.
1061 Add comments for '&'.
1062 (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
1063 (putop): Handle '&'.
1064 (intel_operand_size): Handle indir_v_mode.
1065 (OP_E_register): Likewise.
1066 * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
1067 64-bit indirect call/jmp for AMD64.
1068 * i386-tbl.h: Regenerated
1069
4eb6f892
AB		 10702016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
1071
1072 * arc-dis.c (struct arc_operand_iterator): New structure.
1073 (find_format_from_table): All the old content from find_format,
1074 with some minor adjustments, and parameter renaming.
1075 (find_format_long_instructions): New function.
1076 (find_format): Rewritten.
1077 (arc_insn_length): Add LSB parameter.
1078 (extract_operand_value): New function.
1079 (operand_iterator_next): New function.
1080 (print_insn_arc): Use new functions to find opcode, and iterator
1081 over operands.
1082 * arc-opc.c (insert_nps_3bit_dst_short): New function.
1083 (extract_nps_3bit_dst_short): New function.
1084 (insert_nps_3bit_src2_short): New function.
1085 (extract_nps_3bit_src2_short): New function.
1086 (insert_nps_bitop1_size): New function.
1087 (extract_nps_bitop1_size): New function.
1088 (insert_nps_bitop2_size): New function.
1089 (extract_nps_bitop2_size): New function.
1090 (insert_nps_bitop_mod4_msb): New function.
1091 (extract_nps_bitop_mod4_msb): New function.
1092 (insert_nps_bitop_mod4_lsb): New function.
1093 (extract_nps_bitop_mod4_lsb): New function.
1094 (insert_nps_bitop_dst_pos3_pos4): New function.
1095 (extract_nps_bitop_dst_pos3_pos4): New function.
1096 (insert_nps_bitop_ins_ext): New function.
1097 (extract_nps_bitop_ins_ext): New function.
1098 (arc_operands): Add new operands.
1099 (arc_long_opcodes): New global array.
1100 (arc_num_long_opcodes): New global.
1101 * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
1102
1fe0971e
TS		 11032016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1104
1105 * nds32-asm.h: Add extern "C".
1106 * sh-opc.h: Likewise.
1107
315f180f
GM		 11082016-06-01 Graham Markall <graham.markall@embecosm.com>
1109
1110 * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
1111 0,b,limm to the rflt instruction.
1112
a2b5fccc
TS		 11132016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1114
1115 * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
1116 constant.
1117
0cbd0046
L		 11182016-05-29 H.J. Lu <hongjiu.lu@intel.com>
1119
1120 PR gas/20145
1121 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
1122 CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
1123 CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
1124 CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
1125 CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
1126 * i386-init.h: Regenerated.
1127
1848e567
L		 11282016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1129
1130 PR gas/20145
1131 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
1132 CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
1133 CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
1134 Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
1135 CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
1136 CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
1137 CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
1138 Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
1139 CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
1140 CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
1141 CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
1142 for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
1143 CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
1144 CpuRegMask for AVX512.
1145 (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
1146 and CpuRegMask.
1147 (set_bitfield_from_cpu_flag_init): New function.
1148 (set_bitfield): Remove const on f. Call
1149 set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
1150 * i386-opc.h (CpuRegMMX): New.
1151 (CpuRegXMM): Likewise.
1152 (CpuRegYMM): Likewise.
1153 (CpuRegZMM): Likewise.
1154 (CpuRegMask): Likewise.
1155 (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
1156 and cpuregmask.
1157 * i386-init.h: Regenerated.
1158 * i386-tbl.h: Likewise.
1159
e92bae62
L		 11602016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1161
1162 PR gas/20154
1163 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
1164 (opcode_modifiers): Add AMD64 and Intel64.
1165 (main): Properly verify CpuMax.
1166 * i386-opc.h (CpuAMD64): Removed.
1167 (CpuIntel64): Likewise.
1168 (CpuMax): Set to CpuNo64.
1169 (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
1170 (AMD64): New.
1171 (Intel64): Likewise.
1172 (i386_opcode_modifier): Add amd64 and intel64.
1173 (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
1174 on call and jmp.
1175 * i386-init.h: Regenerated.
1176 * i386-tbl.h: Likewise.
1177
e89c5eaa
L		 11782016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1179
1180 PR gas/20154
1181 * i386-gen.c (main): Fail if CpuMax is incorrect.
1182 * i386-opc.h (CpuMax): Set to CpuIntel64.
1183 * i386-tbl.h: Regenerated.
1184
77d66e7b
NC		 11852016-05-27 Nick Clifton <nickc@redhat.com>
1186
1187 PR target/20150
1188 * msp430-dis.c (msp430dis_read_two_bytes): New function.
1189 (msp430dis_opcode_unsigned): New function.
1190 (msp430dis_opcode_signed): New function.
1191 (msp430_singleoperand): Use the new opcode reading functions.
1192 Only disassenmble bytes if they were successfully read.
1193 (msp430_doubleoperand): Likewise.
1194 (msp430_branchinstr): Likewise.
1195 (msp430x_callx_instr): Likewise.
1196 (print_insn_msp430): Check that it is safe to read bytes before
1197 attempting disassembly. Use the new opcode reading functions.
1198
19dfcc89
PB		 11992016-05-26 Peter Bergner <bergner@vnet.ibm.com>
1200
1201 * ppc-opc.c (CY): New define. Document it.
1202 (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
1203
f3ad7637
L		 12042016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1205
1206 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
1207 CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
1208 and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
1209 CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
1210 CPU_ANY_AVX_FLAGS.
1211 * i386-init.h: Regenerated.
1212
f1360d58
L		 12132016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1214
1215 PR gas/20141
1216 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
1217 CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
1218 * i386-init.h: Regenerated.
1219
293f5f65
L		 12202016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1221
1222 * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
1223 CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
1224 * i386-init.h: Regenerated.
1225
d9eca1df
CZ		 12262016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1227
1228 * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
1229 information.
1230 (print_insn_arc): Set insn_type information.
1231 * arc-opc.c (C_CC): Add F_CLASS_COND.
1232 * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
1233 (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
1234 (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
1235 (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
1236 (brne, brne_s, jeq_s, jne_s): Likewise.
1237
87789e08
CZ		 12382016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1239
1240 * arc-tbl.h (neg): New instruction variant.
1241
c810e0b8
CZ		 12422016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
1243
1244 * arc-dis.c (find_format, find_format, get_auxreg)
1245 (print_insn_arc): Changed.
1246 * arc-ext.h (INSERT_XOP): Likewise.
1247
3d207518
TS		 12482016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1249
1250 * tic54x-dis.c (sprint_mmr): Adjust.
1251 * tic54x-opc.c: Likewise.
1252
514e58b7
AM		 12532016-05-19 Alan Modra <amodra@gmail.com>
1254
1255 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
1256
e43de63c
AM		 12572016-05-19 Alan Modra <amodra@gmail.com>
1258
1259 * ppc-opc.c: Formatting.
1260 (NSISIGNOPT): Define.
1261 (powerpc_opcodes <subis>): Use NSISIGNOPT.
1262
1401d2fe
MR		 12632016-05-18 Maciej W. Rozycki <macro@imgtec.com>
1264
1265 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
1266 replacing references to `micromips_ase' throughout.
1267 (_print_insn_mips): Don't use file-level microMIPS annotation to
1268 determine the disassembly mode with the symbol table.
1269
1178da44
PB		 12702016-05-13 Peter Bergner <bergner@vnet.ibm.com>
1271
1272 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
1273
8f4f9071
MF		 12742016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
1275
1276 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
1277 mips64r6.
1278 * mips-opc.c (D34): New macro.
1279 (mips_builtin_opcodes): Define bposge32c for DSPr3.
1280
8bc52696
AF		 12812016-05-10 Alexander Fomin <alexander.fomin@intel.com>
1282
1283 * i386-dis.c (prefix_table): Add RDPID instruction.
1284 * i386-gen.c (cpu_flag_init): Add RDPID flag.
1285 (cpu_flags): Add RDPID bitfield.
1286 * i386-opc.h (enum): Add RDPID element.
1287 (i386_cpu_flags): Add RDPID field.
1288 * i386-opc.tbl: Add RDPID instruction.
1289 * i386-init.h: Regenerate.
1290 * i386-tbl.h: Regenerate.
1291
39d911fc
TP		 12922016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1293
1294 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
1295 branch type of a symbol.
1296 (print_insn): Likewise.
1297
16a1fa25
TP		 12982016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1299
1300 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1301 Mainline Security Extensions instructions.
1302 (thumb_opcodes): Add entries for narrow ARMv8-M Security
1303 Extensions instructions.
1304 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1305 instructions.
1306 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1307 special registers.
1308
d751b79e
JM		 13092016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
1310
1311 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1312
945e0f82
CZ		 13132016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
1314
1315 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1316 (arcExtMap_genOpcode): Likewise.
1317 * arc-opc.c (arg_32bit_rc): Define new variable.
1318 (arg_32bit_u6): Likewise.
1319 (arg_32bit_limm): Likewise.
1320
20f55f38
SN		 13212016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
1322
1323 * aarch64-gen.c (VERIFIER): Define.
1324 * aarch64-opc.c (VERIFIER): Define.
1325 (verify_ldpsw): Use static linkage.
1326 * aarch64-opc.h (verify_ldpsw): Remove.
1327 * aarch64-tbl.h: Use VERIFIER for verifiers.
1328
4bd13cde
NC		 13292016-04-28 Nick Clifton <nickc@redhat.com>
1330
1331 PR target/19722
1332 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1333 * aarch64-opc.c (verify_ldpsw): New function.
1334 * aarch64-opc.h (verify_ldpsw): New prototype.
1335 * aarch64-tbl.h: Add initialiser for verifier field.
1336 (LDPSW): Set verifier to verify_ldpsw.
1337
c0f92bf9
L		 13382016-04-23 H.J. Lu <hongjiu.lu@intel.com>
1339
1340 PR binutils/19983
1341 PR binutils/19984
1342 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1343 smaller than address size.
1344
e6c7cdec
TS		 13452016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1346
1347 * alpha-dis.c: Regenerate.
1348 * crx-dis.c: Likewise.
1349 * disassemble.c: Likewise.
1350 * epiphany-opc.c: Likewise.
1351 * fr30-opc.c: Likewise.
1352 * frv-opc.c: Likewise.
1353 * ip2k-opc.c: Likewise.
1354 * iq2000-opc.c: Likewise.
1355 * lm32-opc.c: Likewise.
1356 * lm32-opinst.c: Likewise.
1357 * m32c-opc.c: Likewise.
1358 * m32r-opc.c: Likewise.
1359 * m32r-opinst.c: Likewise.
1360 * mep-opc.c: Likewise.
1361 * mt-opc.c: Likewise.
1362 * or1k-opc.c: Likewise.
1363 * or1k-opinst.c: Likewise.
1364 * tic80-opc.c: Likewise.
1365 * xc16x-opc.c: Likewise.
1366 * xstormy16-opc.c: Likewise.
1367
537aefaf
AB		 13682016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1369
1370 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1371 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1372 calcsd, and calcxd instructions.
1373 * arc-opc.c (insert_nps_bitop_size): Delete.
1374 (extract_nps_bitop_size): Delete.
1375 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1376 (extract_nps_qcmp_m3): Define.
1377 (extract_nps_qcmp_m2): Define.
1378 (extract_nps_qcmp_m1): Define.
1379 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1380 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1381 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1382 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1383 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1384 NPS_QCMP_M3.
1385
c8f785f2
AB		 13862016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1387
1388 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1389
6fd8e7c2
L		 13902016-04-15 H.J. Lu <hongjiu.lu@intel.com>
1391
1392 * Makefile.in: Regenerated with automake 1.11.6.
1393 * aclocal.m4: Likewise.
1394
4b0c052e
AB		 13952016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1396
1397 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1398 instructions.
1399 * arc-opc.c (insert_nps_cmem_uimm16): New function.
1400 (extract_nps_cmem_uimm16): New function.
1401 (arc_operands): Add NPS_XLDST_UIMM16 operand.
1402
cb040366
AB		 14032016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1404
1405 * arc-dis.c (arc_insn_length): New function.
1406 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1407 (find_format): Change insnLen parameter to unsigned.
1408
accc0180
NC		 14092016-04-13 Nick Clifton <nickc@redhat.com>
1410
1411 PR target/19937
1412 * v850-opc.c (v850_opcodes): Correct masks for long versions of
1413 the LD.B and LD.BU instructions.
1414
f36e33da
CZ		 14152016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1416
1417 * arc-dis.c (find_format): Check for extension flags.
1418 (print_flags): New function.
1419 (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1420 .extAuxRegister.
1421 * arc-ext.c (arcExtMap_coreRegName): Use
1422 LAST_EXTENSION_CORE_REGISTER.
1423 (arcExtMap_coreReadWrite): Likewise.
1424 (dump_ARC_extmap): Update printing.
1425 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1426 (arc_aux_regs): Add cpu field.
1427 * arc-regs.h: Add cpu field, lower case name aux registers.
1428
1c2e355e
CZ		 14292016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1430
1431 * arc-tbl.h: Add rtsc, sleep with no arguments.
1432
b99747ae
CZ		 14332016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1434
1435 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1436 Initialize.
1437 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1438 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1439 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1440 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1441 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1442 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1443 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1444 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1445 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1446 (arc_opcode arc_opcodes): Null terminate the array.
1447 (arc_num_opcodes): Remove.
1448 * arc-ext.h (INSERT_XOP): Define.
1449 (extInstruction_t): Likewise.
1450 (arcExtMap_instName): Delete.
1451 (arcExtMap_insn): New function.
1452 (arcExtMap_genOpcode): Likewise.
1453 * arc-ext.c (ExtInstruction): Remove.
1454 (create_map): Zero initialize instruction fields.
1455 (arcExtMap_instName): Remove.
1456 (arcExtMap_insn): New function.
1457 (dump_ARC_extmap): More info while debuging.
1458 (arcExtMap_genOpcode): New function.
1459 * arc-dis.c (find_format): New function.
1460 (print_insn_arc): Use find_format.
1461 (arc_get_disassembler): Enable dump_ARC_extmap only when
1462 debugging.
1463
92708cec
MR		 14642016-04-11 Maciej W. Rozycki <macro@imgtec.com>
1465
1466 * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1467 instruction bits out.
1468
a42a4f84
AB		 14692016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1470
1471 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1472 * arc-opc.c (arc_flag_operands): Add new flags.
1473 (arc_flag_classes): Add new classes.
1474
1328504b
AB		 14752016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1476
1477 * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1478
820f03ff
AB		 14792016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
1480
1481 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1482 encode1, rflt, crc16, and crc32 instructions.
1483 * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1484 (arc_flag_classes): Add C_NPS_R.
1485 (insert_nps_bitop_size_2b): New function.
1486 (extract_nps_bitop_size_2b): Likewise.
1487 (insert_nps_bitop_uimm8): Likewise.
1488 (extract_nps_bitop_uimm8): Likewise.
1489 (arc_operands): Add new operand entries.
1490
8ddf6b2a
CZ		 14912016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
1492
b99747ae
CZ		 1493 * arc-regs.h: Add a new subclass field. Add double assist
1494 accumulator register values.
1495 * arc-tbl.h: Use DPA subclass to mark the double assist
1496 instructions. Use DPX/SPX subclas to mark the FPX instructions.
1497 * arc-opc.c (RSP): Define instead of SP.
1498 (arc_aux_regs): Add the subclass field.
8ddf6b2a 1499
589a7d88
JW		 15002016-04-05 Jiong Wang <jiong.wang@arm.com>
1501
1502 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1503
0a191de9 15042016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
2cce10e7
AB		 1505
1506 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1507 NPS_R_SRC1.
1508
0a106562
AB		 15092016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
1510
1511 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1512 issues. No functional changes.
1513
bd05ac5f
CZ		 15142016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
1515
b99747ae
CZ		 1516 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1517 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1518 (RTT): Remove duplicate.
1519 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1520 (PCT_CONFIG*): Remove.
1521 (D1L, D1H, D2H, D2L): Define.
bd05ac5f 1522
9885948f
CZ		 15232016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1524
b99747ae 1525 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
9885948f 1526
f2dd8838
CZ		 15272016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1528
b99747ae
CZ		 1529 * arc-tbl.h (invld07): Remove.
1530 * arc-ext-tbl.h: New file.
1531 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1532 * arc-opc.c (arc_opcodes): Add ext-tbl include.
f2dd8838 1533
0d2f91fe
JK		 15342016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
1535
1536 Fix -Wstack-usage warnings.
1537 * aarch64-dis.c (print_operands): Substitute size.
1538 * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1539
a6b71f42
JM		 15402016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
1541
1542 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1543 to get a proper diagnostic when an invalid ASR register is used.
1544
9780e045
NC		 15452016-03-22 Nick Clifton <nickc@redhat.com>
1546
1547 * configure: Regenerate.
1548
e23e8ebe
AB		 15492016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1550
1551 * arc-nps400-tbl.h: New file.
1552 * arc-opc.c: Add top level comment.
1553 (insert_nps_3bit_dst): New function.
1554 (extract_nps_3bit_dst): New function.
1555 (insert_nps_3bit_src2): New function.
1556 (extract_nps_3bit_src2): New function.
1557 (insert_nps_bitop_size): New function.
1558 (extract_nps_bitop_size): New function.
1559 (arc_flag_operands): Add nps400 entries.
1560 (arc_flag_classes): Add nps400 entries.
1561 (arc_operands): Add nps400 entries.
1562 (arc_opcodes): Add nps400 include.
1563
1ae8ab47
AB		 15642016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1565
1566 * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1567 the new class enum values.
1568
8699fc3e
AB		 15692016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1570
1571 * arc-dis.c (print_insn_arc): Handle nps400.
1572
24740d83
AB		 15732016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1574
1575 * arc-opc.c (BASE): Delete.
1576
8678914f
NC		 15772016-03-18 Nick Clifton <nickc@redhat.com>
1578
1579 PR target/19721
1580 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1581 of MOV insn that aliases an ORR insn.
1582
cc933301
JW		 15832016-03-16 Jiong Wang <jiong.wang@arm.com>
1584
1585 * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1586
f86f5863
TS		 15872016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1588
1589 * mcore-opc.h: Add const qualifiers.
1590 * microblaze-opc.h (struct op_code_struct): Likewise.
1591 * sh-opc.h: Likewise.
1592 * tic4x-dis.c (tic4x_print_indirect): Likewise.
1593 (tic4x_print_op): Likewise.
1594
62de1c63
AM		 15952016-03-02 Alan Modra <amodra@gmail.com>
1596
d11698cd 1597 * or1k-desc.h: Regenerate.
62de1c63 1598 * fr30-ibld.c: Regenerate.
c697cf0b 1599 * rl78-decode.c: Regenerate.
62de1c63 1600
020efce5
NC		 16012016-03-01 Nick Clifton <nickc@redhat.com>
1602
1603 PR target/19747
1604 * rl78-dis.c (print_insn_rl78_common): Fix typo.
1605
b0c11777
RL		 16062016-02-24 Renlin Li <renlin.li@arm.com>
1607
1608 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1609 (print_insn_coprocessor): Support fp16 instructions.
1610
3e309328
RL		 16112016-02-24 Renlin Li <renlin.li@arm.com>
1612
1613 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1614 vminnm, vrint(mpna).
1615
8afc7bea
RL		 16162016-02-24 Renlin Li <renlin.li@arm.com>
1617
1618 * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1619 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1620
4fd7268a
L		 16212016-02-15 H.J. Lu <hongjiu.lu@intel.com>
1622
1623 * i386-dis.c (print_insn): Parenthesize expression to prevent
1624 truncated addresses.
1625 (OP_J): Likewise.
1626
4670103e
CZ		 16272016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
1628 Janek van Oirschot <jvanoirs@synopsys.com>
1629
b99747ae
CZ		 1630 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1631 variable.
4670103e 1632
c1d9289f
NC		 16332016-02-04 Nick Clifton <nickc@redhat.com>
1634
1635 PR target/19561
1636 * msp430-dis.c (print_insn_msp430): Add a special case for
1637 decoding an RRC instruction with the ZC bit set in the extension
1638 word.
1639
a143b004
AB		 16402016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1641
1642 * cgen-ibld.in (insert_normal): Rework calculation of shift.
1643 * epiphany-ibld.c: Regenerate.
1644 * fr30-ibld.c: Regenerate.
1645 * frv-ibld.c: Regenerate.
1646 * ip2k-ibld.c: Regenerate.
1647 * iq2000-ibld.c: Regenerate.
1648 * lm32-ibld.c: Regenerate.
1649 * m32c-ibld.c: Regenerate.
1650 * m32r-ibld.c: Regenerate.
1651 * mep-ibld.c: Regenerate.
1652 * mt-ibld.c: Regenerate.
1653 * or1k-ibld.c: Regenerate.
1654 * xc16x-ibld.c: Regenerate.
1655 * xstormy16-ibld.c: Regenerate.
1656
b89807c6
AB		 16572016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1658
1659 * epiphany-dis.c: Regenerated from latest cpu files.
1660
d8c823c8
MM		 16612016-02-01 Michael McConville <mmcco@mykolab.com>
1662
1663 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1664 test bit.
1665
5bc5ae88
RL		 16662016-01-25 Renlin Li <renlin.li@arm.com>
1667
1668 * arm-dis.c (mapping_symbol_for_insn): New function.
1669 (find_ifthen_state): Call mapping_symbol_for_insn().
1670
0bff6e2d
MW		 16712016-01-20 Matthew Wahab <matthew.wahab@arm.com>
1672
1673 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1674 of MSR UAO immediate operand.
1675
100b4f2e
MR		 16762016-01-18 Maciej W. Rozycki <macro@imgtec.com>
1677
1678 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1679 instruction support.
1680
5c14705f
AM		 16812016-01-17 Alan Modra <amodra@gmail.com>
1682
1683 * configure: Regenerate.
1684
4d82fe66
NC		 16852016-01-14 Nick Clifton <nickc@redhat.com>
1686
1687 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1688 instructions that can support stack pointer operations.
1689 * rl78-decode.c: Regenerate.
1690 * rl78-dis.c: Fix display of stack pointer in MOVW based
1691 instructions.
1692
651657fa
MW		 16932016-01-14 Matthew Wahab <matthew.wahab@arm.com>
1694
1695 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1696 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
1697 erxtatus_el1 and erxaddr_el1.
1698
105bde57
MW		 16992016-01-12 Matthew Wahab <matthew.wahab@arm.com>
1700
1701 * arm-dis.c (arm_opcodes): Add "esb".
1702 (thumb_opcodes): Likewise.
1703
afa8d405
PB		 17042016-01-11 Peter Bergner <bergner@vnet.ibm.com>
1705
1706 * ppc-opc.c <xscmpnedp>: Delete.
1707 <xvcmpnedp>: Likewise.
1708 <xvcmpnedp.>: Likewise.
1709 <xvcmpnesp>: Likewise.
1710 <xvcmpnesp.>: Likewise.
1711
83c3256e
AS		 17122016-01-08 Andreas Schwab <schwab@linux-m68k.org>
1713
1714 PR gas/13050
1715 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1716 addition to ISA_A.
1717
6f2750fe
AM		 17182016-01-01 Alan Modra <amodra@gmail.com>
1719
1720 Update year range in copyright notice of all files.
1721
3499769a
AM		 1722For older changes see ChangeLog-2015
1723\f
1724Copyright (C) 2016 Free Software Foundation, Inc.
1725
1726Copying and distribution of this file, with or without modification,
1727are permitted in any medium without royalty provided the copyright
1728notice and this notice are preserved.
1729
1730Local Variables:
1731mode: change-log
1732left-margin: 8
1733fill-column: 74
1734version-control: never
1735End:
GDB Binutils - Deliverables
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