[deliverable/binutils-gdb.git] / opcodes / ChangeLog

2008-04-03  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (OP_E_register): New.
	(OP_E_memory): Likewise.
	(OP_VEX): Likewise.
	(OP_EX_Vex): Likewise.
	(OP_EX_VexW): Likewise.
	(OP_XMM_Vex): Likewise.
	(OP_XMM_VexW): Likewise.
	(OP_REG_VexI4): Likewise.
	(PCLMUL_Fixup): Likewise.
	(VEXI4_Fixup): Likewise.
	(VZERO_Fixup): Likewise.
	(VCMP_Fixup): Likewise.
	(VPERMIL2_Fixup): Likewise.
	(rex_original): Likewise.
	(rex_ignored): Likewise.
	(Mxmm): Likewise.
	(XMM): Likewise.
	(EXxmm): Likewise.
	(EXxmmq): Likewise.
	(EXymmq): Likewise.
	(Vex): Likewise.
	(Vex128): Likewise.
	(Vex256): Likewise.
	(VexI4): Likewise.
	(EXdVex): Likewise.
	(EXqVex): Likewise.
	(EXVexW): Likewise.
	(EXdVexW): Likewise.
	(EXqVexW): Likewise.
	(XMVex): Likewise.
	(XMVexW): Likewise.
	(XMVexI4): Likewise.
	(PCLMUL): Likewise.
	(VZERO): Likewise.
	(VCMP): Likewise.
	(VPERMIL2): Likewise.
	(xmm_mode): Likewise.
	(xmmq_mode): Likewise.
	(ymmq_mode): Likewise.
	(vex_mode): Likewise.
	(vex128_mode): Likewise.
	(vex256_mode): Likewise.
	(USE_VEX_C4_TABLE): Likewise.
	(USE_VEX_C5_TABLE): Likewise.
	(USE_VEX_LEN_TABLE): Likewise.
	(VEX_C4_TABLE): Likewise.
	(VEX_C5_TABLE): Likewise.
	(VEX_LEN_TABLE): Likewise.
	(REG_VEX_XX): Likewise.
	(MOD_VEX_XXX): Likewise.
	(PREFIX_0F38DB..PREFIX_0F38DF): Likewise.
	(PREFIX_0F3A44): Likewise.
	(PREFIX_0F3ADF): Likewise.
	(PREFIX_VEX_XXX): Likewise.
	(VEX_OF): Likewise.
	(VEX_OF38): Likewise.
	(VEX_OF3A): Likewise.
	(VEX_LEN_XXX): Likewise.
	(vex): Likewise.
	(need_vex): Likewise.
	(need_vex_reg): Likewise.
	(vex_i4_done): Likewise.
	(vex_table): Likewise.
	(vex_len_table): Likewise.
	(OP_REG_VexI4): Likewise.
	(vex_cmp_op): Likewise.
	(pclmul_op): Likewise.
	(vpermil2_op): Likewise.
	(m_mode): Updated.
	(es_reg): Likewise.
	(PREFIX_0F38F0): Likewise.
	(PREFIX_0F3A60): Likewise.
	(reg_table): Add REG_VEX_71...REG_VEX_73 and REG_VEX_AE.
	(prefix_table): Add PREFIX_0F38DB..PREFIX_0F38DF, PREFIX_0F3ADF
	and PREFIX_VEX_XXX entries.
	(x86_64_table): Use VEX_C4_TABLE and VEX_C5_TABLE.
	(three_byte_table): Use PREFIX_0F38DB..PREFIX_0F38DF and
	PREFIX_0F3ADF.
	(mod_table): Use VEX_C4_TABLE, VEX_C5_TABLE and VEX_LEN_TABLE.
	Add MOD_VEX_XXX entries.
	(ckprefix): Initialize rex_original and rex_ignored.  Store the
	REX byte in rex_original.
	(get_valid_dis386): Handle the implicit prefix in VEX prefix
	bytes and USE_VEX_LEN_TABLE/USE_VEX_C4_TABLE/USE_VEX_C5_TABLE.
	(print_insn): Set need_vex/need_vex_reg/vex_i4_done to 0 before
	calling get_valid_dis386.  Use rex_original and rex_ignored when
	printing out REX.
	(putop): Handle "XY".
	(intel_operand_size): Handle VEX, xmm_mode, xmmq_mode and
	ymmq_mode.
	(OP_E_extended): Updated to use OP_E_register and
	OP_E_memory.
	(OP_XMM): Handle VEX.
	(OP_EX): Likewise.
	(XMM_Fixup): Likewise.
	(CMP_Fixup): Use ARRAY_SIZE.

	* i386-gen.c (cpu_flag_init): Add CpuAES, CPU_CLMUL_FLAGS,
	CPU_FMA_FLAGS and CPU_AVX_FLAGS.
	(operand_type_init): Add OPERAND_TYPE_REGYMM and
	OPERAND_TYPE_VEX_IMM4.
	(cpu_flags): Add CpuAVX, CpuAES, CpuCLMUL and CpuFMA.
	(opcode_modifiers): Add Implicit1stXmm0, Vex, Vex256, VexNDD,
	VexNDS, VexW0, VexW1, Vex0F, Vex0F38, Vex0F3A, Vex3Sources,
	VexImmExt and SSE2AVX.
	(operand_types): Add RegYMM, Ymmword and Vex_Imm4.

	* i386-opc.h (CpuAVX): New.
	(CpuAES): Likewise.
	(CpuCLMUL): Likewise.
	(CpuFMA): Likewise.
	(Vex): Likewise.
	(Vex256): Likewise.
	(VexNDS): Likewise.
	(VexNDD): Likewise.
	(VexW0): Likewise.
	(VexW1): Likewise.
	(Vex0F): Likewise.
	(Vex0F38): Likewise.
	(Vex0F3A): Likewise.
	(Vex3Sources): Likewise.
	(VexImmExt): Likewise.
	(SSE2AVX): Likewise.
	(RegYMM): Likewise.
	(Ymmword): Likewise.
	(Vex_Imm4): Likewise.
	(Implicit1stXmm0): Likewise.
	(CpuXsave): Updated.
	(CpuLM): Likewise.
	(ByteOkIntel): Likewise.
	(OldGcc): Likewise.
	(Control): Likewise.
	(Unspecified): Likewise.
	(OTMax): Likewise.
	(i386_cpu_flags): Add cpuavx, cpuaes, cpuclmul and cpufma.
	(i386_opcode_modifier): Add implicit1stxmm0, vex, vex256,
	vexnds, vexndd, vexw0, vexw1, vex0f, vex0f38, vex0f3a,
	vex3sources, veximmext and sse2avx.
	(i386_operand_type): Add regymm, ymmword and vex_imm4.

	* i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions.

	* i386-reg.tbl: Add AVX registers, ymm0..ymm15.

	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2008-03-26  Bernd Schmidt  <bernd.schmidt@analog.com>

	From  Robin Getz  <robin.getz@analog.com>
	* bfin-dis.c (bu32): Typedef.
	(enum const_forms_t): Add c_uimm32 and c_huimm32.
	(constant_formats[]): Add uimm32 and huimm16.
	(fmtconst_val): New.
	(uimm32): Define.
	(huimm32): Define.
	(imm16_val): Define.
	(luimm16_val): Define.
	(struct saved_state): Define.
	(GREG, DPREG, DREG, PREG, SPREG, FPREG, IREG, MREG, BREG, LREG,
	A0XREG, A0WREG, A1XREG, A1WREG,CCREG, LC0REG, LT0REG, LB0REG,
	LC1REG, LT1REG, LB1REG, RETSREG, PCREG): Define.
	(get_allreg): New.
	(decode_LDIMMhalf_0): Print out the whole register value.

	From Jie Zhang  <jie.zhang@analog.com>
	* bfin-dis.c (decode_dsp32mac_0): Decode (IU) option for
	multiply and multiply-accumulate to data register instruction.

	* bfin-dis.c: (c_uimm4s4d, c_imm5d, c_imm7d, c_imm16d, c_uimm16s4d,
	c_imm32, c_huimm32e): Define.
	(constant_formats): Add flags for printing decimal, leading spaces, and
	exact symbols.
	(comment, parallel): Add global flags in all disassembly.
	(fmtconst): Take advantage of new flags, and print default in hex.
	(fmtconst_val): Likewise.
	(decode_macfunc): Be consistant with spaces, tabs, comments,
	capitalization in disassembly, fix minor coding style issues.
	(reg_names, amod0, amod1, amod0amod2, aligndir, get_allreg): Likewise.
	(decode_ProgCtrl_0, decode_PushPopMultiple_0, decode_CCflag_0,
	decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0,
	decode_REGMV_0, decode_ALU2op_0, decode_PTR2op_0, decode_LOGI2op_0,
	decode_COMP3op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
	decode_LDSTpmod_0, decode_dagMODim_0, decode_dagMODik_0,
	decode_dspLDST_0, decode_LDST_0, decode_LDSTiiFP_0, decode_LDSTii_0,
	decode_LoopSetup_0, decode_LDIMMhalf_0, decode_CALLa_0,
	decode_LDSTidxI_0, decode_linkage_0, decode_dsp32alu_0,
	decode_dsp32shift_0, decode_dsp32shiftimm_0, decode_pseudodbg_assert_0,
	_print_insn_bfin, print_insn_bfin): Likewise.

2008-03-17  Ralf Wildenhues  <Ralf.Wildenhues@gmx.de>

	* aclocal.m4: Regenerate.
	* configure: Likewise.
	* Makefile.in: Likewise.

2008-03-13  Alan Modra  <amodra@bigpond.net.au>

	* Makefile.am: Run "make dep-am".
	* Makefile.in: Regenerate.
	* configure: Regenerate.

2008-03-07  Alan Modra  <amodra@bigpond.net.au>

	* ppc-opc.c (powerpc_opcodes): Order and format.

2008-03-01  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.tbl: Allow 16-bit near indirect branches for x86-64.
	* i386-tbl.h: Regenerated.

2008-02-23  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.tbl: Disallow 16-bit near indirect branches for
	x86-64.
	* i386-tbl.h: Regenerated.

2008-02-21  Jan Beulich  <jbeulich@novell.com>

	* i386-opc.tbl: Allow Dword for far indirect call. Allow Dword
	and Fword for far indirect jmp. Allow Reg16 and Word for near
	indirect jmp on x86-64. Disallow Fword for lcall.
	* i386-tbl.h: Re-generate.

2008-02-18  M R Swami Reddy <MR.Swami.Reddy@nsc.com>

	* cr16-opc.c  (cr16_num_optab): Defined

2008-02-16  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c  (operand_type_init): Add OPERAND_TYPE_INOUTPORTREG.
	* i386-init.h: Regenerated.

2008-02-14  Nick Clifton  <nickc@redhat.com>

	PR binutils/5524
	* configure.in (SHARED_LIBADD): Select the correct host specific
	file extension for shared libraries.
	* configure: Regenerate.

2008-02-13  Jan Beulich  <jbeulich@novell.com>

	* i386-opc.h (RegFlat): New.
	* i386-reg.tbl (flat): Add.
	* i386-tbl.h: Re-generate.

2008-02-13  Jan Beulich  <jbeulich@novell.com>

	* i386-dis.c (a_mode): New.
	(cond_jump_mode): Adjust.
	(Ma): Change to a_mode.
	(intel_operand_size): Handle a_mode.
	* i386-opc.tbl: Allow Dword and Qword for bound.
	* i386-tbl.h: Re-generate.

2008-02-13  Jan Beulich  <jbeulich@novell.com>

	* i386-gen.c (process_i386_registers): Process new fields.
	* i386-opc.h (reg_entry): Shrink reg_flags and reg_num to
	unsigned char. Add dw2_regnum and Dw2Inval.
	* i386-reg.tbl: Provide initializers for dw2_regnum. Add pseudo
	register names.
	* i386-tbl.h: Re-generate.

2008-02-11  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (cpu_flag_init): Add CPU_XSAVE_FLAGS.
	* i386-init.h: Updated.

2008-02-11  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (cpu_flags): Add CpuXsave.

	* i386-opc.h (CpuXsave): New.
	(CpuLM): Updated.
	(i386_cpu_flags): Add cpuxsave.

	* i386-dis.c (MOD_0FAE_REG_4): New.
	(RM_0F01_REG_2): Likewise.
	(MOD_0FAE_REG_5): Updated.
	(RM_0F01_REG_3): Likewise.
	(reg_table): Use MOD_0FAE_REG_4.
	(mod_table): Use RM_0F01_REG_2.  Add MOD_0FAE_REG_4.  Updated
	for xrstor.
	(rm_table): Add RM_0F01_REG_2.

	* i386-opc.tbl: Add xsave, xrstor, xgetbv and xsetbv.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2008-02-11  Jan Beulich  <jbeulich@novell.com>

	* i386-opc.tbl: Remove Disp32S from CpuNo64 opcodes. Remove
	Disp16 from Cpu64 non-jump opcodes (including loop and j?cxz).
	* i386-tbl.h: Re-generate.

2008-02-04  H.J. Lu  <hongjiu.lu@intel.com>

	PR 5715
	* configure: Regenerated.

2008-02-04  Adam Nemet  <anemet@caviumnetworks.com>

	* mips-dis.c: Update copyright.
	(mips_arch_choices): Add Octeon.
	* mips-opc.c: Update copyright.
	(IOCT): New macro.
	(mips_builtin_opcodes): Add Octeon instruction synciobdma.

2008-01-29  Alan Modra  <amodra@bigpond.net.au>

	* ppc-opc.c: Support optional L form mtmsr.

2008-01-24  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (OP_E_extended): Handle r12 like rsp.

2008-01-23  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (cpu_flag_init): Add CpuLM to CPU_GENERIC64_FLAGS.
	* i386-init.h: Regenerated.

2008-01-23  Tristan Gingold  <gingold@adacore.com>

	* ia64-dis.c (print_insn_ia64): Display symbolic name of ar.fcr,
	ar.eflag, ar.csd, ar.ssd, ar.cflg, ar.fsr, ar.fir and ar.fdr.

2008-01-22  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (cpu_flag_init): Remove CpuMMX2.
	(cpu_flags): Likewise.

	* i386-opc.h (CpuMMX2): Removed.
	(CpuSSE): Updated.

	* i386-opc.tbl: Replace CpuMMX2 with CpuSSE|Cpu3dnowA.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2008-01-22  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (cpu_flag_init): Add CPU_VMX_FLAGS and
	CPU_SMX_FLAGS.
	* i386-init.h: Regenerated.

2008-01-15  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.tbl: Use Qword on movddup.
	* i386-tbl.h: Regenerated.

2008-01-15  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.tbl: Put back 16bit movsx/movzx for AT&T syntax.
	* i386-tbl.h: Regenerated.

2008-01-15  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (Mx): New.
	(PREFIX_0FC3): Likewise.
	(PREFIX_0FC7_REG_6): Updated.
	(dis386_twobyte): Use PREFIX_0FC3.
	(prefix_table): Add PREFIX_0FC3.  Use Mq on movntq and movntsd.
	Use Mx on movntps, movntpd, movntdq and movntdqa.  Use Md on
	movntss.

2008-01-14  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (opcode_modifiers): Add IntelSyntax.
	(operand_types): Add Mem.

	* i386-opc.h (IntelSyntax): New.
	* i386-opc.h (Mem): New.
	(Byte): Updated.
	(Opcode_Modifier_Max): Updated.
	(i386_opcode_modifier): Add intelsyntax.
	(i386_operand_type): Add mem.

	* i386-opc.tbl: Remove Reg16 from movnti.  Add sizes to more
	instructions.

	* i386-reg.tbl: Add size for accumulator.

	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2008-01-13  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.h (Byte): Fix a typo.

2008-01-12  H.J. Lu  <hongjiu.lu@intel.com>

	PR gas/5534
	* i386-gen.c (operand_type_init): Add Dword to
	OPERAND_TYPE_ACC32.  Add Qword to OPERAND_TYPE_ACC64.
	(opcode_modifiers): Remove CheckSize, Byte, Word, Dword,
	Qword and Xmmword.
	(operand_types): Add Byte, Word, Dword, Fword, Qword, Tbyte,
	Xmmword, Unspecified and Anysize.
	(set_bitfield): Make Mmword an alias of Qword.  Make Oword
	an alias of Xmmword.

	* i386-opc.h (CheckSize): Removed.
	(Byte): Updated.
	(Word): Likewise.
	(Dword): Likewise.
	(Qword): Likewise.
	(Xmmword): Likewise.
	(FWait): Updated.
	(OTMax): Likewise.
	(i386_opcode_modifier): Remove checksize, byte, word, dword,
	qword and xmmword.
	(Fword): New.
	(TBYTE): Likewise.
	(Unspecified): Likewise.
	(Anysize): Likewise.
	(i386_operand_type): Add byte, word, dword, fword, qword,
	tbyte xmmword, unspecified and anysize.

	* i386-opc.tbl: Updated to use Byte, Word, Dword, Fword, Qword,
	Tbyte, Xmmword, Unspecified and Anysize.

	* i386-reg.tbl: Add size for accumulator.

	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2008-01-10  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (REG_0F0E): Renamed to REG_0F0D.
	(REG_0F18): Updated.
	(reg_table): Updated.
	(dis386_twobyte): Updated.  Use "nopQ" on 0x19 to 0x1e.
	(twobyte_has_modrm): Set 1 for 0x19 to 0x1e.

2008-01-08  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (set_bitfield): Use fail () on error.

2008-01-08  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (lineno): New.
	(filename): Likewise.
	(set_bitfield): Report filename and line numer on error.
	(process_i386_opcodes): Set filename and update lineno.
	(process_i386_registers): Likewise.

2008-01-05  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (opcode_modifiers): Rename IntelMnemonic to
	ATTSyntax.

	* i386-opc.h (IntelMnemonic): Renamed to ..
	(ATTSyntax): This
	(Opcode_Modifier_Max): Updated.
	(i386_opcode_modifier): Remove intelmnemonic. Add attsyntax
	and intelsyntax.

	* i386-opc.tbl: Remove IntelMnemonic and update with ATTSyntax 
	on fsub, fubp, fsubr, fsubrp, div, fdivp, fdivr and fdivrp.
	* i386-tbl.h: Regenerated.

2008-01-04  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c: Update copyright to 2008.
	* i386-opc.h: Likewise.
	* i386-opc.tbl: Likewise.

	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2008-01-04  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.tbl: Add NoRex64 to extractps, movmskpd, movmskps,
	pextrb, pextrw, pinsrb, pinsrw and pmovmskb.
	* i386-tbl.h: Regenerated.

2008-01-03  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (cpu_flag_init): Remove CpuSSE4_1_Or_5 and
	CpuSSE4_2_Or_ABM.
	(cpu_flags): Likewise.

	* i386-opc.h (CpuSSE4_1_Or_5): Removed.
	(CpuSSE4_2_Or_ABM): Likewise.
	(CpuLM): Updated.
	(i386_cpu_flags): Remove cpusse4_1_or_5 and cpusse4_2_or_abm.

	* i386-opc.tbl: Replace CpuSSE4_1_Or_5, CpuSSE4_2_Or_ABM and
	Cpu686|CpuPadLock with CpuSSE4_1|CpuSSE5, CpuABM|CpuSSE4_2
	and CpuPadLock, respectively.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2008-01-03  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (opcode_modifiers): Remove No_xSuf.

	* i386-opc.h (No_xSuf): Removed.
	(CheckSize): Updated.

	* i386-tbl.h: Regenerated.

2008-01-02  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (cpu_flag_init): Add CpuSSE4_2_Or_ABM to
	CPU_AMDFAM10_FLAGS, CPU_SSE4_2_FLAGS, CpuABM and
	CPU_SSE5_FLAGS.
	(cpu_flags): Add CpuSSE4_2_Or_ABM.

	* i386-opc.h (CpuSSE4_2_Or_ABM): New.
	(CpuLM): Updated.
	(i386_cpu_flags): Add cpusse4_2_or_abm.

	* i386-opc.tbl: Use CpuSSE4_2_Or_ABM instead of
	CpuABM|CpuSSE4_2 on popcnt.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2008-01-02  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.h: Update comments.

2008-01-02  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (opcode_modifiers): Use Qword instead of QWord.
	* i386-opc.h: Likewise.
	* i386-opc.tbl: Likewise.

2008-01-02  H.J. Lu  <hongjiu.lu@intel.com>

	PR gas/5534
	* i386-gen.c (opcode_modifiers): Add No_xSuf, CheckSize,
	Byte, Word, Dword, QWord and Xmmword.

	* i386-opc.h (No_xSuf): New.
	(CheckSize): Likewise.
	(Byte): Likewise.
	(Word): Likewise.
	(Dword): Likewise.
	(QWord): Likewise.
	(Xmmword): Likewise.
	(FWait): Updated.
	(i386_opcode_modifier): Add No_xSuf, CheckSize, Byte, Word,
	Dword, QWord and Xmmword.

	* i386-opc.tbl: Add CheckSize|QWord to movq if IgnoreSize is
	used.
	* i386-tbl.h: Regenerated.

2008-01-02  Mark Kettenis  <kettenis@gnu.org>

	* m88k-dis.c (instructions): Fix fcvt.* instructions.
	From Miod Vallat.

For older changes see ChangeLog-2007
\f
Local Variables:
mode: change-log
left-margin: 8
fill-column: 74
version-control: never
End:
Commit	Line	Data
c0f3af97 L	1	2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
	2
	3	* i386-dis.c (OP_E_register): New.
	4	(OP_E_memory): Likewise.
	5	(OP_VEX): Likewise.
	6	(OP_EX_Vex): Likewise.
	7	(OP_EX_VexW): Likewise.
	8	(OP_XMM_Vex): Likewise.
	9	(OP_XMM_VexW): Likewise.
	10	(OP_REG_VexI4): Likewise.
	11	(PCLMUL_Fixup): Likewise.
	12	(VEXI4_Fixup): Likewise.
	13	(VZERO_Fixup): Likewise.
	14	(VCMP_Fixup): Likewise.
	15	(VPERMIL2_Fixup): Likewise.
	16	(rex_original): Likewise.
	17	(rex_ignored): Likewise.
	18	(Mxmm): Likewise.
	19	(XMM): Likewise.
	20	(EXxmm): Likewise.
	21	(EXxmmq): Likewise.
	22	(EXymmq): Likewise.
	23	(Vex): Likewise.
	24	(Vex128): Likewise.
	25	(Vex256): Likewise.
	26	(VexI4): Likewise.
	27	(EXdVex): Likewise.
	28	(EXqVex): Likewise.
	29	(EXVexW): Likewise.
	30	(EXdVexW): Likewise.
	31	(EXqVexW): Likewise.
	32	(XMVex): Likewise.
	33	(XMVexW): Likewise.
	34	(XMVexI4): Likewise.
	35	(PCLMUL): Likewise.
	36	(VZERO): Likewise.
	37	(VCMP): Likewise.
	38	(VPERMIL2): Likewise.
	39	(xmm_mode): Likewise.
	40	(xmmq_mode): Likewise.
	41	(ymmq_mode): Likewise.
	42	(vex_mode): Likewise.
	43	(vex128_mode): Likewise.
	44	(vex256_mode): Likewise.
	45	(USE_VEX_C4_TABLE): Likewise.
	46	(USE_VEX_C5_TABLE): Likewise.
	47	(USE_VEX_LEN_TABLE): Likewise.
	48	(VEX_C4_TABLE): Likewise.
	49	(VEX_C5_TABLE): Likewise.
	50	(VEX_LEN_TABLE): Likewise.
	51	(REG_VEX_XX): Likewise.
	52	(MOD_VEX_XXX): Likewise.
	53	(PREFIX_0F38DB..PREFIX_0F38DF): Likewise.
	54	(PREFIX_0F3A44): Likewise.
	55	(PREFIX_0F3ADF): Likewise.
	56	(PREFIX_VEX_XXX): Likewise.
	57	(VEX_OF): Likewise.
	58	(VEX_OF38): Likewise.
	59	(VEX_OF3A): Likewise.
	60	(VEX_LEN_XXX): Likewise.
	61	(vex): Likewise.
	62	(need_vex): Likewise.
	63	(need_vex_reg): Likewise.
	64	(vex_i4_done): Likewise.
65	(vex_table): Likewise.
66	(vex_len_table): Likewise.
67	(OP_REG_VexI4): Likewise.
68	(vex_cmp_op): Likewise.
69	(pclmul_op): Likewise.
70	(vpermil2_op): Likewise.
71	(m_mode): Updated.
72	(es_reg): Likewise.
73	(PREFIX_0F38F0): Likewise.
74	(PREFIX_0F3A60): Likewise.
75	(reg_table): Add REG_VEX_71...REG_VEX_73 and REG_VEX_AE.
76	(prefix_table): Add PREFIX_0F38DB..PREFIX_0F38DF, PREFIX_0F3ADF
77	and PREFIX_VEX_XXX entries.
78	(x86_64_table): Use VEX_C4_TABLE and VEX_C5_TABLE.
79	(three_byte_table): Use PREFIX_0F38DB..PREFIX_0F38DF and
80	PREFIX_0F3ADF.
81	(mod_table): Use VEX_C4_TABLE, VEX_C5_TABLE and VEX_LEN_TABLE.
82	Add MOD_VEX_XXX entries.
83	(ckprefix): Initialize rex_original and rex_ignored. Store the
84	REX byte in rex_original.
85	(get_valid_dis386): Handle the implicit prefix in VEX prefix
86	bytes and USE_VEX_LEN_TABLE/USE_VEX_C4_TABLE/USE_VEX_C5_TABLE.
87	(print_insn): Set need_vex/need_vex_reg/vex_i4_done to 0 before
88	calling get_valid_dis386. Use rex_original and rex_ignored when
89	printing out REX.
90	(putop): Handle "XY".
91	(intel_operand_size): Handle VEX, xmm_mode, xmmq_mode and
92	ymmq_mode.
93	(OP_E_extended): Updated to use OP_E_register and
94	OP_E_memory.
95	(OP_XMM): Handle VEX.
96	(OP_EX): Likewise.
97	(XMM_Fixup): Likewise.
98	(CMP_Fixup): Use ARRAY_SIZE.
99
100	* i386-gen.c (cpu_flag_init): Add CpuAES, CPU_CLMUL_FLAGS,
101	CPU_FMA_FLAGS and CPU_AVX_FLAGS.
102	(operand_type_init): Add OPERAND_TYPE_REGYMM and
103	OPERAND_TYPE_VEX_IMM4.
104	(cpu_flags): Add CpuAVX, CpuAES, CpuCLMUL and CpuFMA.
105	(opcode_modifiers): Add Implicit1stXmm0, Vex, Vex256, VexNDD,
106	VexNDS, VexW0, VexW1, Vex0F, Vex0F38, Vex0F3A, Vex3Sources,
107	VexImmExt and SSE2AVX.
108	(operand_types): Add RegYMM, Ymmword and Vex_Imm4.
109
110	* i386-opc.h (CpuAVX): New.
111	(CpuAES): Likewise.
112	(CpuCLMUL): Likewise.
113	(CpuFMA): Likewise.
114	(Vex): Likewise.
115	(Vex256): Likewise.
116	(VexNDS): Likewise.
117	(VexNDD): Likewise.
118	(VexW0): Likewise.
119	(VexW1): Likewise.
120	(Vex0F): Likewise.
121	(Vex0F38): Likewise.
122	(Vex0F3A): Likewise.
123	(Vex3Sources): Likewise.
124	(VexImmExt): Likewise.
125	(SSE2AVX): Likewise.
126	(RegYMM): Likewise.
127	(Ymmword): Likewise.
128	(Vex_Imm4): Likewise.
129	(Implicit1stXmm0): Likewise.
130	(CpuXsave): Updated.
131	(CpuLM): Likewise.
132	(ByteOkIntel): Likewise.
133	(OldGcc): Likewise.
134	(Control): Likewise.
135	(Unspecified): Likewise.
136	(OTMax): Likewise.
137	(i386_cpu_flags): Add cpuavx, cpuaes, cpuclmul and cpufma.
138	(i386_opcode_modifier): Add implicit1stxmm0, vex, vex256,
139	vexnds, vexndd, vexw0, vexw1, vex0f, vex0f38, vex0f3a,
140	vex3sources, veximmext and sse2avx.
141	(i386_operand_type): Add regymm, ymmword and vex_imm4.
142
143	* i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions.
144
145	* i386-reg.tbl: Add AVX registers, ymm0..ymm15.
146
147	* i386-init.h: Regenerated.
148	* i386-tbl.h: Likewise.
149
b21c9cb4 BS	150	2008-03-26 Bernd Schmidt <bernd.schmidt@analog.com>
	151
	152	From Robin Getz <robin.getz@analog.com>
	153	* bfin-dis.c (bu32): Typedef.
	154	(enum const_forms_t): Add c_uimm32 and c_huimm32.
	155	(constant_formats[]): Add uimm32 and huimm16.
	156	(fmtconst_val): New.
	157	(uimm32): Define.
	158	(huimm32): Define.
	159	(imm16_val): Define.
	160	(luimm16_val): Define.
	161	(struct saved_state): Define.
	162	(GREG, DPREG, DREG, PREG, SPREG, FPREG, IREG, MREG, BREG, LREG,
	163	A0XREG, A0WREG, A1XREG, A1WREG,CCREG, LC0REG, LT0REG, LB0REG,
	164	LC1REG, LT1REG, LB1REG, RETSREG, PCREG): Define.
	165	(get_allreg): New.
	166	(decode_LDIMMhalf_0): Print out the whole register value.
	167
ee171c8f BS	168	From Jie Zhang <jie.zhang@analog.com>
	169	* bfin-dis.c (decode_dsp32mac_0): Decode (IU) option for
	170	multiply and multiply-accumulate to data register instruction.
	171
086134ec BS	172	* bfin-dis.c: (c_uimm4s4d, c_imm5d, c_imm7d, c_imm16d, c_uimm16s4d,
	173	c_imm32, c_huimm32e): Define.
	174	(constant_formats): Add flags for printing decimal, leading spaces, and
	175	exact symbols.
	176	(comment, parallel): Add global flags in all disassembly.
	177	(fmtconst): Take advantage of new flags, and print default in hex.
	178	(fmtconst_val): Likewise.
	179	(decode_macfunc): Be consistant with spaces, tabs, comments,
	180	capitalization in disassembly, fix minor coding style issues.
	181	(reg_names, amod0, amod1, amod0amod2, aligndir, get_allreg): Likewise.
	182	(decode_ProgCtrl_0, decode_PushPopMultiple_0, decode_CCflag_0,
	183	decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0,
	184	decode_REGMV_0, decode_ALU2op_0, decode_PTR2op_0, decode_LOGI2op_0,
	185	decode_COMP3op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
	186	decode_LDSTpmod_0, decode_dagMODim_0, decode_dagMODik_0,
	187	decode_dspLDST_0, decode_LDST_0, decode_LDSTiiFP_0, decode_LDSTii_0,
	188	decode_LoopSetup_0, decode_LDIMMhalf_0, decode_CALLa_0,
	189	decode_LDSTidxI_0, decode_linkage_0, decode_dsp32alu_0,
	190	decode_dsp32shift_0, decode_dsp32shiftimm_0, decode_pseudodbg_assert_0,
	191	_print_insn_bfin, print_insn_bfin): Likewise.
	192
58c85be7 RW	193	2008-03-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
	194
	195	* aclocal.m4: Regenerate.
	196	* configure: Likewise.
	197	* Makefile.in: Likewise.
	198
50e7d84b AM	199	2008-03-13 Alan Modra <amodra@bigpond.net.au>
	200
	201	* Makefile.am: Run "make dep-am".
	202	* Makefile.in: Regenerate.
	203	* configure: Regenerate.
	204
de866fcc AM	205	2008-03-07 Alan Modra <amodra@bigpond.net.au>
	206
	207	* ppc-opc.c (powerpc_opcodes): Order and format.
	208
28dbc079 L	209	2008-03-01 H.J. Lu <hongjiu.lu@intel.com>
	210
	211	* i386-opc.tbl: Allow 16-bit near indirect branches for x86-64.
	212	* i386-tbl.h: Regenerated.
	213
849830bd L	214	2008-02-23 H.J. Lu <hongjiu.lu@intel.com>
	215
	216	* i386-opc.tbl: Disallow 16-bit near indirect branches for
	217	x86-64.
	218	* i386-tbl.h: Regenerated.
	219
743ddb6b JB	220	2008-02-21 Jan Beulich <jbeulich@novell.com>
	221
	222	* i386-opc.tbl: Allow Dword for far indirect call. Allow Dword
	223	and Fword for far indirect jmp. Allow Reg16 and Word for near
	224	indirect jmp on x86-64. Disallow Fword for lcall.
	225	* i386-tbl.h: Re-generate.
	226
796d5313 NC	227	2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
	228
	229	* cr16-opc.c (cr16_num_optab): Defined
	230
65da13b5 L	231	2008-02-16 H.J. Lu <hongjiu.lu@intel.com>
	232
	233	* i386-gen.c (operand_type_init): Add OPERAND_TYPE_INOUTPORTREG.
	234	* i386-init.h: Regenerated.
	235
0e336180 NC	236	2008-02-14 Nick Clifton <nickc@redhat.com>
	237
	238	PR binutils/5524
	239	* configure.in (SHARED_LIBADD): Select the correct host specific
	240	file extension for shared libraries.
	241	* configure: Regenerate.
	242
b7240065 JB	243	2008-02-13 Jan Beulich <jbeulich@novell.com>
	244
	245	* i386-opc.h (RegFlat): New.
	246	* i386-reg.tbl (flat): Add.
	247	* i386-tbl.h: Re-generate.
	248
34b772a6 JB	249	2008-02-13 Jan Beulich <jbeulich@novell.com>
	250
	251	* i386-dis.c (a_mode): New.
	252	(cond_jump_mode): Adjust.
	253	(Ma): Change to a_mode.
	254	(intel_operand_size): Handle a_mode.
	255	* i386-opc.tbl: Allow Dword and Qword for bound.
	256	* i386-tbl.h: Re-generate.
	257
a60de03c JB	258	2008-02-13 Jan Beulich <jbeulich@novell.com>
	259
	260	* i386-gen.c (process_i386_registers): Process new fields.
	261	* i386-opc.h (reg_entry): Shrink reg_flags and reg_num to
	262	unsigned char. Add dw2_regnum and Dw2Inval.
	263	* i386-reg.tbl: Provide initializers for dw2_regnum. Add pseudo
	264	register names.
	265	* i386-tbl.h: Re-generate.
	266
f03fe4c1 L	267	2008-02-11 H.J. Lu <hongjiu.lu@intel.com>
f03fe4c1 L	268
4b6bc8eb	269	* i386-gen.c (cpu_flag_init): Add CPU_XSAVE_FLAGS.
f03fe4c1 L	270	* i386-init.h: Updated.
f03fe4c1 L	271
475a2301 L	272	2008-02-11 H.J. Lu <hongjiu.lu@intel.com>
	273
	274	* i386-gen.c (cpu_flags): Add CpuXsave.
	275
	276	* i386-opc.h (CpuXsave): New.
4b6bc8eb	277	(CpuLM): Updated.
475a2301 L	278	(i386_cpu_flags): Add cpuxsave.
	279
	280	* i386-dis.c (MOD_0FAE_REG_4): New.
	281	(RM_0F01_REG_2): Likewise.
	282	(MOD_0FAE_REG_5): Updated.
	283	(RM_0F01_REG_3): Likewise.
	284	(reg_table): Use MOD_0FAE_REG_4.
	285	(mod_table): Use RM_0F01_REG_2. Add MOD_0FAE_REG_4. Updated
	286	for xrstor.
	287	(rm_table): Add RM_0F01_REG_2.
	288
	289	* i386-opc.tbl: Add xsave, xrstor, xgetbv and xsetbv.
	290	* i386-init.h: Regenerated.
	291	* i386-tbl.h: Likewise.
	292
595785c6	293	2008-02-11 Jan Beulich <jbeulich@novell.com>
041179fc	294
595785c6 JB	295	* i386-opc.tbl: Remove Disp32S from CpuNo64 opcodes. Remove
	296	Disp16 from Cpu64 non-jump opcodes (including loop and j?cxz).
	297	* i386-tbl.h: Re-generate.
	298
bb8541b9 L	299	2008-02-04 H.J. Lu <hongjiu.lu@intel.com>
	300
	301	PR 5715
	302	* configure: Regenerated.
	303
57b592a3 AN	304	2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
	305
	306	* mips-dis.c: Update copyright.
	307	(mips_arch_choices): Add Octeon.
	308	* mips-opc.c: Update copyright.
	309	(IOCT): New macro.
	310	(mips_builtin_opcodes): Add Octeon instruction synciobdma.
	311
930bb4cf AM	312	2008-01-29 Alan Modra <amodra@bigpond.net.au>
	313
	314	* ppc-opc.c: Support optional L form mtmsr.
	315
82c18208 L	316	2008-01-24 H.J. Lu <hongjiu.lu@intel.com>
	317
	318	* i386-dis.c (OP_E_extended): Handle r12 like rsp.
	319
599121aa L	320	2008-01-23 H.J. Lu <hongjiu.lu@intel.com>
	321
	322	* i386-gen.c (cpu_flag_init): Add CpuLM to CPU_GENERIC64_FLAGS.
	323	* i386-init.h: Regenerated.
	324
80098f51 TG	325	2008-01-23 Tristan Gingold <gingold@adacore.com>
	326
	327	* ia64-dis.c (print_insn_ia64): Display symbolic name of ar.fcr,
	328	ar.eflag, ar.csd, ar.ssd, ar.cflg, ar.fsr, ar.fir and ar.fdr.
	329
115c7c25 L	330	2008-01-22 H.J. Lu <hongjiu.lu@intel.com>
	331
	332	* i386-gen.c (cpu_flag_init): Remove CpuMMX2.
	333	(cpu_flags): Likewise.
	334
	335	* i386-opc.h (CpuMMX2): Removed.
	336	(CpuSSE): Updated.
	337
	338	* i386-opc.tbl: Replace CpuMMX2 with CpuSSE\|Cpu3dnowA.
	339	* i386-init.h: Regenerated.
	340	* i386-tbl.h: Likewise.
	341
6305a203 L	342	2008-01-22 H.J. Lu <hongjiu.lu@intel.com>
	343
	344	* i386-gen.c (cpu_flag_init): Add CPU_VMX_FLAGS and
	345	CPU_SMX_FLAGS.
	346	* i386-init.h: Regenerated.
	347
fd07a1c8 L	348	2008-01-15 H.J. Lu <hongjiu.lu@intel.com>
	349
	350	* i386-opc.tbl: Use Qword on movddup.
	351	* i386-tbl.h: Regenerated.
	352
321fd21e L	353	2008-01-15 H.J. Lu <hongjiu.lu@intel.com>
	354
	355	* i386-opc.tbl: Put back 16bit movsx/movzx for AT&T syntax.
	356	* i386-tbl.h: Regenerated.
	357
4ee52178 L	358	2008-01-15 H.J. Lu <hongjiu.lu@intel.com>
	359
	360	* i386-dis.c (Mx): New.
	361	(PREFIX_0FC3): Likewise.
	362	(PREFIX_0FC7_REG_6): Updated.
	363	(dis386_twobyte): Use PREFIX_0FC3.
	364	(prefix_table): Add PREFIX_0FC3. Use Mq on movntq and movntsd.
	365	Use Mx on movntps, movntpd, movntdq and movntdqa. Use Md on
	366	movntss.
	367
5c07affc L	368	2008-01-14 H.J. Lu <hongjiu.lu@intel.com>
	369
	370	* i386-gen.c (opcode_modifiers): Add IntelSyntax.
	371	(operand_types): Add Mem.
	372
	373	* i386-opc.h (IntelSyntax): New.
	374	* i386-opc.h (Mem): New.
	375	(Byte): Updated.
	376	(Opcode_Modifier_Max): Updated.
	377	(i386_opcode_modifier): Add intelsyntax.
	378	(i386_operand_type): Add mem.
	379
	380	* i386-opc.tbl: Remove Reg16 from movnti. Add sizes to more
	381	instructions.
	382
	383	* i386-reg.tbl: Add size for accumulator.
	384
	385	* i386-init.h: Regenerated.
	386	* i386-tbl.h: Likewise.
	387
0d6a2f58 L	388	2008-01-13 H.J. Lu <hongjiu.lu@intel.com>
	389
	390	* i386-opc.h (Byte): Fix a typo.
	391
7d5e4556 L	392	2008-01-12 H.J. Lu <hongjiu.lu@intel.com>
	393
	394	PR gas/5534
	395	* i386-gen.c (operand_type_init): Add Dword to
	396	OPERAND_TYPE_ACC32. Add Qword to OPERAND_TYPE_ACC64.
	397	(opcode_modifiers): Remove CheckSize, Byte, Word, Dword,
	398	Qword and Xmmword.
	399	(operand_types): Add Byte, Word, Dword, Fword, Qword, Tbyte,
	400	Xmmword, Unspecified and Anysize.
	401	(set_bitfield): Make Mmword an alias of Qword. Make Oword
	402	an alias of Xmmword.
	403
	404	* i386-opc.h (CheckSize): Removed.
	405	(Byte): Updated.
	406	(Word): Likewise.
	407	(Dword): Likewise.
	408	(Qword): Likewise.
	409	(Xmmword): Likewise.
	410	(FWait): Updated.
	411	(OTMax): Likewise.
	412	(i386_opcode_modifier): Remove checksize, byte, word, dword,
	413	qword and xmmword.
	414	(Fword): New.
	415	(TBYTE): Likewise.
	416	(Unspecified): Likewise.
	417	(Anysize): Likewise.
	418	(i386_operand_type): Add byte, word, dword, fword, qword,
	419	tbyte xmmword, unspecified and anysize.
	420
	421	* i386-opc.tbl: Updated to use Byte, Word, Dword, Fword, Qword,
	422	Tbyte, Xmmword, Unspecified and Anysize.
	423
	424	* i386-reg.tbl: Add size for accumulator.
	425
	426	* i386-init.h: Regenerated.
	427	* i386-tbl.h: Likewise.
	428
b5b1fc4f L	429	2008-01-10 H.J. Lu <hongjiu.lu@intel.com>
	430
	431	* i386-dis.c (REG_0F0E): Renamed to REG_0F0D.
	432	(REG_0F18): Updated.
	433	(reg_table): Updated.
	434	(dis386_twobyte): Updated. Use "nopQ" on 0x19 to 0x1e.
	435	(twobyte_has_modrm): Set 1 for 0x19 to 0x1e.
	436
50e8458f L	437	2008-01-08 H.J. Lu <hongjiu.lu@intel.com>
	438
	439	* i386-gen.c (set_bitfield): Use fail () on error.
	440
3d4d5afa L	441	2008-01-08 H.J. Lu <hongjiu.lu@intel.com>
	442
	443	* i386-gen.c (lineno): New.
	444	(filename): Likewise.
	445	(set_bitfield): Report filename and line numer on error.
	446	(process_i386_opcodes): Set filename and update lineno.
	447	(process_i386_registers): Likewise.
	448
e1d4d893 L	449	2008-01-05 H.J. Lu <hongjiu.lu@intel.com>
	450
	451	* i386-gen.c (opcode_modifiers): Rename IntelMnemonic to
	452	ATTSyntax.
	453
	454	* i386-opc.h (IntelMnemonic): Renamed to ..
	455	(ATTSyntax): This
	456	(Opcode_Modifier_Max): Updated.
	457	(i386_opcode_modifier): Remove intelmnemonic. Add attsyntax
	458	and intelsyntax.
	459
	460	* i386-opc.tbl: Remove IntelMnemonic and update with ATTSyntax
	461	on fsub, fubp, fsubr, fsubrp, div, fdivp, fdivr and fdivrp.
	462	* i386-tbl.h: Regenerated.
	463
6f143e4d L	464	2008-01-04 H.J. Lu <hongjiu.lu@intel.com>
	465
	466	* i386-gen.c: Update copyright to 2008.
	467	* i386-opc.h: Likewise.
	468	* i386-opc.tbl: Likewise.
	469
	470	* i386-init.h: Regenerated.
	471	* i386-tbl.h: Likewise.
	472
c6add537 L	473	2008-01-04 H.J. Lu <hongjiu.lu@intel.com>
	474
	475	* i386-opc.tbl: Add NoRex64 to extractps, movmskpd, movmskps,
	476	pextrb, pextrw, pinsrb, pinsrw and pmovmskb.
	477	* i386-tbl.h: Regenerated.
	478
3629bb00 L	479	2008-01-03 H.J. Lu <hongjiu.lu@intel.com>
	480
	481	* i386-gen.c (cpu_flag_init): Remove CpuSSE4_1_Or_5 and
	482	CpuSSE4_2_Or_ABM.
	483	(cpu_flags): Likewise.
	484
	485	* i386-opc.h (CpuSSE4_1_Or_5): Removed.
	486	(CpuSSE4_2_Or_ABM): Likewise.
	487	(CpuLM): Updated.
	488	(i386_cpu_flags): Remove cpusse4_1_or_5 and cpusse4_2_or_abm.
	489
	490	* i386-opc.tbl: Replace CpuSSE4_1_Or_5, CpuSSE4_2_Or_ABM and
	491	Cpu686\|CpuPadLock with CpuSSE4_1\|CpuSSE5, CpuABM\|CpuSSE4_2
	492	and CpuPadLock, respectively.
	493	* i386-init.h: Regenerated.
	494	* i386-tbl.h: Likewise.
	495
24995bd6 L	496	2008-01-03 H.J. Lu <hongjiu.lu@intel.com>
	497
	498	* i386-gen.c (opcode_modifiers): Remove No_xSuf.
	499
	500	* i386-opc.h (No_xSuf): Removed.
	501	(CheckSize): Updated.
	502
	503	* i386-tbl.h: Regenerated.
	504
e0329a22 L	505	2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
	506
	507	* i386-gen.c (cpu_flag_init): Add CpuSSE4_2_Or_ABM to
	508	CPU_AMDFAM10_FLAGS, CPU_SSE4_2_FLAGS, CpuABM and
	509	CPU_SSE5_FLAGS.
	510	(cpu_flags): Add CpuSSE4_2_Or_ABM.
	511
	512	* i386-opc.h (CpuSSE4_2_Or_ABM): New.
	513	(CpuLM): Updated.
	514	(i386_cpu_flags): Add cpusse4_2_or_abm.
	515
	516	* i386-opc.tbl: Use CpuSSE4_2_Or_ABM instead of
	517	CpuABM\|CpuSSE4_2 on popcnt.
	518	* i386-init.h: Regenerated.
	519	* i386-tbl.h: Likewise.
	520
f2a9c676 L	521	2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
	522
	523	* i386-opc.h: Update comments.
	524
d978b5be L	525	2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
	526
	527	* i386-gen.c (opcode_modifiers): Use Qword instead of QWord.
	528	* i386-opc.h: Likewise.
	529	* i386-opc.tbl: Likewise.
	530
582d5edd L	531	2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
	532
	533	PR gas/5534
	534	* i386-gen.c (opcode_modifiers): Add No_xSuf, CheckSize,
	535	Byte, Word, Dword, QWord and Xmmword.
	536
	537	* i386-opc.h (No_xSuf): New.
	538	(CheckSize): Likewise.
	539	(Byte): Likewise.
	540	(Word): Likewise.
	541	(Dword): Likewise.
	542	(QWord): Likewise.
	543	(Xmmword): Likewise.
	544	(FWait): Updated.
	545	(i386_opcode_modifier): Add No_xSuf, CheckSize, Byte, Word,
	546	Dword, QWord and Xmmword.
	547
	548	* i386-opc.tbl: Add CheckSize\|QWord to movq if IgnoreSize is
	549	used.
	550	* i386-tbl.h: Regenerated.
	551
3fe15143 MK	552	2008-01-02 Mark Kettenis <kettenis@gnu.org>
	553
	554	* m88k-dis.c (instructions): Fix fcvt.* instructions.
	555	From Miod Vallat.
	556
6c7ac64e	557	For older changes see ChangeLog-2007
252b5132 RH	558	\f
252b5132 RH	559	Local Variables:
2f6d2f85 NC	560	mode: change-log
	561	left-margin: 8
	562	fill-column: 74
252b5132 RH	563	version-control: never
252b5132 RH	564	End: