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Use target_desc fields expedite_regs and xmltarget ifndef IN_PROCESS_AGENT
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
65a55fbb
TC		 12017-06-28 Tamar Christina <tamar.christina@arm.com>
2
3 * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod.
4 * aarch64-dis.c (aarch64_ext_reglane): Likewise.
5 * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New.
6 (aarch64_feature_dotprod, DOT_INSN): New.
7 (udot, sdot): New.
8 * aarch64-dis-2.c: Regenerated.
9
c604a79a
JW		 102017-06-28 Jiong Wang <jiong.wang@arm.com>
11
12 * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
13
38bf472a
MR		 142017-06-28 Maciej W. Rozycki <macro@imgtec.com>
15 Matthew Fortune <matthew.fortune@imgtec.com>
16 Andrew Bennett <andrew.bennett@imgtec.com>
17
18 * mips-formats.h (INT_BIAS): New macro.
19 (INT_ADJ): Redefine in INT_BIAS terms.
20 * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
21 (mips_print_save_restore): New function.
22 (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
23 (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
24 call.
25 (print_insn_args): Handle OP_SAVE_RESTORE_LIST.
26 (print_mips16_insn_arg): Call `mips_print_save_restore' for
27 OP_SAVE_RESTORE_LIST handling, factored out from here.
28 * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
29 (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
30 (mips_builtin_opcodes): Add "restore" and "save" entries.
31 * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
32 (IAMR2): New macro.
33 (mips16_opcodes): Add "copyw" and "ucopyw" entries.
34
9bdfdbf9
AW		 352017-06-23 Andrew Waterman <andrew@sifive.com>
36
37 * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
38 alias; do not mark SLTI instruction as an alias.
39
2234eee6
L		 402017-06-21 H.J. Lu <hongjiu.lu@intel.com>
41
42 * i386-dis.c (RM_0FAE_REG_5): Removed.
43 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
44 (PREFIX_MOD_3_0F01_REG_5_RM_0): New.
45 (PREFIX_MOD_3_0FAE_REG_5): Likewise.
46 (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1. Add
47 PREFIX_MOD_3_0F01_REG_5_RM_0.
48 (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5. Add
49 PREFIX_MOD_3_0FAE_REG_5.
50 (mod_table): Update MOD_0FAE_REG_5.
51 (rm_table): Update RM_0F01_REG_5. Remove RM_0FAE_REG_5.
52 * i386-opc.tbl: Update incsspd, incsspq and setssbsy.
53 * i386-tbl.h: Regenerated.
54
c2f76402
L		 552017-06-21 H.J. Lu <hongjiu.lu@intel.com>
56
57 * i386-dis.c (prefix_table): Replace savessp with saveprevssp.
58 * i386-opc.tbl: Likewise.
59 * i386-tbl.h: Regenerated.
60
9fef80d6
L		 612017-06-21 H.J. Lu <hongjiu.lu@intel.com>
62
63 * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"
64 and "jmp{&|}".
65 (NOTRACK_Fixup): Support memory indirect branch with NOTRACK
66 prefix.
67
0f6d864d
NC		 682017-06-19 Nick Clifton <nickc@redhat.com>
69
70 PR binutils/21614
71 * score-dis.c (score_opcodes): Add sentinel.
72
e197589b
AM		 732017-06-16 Alan Modra <amodra@gmail.com>
74
75 * rx-decode.c: Regenerate.
76
0d96e4df
L		 772017-06-15 H.J. Lu <hongjiu.lu@intel.com>
78
79 PR binutils/21594
80 * i386-dis.c (OP_E_register): Check valid bnd register.
81 (OP_G): Likewise.
82
cd3ea7c6
NC		 832017-06-15 Nick Clifton <nickc@redhat.com>
84
85 PR binutils/21595
86 * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
87 range value.
88
63323b5b
NC		 892017-06-15 Nick Clifton <nickc@redhat.com>
90
91 PR binutils/21588
92 * rl78-decode.opc (OP_BUF_LEN): Define.
93 (GETBYTE): Check for the index exceeding OP_BUF_LEN.
94 (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
95 array.
96 * rl78-decode.c: Regenerate.
97
08c7881b
NC		 982017-06-15 Nick Clifton <nickc@redhat.com>
99
100 PR binutils/21586
101 * bfin-dis.c (gregs): Clip index to prevent overflow.
102 (regs): Likewise.
103 (regs_lo): Likewise.
104 (regs_hi): Likewise.
105
e64519d1
NC		 1062017-06-14 Nick Clifton <nickc@redhat.com>
107
108 PR binutils/21576
109 * score7-dis.c (score_opcodes): Add sentinel.
110
6394c606
YQ		 1112017-06-14 Yao Qi <yao.qi@linaro.org>
112
113 * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
114 * arm-dis.c: Likewise.
115 * ia64-dis.c: Likewise.
116 * mips-dis.c: Likewise.
117 * spu-dis.c: Likewise.
118 * disassemble.h (print_insn_aarch64): New declaration, moved from
119 include/dis-asm.h.
120 (print_insn_big_arm, print_insn_big_mips): Likewise.
121 (print_insn_i386, print_insn_ia64): Likewise.
122 (print_insn_little_arm, print_insn_little_mips): Likewise.
123
db5fa770
NC		 1242017-06-14 Nick Clifton <nickc@redhat.com>
125
126 PR binutils/21587
127 * rx-decode.opc: Include libiberty.h
128 (GET_SCALE): New macro - validates access to SCALE array.
129 (GET_PSCALE): New macro - validates access to PSCALE array.
130 (DIs, SIs, S2Is, rx_disp): Use new macros.
131 * rx-decode.c: Regenerate.
132
05c966f3
AV		 1332017-07-14 Andre Vieira <andre.simoesdiasvieira@arm.com>
134
135 * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
136
10045478
AK		 1372017-05-30 Anton Kolesov <anton.kolesov@synopsys.com>
138
139 * arc-dis.c (enforced_isa_mask): Declare.
140 (cpu_types): Likewise.
141 (parse_cpu_option): New function.
142 (parse_disassembler_options): Use it.
143 (print_insn_arc): Use enforced_isa_mask.
144 (print_arc_disassembler_options): Document new options.
145
88c1242d
YQ		 1462017-05-24 Yao Qi <yao.qi@linaro.org>
147
148 * alpha-dis.c: Include disassemble.h, don't include
149 dis-asm.h.
150 * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
151 * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
152 * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
153 * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
154 * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
155 * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
156 * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
157 * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
158 * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
159 * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
160 * moxie-dis.c, msp430-dis.c, mt-dis.c:
161 * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
162 * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
163 * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
164 * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
165 * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
166 * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
167 * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
168 * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
169 * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
170 * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
171 * z80-dis.c, z8k-dis.c: Likewise.
172 * disassemble.h: New file.
173
ab20fa4a
YQ		 1742017-05-24 Yao Qi <yao.qi@linaro.org>
175
176 * rl78-dis.c (rl78_get_disassembler): If parameter abfd
177 is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
178
003ca0fd
YQ		 1792017-05-24 Yao Qi <yao.qi@linaro.org>
180
181 * disassemble.c (disassembler): Add arguments a, big and mach.
182 Use them.
183
04ef582a
L		 1842017-05-22 H.J. Lu <hongjiu.lu@intel.com>
185
186 * i386-dis.c (NOTRACK_Fixup): New.
187 (NOTRACK): Likewise.
188 (NOTRACK_PREFIX): Likewise.
189 (last_active_prefix): Likewise.
190 (reg_table): Use NOTRACK on indirect call and jmp.
191 (ckprefix): Set last_active_prefix.
192 (prefix_name): Return "notrack" for NOTRACK_PREFIX.
193 * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
194 * i386-opc.h (NoTrackPrefixOk): New.
195 (i386_opcode_modifier): Add notrackprefixok.
196 * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
197 Add notrack.
198 * i386-tbl.h: Regenerated.
199
64517994
JM		 2002017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
201
202 * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
203 (X_IMM2): Define.
204 (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
205 bfd_mach_sparc_v9m8.
206 (print_insn_sparc): Handle new operand types.
207 * sparc-opc.c (MASK_M8): Define.
208 (v6): Add MASK_M8.
209 (v6notlet): Likewise.
210 (v7): Likewise.
211 (v8): Likewise.
212 (v9): Likewise.
213 (v9a): Likewise.
214 (v9b): Likewise.
215 (v9c): Likewise.
216 (v9d): Likewise.
217 (v9e): Likewise.
218 (v9v): Likewise.
219 (v9m): Likewise.
220 (v9andleon): Likewise.
221 (m8): Define.
222 (HWS_VM8): Define.
223 (HWS2_VM8): Likewise.
224 (sparc_opcode_archs): Add entry for "m8".
225 (sparc_opcodes): Add OSA2017 and M8 instructions
226 dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
227 fpx{ll,ra,rl}64x,
228 ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
229 ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
230 revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
231 stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
232 (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
233 ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
234 ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
235 ASI_CORE_SELECT_COMMIT_NHT.
236
535b785f
AM		 2372017-05-18 Alan Modra <amodra@gmail.com>
238
239 * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
240 * aarch64-dis.c: Likewise.
241 * aarch64-gen.c: Likewise.
242 * aarch64-opc.c: Likewise.
243
25499ac7
MR		 2442017-05-15 Maciej W. Rozycki <macro@imgtec.com>
245 Matthew Fortune <matthew.fortune@imgtec.com>
246
247 * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
248 ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
249 (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
250 (print_insn_arg) <OP_REG28>: Add handler.
251 (validate_insn_args) <OP_REG28>: Handle.
252 (print_mips16_insn_arg): Handle MIPS16 instructions that require
253 32-bit encoding and 9-bit immediates.
254 (print_insn_mips16): Handle MIPS16 instructions that require
255 32-bit encoding and MFC0/MTC0 operand decoding.
256 * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
257 <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
258 (RD_C0, WR_C0, E2, E2MT): New macros.
259 (mips16_opcodes): Add entries for MIPS16e2 instructions:
260 GP-relative "addiu" and its "addu" spelling, "andi", "cache",
261 "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
262 "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
263 "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
264 "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
265 instructions, "swl", "swr", "sync" and its "sync_acquire",
266 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
267 "xori", "dmt", "dvpe", "emt" and "evpe". Add split
268 regular/extended entries for original MIPS16 ISA revision
269 instructions whose extended forms are subdecoded in the MIPS16e2
270 ISA revision: "li", "sll" and "srl".
271
fdfb4752
MR		 2722017-05-15 Maciej W. Rozycki <macro@imgtec.com>
273
274 * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
275 reference in CP0 move operand decoding.
276
a4f89915
MR		 2772017-05-12 Maciej W. Rozycki <macro@imgtec.com>
278
279 * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
280 type to hexadecimal.
281 (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
282
99e2d67a
MR		 2832017-05-11 Maciej W. Rozycki <macro@imgtec.com>
284
285 * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
286 "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
287 "sync_rmb" and "sync_wmb" as aliases.
288 * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
289 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
290
53a346d8
CZ		 2912017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
292
293 * arc-dis.c (parse_option): Update quarkse_em option..
294 * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
295 QUARKSE1.
296 (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
297
f91d48de
KC		 2982017-05-03 Kito Cheng <kito.cheng@gmail.com>
299
300 * riscv-dis.c (print_insn_args): Handle 'Co' operands.
301
43e379d7
MC		 3022017-05-01 Michael Clark <michaeljclark@mac.com>
303
304 * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
305 register.
306
a4ddc54e
MR		 3072017-05-02 Maciej W. Rozycki <macro@imgtec.com>
308
309 * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
310 and branches and not synthetic data instructions.
311
fe50e98c
BE		 3122017-05-02 Bernd Edlinger <bernd.edlinger@hotmail.de>
313
314 * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
315
126124cc
CZ		 3162017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
317
318 * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
319 * arc-opc.c (insert_r13el): New function.
320 (R13_EL): Define.
321 * arc-tbl.h: Add new enter/leave variants.
322
be6a24d8
CZ		 3232017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
324
325 * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
326
0348fd79
MR		 3272017-04-25 Maciej W. Rozycki <macro@imgtec.com>
328
329 * mips-dis.c (print_mips_disassembler_options): Add
330 `no-aliases'.
331
6e3d1f07
MR		 3322017-04-25 Maciej W. Rozycki <macro@imgtec.com>
333
334 * mips16-opc.c (AL): New macro.
335 (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
336 of "ld" and "lw" as aliases.
337
957f6b39
TC		 3382017-04-24 Tamar Christina <tamar.christina@arm.com>
339
340 * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
341 arguments.
342
a8cc8a54
AM		 3432017-04-22 Alexander Fedotov <alfedotov@gmail.com>
344 Alan Modra <amodra@gmail.com>
345
346 * ppc-opc.c (ELEV): Define.
347 (vle_opcodes): Add se_rfgi and e_sc.
348 (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
349 for E200Z4.
350
3ab87b68
JM		 3512017-04-21 Jose E. Marchesi <jose.marchesi@oracle.com>
352
353 * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
354
792f174f
NC		 3552017-04-21 Nick Clifton <nickc@redhat.com>
356
357 PR binutils/21380
358 * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
359 LD3R and LD4R.
360
42742084
AM		 3612017-04-13 Alan Modra <amodra@gmail.com>
362
363 * epiphany-desc.c: Regenerate.
364 * fr30-desc.c: Regenerate.
365 * frv-desc.c: Regenerate.
366 * ip2k-desc.c: Regenerate.
367 * iq2000-desc.c: Regenerate.
368 * lm32-desc.c: Regenerate.
369 * m32c-desc.c: Regenerate.
370 * m32r-desc.c: Regenerate.
371 * mep-desc.c: Regenerate.
372 * mt-desc.c: Regenerate.
373 * or1k-desc.c: Regenerate.
374 * xc16x-desc.c: Regenerate.
375 * xstormy16-desc.c: Regenerate.
376
9a85b496
AM		 3772017-04-11 Alan Modra <amodra@gmail.com>
378
ef85eab0 379 * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
c03dc33b
AM		 380 PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm". Formatting. Set
381 PPC_OPCODE_TMR for e6500.
9a85b496
AM		 382 * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
383 (PPCVEC3): Define as PPC_OPCODE_POWER9.
9570835e
AM		 384 (PPCVSX2): Define as PPC_OPCODE_POWER8.
385 (PPCVSX3): Define as PPC_OPCODE_POWER9.
ef85eab0 386 (PPCHTM): Define as PPC_OPCODE_POWER8.
c03dc33b 387 (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
9a85b496 388
62adc510
AM		 3892017-04-10 Alan Modra <amodra@gmail.com>
390
391 * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
392 * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
393 (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
394 removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
395
aa808707
PC		 3962017-04-09 Pip Cet <pipcet@gmail.com>
397
398 * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
399 appropriate floating-point precision directly.
400
ac8f0f72
AM		 4012017-04-07 Alan Modra <amodra@gmail.com>
402
403 * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
404 lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
405 lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
406 lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
407 vector instructions with E6500 not PPCVEC2.
408
62ecb94c
PC		 4092017-04-06 Pip Cet <pipcet@gmail.com>
410
411 * Makefile.am: Add wasm32-dis.c.
412 * configure.ac: Add wasm32-dis.c to wasm32 target.
413 * disassemble.c: Add wasm32 disassembler code.
414 * wasm32-dis.c: New file.
415 * Makefile.in: Regenerate.
416 * configure: Regenerate.
417 * po/POTFILES.in: Regenerate.
418 * po/opcodes.pot: Regenerate.
419
f995bbe8
PA		 4202017-04-05 Pedro Alves <palves@redhat.com>
421
422 * arc-dis.c (parse_option, parse_disassembler_options): Constify.
423 * arm-dis.c (parse_arm_disassembler_options): Constify.
424 * ppc-dis.c (powerpc_init_dialect): Constify local.
425 * vax-dis.c (parse_disassembler_options): Constify.
426
b5292032
PD		 4272017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
428
429 * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
430 RISCV_GP_SYMBOL.
431
f96bd6c2
PC		 4322017-03-30 Pip Cet <pipcet@gmail.com>
433
434 * configure.ac: Add (empty) bfd_wasm32_arch target.
435 * configure: Regenerate
436 * po/opcodes.pot: Regenerate.
437
f7c514a3
JM		 4382017-03-29 Sheldon Lobo <sheldon.lobo@oracle.com>
439
440 Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
441 OSA2015.
442 * opcodes/sparc-opc.c (asi_table): New ASIs.
443
52be03fd
AM		 4442017-03-29 Alan Modra <amodra@gmail.com>
445
446 * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add
447 "raw" option.
448 (lookup_powerpc): Don't special case -1 dialect. Handle
449 PPC_OPCODE_RAW.
450 (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
451 lookup_powerpc call, pass it on second.
452
9b753937
AM		 4532017-03-27 Alan Modra <amodra@gmail.com>
454
455 PR 21303
456 * ppc-dis.c (struct ppc_mopt): Comment.
457 (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
458
c0c31e91
RZ		 4592017-03-27 Rinat Zelig <rinat@mellanox.com>
460
461 * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
462 * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
463 F_NPS_M, F_NPS_CORE, F_NPS_ALL.
464 (insert_nps_misc_imm_offset): New function.
465 (extract_nps_misc imm_offset): New function.
466 (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
467 (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
468
2253c8f0
AK		 4692017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
470
471 * s390-mkopc.c (main): Remove vx2 check.
472 * s390-opc.txt: Remove vx2 instruction flags.
473
645d3342
RZ		 4742017-03-21 Rinat Zelig <rinat@mellanox.com>
475
476 * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
477 * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
478 (insert_nps_imm_offset): New function.
479 (extract_nps_imm_offset): New function.
480 (insert_nps_imm_entry): New function.
481 (extract_nps_imm_entry): New function.
482
4b94dd2d
AM		 4832017-03-17 Alan Modra <amodra@gmail.com>
484
485 PR 21248
486 * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
487 mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after
488 those spr mnemonics they alias. Similarly for mtibatl, mtibatu.
489
b416fe87
KC		 4902017-03-14 Kito Cheng <kito.cheng@gmail.com>
491
492 * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
493 <c.andi>: Likewise.
494 <c.addiw> Likewise.
495
03b039a5
KC		 4962017-03-14 Kito Cheng <kito.cheng@gmail.com>
497
498 * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
499
2c232b83
AW		 5002017-03-13 Andrew Waterman <andrew@sifive.com>
501
502 * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
503 <srl> Likewise.
504 <srai> Likewise.
505 <sra> Likewise.
506
86fa6981
L		 5072017-03-09 H.J. Lu <hongjiu.lu@intel.com>
508
509 * i386-gen.c (opcode_modifiers): Replace S with Load.
510 * i386-opc.h (S): Removed.
511 (Load): New.
512 (i386_opcode_modifier): Replace s with load.
513 * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
514 and {evex}. Replace S with Load.
515 * i386-tbl.h: Regenerated.
516
c1fe188b
L		 5172017-03-09 H.J. Lu <hongjiu.lu@intel.com>
518
519 * i386-opc.tbl: Use CpuCET on rdsspq.
520 * i386-tbl.h: Regenerated.
521
4b8b687e
PB		 5222017-03-08 Peter Bergner <bergner@vnet.ibm.com>
523
524 * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
525 <vsx>: Do not use PPC_OPCODE_VSX3;
526
1437d063
PB		 5272017-03-08 Peter Bergner <bergner@vnet.ibm.com>
528
529 * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
530
603555e5
L		 5312017-03-06 H.J. Lu <hongjiu.lu@intel.com>
532
533 * i386-dis.c (REG_0F1E_MOD_3): New enum.
534 (MOD_0F1E_PREFIX_1): Likewise.
535 (MOD_0F38F5_PREFIX_2): Likewise.
536 (MOD_0F38F6_PREFIX_0): Likewise.
537 (RM_0F1E_MOD_3_REG_7): Likewise.
538 (PREFIX_MOD_0_0F01_REG_5): Likewise.
539 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
540 (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
541 (PREFIX_0F1E): Likewise.
542 (PREFIX_MOD_0_0FAE_REG_5): Likewise.
543 (PREFIX_0F38F5): Likewise.
544 (dis386_twobyte): Use PREFIX_0F1E.
545 (reg_table): Add REG_0F1E_MOD_3.
546 (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
547 PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
548 PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
549 PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
550 (three_byte_table): Use PREFIX_0F38F5.
551 (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
552 Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
553 (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
554 RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
555 PREFIX_MOD_3_0F01_REG_5_RM_2.
556 * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
557 (cpu_flags): Add CpuCET.
558 * i386-opc.h (CpuCET): New enum.
559 (CpuUnused): Commented out.
560 (i386_cpu_flags): Add cpucet.
561 * i386-opc.tbl: Add Intel CET instructions.
562 * i386-init.h: Regenerated.
563 * i386-tbl.h: Likewise.
564
73f07bff
AM		 5652017-03-06 Alan Modra <amodra@gmail.com>
566
567 PR 21124
568 * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
569 (extract_raq, extract_ras, extract_rbx): New functions.
570 (powerpc_operands): Use opposite corresponding insert function.
571 (Q_MASK): Define.
572 (powerpc_opcodes): Apply Q_MASK to all quad insns with even
573 register restriction.
574
65b48a81
PB		 5752017-02-28 Peter Bergner <bergner@vnet.ibm.com>
576
577 * disassemble.c Include "safe-ctype.h".
578 (disassemble_init_for_target): Handle s390 init.
579 (remove_whitespace_and_extra_commas): New function.
580 (disassembler_options_cmp): Likewise.
581 * arm-dis.c: Include "libiberty.h".
582 (NUM_ELEM): Delete.
583 (regnames): Use long disassembler style names.
584 Add force-thumb and no-force-thumb options.
585 (NUM_ARM_REGNAMES): Rename from this...
586 (NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE.
587 (get_arm_regname_num_options): Delete.
588 (set_arm_regname_option): Likewise.
589 (get_arm_regnames): Likewise.
590 (parse_disassembler_options): Likewise.
591 (parse_arm_disassembler_option): Rename from this...
592 (parse_arm_disassembler_options): ...to this. Make static.
593 Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
594 (print_insn): Use parse_arm_disassembler_options.
595 (disassembler_options_arm): New function.
596 (print_arm_disassembler_options): Handle updated regnames.
597 * ppc-dis.c: Include "libiberty.h".
598 (ppc_opts): Add "32" and "64" entries.
599 (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
600 (powerpc_init_dialect): Add break to switch statement.
601 Use new FOR_EACH_DISASSEMBLER_OPTION macro.
602 (disassembler_options_powerpc): New function.
603 (print_ppc_disassembler_options): Use ARRAY_SIZE.
604 Remove printing of "32" and "64".
605 * s390-dis.c: Include "libiberty.h".
606 (init_flag): Remove unneeded variable.
607 (struct s390_options_t): New structure type.
608 (options): New structure.
609 (init_disasm): Rename from this...
610 (disassemble_init_s390): ...to this. Add initializations for
611 current_arch_mask and option_use_insn_len_bits_p. Remove init_flag.
612 (print_insn_s390): Delete call to init_disasm.
613 (disassembler_options_s390): New function.
614 (print_s390_disassembler_options): Print using information from
615 struct 'options'.
616 * po/opcodes.pot: Regenerate.
617
15c7c1d8
JB		 6182017-02-28 Jan Beulich <jbeulich@suse.com>
619
620 * i386-dis.c (PCMPESTR_Fixup): New.
621 (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
622 (prefix_table): Use PCMPESTR_Fixup.
623 (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
624 PCMPESTR_Fixup.
625 (vex_w_table): Delete VPCMPESTR{I,M} entries.
626 * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
627 Split 64-bit and non-64-bit variants.
628 * opcodes/i386-tbl.h: Re-generate.
629
582e12bf
RS		 6302017-02-24 Richard Sandiford <richard.sandiford@arm.com>
631
632 * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
633 (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
634 (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
635 (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
636 (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
637 (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
638 (OP_SVE_V_HSD): New macros.
639 (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
640 (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
641 (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
642 (aarch64_opcode_table): Add new SVE instructions.
643 (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
644 for rotation operands. Add new SVE operands.
645 * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
646 (ins_sve_quad_index): Likewise.
647 (ins_imm_rotate): Split into...
648 (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
649 * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
650 (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
651 functions.
652 (aarch64_ins_sve_addr_ri_s4): New function.
653 (aarch64_ins_sve_quad_index): Likewise.
654 (do_misc_encoding): Handle "MOV Zn.Q, Qm".
655 * aarch64-asm-2.c: Regenerate.
656 * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
657 (ext_sve_quad_index): Likewise.
658 (ext_imm_rotate): Split into...
659 (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
660 * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
661 (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
662 functions.
663 (aarch64_ext_sve_addr_ri_s4): New function.
664 (aarch64_ext_sve_quad_index): Likewise.
665 (aarch64_ext_sve_index): Allow quad indices.
666 (do_misc_decoding): Likewise.
667 * aarch64-dis-2.c: Regenerate.
668 * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
669 aarch64_field_kinds.
670 (OPD_F_OD_MASK): Widen by one bit.
671 (OPD_F_NO_ZR): Bump accordingly.
672 (get_operand_field_width): New function.
673 * aarch64-opc.c (fields): Add new SVE fields.
674 (operand_general_constraint_met_p): Handle new SVE operands.
675 (aarch64_print_operand): Likewise.
676 * aarch64-opc-2.c: Regenerate.
677
f482d304
RS		 6782017-02-24 Richard Sandiford <richard.sandiford@arm.com>
679
680 * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
681 (aarch64_feature_compnum): ...this.
682 (SIMD_V8_3): Replace with...
683 (COMPNUM): ...this.
684 (CNUM_INSN): New macro.
685 (aarch64_opcode_table): Use it for the complex number instructions.
686
7db2c588
JB		 6872017-02-24 Jan Beulich <jbeulich@suse.com>
688
689 * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
690
1e9d41d4
SL		 6912017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
692
693 Add support for associating SPARC ASIs with an architecture level.
694 * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
695 * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
696 decoding of SPARC ASIs.
697
53c4d625
JB		 6982017-02-23 Jan Beulich <jbeulich@suse.com>
699
700 * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
701 82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
702
11648de5
JB		 7032017-02-21 Jan Beulich <jbeulich@suse.com>
704
705 * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
706 1 (instead of to itself). Correct typo.
707
f98d33be
AW		 7082017-02-14 Andrew Waterman <andrew@sifive.com>
709
710 * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
711 pseudoinstructions.
712
773fb663
RS		 7132017-02-15 Richard Sandiford <richard.sandiford@arm.com>
714
715 * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
716 (aarch64_sys_reg_supported_p): Handle them.
717
cc07cda6
CZ		 7182017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
719
720 * arc-opc.c (UIMM6_20R): Define.
721 (SIMM12_20): Use above.
722 (SIMM12_20R): Define.
723 (SIMM3_5_S): Use above.
724 (UIMM7_A32_11R_S): Define.
725 (UIMM7_9_S): Use above.
726 (UIMM3_13R_S): Define.
727 (SIMM11_A32_7_S): Use above.
728 (SIMM9_8R): Define.
729 (UIMM10_A32_8_S): Use above.
730 (UIMM8_8R_S): Define.
731 (W6): Use above.
732 (arc_relax_opcodes): Use all above defines.
733
66a5a740
VG		 7342017-02-15 Vineet Gupta <vgupta@synopsys.com>
735
736 * arc-regs.h: Distinguish some of the registers different on
737 ARC700 and HS38 cpus.
738
7e0de605
AM		 7392017-02-14 Alan Modra <amodra@gmail.com>
740
741 PR 21118
742 * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
743 with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
744
54064fdb
AM		 7452017-02-11 Stafford Horne <shorne@gmail.com>
746 Alan Modra <amodra@gmail.com>
747
748 * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
749 Use insn_bytes_value and insn_int_value directly instead. Don't
750 free allocated memory until function exit.
751
dce75bf9
NP		 7522017-02-10 Nicholas Piggin <npiggin@gmail.com>
753
754 * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
755
1b7e3d2f
NC		 7562017-02-03 Nick Clifton <nickc@redhat.com>
757
758 PR 21096
759 * aarch64-opc.c (print_register_list): Ensure that the register
760 list index will fir into the tb buffer.
761 (print_register_offset_address): Likewise.
762 * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
763
8ec5cf65
AD		 7642017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
765
766 PR 21056
767 * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
768 instructions when the previous fetch packet ends with a 32-bit
769 instruction.
770
a1aa5e81
DD		 7712017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
772
773 * pru-opc.c: Remove vague reference to a future GDB port.
774
add3afb2
NC		 7752017-01-20 Nick Clifton <nickc@redhat.com>
776
777 * po/ga.po: Updated Irish translation.
778
c13a63b0
SN		 7792017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
780
781 * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
782
9608051a
YQ		 7832017-01-13 Yao Qi <yao.qi@linaro.org>
784
785 * m68k-dis.c (match_insn_m68k): Extend comments. Return -1
786 if FETCH_DATA returns 0.
787 (m68k_scan_mask): Likewise.
788 (print_insn_m68k): Update code to handle -1 return value.
789
f622ea96
YQ		 7902017-01-13 Yao Qi <yao.qi@linaro.org>
791
792 * m68k-dis.c (enum print_insn_arg_error): New.
793 (NEXTBYTE): Replace -3 with
794 PRINT_INSN_ARG_MEMORY_ERROR.
795 (NEXTULONG): Likewise.
796 (NEXTSINGLE): Likewise.
797 (NEXTDOUBLE): Likewise.
798 (NEXTDOUBLE): Likewise.
799 (NEXTPACKED): Likewise.
800 (FETCH_ARG): Likewise.
801 (FETCH_DATA): Update comments.
802 (print_insn_arg): Update comments. Replace magic numbers with
803 enum.
804 (match_insn_m68k): Likewise.
805
620214f7
IT		 8062017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
807
808 * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
809 * i386-dis-evex.h (evex_table): Updated.
810 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
811 CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
812 (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
813 * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
814 (i386_cpu_flags): Add cpuavx512_vpopcntdq.
815 * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
816 * i386-init.h: Regenerate.
817 * i386-tbl.h: Ditto.
818
d95014a2
YQ		 8192017-01-12 Yao Qi <yao.qi@linaro.org>
820
821 * msp430-dis.c (msp430_singleoperand): Return -1 if
822 msp430dis_opcode_signed returns false.
823 (msp430_doubleoperand): Likewise.
824 (msp430_branchinstr): Return -1 if
825 msp430dis_opcode_unsigned returns false.
826 (msp430x_calla_instr): Likewise.
827 (print_insn_msp430): Likewise.
828
0ae60c3e
NC		 8292017-01-05 Nick Clifton <nickc@redhat.com>
830
831 PR 20946
832 * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
833 could not be matched.
834 (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
835 NULL.
836
d74d4880
SN		 8372017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
838
839 * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
840 (aarch64_opcode_table): Use RCPC_INSN.
841
cc917fd9
KC		 8422017-01-03 Kito Cheng <kito.cheng@gmail.com>
843
844 * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
845 extension.
846 * riscv-opcodes/all-opcodes: Likewise.
847
b52d3cfc
DP		 8482017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
849
850 * riscv-dis.c (print_insn_args): Add fall through comment.
851
f90c58d5
NC		 8522017-01-03 Nick Clifton <nickc@redhat.com>
853
854 * po/sr.po: New Serbian translation.
855 * configure.ac (ALL_LINGUAS): Add sr.
856 * configure: Regenerate.
857
f47b0d4a
AM		 8582017-01-02 Alan Modra <amodra@gmail.com>
859
860 * epiphany-desc.h: Regenerate.
861 * epiphany-opc.h: Regenerate.
862 * fr30-desc.h: Regenerate.
863 * fr30-opc.h: Regenerate.
864 * frv-desc.h: Regenerate.
865 * frv-opc.h: Regenerate.
866 * ip2k-desc.h: Regenerate.
867 * ip2k-opc.h: Regenerate.
868 * iq2000-desc.h: Regenerate.
869 * iq2000-opc.h: Regenerate.
870 * lm32-desc.h: Regenerate.
871 * lm32-opc.h: Regenerate.
872 * m32c-desc.h: Regenerate.
873 * m32c-opc.h: Regenerate.
874 * m32r-desc.h: Regenerate.
875 * m32r-opc.h: Regenerate.
876 * mep-desc.h: Regenerate.
877 * mep-opc.h: Regenerate.
878 * mt-desc.h: Regenerate.
879 * mt-opc.h: Regenerate.
880 * or1k-desc.h: Regenerate.
881 * or1k-opc.h: Regenerate.
882 * xc16x-desc.h: Regenerate.
883 * xc16x-opc.h: Regenerate.
884 * xstormy16-desc.h: Regenerate.
885 * xstormy16-opc.h: Regenerate.
886
2571583a
AM		 8872017-01-02 Alan Modra <amodra@gmail.com>
888
889 Update year range in copyright notice of all files.
890
5c1ad6b5 891For older changes see ChangeLog-2016
3499769a 892\f
5c1ad6b5 893Copyright (C) 2017 Free Software Foundation, Inc.
3499769a
AM		 894
895Copying and distribution of this file, with or without modification,
896are permitted in any medium without royalty provided the copyright
897notice and this notice are preserved.
898
899Local Variables:
900mode: change-log
901left-margin: 8
902fill-column: 74
903version-control: never
904End:
GDB Binutils - Deliverables
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