ubsan: frv: left shift of negative value
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
b2b1453a
AM
12020-02-01 Alan Modra <amodra@gmail.com>
2
3 * frv-ibld.c: Regenerate.
4
4102be5c
JB
52020-01-31 Jan Beulich <jbeulich@suse.com>
6
7 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
8 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
9 (OP_E_memory): Replace xmm_mdq_mode case label by
10 vex_scalar_w_dq_mode one.
11 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
12
825bd36c
JB
132020-01-31 Jan Beulich <jbeulich@suse.com>
14
15 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
16 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
17 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
18 (intel_operand_size): Drop vex_w_dq_mode case label.
19
c3036ed0
RS
202020-01-31 Richard Sandiford <richard.sandiford@arm.com>
21
22 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
23 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
24
0c115f84
AM
252020-01-30 Alan Modra <amodra@gmail.com>
26
27 * m32c-ibld.c: Regenerate.
28
bd434cc4
JM
292020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
30
31 * bpf-opc.c: Regenerate.
32
aeab2b26
JB
332020-01-30 Jan Beulich <jbeulich@suse.com>
34
35 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
36 (dis386): Use them to replace C2/C3 table entries.
37 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
38 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
39 ones. Use Size64 instead of DefaultSize on Intel64 ones.
40 * i386-tbl.h: Re-generate.
41
62b3f548
JB
422020-01-30 Jan Beulich <jbeulich@suse.com>
43
44 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
45 forms.
46 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
47 DefaultSize.
48 * i386-tbl.h: Re-generate.
49
1bd8ae10
AM
502020-01-30 Alan Modra <amodra@gmail.com>
51
52 * tic4x-dis.c (tic4x_dp): Make unsigned.
53
bc31405e
L
542020-01-27 H.J. Lu <hongjiu.lu@intel.com>
55 Jan Beulich <jbeulich@suse.com>
56
57 PR binutils/25445
58 * i386-dis.c (MOVSXD_Fixup): New function.
59 (movsxd_mode): New enum.
60 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
61 (intel_operand_size): Handle movsxd_mode.
62 (OP_E_register): Likewise.
63 (OP_G): Likewise.
64 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
65 register on movsxd. Add movsxd with 16-bit destination register
66 for AMD64 and Intel64 ISAs.
67 * i386-tbl.h: Regenerated.
68
7568c93b
TC
692020-01-27 Tamar Christina <tamar.christina@arm.com>
70
71 PR 25403
72 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
73 * aarch64-asm-2.c: Regenerate
74 * aarch64-dis-2.c: Likewise.
75 * aarch64-opc-2.c: Likewise.
76
c006a730
JB
772020-01-21 Jan Beulich <jbeulich@suse.com>
78
79 * i386-opc.tbl (sysret): Drop DefaultSize.
80 * i386-tbl.h: Re-generate.
81
c906a69a
JB
822020-01-21 Jan Beulich <jbeulich@suse.com>
83
84 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
85 Dword.
86 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
87 * i386-tbl.h: Re-generate.
88
26916852
NC
892020-01-20 Nick Clifton <nickc@redhat.com>
90
91 * po/de.po: Updated German translation.
92 * po/pt_BR.po: Updated Brazilian Portuguese translation.
93 * po/uk.po: Updated Ukranian translation.
94
4d6cbb64
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952020-01-20 Alan Modra <amodra@gmail.com>
96
97 * hppa-dis.c (fput_const): Remove useless cast.
98
2bddb71a
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992020-01-20 Alan Modra <amodra@gmail.com>
100
101 * arm-dis.c (print_insn_arm): Wrap 'T' value.
102
1b1bb2c6
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1032020-01-18 Nick Clifton <nickc@redhat.com>
104
105 * configure: Regenerate.
106 * po/opcodes.pot: Regenerate.
107
ae774686
NC
1082020-01-18 Nick Clifton <nickc@redhat.com>
109
110 Binutils 2.34 branch created.
111
07f1f3aa
CB
1122020-01-17 Christian Biesinger <cbiesinger@google.com>
113
114 * opintl.h: Fix spelling error (seperate).
115
42e04b36
L
1162020-01-17 H.J. Lu <hongjiu.lu@intel.com>
117
118 * i386-opc.tbl: Add {vex} pseudo prefix.
119 * i386-tbl.h: Regenerated.
120
2da2eaf4
AV
1212020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
122
123 PR 25376
124 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
125 (neon_opcodes): Likewise.
126 (select_arm_features): Make sure we enable MVE bits when selecting
127 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
128 any architecture.
129
d0849eed
JB
1302020-01-16 Jan Beulich <jbeulich@suse.com>
131
132 * i386-opc.tbl: Drop stale comment from XOP section.
133
9cf70a44
JB
1342020-01-16 Jan Beulich <jbeulich@suse.com>
135
136 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
137 (extractps): Add VexWIG to SSE2AVX forms.
138 * i386-tbl.h: Re-generate.
139
4814632e
JB
1402020-01-16 Jan Beulich <jbeulich@suse.com>
141
142 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
143 Size64 from and use VexW1 on SSE2AVX forms.
144 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
145 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
146 * i386-tbl.h: Re-generate.
147
aad09917
AM
1482020-01-15 Alan Modra <amodra@gmail.com>
149
150 * tic4x-dis.c (tic4x_version): Make unsigned long.
151 (optab, optab_special, registernames): New file scope vars.
152 (tic4x_print_register): Set up registernames rather than
153 malloc'd registertable.
154 (tic4x_disassemble): Delete optable and optable_special. Use
155 optab and optab_special instead. Throw away old optab,
156 optab_special and registernames when info->mach changes.
157
7a6bf3be
SB
1582020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
159
160 PR 25377
161 * z80-dis.c (suffix): Use .db instruction to generate double
162 prefix.
163
ca1eaac0
AM
1642020-01-14 Alan Modra <amodra@gmail.com>
165
166 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
167 values to unsigned before shifting.
168
1d67fe3b
TT
1692020-01-13 Thomas Troeger <tstroege@gmx.de>
170
171 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
172 flow instructions.
173 (print_insn_thumb16, print_insn_thumb32): Likewise.
174 (print_insn): Initialize the insn info.
175 * i386-dis.c (print_insn): Initialize the insn info fields, and
176 detect jumps.
177
5e4f7e05
CZ
1782012-01-13 Claudiu Zissulescu <claziss@gmail.com>
179
180 * arc-opc.c (C_NE): Make it required.
181
b9fe6b8a
CZ
1822012-01-13 Claudiu Zissulescu <claziss@gmail.com>
183
184 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
185 reserved register name.
186
90dee485
AM
1872020-01-13 Alan Modra <amodra@gmail.com>
188
189 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
190 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
191
febda64f
AM
1922020-01-13 Alan Modra <amodra@gmail.com>
193
194 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
195 result of wasm_read_leb128 in a uint64_t and check that bits
196 are not lost when copying to other locals. Use uint32_t for
197 most locals. Use PRId64 when printing int64_t.
198
df08b588
AM
1992020-01-13 Alan Modra <amodra@gmail.com>
200
201 * score-dis.c: Formatting.
202 * score7-dis.c: Formatting.
203
b2c759ce
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2042020-01-13 Alan Modra <amodra@gmail.com>
205
206 * score-dis.c (print_insn_score48): Use unsigned variables for
207 unsigned values. Don't left shift negative values.
208 (print_insn_score32): Likewise.
209 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
210
5496abe1
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2112020-01-13 Alan Modra <amodra@gmail.com>
212
213 * tic4x-dis.c (tic4x_print_register): Remove dead code.
214
202e762b
AM
2152020-01-13 Alan Modra <amodra@gmail.com>
216
217 * fr30-ibld.c: Regenerate.
218
7ef412cf
AM
2192020-01-13 Alan Modra <amodra@gmail.com>
220
221 * xgate-dis.c (print_insn): Don't left shift signed value.
222 (ripBits): Formatting, use 1u.
223
7f578b95
AM
2242020-01-10 Alan Modra <amodra@gmail.com>
225
226 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
227 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
228
441af85b
AM
2292020-01-10 Alan Modra <amodra@gmail.com>
230
231 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
232 and XRREG value earlier to avoid a shift with negative exponent.
233 * m10200-dis.c (disassemble): Similarly.
234
bce58db4
NC
2352020-01-09 Nick Clifton <nickc@redhat.com>
236
237 PR 25224
238 * z80-dis.c (ld_ii_ii): Use correct cast.
239
40c75bc8
SB
2402020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
241
242 PR 25224
243 * z80-dis.c (ld_ii_ii): Use character constant when checking
244 opcode byte value.
245
d835a58b
JB
2462020-01-09 Jan Beulich <jbeulich@suse.com>
247
248 * i386-dis.c (SEP_Fixup): New.
249 (SEP): Define.
250 (dis386_twobyte): Use it for sysenter/sysexit.
251 (enum x86_64_isa): Change amd64 enumerator to value 1.
252 (OP_J): Compare isa64 against intel64 instead of amd64.
253 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
254 forms.
255 * i386-tbl.h: Re-generate.
256
030a2e78
AM
2572020-01-08 Alan Modra <amodra@gmail.com>
258
259 * z8k-dis.c: Include libiberty.h
260 (instr_data_s): Make max_fetched unsigned.
261 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
262 Don't exceed byte_info bounds.
263 (output_instr): Make num_bytes unsigned.
264 (unpack_instr): Likewise for nibl_count and loop.
265 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
266 idx unsigned.
267 * z8k-opc.h: Regenerate.
268
bb82aefe
SV
2692020-01-07 Shahab Vahedi <shahab@synopsys.com>
270
271 * arc-tbl.h (llock): Use 'LLOCK' as class.
272 (llockd): Likewise.
273 (scond): Use 'SCOND' as class.
274 (scondd): Likewise.
275 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
276 (scondd): Likewise.
277
cc6aa1a6
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2782020-01-06 Alan Modra <amodra@gmail.com>
279
280 * m32c-ibld.c: Regenerate.
281
660e62b1
AM
2822020-01-06 Alan Modra <amodra@gmail.com>
283
284 PR 25344
285 * z80-dis.c (suffix): Don't use a local struct buffer copy.
286 Peek at next byte to prevent recursion on repeated prefix bytes.
287 Ensure uninitialised "mybuf" is not accessed.
288 (print_insn_z80): Don't zero n_fetch and n_used here,..
289 (print_insn_z80_buf): ..do it here instead.
290
c9ae58fe
AM
2912020-01-04 Alan Modra <amodra@gmail.com>
292
293 * m32r-ibld.c: Regenerate.
294
5f57d4ec
AM
2952020-01-04 Alan Modra <amodra@gmail.com>
296
297 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
298
2c5c1196
AM
2992020-01-04 Alan Modra <amodra@gmail.com>
300
301 * crx-dis.c (match_opcode): Avoid shift left of signed value.
302
2e98c6c5
AM
3032020-01-04 Alan Modra <amodra@gmail.com>
304
305 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
306
567dfba2
JB
3072020-01-03 Jan Beulich <jbeulich@suse.com>
308
5437a02a
JB
309 * aarch64-tbl.h (aarch64_opcode_table): Use
310 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
311
3122020-01-03 Jan Beulich <jbeulich@suse.com>
313
314 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
567dfba2
JB
315 forms of SUDOT and USDOT.
316
8c45011a
JB
3172020-01-03 Jan Beulich <jbeulich@suse.com>
318
5437a02a 319 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
8c45011a
JB
320 uzip{1,2}.
321 * opcodes/aarch64-dis-2.c: Re-generate.
322
f4950f76
JB
3232020-01-03 Jan Beulich <jbeulich@suse.com>
324
5437a02a 325 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
f4950f76
JB
326 FMMLA encoding.
327 * opcodes/aarch64-dis-2.c: Re-generate.
328
6655dba2
SB
3292020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
330
331 * z80-dis.c: Add support for eZ80 and Z80 instructions.
332
b14ce8bf
AM
3332020-01-01 Alan Modra <amodra@gmail.com>
334
335 Update year range in copyright notice of all files.
336
0b114740 337For older changes see ChangeLog-2019
3499769a 338\f
0b114740 339Copyright (C) 2020 Free Software Foundation, Inc.
3499769a
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340
341Copying and distribution of this file, with or without modification,
342are permitted in any medium without royalty provided the copyright
343notice and this notice are preserved.
344
345Local Variables:
346mode: change-log
347left-margin: 8
348fill-column: 74
349version-control: never
350End:
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