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* gstdint.h: New file.
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
6ba2a415
RS		 12008-06-30 Richard Sandiford <rdsandiford@googlemail.com>
2
3 * mips-dis.c (_print_insn_mips): Use bfd_asymbol_flavour to check
4 for ELF symbols.
5
c8187e15
PB		 62008-06-25 Peter Bergner <bergner@vnet.ibm.com>
7
8 * ppc-dis.c (powerpc_init_dialect): Handle -M464.
9 (print_ppc_disassembler_options): Likewise.
10 * ppc-opc.c (PPC464): Define.
11 (powerpc_opcodes): Add mfdcrux and mtdcrux.
12
7a283e07
RW		 132008-06-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
14
15 * configure: Regenerate.
16
fa452fa6
PB		 172008-06-13 Peter Bergner <bergner@vnet.ibm.com>
18
19 * ppc-dis.c (print_insn_powerpc): Update prototye to use new
20 ppc_cpu_t typedef.
21 (struct dis_private): New.
22 (POWERPC_DIALECT): New define.
23 (powerpc_dialect): Renamed to...
24 (powerpc_init_dialect): This. Update to use ppc_cpu_t and
25 struct dis_private.
26 (print_insn_big_powerpc): Update for using structure in
27 info->private_data.
28 (print_insn_little_powerpc): Likewise.
29 (operand_value_powerpc): Change type of dialect param to ppc_cpu_t.
30 (skip_optional_operands): Likewise.
31 (print_insn_powerpc): Likewise. Remove initialization of dialect.
32 * ppc-opc.c (extract_bat, extract_bba, extract_bdm, extract_bdp,
33 extract_bo, extract_boe, extract_fxm, extract_mb6, extract_mbe,
34 extract_nb, extract_nsi, extract_rbs, extract_sh6, extract_spr,
35 extract_sprg, extract_tbr insert_bat, insert_bba, insert_bdm,
36 insert_bdp, insert_bo, insert_boe, insert_fxm, insert_mb6, insert_mbe,
37 insert_nsi, insert_ral, insert_ram, insert_raq, insert_ras, insert_rbs,
38 insert_sh6, insert_spr, insert_sprg, insert_tbr): Change the dialect
39 param to be of type ppc_cpu_t. Update prototype.
40
bb35fb24
NC		 412008-06-12 Adam Nemet <anemet@caviumnetworks.com>
42
43 * mips-dis.c (print_insn_args): Handle field descriptors +x, +p,
44 +s, +S.
45 * mips-opc.c (mips_builtin_opcodes): Add Octeon instructions
46 baddu, bbit*, cins*, dmul, pop, dpop, exts*, mtm*, mtp*, syncs,
47 syncw, syncws, vm3mulu, vm0 and vmulu.
48
dd3cbb7e
NC		 49 * mips-dis.c (print_insn_args): Handle field descriptor +Q.
50 * mips-opc.c (mips_builtin_opcodes): Add Octeon instructions seq,
51 seqi, sne and snei.
52
a5dabbb0
L		 532008-05-30 H.J. Lu <hongjiu.lu@intel.com>
54
55 * i386-opc.tbl: Add vmovd with 64bit operand.
56 * i386-tbl.h: Regenerated.
57
725a9891
MS		 582008-05-27 Martin Schwidefsky <schwidefsky@de.ibm.com>
59
60 * s390-opc.c (INSTR_RRF_R0RR): Fix RRF_R0RR operand format.
61
cbc80391
L		 622008-05-22 H.J. Lu <hongjiu.lu@intel.com>
63
64 * i386-opc.tbl: Add NoAVX to cvtpd2pi, cvtpi2pd and cvttpd2pi.
65 * i386-tbl.h: Regenerated.
66
116615c5
L		 672008-05-22 H.J. Lu <hongjiu.lu@intel.com>
68
69 PR gas/6517
70 * i386-opc.tbl: Break cvtsi2ss/cvtsi2sd/vcvtsi2sd/vcvtsi2ss
71 into 32bit and 64bit. Remove Reg64|Qword and add
72 IgnoreSize|No_qSuf on 32bit version.
73 * i386-tbl.h: Regenerated.
74
d9479f2d
L		 752008-05-21 H.J. Lu <hongjiu.lu@intel.com>
76
77 * i386-opc.tbl: Add NoAVX to movdq2q and movq2dq.
78 * i386-tbl.h: Regenerated.
79
3ce6fddb
NC		 802008-05-21 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
81
82 * cr16-dis.c (build_mask): Adjust the mask for 32-bit bcond.
83
8944f3c2
AM		 842008-05-14 Alan Modra <amodra@bigpond.net.au>
85
86 * Makefile.am: Run "make dep-am".
87 * Makefile.in: Regenerate.
88
f1f8f695
L		 892008-05-02 H.J. Lu <hongjiu.lu@intel.com>
90
91 * i386-dis.c (MOVBE_Fixup): New.
92 (Mo): Likewise.
93 (PREFIX_0F3880): Likewise.
94 (PREFIX_0F3881): Likewise.
95 (PREFIX_0F38F0): Updated.
96 (prefix_table): Add PREFIX_0F3880 and PREFIX_0F3881. Update
97 PREFIX_0F38F0 and PREFIX_0F38F1 for movbe.
98 (three_byte_table): Use PREFIX_0F3880 and PREFIX_0F3881.
99
100 * i386-gen.c (cpu_flag_init): Add CPU_MOVBE_FLAGS and
101 CPU_EPT_FLAGS.
102 (cpu_flags): Add CpuMovbe and CpuEPT.
103
104 * i386-opc.h (CpuMovbe): New.
105 (CpuEPT): Likewise.
106 (CpuLM): Updated.
107 (i386_cpu_flags): Add cpumovbe and cpuept.
108
109 * i386-opc.tbl: Add entries for movbe and EPT instructions.
110 * i386-init.h: Regenerated.
111 * i386-tbl.h: Likewise.
112
89aa3097
AN		 1132008-04-29 Adam Nemet <anemet@caviumnetworks.com>
114
115 * mips-opc.c (mips_builtin_opcodes): Set field `match' to 0 for
116 the two drem and the two dremu macros.
117
39c5c168
AN		 1182008-04-28 Adam Nemet <anemet@caviumnetworks.com>
119
120 * mips-opc.c (mips_builtin_opcodes): Mark prefx and c1
121 instructions FP_S. Mark l.s, li.s, lwc1, swc1, s.s, trunc.w.s and
122 cop1 macros INSN2_M_FP_S. Mark l.d, li.d, ldc1 and sdc1 macros
123 INSN2_M_FP_D. Mark trunc.w.d macro INSN2_M_FP_S and INSN2_M_FP_D.
124
f04d18b7
DM		 1252008-04-25 David S. Miller <davem@davemloft.net>
126
127 * sparc-dis.c: Emit %stick instead of %sys_tick, and %stick_cmpr
128 instead of %sys_tick_cmpr, as suggested in architecture manuals.
129
6194aaab
L		 1302008-04-23 Paolo Bonzini <bonzini@gnu.org>
131
132 * aclocal.m4: Regenerate.
133 * configure: Regenerate.
134
1a6b486f
DM		 1352008-04-23 David S. Miller <davem@davemloft.net>
136
137 * sparc-opc.c (asi_table): Add UltraSPARC and Niagara
138 extended values.
139 (prefetch_table): Add missing values.
140
81f8a913
L		 1412008-04-22 H.J. Lu <hongjiu.lu@intel.com>
142
143 * i386-gen.c (opcode_modifiers): Add NoAVX.
144
145 * i386-opc.h (NoAVX): New.
146 (OldGcc): Updated.
147 (i386_opcode_modifier): Add noavx.
148
149 * i386-opc.tbl: Add NoAVX to SSE, SSE2, SSE3 and SSSE3
150 instructions which don't have AVX equivalent.
151 * i386-tbl.h: Regenerated.
152
dae39acc
L		 1532008-04-18 H.J. Lu <hongjiu.lu@intel.com>
154
155 * i386-dis.c (OP_VEX_FMA): New.
156 (OP_EX_VexImmW): Likewise.
157 (VexFMA): Likewise.
158 (Vex128FMA): Likewise.
159 (EXVexImmW): Likewise.
160 (get_vex_imm8): Likewise.
161 (OP_EX_VexReg): Likewise.
162 (vex_i4_done): Renamed to ...
163 (vex_w_done): This.
164 (prefix_table): Replace EXVexW with EXVexImmW on vpermil2ps
165 and vpermil2pd. Replace Vex/Vex128 with VexFMA/Vex128FMA on
166 FMA instructions.
167 (print_insn): Updated.
168 (OP_EX_VexW): Rewrite to swap register in VEX with EX.
169 (OP_REG_VexI4): Check invalid high registers.
170
ce886ab1
DR		 1712008-04-16 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
172 Michael Meissner <michael.meissner@amd.com>
173
174 * i386-opc.tbl: Fix protX to allow memory in the middle operand.
175 * i386-tbl.h: Regenerate from i386-opc.tbl.
8944f3c2 176
19a6653c
AM		 1772008-04-14 Edmar Wienskoski <edmar@freescale.com>
178
179 * ppc-dis.c (powerpc_dialect): Handle "e500mc". Extend "e500" to
180 accept Power E500MC instructions.
181 (print_ppc_disassembler_options): Document -Me500mc.
182 * ppc-opc.c (DUIS, DUI, T): New.
183 (XRT, XRTRA): Likewise.
184 (E500MC): Likewise.
185 (powerpc_opcodes): Add new Power E500MC instructions.
186
112b7c50
AK		 1872008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
188
189 * s390-dis.c (init_disasm): Evaluate disassembler_options.
190 (print_s390_disassembler_options): New function.
191 * disassemble.c (disassembler_usage): Invoke
192 print_s390_disassembler_options.
193
7ff42648
AK		 1942008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
195
196 * s390-mkopc.c (insertExpandedMnemonic): Expand string sizes
197 of local variables used for mnemonic parsing: prefix, suffix and
198 number.
199
45a5551e
AK		 2002008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
201
202 * s390-mkopc.c (s390_cond_ext_format): Add back the mnemonic
203 extensions for conditional jumps (o, p, m, nz, z, nm, np, no).
204 (s390_crb_extensions): New extensions table.
205 (insertExpandedMnemonic): Handle '$' tag.
206 * s390-opc.txt: Remove conditional jump variants which can now
207 be expanded automatically.
208 Replace '*' tag with '$' in the compare and branch instructions.
209
06c8514a
L		 2102008-04-07 H.J. Lu <hongjiu.lu@intel.com>
211
212 * i386-dis.c (PREFIX_VEX_38XX): Add a tab.
213 (PREFIX_VEX_3AXX): Likewis.
214
b122c285
L		 2152008-04-07 H.J. Lu <hongjiu.lu@intel.com>
216
217 * i386-opc.tbl: Remove 4 extra blank lines.
218
594ab6a3
L		 2192008-04-04 H.J. Lu <hongjiu.lu@intel.com>
220
221 * i386-gen.c (cpu_flag_init): Replace CPU_CLMUL_FLAGS/CpuCLMUL
222 with CPU_PCLMUL_FLAGS/CpuPCLMUL.
223 (cpu_flags): Replace CpuCLMUL with CpuPCLMUL.
224 * i386-opc.tbl: Likewise.
225
226 * i386-opc.h (CpuCLMUL): Renamed to ...
227 (CpuPCLMUL): This.
228 (CpuFMA): Updated.
229 (i386_cpu_flags): Replace cpuclmul with cpupclmul.
230
231 * i386-init.h: Regenerated.
232
c0f3af97
L		 2332008-04-03 H.J. Lu <hongjiu.lu@intel.com>
234
235 * i386-dis.c (OP_E_register): New.
236 (OP_E_memory): Likewise.
237 (OP_VEX): Likewise.
238 (OP_EX_Vex): Likewise.
239 (OP_EX_VexW): Likewise.
240 (OP_XMM_Vex): Likewise.
241 (OP_XMM_VexW): Likewise.
242 (OP_REG_VexI4): Likewise.
243 (PCLMUL_Fixup): Likewise.
244 (VEXI4_Fixup): Likewise.
245 (VZERO_Fixup): Likewise.
246 (VCMP_Fixup): Likewise.
247 (VPERMIL2_Fixup): Likewise.
248 (rex_original): Likewise.
249 (rex_ignored): Likewise.
250 (Mxmm): Likewise.
251 (XMM): Likewise.
252 (EXxmm): Likewise.
253 (EXxmmq): Likewise.
254 (EXymmq): Likewise.
255 (Vex): Likewise.
256 (Vex128): Likewise.
257 (Vex256): Likewise.
258 (VexI4): Likewise.
259 (EXdVex): Likewise.
260 (EXqVex): Likewise.
261 (EXVexW): Likewise.
262 (EXdVexW): Likewise.
263 (EXqVexW): Likewise.
264 (XMVex): Likewise.
265 (XMVexW): Likewise.
266 (XMVexI4): Likewise.
267 (PCLMUL): Likewise.
268 (VZERO): Likewise.
269 (VCMP): Likewise.
270 (VPERMIL2): Likewise.
271 (xmm_mode): Likewise.
272 (xmmq_mode): Likewise.
273 (ymmq_mode): Likewise.
274 (vex_mode): Likewise.
275 (vex128_mode): Likewise.
276 (vex256_mode): Likewise.
277 (USE_VEX_C4_TABLE): Likewise.
278 (USE_VEX_C5_TABLE): Likewise.
279 (USE_VEX_LEN_TABLE): Likewise.
280 (VEX_C4_TABLE): Likewise.
281 (VEX_C5_TABLE): Likewise.
282 (VEX_LEN_TABLE): Likewise.
283 (REG_VEX_XX): Likewise.
284 (MOD_VEX_XXX): Likewise.
285 (PREFIX_0F38DB..PREFIX_0F38DF): Likewise.
286 (PREFIX_0F3A44): Likewise.
287 (PREFIX_0F3ADF): Likewise.
288 (PREFIX_VEX_XXX): Likewise.
289 (VEX_OF): Likewise.
290 (VEX_OF38): Likewise.
291 (VEX_OF3A): Likewise.
292 (VEX_LEN_XXX): Likewise.
293 (vex): Likewise.
294 (need_vex): Likewise.
295 (need_vex_reg): Likewise.
296 (vex_i4_done): Likewise.
297 (vex_table): Likewise.
298 (vex_len_table): Likewise.
299 (OP_REG_VexI4): Likewise.
300 (vex_cmp_op): Likewise.
301 (pclmul_op): Likewise.
302 (vpermil2_op): Likewise.
303 (m_mode): Updated.
304 (es_reg): Likewise.
305 (PREFIX_0F38F0): Likewise.
306 (PREFIX_0F3A60): Likewise.
307 (reg_table): Add REG_VEX_71...REG_VEX_73 and REG_VEX_AE.
308 (prefix_table): Add PREFIX_0F38DB..PREFIX_0F38DF, PREFIX_0F3ADF
309 and PREFIX_VEX_XXX entries.
310 (x86_64_table): Use VEX_C4_TABLE and VEX_C5_TABLE.
311 (three_byte_table): Use PREFIX_0F38DB..PREFIX_0F38DF and
312 PREFIX_0F3ADF.
313 (mod_table): Use VEX_C4_TABLE, VEX_C5_TABLE and VEX_LEN_TABLE.
314 Add MOD_VEX_XXX entries.
315 (ckprefix): Initialize rex_original and rex_ignored. Store the
316 REX byte in rex_original.
317 (get_valid_dis386): Handle the implicit prefix in VEX prefix
318 bytes and USE_VEX_LEN_TABLE/USE_VEX_C4_TABLE/USE_VEX_C5_TABLE.
319 (print_insn): Set need_vex/need_vex_reg/vex_i4_done to 0 before
320 calling get_valid_dis386. Use rex_original and rex_ignored when
321 printing out REX.
322 (putop): Handle "XY".
323 (intel_operand_size): Handle VEX, xmm_mode, xmmq_mode and
324 ymmq_mode.
325 (OP_E_extended): Updated to use OP_E_register and
326 OP_E_memory.
327 (OP_XMM): Handle VEX.
328 (OP_EX): Likewise.
329 (XMM_Fixup): Likewise.
330 (CMP_Fixup): Use ARRAY_SIZE.
331
332 * i386-gen.c (cpu_flag_init): Add CpuAES, CPU_CLMUL_FLAGS,
333 CPU_FMA_FLAGS and CPU_AVX_FLAGS.
334 (operand_type_init): Add OPERAND_TYPE_REGYMM and
335 OPERAND_TYPE_VEX_IMM4.
336 (cpu_flags): Add CpuAVX, CpuAES, CpuCLMUL and CpuFMA.
337 (opcode_modifiers): Add Implicit1stXmm0, Vex, Vex256, VexNDD,
338 VexNDS, VexW0, VexW1, Vex0F, Vex0F38, Vex0F3A, Vex3Sources,
339 VexImmExt and SSE2AVX.
340 (operand_types): Add RegYMM, Ymmword and Vex_Imm4.
341
342 * i386-opc.h (CpuAVX): New.
343 (CpuAES): Likewise.
344 (CpuCLMUL): Likewise.
345 (CpuFMA): Likewise.
346 (Vex): Likewise.
347 (Vex256): Likewise.
348 (VexNDS): Likewise.
349 (VexNDD): Likewise.
350 (VexW0): Likewise.
351 (VexW1): Likewise.
352 (Vex0F): Likewise.
353 (Vex0F38): Likewise.
354 (Vex0F3A): Likewise.
355 (Vex3Sources): Likewise.
356 (VexImmExt): Likewise.
357 (SSE2AVX): Likewise.
358 (RegYMM): Likewise.
359 (Ymmword): Likewise.
360 (Vex_Imm4): Likewise.
361 (Implicit1stXmm0): Likewise.
362 (CpuXsave): Updated.
363 (CpuLM): Likewise.
364 (ByteOkIntel): Likewise.
365 (OldGcc): Likewise.
366 (Control): Likewise.
367 (Unspecified): Likewise.
368 (OTMax): Likewise.
369 (i386_cpu_flags): Add cpuavx, cpuaes, cpuclmul and cpufma.
370 (i386_opcode_modifier): Add implicit1stxmm0, vex, vex256,
371 vexnds, vexndd, vexw0, vexw1, vex0f, vex0f38, vex0f3a,
372 vex3sources, veximmext and sse2avx.
373 (i386_operand_type): Add regymm, ymmword and vex_imm4.
374
375 * i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions.
376
377 * i386-reg.tbl: Add AVX registers, ymm0..ymm15.
378
379 * i386-init.h: Regenerated.
380 * i386-tbl.h: Likewise.
381
b21c9cb4
BS		 3822008-03-26 Bernd Schmidt <bernd.schmidt@analog.com>
383
384 From Robin Getz <robin.getz@analog.com>
385 * bfin-dis.c (bu32): Typedef.
386 (enum const_forms_t): Add c_uimm32 and c_huimm32.
387 (constant_formats[]): Add uimm32 and huimm16.
388 (fmtconst_val): New.
389 (uimm32): Define.
390 (huimm32): Define.
391 (imm16_val): Define.
392 (luimm16_val): Define.
393 (struct saved_state): Define.
394 (GREG, DPREG, DREG, PREG, SPREG, FPREG, IREG, MREG, BREG, LREG,
395 A0XREG, A0WREG, A1XREG, A1WREG,CCREG, LC0REG, LT0REG, LB0REG,
396 LC1REG, LT1REG, LB1REG, RETSREG, PCREG): Define.
397 (get_allreg): New.
398 (decode_LDIMMhalf_0): Print out the whole register value.
399
ee171c8f
BS		 400 From Jie Zhang <jie.zhang@analog.com>
401 * bfin-dis.c (decode_dsp32mac_0): Decode (IU) option for
402 multiply and multiply-accumulate to data register instruction.
403
086134ec
BS		 404 * bfin-dis.c: (c_uimm4s4d, c_imm5d, c_imm7d, c_imm16d, c_uimm16s4d,
405 c_imm32, c_huimm32e): Define.
406 (constant_formats): Add flags for printing decimal, leading spaces, and
407 exact symbols.
408 (comment, parallel): Add global flags in all disassembly.
409 (fmtconst): Take advantage of new flags, and print default in hex.
410 (fmtconst_val): Likewise.
411 (decode_macfunc): Be consistant with spaces, tabs, comments,
412 capitalization in disassembly, fix minor coding style issues.
413 (reg_names, amod0, amod1, amod0amod2, aligndir, get_allreg): Likewise.
414 (decode_ProgCtrl_0, decode_PushPopMultiple_0, decode_CCflag_0,
415 decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0,
416 decode_REGMV_0, decode_ALU2op_0, decode_PTR2op_0, decode_LOGI2op_0,
417 decode_COMP3op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
418 decode_LDSTpmod_0, decode_dagMODim_0, decode_dagMODik_0,
419 decode_dspLDST_0, decode_LDST_0, decode_LDSTiiFP_0, decode_LDSTii_0,
420 decode_LoopSetup_0, decode_LDIMMhalf_0, decode_CALLa_0,
421 decode_LDSTidxI_0, decode_linkage_0, decode_dsp32alu_0,
422 decode_dsp32shift_0, decode_dsp32shiftimm_0, decode_pseudodbg_assert_0,
423 _print_insn_bfin, print_insn_bfin): Likewise.
424
58c85be7
RW		 4252008-03-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
426
427 * aclocal.m4: Regenerate.
428 * configure: Likewise.
429 * Makefile.in: Likewise.
430
50e7d84b
AM		 4312008-03-13 Alan Modra <amodra@bigpond.net.au>
432
433 * Makefile.am: Run "make dep-am".
434 * Makefile.in: Regenerate.
435 * configure: Regenerate.
436
de866fcc
AM		 4372008-03-07 Alan Modra <amodra@bigpond.net.au>
438
439 * ppc-opc.c (powerpc_opcodes): Order and format.
440
28dbc079
L		 4412008-03-01 H.J. Lu <hongjiu.lu@intel.com>
442
443 * i386-opc.tbl: Allow 16-bit near indirect branches for x86-64.
444 * i386-tbl.h: Regenerated.
445
849830bd
L		 4462008-02-23 H.J. Lu <hongjiu.lu@intel.com>
447
448 * i386-opc.tbl: Disallow 16-bit near indirect branches for
449 x86-64.
450 * i386-tbl.h: Regenerated.
451
743ddb6b
JB		 4522008-02-21 Jan Beulich <jbeulich@novell.com>
453
454 * i386-opc.tbl: Allow Dword for far indirect call. Allow Dword
455 and Fword for far indirect jmp. Allow Reg16 and Word for near
456 indirect jmp on x86-64. Disallow Fword for lcall.
457 * i386-tbl.h: Re-generate.
458
796d5313
NC		 4592008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
460
461 * cr16-opc.c (cr16_num_optab): Defined
462
65da13b5
L		 4632008-02-16 H.J. Lu <hongjiu.lu@intel.com>
464
465 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_INOUTPORTREG.
466 * i386-init.h: Regenerated.
467
0e336180
NC		 4682008-02-14 Nick Clifton <nickc@redhat.com>
469
470 PR binutils/5524
471 * configure.in (SHARED_LIBADD): Select the correct host specific
472 file extension for shared libraries.
473 * configure: Regenerate.
474
b7240065
JB		 4752008-02-13 Jan Beulich <jbeulich@novell.com>
476
477 * i386-opc.h (RegFlat): New.
478 * i386-reg.tbl (flat): Add.
479 * i386-tbl.h: Re-generate.
480
34b772a6
JB		 4812008-02-13 Jan Beulich <jbeulich@novell.com>
482
483 * i386-dis.c (a_mode): New.
484 (cond_jump_mode): Adjust.
485 (Ma): Change to a_mode.
486 (intel_operand_size): Handle a_mode.
487 * i386-opc.tbl: Allow Dword and Qword for bound.
488 * i386-tbl.h: Re-generate.
489
a60de03c
JB		 4902008-02-13 Jan Beulich <jbeulich@novell.com>
491
492 * i386-gen.c (process_i386_registers): Process new fields.
493 * i386-opc.h (reg_entry): Shrink reg_flags and reg_num to
494 unsigned char. Add dw2_regnum and Dw2Inval.
495 * i386-reg.tbl: Provide initializers for dw2_regnum. Add pseudo
496 register names.
497 * i386-tbl.h: Re-generate.
498
f03fe4c1
L		 4992008-02-11 H.J. Lu <hongjiu.lu@intel.com>
500
4b6bc8eb 501 * i386-gen.c (cpu_flag_init): Add CPU_XSAVE_FLAGS.
f03fe4c1
L		 502 * i386-init.h: Updated.
503
475a2301
L		 5042008-02-11 H.J. Lu <hongjiu.lu@intel.com>
505
506 * i386-gen.c (cpu_flags): Add CpuXsave.
507
508 * i386-opc.h (CpuXsave): New.
4b6bc8eb 509 (CpuLM): Updated.
475a2301
L		 510 (i386_cpu_flags): Add cpuxsave.
511
512 * i386-dis.c (MOD_0FAE_REG_4): New.
513 (RM_0F01_REG_2): Likewise.
514 (MOD_0FAE_REG_5): Updated.
515 (RM_0F01_REG_3): Likewise.
516 (reg_table): Use MOD_0FAE_REG_4.
517 (mod_table): Use RM_0F01_REG_2. Add MOD_0FAE_REG_4. Updated
518 for xrstor.
519 (rm_table): Add RM_0F01_REG_2.
520
521 * i386-opc.tbl: Add xsave, xrstor, xgetbv and xsetbv.
522 * i386-init.h: Regenerated.
523 * i386-tbl.h: Likewise.
524
595785c6 5252008-02-11 Jan Beulich <jbeulich@novell.com>
041179fc 526
595785c6
JB		 527 * i386-opc.tbl: Remove Disp32S from CpuNo64 opcodes. Remove
528 Disp16 from Cpu64 non-jump opcodes (including loop and j?cxz).
529 * i386-tbl.h: Re-generate.
530
bb8541b9
L		 5312008-02-04 H.J. Lu <hongjiu.lu@intel.com>
532
533 PR 5715
534 * configure: Regenerated.
535
57b592a3
AN		 5362008-02-04 Adam Nemet <anemet@caviumnetworks.com>
537
538 * mips-dis.c: Update copyright.
539 (mips_arch_choices): Add Octeon.
540 * mips-opc.c: Update copyright.
541 (IOCT): New macro.
542 (mips_builtin_opcodes): Add Octeon instruction synciobdma.
543
930bb4cf
AM		 5442008-01-29 Alan Modra <amodra@bigpond.net.au>
545
546 * ppc-opc.c: Support optional L form mtmsr.
547
82c18208
L		 5482008-01-24 H.J. Lu <hongjiu.lu@intel.com>
549
550 * i386-dis.c (OP_E_extended): Handle r12 like rsp.
551
599121aa
L		 5522008-01-23 H.J. Lu <hongjiu.lu@intel.com>
553
554 * i386-gen.c (cpu_flag_init): Add CpuLM to CPU_GENERIC64_FLAGS.
555 * i386-init.h: Regenerated.
556
80098f51
TG		 5572008-01-23 Tristan Gingold <gingold@adacore.com>
558
559 * ia64-dis.c (print_insn_ia64): Display symbolic name of ar.fcr,
560 ar.eflag, ar.csd, ar.ssd, ar.cflg, ar.fsr, ar.fir and ar.fdr.
561
115c7c25
L		 5622008-01-22 H.J. Lu <hongjiu.lu@intel.com>
563
564 * i386-gen.c (cpu_flag_init): Remove CpuMMX2.
565 (cpu_flags): Likewise.
566
567 * i386-opc.h (CpuMMX2): Removed.
568 (CpuSSE): Updated.
569
570 * i386-opc.tbl: Replace CpuMMX2 with CpuSSE|Cpu3dnowA.
571 * i386-init.h: Regenerated.
572 * i386-tbl.h: Likewise.
573
6305a203
L		 5742008-01-22 H.J. Lu <hongjiu.lu@intel.com>
575
576 * i386-gen.c (cpu_flag_init): Add CPU_VMX_FLAGS and
577 CPU_SMX_FLAGS.
578 * i386-init.h: Regenerated.
579
fd07a1c8
L		 5802008-01-15 H.J. Lu <hongjiu.lu@intel.com>
581
582 * i386-opc.tbl: Use Qword on movddup.
583 * i386-tbl.h: Regenerated.
584
321fd21e
L		 5852008-01-15 H.J. Lu <hongjiu.lu@intel.com>
586
587 * i386-opc.tbl: Put back 16bit movsx/movzx for AT&T syntax.
588 * i386-tbl.h: Regenerated.
589
4ee52178
L		 5902008-01-15 H.J. Lu <hongjiu.lu@intel.com>
591
592 * i386-dis.c (Mx): New.
593 (PREFIX_0FC3): Likewise.
594 (PREFIX_0FC7_REG_6): Updated.
595 (dis386_twobyte): Use PREFIX_0FC3.
596 (prefix_table): Add PREFIX_0FC3. Use Mq on movntq and movntsd.
597 Use Mx on movntps, movntpd, movntdq and movntdqa. Use Md on
598 movntss.
599
5c07affc
L		 6002008-01-14 H.J. Lu <hongjiu.lu@intel.com>
601
602 * i386-gen.c (opcode_modifiers): Add IntelSyntax.
603 (operand_types): Add Mem.
604
605 * i386-opc.h (IntelSyntax): New.
606 * i386-opc.h (Mem): New.
607 (Byte): Updated.
608 (Opcode_Modifier_Max): Updated.
609 (i386_opcode_modifier): Add intelsyntax.
610 (i386_operand_type): Add mem.
611
612 * i386-opc.tbl: Remove Reg16 from movnti. Add sizes to more
613 instructions.
614
615 * i386-reg.tbl: Add size for accumulator.
616
617 * i386-init.h: Regenerated.
618 * i386-tbl.h: Likewise.
619
0d6a2f58
L		 6202008-01-13 H.J. Lu <hongjiu.lu@intel.com>
621
622 * i386-opc.h (Byte): Fix a typo.
623
7d5e4556
L		 6242008-01-12 H.J. Lu <hongjiu.lu@intel.com>
625
626 PR gas/5534
627 * i386-gen.c (operand_type_init): Add Dword to
628 OPERAND_TYPE_ACC32. Add Qword to OPERAND_TYPE_ACC64.
629 (opcode_modifiers): Remove CheckSize, Byte, Word, Dword,
630 Qword and Xmmword.
631 (operand_types): Add Byte, Word, Dword, Fword, Qword, Tbyte,
632 Xmmword, Unspecified and Anysize.
633 (set_bitfield): Make Mmword an alias of Qword. Make Oword
634 an alias of Xmmword.
635
636 * i386-opc.h (CheckSize): Removed.
637 (Byte): Updated.
638 (Word): Likewise.
639 (Dword): Likewise.
640 (Qword): Likewise.
641 (Xmmword): Likewise.
642 (FWait): Updated.
643 (OTMax): Likewise.
644 (i386_opcode_modifier): Remove checksize, byte, word, dword,
645 qword and xmmword.
646 (Fword): New.
647 (TBYTE): Likewise.
648 (Unspecified): Likewise.
649 (Anysize): Likewise.
650 (i386_operand_type): Add byte, word, dword, fword, qword,
651 tbyte xmmword, unspecified and anysize.
652
653 * i386-opc.tbl: Updated to use Byte, Word, Dword, Fword, Qword,
654 Tbyte, Xmmword, Unspecified and Anysize.
655
656 * i386-reg.tbl: Add size for accumulator.
657
658 * i386-init.h: Regenerated.
659 * i386-tbl.h: Likewise.
660
b5b1fc4f
L		 6612008-01-10 H.J. Lu <hongjiu.lu@intel.com>
662
663 * i386-dis.c (REG_0F0E): Renamed to REG_0F0D.
664 (REG_0F18): Updated.
665 (reg_table): Updated.
666 (dis386_twobyte): Updated. Use "nopQ" on 0x19 to 0x1e.
667 (twobyte_has_modrm): Set 1 for 0x19 to 0x1e.
668
50e8458f
L		 6692008-01-08 H.J. Lu <hongjiu.lu@intel.com>
670
671 * i386-gen.c (set_bitfield): Use fail () on error.
672
3d4d5afa
L		 6732008-01-08 H.J. Lu <hongjiu.lu@intel.com>
674
675 * i386-gen.c (lineno): New.
676 (filename): Likewise.
677 (set_bitfield): Report filename and line numer on error.
678 (process_i386_opcodes): Set filename and update lineno.
679 (process_i386_registers): Likewise.
680
e1d4d893
L		 6812008-01-05 H.J. Lu <hongjiu.lu@intel.com>
682
683 * i386-gen.c (opcode_modifiers): Rename IntelMnemonic to
684 ATTSyntax.
685
686 * i386-opc.h (IntelMnemonic): Renamed to ..
687 (ATTSyntax): This
688 (Opcode_Modifier_Max): Updated.
689 (i386_opcode_modifier): Remove intelmnemonic. Add attsyntax
690 and intelsyntax.
691
8944f3c2 692 * i386-opc.tbl: Remove IntelMnemonic and update with ATTSyntax
e1d4d893
L		 693 on fsub, fubp, fsubr, fsubrp, div, fdivp, fdivr and fdivrp.
694 * i386-tbl.h: Regenerated.
695
6f143e4d
L		 6962008-01-04 H.J. Lu <hongjiu.lu@intel.com>
697
698 * i386-gen.c: Update copyright to 2008.
699 * i386-opc.h: Likewise.
700 * i386-opc.tbl: Likewise.
701
702 * i386-init.h: Regenerated.
703 * i386-tbl.h: Likewise.
704
c6add537
L		 7052008-01-04 H.J. Lu <hongjiu.lu@intel.com>
706
707 * i386-opc.tbl: Add NoRex64 to extractps, movmskpd, movmskps,
708 pextrb, pextrw, pinsrb, pinsrw and pmovmskb.
709 * i386-tbl.h: Regenerated.
710
3629bb00
L		 7112008-01-03 H.J. Lu <hongjiu.lu@intel.com>
712
713 * i386-gen.c (cpu_flag_init): Remove CpuSSE4_1_Or_5 and
714 CpuSSE4_2_Or_ABM.
715 (cpu_flags): Likewise.
716
717 * i386-opc.h (CpuSSE4_1_Or_5): Removed.
718 (CpuSSE4_2_Or_ABM): Likewise.
719 (CpuLM): Updated.
720 (i386_cpu_flags): Remove cpusse4_1_or_5 and cpusse4_2_or_abm.
721
722 * i386-opc.tbl: Replace CpuSSE4_1_Or_5, CpuSSE4_2_Or_ABM and
723 Cpu686|CpuPadLock with CpuSSE4_1|CpuSSE5, CpuABM|CpuSSE4_2
724 and CpuPadLock, respectively.
725 * i386-init.h: Regenerated.
726 * i386-tbl.h: Likewise.
727
24995bd6
L		 7282008-01-03 H.J. Lu <hongjiu.lu@intel.com>
729
730 * i386-gen.c (opcode_modifiers): Remove No_xSuf.
731
732 * i386-opc.h (No_xSuf): Removed.
733 (CheckSize): Updated.
734
735 * i386-tbl.h: Regenerated.
736
e0329a22
L		 7372008-01-02 H.J. Lu <hongjiu.lu@intel.com>
738
739 * i386-gen.c (cpu_flag_init): Add CpuSSE4_2_Or_ABM to
740 CPU_AMDFAM10_FLAGS, CPU_SSE4_2_FLAGS, CpuABM and
741 CPU_SSE5_FLAGS.
742 (cpu_flags): Add CpuSSE4_2_Or_ABM.
743
744 * i386-opc.h (CpuSSE4_2_Or_ABM): New.
745 (CpuLM): Updated.
746 (i386_cpu_flags): Add cpusse4_2_or_abm.
747
748 * i386-opc.tbl: Use CpuSSE4_2_Or_ABM instead of
749 CpuABM|CpuSSE4_2 on popcnt.
750 * i386-init.h: Regenerated.
751 * i386-tbl.h: Likewise.
752
f2a9c676
L		 7532008-01-02 H.J. Lu <hongjiu.lu@intel.com>
754
755 * i386-opc.h: Update comments.
756
d978b5be
L		 7572008-01-02 H.J. Lu <hongjiu.lu@intel.com>
758
759 * i386-gen.c (opcode_modifiers): Use Qword instead of QWord.
760 * i386-opc.h: Likewise.
761 * i386-opc.tbl: Likewise.
762
582d5edd
L		 7632008-01-02 H.J. Lu <hongjiu.lu@intel.com>
764
765 PR gas/5534
766 * i386-gen.c (opcode_modifiers): Add No_xSuf, CheckSize,
767 Byte, Word, Dword, QWord and Xmmword.
768
769 * i386-opc.h (No_xSuf): New.
770 (CheckSize): Likewise.
771 (Byte): Likewise.
772 (Word): Likewise.
773 (Dword): Likewise.
774 (QWord): Likewise.
775 (Xmmword): Likewise.
776 (FWait): Updated.
777 (i386_opcode_modifier): Add No_xSuf, CheckSize, Byte, Word,
778 Dword, QWord and Xmmword.
779
780 * i386-opc.tbl: Add CheckSize|QWord to movq if IgnoreSize is
781 used.
782 * i386-tbl.h: Regenerated.
783
3fe15143
MK		 7842008-01-02 Mark Kettenis <kettenis@gnu.org>
785
786 * m88k-dis.c (instructions): Fix fcvt.* instructions.
787 From Miod Vallat.
788
6c7ac64e 789For older changes see ChangeLog-2007
252b5132
RH		 790\f
791Local Variables:
2f6d2f85
NC		 792mode: change-log
793left-margin: 8
794fill-column: 74
252b5132
RH		 795version-control: never
796End:
GDB Binutils - Deliverables
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