[deliverable/binutils-gdb.git] / opcodes / ChangeLog

2011-07-24  Maciej W. Rozycki  <macro@codesourcery.com>

	* mips-opc.c (NODS): New macro.
	(TRAP): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT.
	(DSP_VOLA): Likewise.
	(mips_builtin_opcodes): Add NODS annotation to "deret" and
	"eret". Replace INSN_SYNC with NODS throughout.  Use NODS in
	place of TRAP for "wait", "waiti" and "yield".
	* mips16-opc.c (NODS): New macro.
	(TRAP): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT.
	(mips16_opcodes):  Use NODS in place of TRAP for "jalrc", "jrc",
	"restore" and "save".

2011-07-22  H.J. Lu  <hongjiu.lu@intel.com>

	* configure.in: Handle bfd_k1om_arch.
	* configure: Regenerated.

	* disassemble.c (disassembler): Handle bfd_k1om_arch.

	* i386-dis.c (print_insn): Handle bfd_mach_k1om and
	bfd_mach_k1om_intel_syntax.

	* i386-gen.c (cpu_flag_init): Set CPU_UNKNOWN_FLAGS to
	~(CpuL1OM|CpuK1OM).  Add CPU_K1OM_FLAGS.
	(cpu_flags): Add CpuK1OM.

	* i386-opc.h (CpuK1OM): New.
	(i386_cpu_flags): Add cpuk1om.

	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2011-07-12  Nick Clifton  <nickc@redhat.com>

	* arm-dis.c (print_insn_arm): Revert previous, undocumented,
	accidental change.

2011-07-01  Nick Clifton  <nickc@redhat.com>

	PR binutils/12329
	* avr-dis.c (avr_operand): Fix disassembly of ELPM, LPM and SPM
	insns using post-increment addressing.

2011-06-30  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (vex_len_table): Update rorxS.

2011-06-30  H.J. Lu  <hongjiu.lu@intel.com>

	AVX Programming Reference (June, 2011)
	* i386-dis.c (vex_len_table): Correct rorxS.

	* i386-opc.tbl: Correct rorx.
	* i386-tbl.h: Regenerated.

2011-06-29  H.J. Lu  <hongjiu.lu@intel.com>

	* tilegx-opc.c (find_opcode): Replace "index" with "i".
	* tilepro-opc.c (find_opcode): Likewise.

2011-06-29  Richard Sandiford  <rdsandiford@googlemail.com>

	* mips16-opc.c (jalrc, jrc): Move earlier in file.

2011-06-21  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (prefix_table): Re-indent PREFIX_VEX_0F388C and
	PREFIX_VEX_0F388E.

2011-06-17  Andreas Schwab  <schwab@redhat.com>

	* Makefile.am (MAINTAINERCLEANFILES): Move s390-opc.tab ...
	(MOSTLYCLEANFILES): ... here.
	* Makefile.in: Regenerate.

2011-06-14  Alan Modra  <amodra@gmail.com>

	* Makefile.in: Regenerate.

2011-06-13  Walter Lee  <walt@tilera.com>

	* Makefile.am (TARGET_LIBOPCODES_CFILES): Add tilegx-dis.c,
	tilegx-opc.c, tilepro-dis.c, and tilepro-opc.c.
	* Makefile.in: Regenerate.
	* configure.in: Handle bfd_tilegx_arch and bfd_tilepro_arch.
	* configure: Regenerate.
	* disassemble.c (disassembler): Add ARCH_tilegx and ARCH_tilepro.
	* po/POTFILES.in: Regenerate.
	* tilegx-dis.c: New file.
	* tilegx-opc.c: New file.
	* tilepro-dis.c: New file.
	* tilepro-opc.c: New file.

2011-06-10  H.J. Lu  <hongjiu.lu@intel.com>

	AVX Programming Reference (June, 2011)
	* i386-dis.c (XMGatherQ): New.
	* i386-dis.c (EXxmm_mb): New.
	(EXxmm_mb): Likewise.
	(EXxmm_mw): Likewise.
	(EXxmm_md): Likewise.
	(EXxmm_mq): Likewise.
	(EXxmmdw): Likewise.
	(EXxmmqd): Likewise.
	(VexGatherQ): Likewise.
	(MVexVSIBDWpX): Likewise.
	(MVexVSIBQWpX): Likewise.
	(xmm_mb_mode): Likewise.
	(xmm_mw_mode): Likewise.
	(xmm_md_mode): Likewise.
	(xmm_mq_mode): Likewise.
	(xmmdw_mode): Likewise.
	(xmmqd_mode): Likewise.
	(ymmxmm_mode): Likewise.
	(vex_vsib_d_w_dq_mode): Likewise.
	(vex_vsib_q_w_dq_mode): Likewise.
	(MOD_VEX_0F385A_PREFIX_2): Likewise.
	(MOD_VEX_0F388C_PREFIX_2): Likewise.
	(MOD_VEX_0F388E_PREFIX_2): Likewise.
	(PREFIX_0F3882): Likewise.
	(PREFIX_VEX_0F3816): Likewise.
	(PREFIX_VEX_0F3836): Likewise.
	(PREFIX_VEX_0F3845): Likewise.
	(PREFIX_VEX_0F3846): Likewise.
	(PREFIX_VEX_0F3847): Likewise.
	(PREFIX_VEX_0F3858): Likewise.
	(PREFIX_VEX_0F3859): Likewise.
	(PREFIX_VEX_0F385A): Likewise.
	(PREFIX_VEX_0F3878): Likewise.
	(PREFIX_VEX_0F3879): Likewise.
	(PREFIX_VEX_0F388C): Likewise.
	(PREFIX_VEX_0F388E): Likewise.
	(PREFIX_VEX_0F3890..PREFIX_VEX_0F3893): Likewise.
	(PREFIX_VEX_0F38F5): Likewise.
	(PREFIX_VEX_0F38F6): Likewise.
	(PREFIX_VEX_0F3A00): Likewise.
	(PREFIX_VEX_0F3A01): Likewise.
	(PREFIX_VEX_0F3A02): Likewise.
	(PREFIX_VEX_0F3A38): Likewise.
	(PREFIX_VEX_0F3A39): Likewise.
	(PREFIX_VEX_0F3A46): Likewise.
	(PREFIX_VEX_0F3AF0): Likewise.
	(VEX_LEN_0F3816_P_2): Likewise.
	(VEX_LEN_0F3819_P_2): Likewise.
	(VEX_LEN_0F3836_P_2): Likewise.
	(VEX_LEN_0F385A_P_2_M_0): Likewise.
	(VEX_LEN_0F38F5_P_0): Likewise.
	(VEX_LEN_0F38F5_P_1): Likewise.
	(VEX_LEN_0F38F5_P_3): Likewise.
	(VEX_LEN_0F38F6_P_3): Likewise.
	(VEX_LEN_0F38F7_P_1): Likewise.
	(VEX_LEN_0F38F7_P_2): Likewise.
	(VEX_LEN_0F38F7_P_3): Likewise.
	(VEX_LEN_0F3A00_P_2): Likewise.
	(VEX_LEN_0F3A01_P_2): Likewise.
	(VEX_LEN_0F3A38_P_2): Likewise.
	(VEX_LEN_0F3A39_P_2): Likewise.
	(VEX_LEN_0F3A46_P_2): Likewise.
	(VEX_LEN_0F3AF0_P_3): Likewise.
	(VEX_W_0F3816_P_2): Likewise.
	(VEX_W_0F3818_P_2): Likewise.
	(VEX_W_0F3819_P_2): Likewise.
	(VEX_W_0F3836_P_2): Likewise.
	(VEX_W_0F3846_P_2): Likewise.
	(VEX_W_0F3858_P_2): Likewise.
	(VEX_W_0F3859_P_2): Likewise.
	(VEX_W_0F385A_P_2_M_0): Likewise.
	(VEX_W_0F3878_P_2): Likewise.
	(VEX_W_0F3879_P_2): Likewise.
	(VEX_W_0F3A00_P_2): Likewise.
	(VEX_W_0F3A01_P_2): Likewise.
	(VEX_W_0F3A02_P_2): Likewise.
	(VEX_W_0F3A38_P_2): Likewise.
	(VEX_W_0F3A39_P_2): Likewise.
	(VEX_W_0F3A46_P_2): Likewise.
	(MOD_VEX_0F3818_PREFIX_2): Removed.
	(MOD_VEX_0F3819_PREFIX_2): Likewise.
	(VEX_LEN_0F60_P_2..VEX_LEN_0F6D_P_2): Likewise.
	(VEX_LEN_0F70_P_1..VEX_LEN_0F76_P_2): Likewise.
	(VEX_LEN_0FD1_P_2..VEX_LEN_0FD5_P_2): Likewise.
	(VEX_LEN_0FD7_P_2_M_1..VEX_LEN_0F3819_P_2_M_0): Likewise.
	(VEX_LEN_0F381C_P_2..VEX_LEN_0F3840_P_2): Likewise.
	(VEX_LEN_0F3A0E_P_2): Likewise.
	(VEX_LEN_0F3A0F_P_2): Likewise.
	(VEX_LEN_0F3A42_P_2): Likewise.
	(VEX_LEN_0F3A4C_P_2): Likewise.
	(VEX_W_0F3818_P_2_M_0): Likewise.
	(VEX_W_0F3819_P_2_M_0): Likewise.
	(prefix_table): Updated.
	(three_byte_table): Likewise.
	(vex_table): Likewise.
	(vex_len_table): Likewise.
	(vex_w_table): Likewise.
	(mod_table): Likewise.
	(putop): Handle "LW".
	(intel_operand_size): Handle xmm_mb_mode, xmm_mw_mode,
	xmm_md_mode, xmm_mq_mode, xmmdw_mode, xmmqd_mode, ymmxmm_mode,
	vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode.
	(OP_EX): Likewise.
	(OP_E_memory): Handle vex_vsib_d_w_dq_mode and
	vex_vsib_q_w_dq_mode.
	(OP_XMM): Handle vex_vsib_q_w_dq_mode.
	(OP_VEX): Likewise.

	* i386-gen.c (cpu_flag_init): Add CpuAVX2 to CPU_ANY_SSE_FLAGS
	and CPU_ANY_AVX_FLAGS.  Add CPU_BMI2_FLAGS, CPU_LZCNT_FLAGS,
	CPU_INVPCID_FLAGS and CPU_AVX2_FLAGS.
	(cpu_flags): Add CpuAVX2, CpuBMI2, CpuLZCNT and CpuINVPCID.
	(opcode_modifiers): Add VecSIB.

	* i386-opc.h (CpuAVX2): New.
	(CpuBMI2): Likewise.
	(CpuLZCNT): Likewise.
	(CpuINVPCID): Likewise.
	(VecSIB128): Likewise.
	(VecSIB256): Likewise.
	(VecSIB): Likewise.
	(i386_cpu_flags): Add cpuavx2, cpubmi2, cpulzcnt and cpuinvpcid.
	(i386_opcode_modifier): Add vecsib.

	* i386-opc.tbl: Add invpcid, AVX2 and BMI2 instructions.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2011-06-03  Quentin Neill  <quentin.neill@amd.com>

	* i386-gen.c (cpu_flag_init): Add CpuF16C to CPU_BDVER2_FLAGS.
	* i386-init.h: Regenerated.

2011-06-03  Nick Clifton  <nickc@redhat.com>

	PR binutils/12752
	* arm-dis.c (print_insn_coprocessor): Use bfd_vma type for
	computing address offsets.
	(print_arm_address): Likewise.
	(print_insn_arm): Likewise.
	(print_insn_thumb16): Likewise.
	(print_insn_thumb32): Likewise.

2011-06-02  Jie Zhang <jie@codesourcery.com>
	    Nathan Sidwell <nathan@codesourcery.com>
	    Maciej Rozycki <macro@codesourcery.com>

	* arm-dis.c (print_insn_coprocessor): Explicitly print #-0
	as address offset.
	(print_arm_address): Likewise. Elide positive #0 appropriately.
	(print_insn_arm): Likewise.

2011-06-02  Nick Clifton  <nickc@redhat.com>

	PR gas/12752
	* arm-dis.c (print_insn_thumb32): Do not sign extend  addresses
	passed to print_address_func.

2011-06-02  Nick Clifton  <nickc@redhat.com>

	* arm-dis.c: Fix spelling mistakes.
	* op/opcodes.pot: Regenerate.

2011-05-24  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>

	* s390-opc.c: Replace S390_OPERAND_REG_EVEN with
	S390_OPERAND_REG_PAIR.  Fix INSTR_RRF_0UFEF instruction type.
	* s390-opc.txt: Fix cxr instruction type.

2011-05-24  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>

	* s390-opc.c: Add new instruction types marking register pair
	operands.
	* s390-opc.txt: Match instructions having register pair operands
	to the new instruction types.

2011-05-19  Nick Clifton  <nickc@redhat.com>

	* v850-opc.c (cmpf.[sd]): Reverse the order of the reg1 and reg2
	operands.

2011-05-10  Quentin Neill  <quentin.neill@amd.com>

	* i386-gen.c (cpu_flag_init): Add new CPU_BDVER2_FLAGS.
	* i386-init.h: Regenerated.

2011-04-27  Nick Clifton  <nickc@redhat.com>

	* po/da.po: Updated Danish translation.

2011-04-26  Anton Blanchard  <anton@samba.org>

	* ppc-opc.c: (powerpc_opcodes): Enable icswx for POWER7.

2011-04-21  DJ Delorie  <dj@redhat.com>

	* rx-decode.opc (rx_decode_opcode): Set the syntax for multi-byte NOPs.
	* rx-decode.c: Regenerate.

2011-04-20  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-init.h: Regenerated.

2011-04-19  Quentin Neill  <quentin.neill@amd.com>

	* i386-gen.c (cpu_flag_init): Remove 3dnow and 3dnowa bits
	from bdver1 flags.

2011-04-13  Nick Clifton  <nickc@redhat.com>

	* v850-dis.c (disassemble): Always print a closing square brace if
	an opening square brace was printed.

2011-04-12  Nick Clifton  <nickc@redhat.com>

	PR binutils/12534
	* arm-dis.c (thumb32_opcodes): Add %L suffix to LDRD and STRD insn
	patterns.
	(print_insn_thumb32): Handle %L.

2011-04-11  Julian Brown  <julian@codesourcery.com>

	* arm-dis.c (psr_name): Fix typo for BASEPRI_MAX.
	(print_insn_thumb32): Add APSR bitmask support.

2011-04-07  Paul Carroll<pcarroll@codesourcery.com>

	* arm-dis.c (print_insn): init vars moved into private_data structure.

2011-03-24  Mike Frysinger  <vapier@gentoo.org>

	* bfin-dis.c (decode_dsp32mac_0): Move MM zeroing down to MAC0 logic.

2011-03-22  Eric B. Weddington  <eric.weddington@atmel.com>

	* avr-dis.c (avr_operand): Add opcode_str parameter. Check for
	post-increment to support LPM Z+ instruction. Add support for 'E'
	constraint for DES instruction.
	(print_insn_avr): Adjust calls to avr_operand. Rename variable.

2011-03-14  Richard Sandiford  <richard.sandiford@linaro.org>

	* arm-dis.c (get_sym_code_type): Treat STT_GNU_IFUNCs as code.

2011-03-14  Richard Sandiford  <richard.sandiford@linaro.org>

	* arm-dis.c (get_sym_code_type): Don't check for STT_ARM_TFUNC.
	Use branch types instead.
	(print_insn): Likewise.

2011-02-28  Maciej W. Rozycki  <macro@codesourcery.com>

	* mips-opc.c (mips_builtin_opcodes): Correct register use
	annotation of "alnv.ps".

2011-02-28  Maciej W. Rozycki  <macro@codesourcery.com>

	* mips-opc.c (mips_builtin_opcodes): Add "pref" macro.

2011-02-22  Mike Frysinger  <vapier@gentoo.org>

	* bfin-dis.c (OUTS): Remove p NULL check and txt NUL check.

2011-02-22  Mike Frysinger  <vapier@gentoo.org>

	* bfin-dis.c (print_insn_bfin): Change outf->fprintf_func to OUTS.

2011-02-19  Mike Frysinger  <vapier@gentoo.org>

	* bfin-dis.c (saved_state): Mark static.  Change a[01]x to ax[] and
	a[01]w to aw[].  Delete ac0, ac0_copy, ac1, an, aq, av0, av0s, av1,
	av1s, az, cc, v, v_copy, vs, rnd_mod, v_internal, pc, ticks, insts,
	exception, end_of_registers, msize, memory, bfd_mach.
	(CCREG, PCREG, A0XREG, A0WREG, A1XREG, A1WREG, LC0REG, LT0REG,
	LB0REG, LC1REG, LT1REG, LB1REG): Delete
	(AXREG, AWREG, LCREG, LTREG, LBREG): Define.
	(get_allreg): Change to new defines.  Fallback to abort().

2011-02-14  Mike Frysinger  <vapier@gentoo.org>

	* bfin-dis.c: Add whitespace/parenthesis where needed.

2011-02-14  Mike Frysinger  <vapier@gentoo.org>

	* bfin-dis.c (decode_LoopSetup_0): Return when reg is greater
	than 7.

2011-02-13  Ralf Wildenhues  <Ralf.Wildenhues@gmx.de>

	* configure: Regenerate.

2011-02-13  Mike Frysinger  <vapier@gentoo.org>

	* bfin-dis.c (decode_dsp32alu_0): Fix typo with A1 reg.

2011-02-13  Mike Frysinger  <vapier@gentoo.org>

	* bfin-dis.c (decode_dsp32mult_0): Add 1 to dst for mac1.  Output
	dregs only when P is set, and dregs_lo otherwise.

2011-02-13  Mike Frysinger  <vapier@gentoo.org>

	* bfin-dis.c (decode_dsp32alu_0): Delete BYTEOP2M code.

2011-02-12  Mike Frysinger  <vapier@gentoo.org>

	* bfin-dis.c (decode_pseudoDEBUG_0): Add space after PRNT.

2011-02-12  Mike Frysinger  <vapier@gentoo.org>

	* bfin-dis.c (machine_registers): Delete REG_GP.
	(reg_names): Delete "GP".
	(decode_allregs): Change REG_GP to REG_LASTREG.

2011-02-12  Mike Frysinger  <vapier@gentoo.org>

	* bfin-dis.c (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2,
	M_IH, M_IU): Delete.

2011-02-11  Mike Frysinger  <vapier@gentoo.org>

	* bfin-dis.c (reg_names): Add const.
	(decode_dregs_lo, decode_dregs_hi, decode_dregs, decode_dregs_byte,
	decode_pregs, decode_iregs, decode_mregs, decode_dpregs, decode_gregs,
	decode_regs, decode_regs_lo, decode_regs_hi, decode_statbits,
	decode_counters, decode_allregs): Likewise.

2011-02-09  Michael Snyder  <msnyder@vmware.com>

	* i386-dis.c (OP_J): Parenthesize expression to prevent
	truncated addresses.
	(print_insn): Fix indentation off-by-one.

2011-02-01  Nick Clifton  <nickc@redhat.com>

	* po/da.po: Updated Danish translation.

2011-01-21  Dave Murphy  <davem@devkitpro.org>

	* ppc-opc.c (NON32, NO371): Remove PPC_OPCODE_PPCPS.

2011-01-18  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (sIbT): New.
	(b_T_mode): Likewise.
	(dis386): Replace sIb with sIbT on "pushT".
	(x86_64_table): Replace sIb with Ib on "aam" and "aad".
	(OP_sI): Handle b_T_mode.  Properly sign-extend byte.

2011-01-18  Jan Kratochvil  <jan.kratochvil@redhat.com>

	* i386-init.h: Regenerated.
	* i386-tbl.h: Regenerated

2011-01-17  Quentin Neill  <quentin.neill@amd.com>

	* i386-dis.c (REG_XOP_TBM_01): New.
	(REG_XOP_TBM_02): New.
	(reg_table): Add REG_XOP_TBM_01 and REG_XOP_TBM_02 tables.
	(xop_table): Redirect to REG_XOP_TBM_01 and REG_XOP_TBM_02
	entries, and add bextr instruction.

	* i386-gen.c (cpu_flag_init): Add CPU_TBM_FLAGS, CpuTBM.
	(cpu_flags): Add CpuTBM.

	* i386-opc.h (CpuTBM) New.
	(i386_cpu_flags): Add bit cputbm.

	* i386-opc.tbl: Add bextr, blcfill, blci, blcic, blcmsk,
	blcs, blsfill, blsic, t1mskc, and tzmsk.

2011-01-12  DJ Delorie  <dj@redhat.com>

	* rx-dis.c (print_insn_rx): Support RX_Operand_TwoReg.

2011-01-11  Mingjie Xing  <mingjie.xing@gmail.com>

	* mips-dis.c (print_insn_args): Adjust the value to print the real
	offset for "+c" argument.

2011-01-10  Nick Clifton  <nickc@redhat.com>

	* po/da.po: Updated Danish translation.

2011-01-05  Nathan Sidwell  <nathan@codesourcery.com>

	* arm-dis.c (thumb32_opcodes): BLX must have bit zero clear.

2011-01-04  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (REG_VEX_38F3): New.
	(PREFIX_0FBC): Likewise.
	(PREFIX_VEX_38F2): Likewise.
	(PREFIX_VEX_38F3_REG_1): Likewise.
	(PREFIX_VEX_38F3_REG_2): Likewise.
	(PREFIX_VEX_38F3_REG_3): Likewise.
	(PREFIX_VEX_38F7): Likewise.
	(VEX_LEN_38F2_P_0): Likewise.
	(VEX_LEN_38F3_R_1_P_0): Likewise.
	(VEX_LEN_38F3_R_2_P_0): Likewise.
	(VEX_LEN_38F3_R_3_P_0): Likewise.
	(VEX_LEN_38F7_P_0): Likewise.
	(dis386_twobyte): Use PREFIX_0FBC.
	(reg_table): Add REG_VEX_38F3.
	(prefix_table): Add PREFIX_0FBC, PREFIX_VEX_38F2,
	PREFIX_VEX_38F3_REG_1, PREFIX_VEX_38F3_REG_2,
	PREFIX_VEX_38F3_REG_3 and PREFIX_VEX_38F7.
	(vex_table): Use PREFIX_VEX_38F2, REG_VEX_38F3 and
	PREFIX_VEX_38F7.
	(vex_len_table): Add VEX_LEN_38F2_P_0, VEX_LEN_38F3_R_1_P_0,
	VEX_LEN_38F3_R_2_P_0, VEX_LEN_38F3_R_3_P_0 and
	VEX_LEN_38F7_P_0.

	* i386-gen.c (cpu_flag_init): Add CPU_BMI_FLAGS.
	(cpu_flags): Add CpuBMI.

	* i386-opc.h (CpuBMI): New.
	(i386_cpu_flags): Add cpubmi.

	* i386-opc.tbl: Add andn, bextr, blsi, blsmsk, blsr and tzcnt.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2011-01-04  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (VexGdq): New.
	(OP_VEX): Handle dq_mode.

2011-01-01  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (process_copyright): Update copyright to 2011.

For older changes see ChangeLog-2010
\f
Local Variables:
mode: change-log
left-margin: 8
fill-column: 74
version-control: never
End:
Commit	Line	Data
bcd530a7 RS	1	2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
	2
	3	* mips-opc.c (NODS): New macro.
	4	(TRAP): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT.
	5	(DSP_VOLA): Likewise.
	6	(mips_builtin_opcodes): Add NODS annotation to "deret" and
	7	"eret". Replace INSN_SYNC with NODS throughout. Use NODS in
	8	place of TRAP for "wait", "waiti" and "yield".
	9	* mips16-opc.c (NODS): New macro.
	10	(TRAP): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT.
	11	(mips16_opcodes): Use NODS in place of TRAP for "jalrc", "jrc",
	12	"restore" and "save".
	13
7a9068fe L	14	2011-07-22 H.J. Lu <hongjiu.lu@intel.com>
	15
	16	* configure.in: Handle bfd_k1om_arch.
	17	* configure: Regenerated.
	18
	19	* disassemble.c (disassembler): Handle bfd_k1om_arch.
	20
	21	* i386-dis.c (print_insn): Handle bfd_mach_k1om and
	22	bfd_mach_k1om_intel_syntax.
	23
	24	* i386-gen.c (cpu_flag_init): Set CPU_UNKNOWN_FLAGS to
	25	~(CpuL1OM\|CpuK1OM). Add CPU_K1OM_FLAGS.
	26	(cpu_flags): Add CpuK1OM.
	27
	28	* i386-opc.h (CpuK1OM): New.
	29	(i386_cpu_flags): Add cpuk1om.
	30
	31	* i386-init.h: Regenerated.
	32	* i386-tbl.h: Likewise.
	33
1b93226d NC	34	2011-07-12 Nick Clifton <nickc@redhat.com>
	35
	36	* arm-dis.c (print_insn_arm): Revert previous, undocumented,
	37	accidental change.
	38
5d73b1f1 NC	39	2011-07-01 Nick Clifton <nickc@redhat.com>
	40
	41	PR binutils/12329
	42	* avr-dis.c (avr_operand): Fix disassembly of ELPM, LPM and SPM
	43	insns using post-increment addressing.
	44
182ae480 L	45	2011-06-30 H.J. Lu <hongjiu.lu@intel.com>
	46
	47	* i386-dis.c (vex_len_table): Update rorxS.
	48
4cb0953d L	49	2011-06-30 H.J. Lu <hongjiu.lu@intel.com>
	50
	51	AVX Programming Reference (June, 2011)
	52	* i386-dis.c (vex_len_table): Correct rorxS.
	53
	54	* i386-opc.tbl: Correct rorx.
	55	* i386-tbl.h: Regenerated.
	56
906efcbc L	57	2011-06-29 H.J. Lu <hongjiu.lu@intel.com>
	58
	59	* tilegx-opc.c (find_opcode): Replace "index" with "i".
	60	* tilepro-opc.c (find_opcode): Likewise.
	61
ceb94aa5 RS	62	2011-06-29 Richard Sandiford <rdsandiford@googlemail.com>
	63
	64	* mips16-opc.c (jalrc, jrc): Move earlier in file.
	65
f7002f42 L	66	2011-06-21 H.J. Lu <hongjiu.lu@intel.com>
	67
	68	* i386-dis.c (prefix_table): Re-indent PREFIX_VEX_0F388C and
	69	PREFIX_VEX_0F388E.
	70
56300268 AS	71	2011-06-17 Andreas Schwab <schwab@redhat.com>
	72
	73	* Makefile.am (MAINTAINERCLEANFILES): Move s390-opc.tab ...
	74	(MOSTLYCLEANFILES): ... here.
	75	* Makefile.in: Regenerate.
	76
bcf2cf9f AM	77	2011-06-14 Alan Modra <amodra@gmail.com>
	78
	79	* Makefile.in: Regenerate.
	80
aa137e4d NC	81	2011-06-13 Walter Lee <walt@tilera.com>
	82
	83	* Makefile.am (TARGET_LIBOPCODES_CFILES): Add tilegx-dis.c,
	84	tilegx-opc.c, tilepro-dis.c, and tilepro-opc.c.
	85	* Makefile.in: Regenerate.
	86	* configure.in: Handle bfd_tilegx_arch and bfd_tilepro_arch.
	87	* configure: Regenerate.
	88	* disassemble.c (disassembler): Add ARCH_tilegx and ARCH_tilepro.
	89	* po/POTFILES.in: Regenerate.
	90	* tilegx-dis.c: New file.
	91	* tilegx-opc.c: New file.
	92	* tilepro-dis.c: New file.
	93	* tilepro-opc.c: New file.
	94
6c30d220 L	95	2011-06-10 H.J. Lu <hongjiu.lu@intel.com>
	96
	97	AVX Programming Reference (June, 2011)
	98	* i386-dis.c (XMGatherQ): New.
	99	* i386-dis.c (EXxmm_mb): New.
	100	(EXxmm_mb): Likewise.
	101	(EXxmm_mw): Likewise.
	102	(EXxmm_md): Likewise.
	103	(EXxmm_mq): Likewise.
	104	(EXxmmdw): Likewise.
	105	(EXxmmqd): Likewise.
	106	(VexGatherQ): Likewise.
	107	(MVexVSIBDWpX): Likewise.
	108	(MVexVSIBQWpX): Likewise.
	109	(xmm_mb_mode): Likewise.
	110	(xmm_mw_mode): Likewise.
	111	(xmm_md_mode): Likewise.
	112	(xmm_mq_mode): Likewise.
	113	(xmmdw_mode): Likewise.
	114	(xmmqd_mode): Likewise.
	115	(ymmxmm_mode): Likewise.
	116	(vex_vsib_d_w_dq_mode): Likewise.
	117	(vex_vsib_q_w_dq_mode): Likewise.
	118	(MOD_VEX_0F385A_PREFIX_2): Likewise.
	119	(MOD_VEX_0F388C_PREFIX_2): Likewise.
	120	(MOD_VEX_0F388E_PREFIX_2): Likewise.
	121	(PREFIX_0F3882): Likewise.
	122	(PREFIX_VEX_0F3816): Likewise.
	123	(PREFIX_VEX_0F3836): Likewise.
	124	(PREFIX_VEX_0F3845): Likewise.
	125	(PREFIX_VEX_0F3846): Likewise.
	126	(PREFIX_VEX_0F3847): Likewise.
	127	(PREFIX_VEX_0F3858): Likewise.
	128	(PREFIX_VEX_0F3859): Likewise.
	129	(PREFIX_VEX_0F385A): Likewise.
	130	(PREFIX_VEX_0F3878): Likewise.
	131	(PREFIX_VEX_0F3879): Likewise.
	132	(PREFIX_VEX_0F388C): Likewise.
	133	(PREFIX_VEX_0F388E): Likewise.
	134	(PREFIX_VEX_0F3890..PREFIX_VEX_0F3893): Likewise.
	135	(PREFIX_VEX_0F38F5): Likewise.
	136	(PREFIX_VEX_0F38F6): Likewise.
	137	(PREFIX_VEX_0F3A00): Likewise.
	138	(PREFIX_VEX_0F3A01): Likewise.
	139	(PREFIX_VEX_0F3A02): Likewise.
	140	(PREFIX_VEX_0F3A38): Likewise.
	141	(PREFIX_VEX_0F3A39): Likewise.
	142	(PREFIX_VEX_0F3A46): Likewise.
	143	(PREFIX_VEX_0F3AF0): Likewise.
	144	(VEX_LEN_0F3816_P_2): Likewise.
	145	(VEX_LEN_0F3819_P_2): Likewise.
	146	(VEX_LEN_0F3836_P_2): Likewise.
	147	(VEX_LEN_0F385A_P_2_M_0): Likewise.
	148	(VEX_LEN_0F38F5_P_0): Likewise.
	149	(VEX_LEN_0F38F5_P_1): Likewise.
	150	(VEX_LEN_0F38F5_P_3): Likewise.
	151	(VEX_LEN_0F38F6_P_3): Likewise.
	152	(VEX_LEN_0F38F7_P_1): Likewise.
	153	(VEX_LEN_0F38F7_P_2): Likewise.
	154	(VEX_LEN_0F38F7_P_3): Likewise.
	155	(VEX_LEN_0F3A00_P_2): Likewise.
	156	(VEX_LEN_0F3A01_P_2): Likewise.
	157	(VEX_LEN_0F3A38_P_2): Likewise.
	158	(VEX_LEN_0F3A39_P_2): Likewise.
159	(VEX_LEN_0F3A46_P_2): Likewise.
160	(VEX_LEN_0F3AF0_P_3): Likewise.
161	(VEX_W_0F3816_P_2): Likewise.
162	(VEX_W_0F3818_P_2): Likewise.
163	(VEX_W_0F3819_P_2): Likewise.
164	(VEX_W_0F3836_P_2): Likewise.
165	(VEX_W_0F3846_P_2): Likewise.
166	(VEX_W_0F3858_P_2): Likewise.
167	(VEX_W_0F3859_P_2): Likewise.
168	(VEX_W_0F385A_P_2_M_0): Likewise.
169	(VEX_W_0F3878_P_2): Likewise.
170	(VEX_W_0F3879_P_2): Likewise.
171	(VEX_W_0F3A00_P_2): Likewise.
172	(VEX_W_0F3A01_P_2): Likewise.
173	(VEX_W_0F3A02_P_2): Likewise.
174	(VEX_W_0F3A38_P_2): Likewise.
175	(VEX_W_0F3A39_P_2): Likewise.
176	(VEX_W_0F3A46_P_2): Likewise.
177	(MOD_VEX_0F3818_PREFIX_2): Removed.
178	(MOD_VEX_0F3819_PREFIX_2): Likewise.
179	(VEX_LEN_0F60_P_2..VEX_LEN_0F6D_P_2): Likewise.
180	(VEX_LEN_0F70_P_1..VEX_LEN_0F76_P_2): Likewise.
181	(VEX_LEN_0FD1_P_2..VEX_LEN_0FD5_P_2): Likewise.
182	(VEX_LEN_0FD7_P_2_M_1..VEX_LEN_0F3819_P_2_M_0): Likewise.
183	(VEX_LEN_0F381C_P_2..VEX_LEN_0F3840_P_2): Likewise.
184	(VEX_LEN_0F3A0E_P_2): Likewise.
185	(VEX_LEN_0F3A0F_P_2): Likewise.
186	(VEX_LEN_0F3A42_P_2): Likewise.
187	(VEX_LEN_0F3A4C_P_2): Likewise.
188	(VEX_W_0F3818_P_2_M_0): Likewise.
189	(VEX_W_0F3819_P_2_M_0): Likewise.
190	(prefix_table): Updated.
191	(three_byte_table): Likewise.
192	(vex_table): Likewise.
193	(vex_len_table): Likewise.
194	(vex_w_table): Likewise.
195	(mod_table): Likewise.
196	(putop): Handle "LW".
197	(intel_operand_size): Handle xmm_mb_mode, xmm_mw_mode,
198	xmm_md_mode, xmm_mq_mode, xmmdw_mode, xmmqd_mode, ymmxmm_mode,
199	vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode.
200	(OP_EX): Likewise.
201	(OP_E_memory): Handle vex_vsib_d_w_dq_mode and
202	vex_vsib_q_w_dq_mode.
203	(OP_XMM): Handle vex_vsib_q_w_dq_mode.
204	(OP_VEX): Likewise.
205
206	* i386-gen.c (cpu_flag_init): Add CpuAVX2 to CPU_ANY_SSE_FLAGS
207	and CPU_ANY_AVX_FLAGS. Add CPU_BMI2_FLAGS, CPU_LZCNT_FLAGS,
208	CPU_INVPCID_FLAGS and CPU_AVX2_FLAGS.
209	(cpu_flags): Add CpuAVX2, CpuBMI2, CpuLZCNT and CpuINVPCID.
210	(opcode_modifiers): Add VecSIB.
211
212	* i386-opc.h (CpuAVX2): New.
213	(CpuBMI2): Likewise.
214	(CpuLZCNT): Likewise.
215	(CpuINVPCID): Likewise.
216	(VecSIB128): Likewise.
217	(VecSIB256): Likewise.
218	(VecSIB): Likewise.
219	(i386_cpu_flags): Add cpuavx2, cpubmi2, cpulzcnt and cpuinvpcid.
220	(i386_opcode_modifier): Add vecsib.
221
222	* i386-opc.tbl: Add invpcid, AVX2 and BMI2 instructions.
223	* i386-init.h: Regenerated.
224	* i386-tbl.h: Likewise.
225
d535accd QN	226	2011-06-03 Quentin Neill <quentin.neill@amd.com>
	227
	228	* i386-gen.c (cpu_flag_init): Add CpuF16C to CPU_BDVER2_FLAGS.
	229	* i386-init.h: Regenerated.
	230
f8b960bc NC	231	2011-06-03 Nick Clifton <nickc@redhat.com>
	232
	233	PR binutils/12752
	234	* arm-dis.c (print_insn_coprocessor): Use bfd_vma type for
	235	computing address offsets.
	236	(print_arm_address): Likewise.
	237	(print_insn_arm): Likewise.
	238	(print_insn_thumb16): Likewise.
	239	(print_insn_thumb32): Likewise.
	240
26d97720 NS	241	2011-06-02 Jie Zhang <jie@codesourcery.com>
	242	Nathan Sidwell <nathan@codesourcery.com>
	243	Maciej Rozycki <macro@codesourcery.com>
	244
	245	* arm-dis.c (print_insn_coprocessor): Explicitly print #-0
	246	as address offset.
	247	(print_arm_address): Likewise. Elide positive #0 appropriately.
	248	(print_insn_arm): Likewise.
	249
f8b960bc NC	250	2011-06-02 Nick Clifton <nickc@redhat.com>
	251
	252	PR gas/12752
	253	* arm-dis.c (print_insn_thumb32): Do not sign extend addresses
	254	passed to print_address_func.
	255
cc643b88 NC	256	2011-06-02 Nick Clifton <nickc@redhat.com>
	257
	258	* arm-dis.c: Fix spelling mistakes.
	259	* op/opcodes.pot: Regenerate.
	260
c8fa16ed AK	261	2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
	262
	263	* s390-opc.c: Replace S390_OPERAND_REG_EVEN with
	264	S390_OPERAND_REG_PAIR. Fix INSTR_RRF_0UFEF instruction type.
	265	* s390-opc.txt: Fix cxr instruction type.
	266
5e4b319c AK	267	2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
	268
	269	* s390-opc.c: Add new instruction types marking register pair
	270	operands.
	271	* s390-opc.txt: Match instructions having register pair operands
	272	to the new instruction types.
	273
fda544a2 NC	274	2011-05-19 Nick Clifton <nickc@redhat.com>
	275
	276	* v850-opc.c (cmpf.[sd]): Reverse the order of the reg1 and reg2
	277	operands.
	278
4cab4add QN	279	2011-05-10 Quentin Neill <quentin.neill@amd.com>
	280
	281	* i386-gen.c (cpu_flag_init): Add new CPU_BDVER2_FLAGS.
	282	* i386-init.h: Regenerated.
	283
b4e7b885 NC	284	2011-04-27 Nick Clifton <nickc@redhat.com>
	285
	286	* po/da.po: Updated Danish translation.
	287
2f7f7710 AM	288	2011-04-26 Anton Blanchard <anton@samba.org>
	289
	290	* ppc-opc.c: (powerpc_opcodes): Enable icswx for POWER7.
	291
9887672f DD	292	2011-04-21 DJ Delorie <dj@redhat.com>
	293
	294	* rx-decode.opc (rx_decode_opcode): Set the syntax for multi-byte NOPs.
	295	* rx-decode.c: Regenerate.
	296
3251b375 L	297	2011-04-20 H.J. Lu <hongjiu.lu@intel.com>
	298
	299	* i386-init.h: Regenerated.
	300
b13a3ca6 QN	301	2011-04-19 Quentin Neill <quentin.neill@amd.com>
	302
	303	* i386-gen.c (cpu_flag_init): Remove 3dnow and 3dnowa bits
	304	from bdver1 flags.
	305
7d063384 NC	306	2011-04-13 Nick Clifton <nickc@redhat.com>
	307
	308	* v850-dis.c (disassemble): Always print a closing square brace if
	309	an opening square brace was printed.
	310
32a94698 NC	311	2011-04-12 Nick Clifton <nickc@redhat.com>
	312
	313	PR binutils/12534
	314	* arm-dis.c (thumb32_opcodes): Add %L suffix to LDRD and STRD insn
	315	patterns.
	316	(print_insn_thumb32): Handle %L.
	317
d2cd1205 JB	318	2011-04-11 Julian Brown <julian@codesourcery.com>
	319
	320	* arm-dis.c (psr_name): Fix typo for BASEPRI_MAX.
	321	(print_insn_thumb32): Add APSR bitmask support.
	322
1fbaefec PB	323	2011-04-07 Paul Carroll<pcarroll@codesourcery.com>
	324
	325	* arm-dis.c (print_insn): init vars moved into private_data structure.
	326
67171547 MF	327	2011-03-24 Mike Frysinger <vapier@gentoo.org>
	328
	329	* bfin-dis.c (decode_dsp32mac_0): Move MM zeroing down to MAC0 logic.
	330
8cc66334 EW	331	2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
	332
	333	* avr-dis.c (avr_operand): Add opcode_str parameter. Check for
	334	post-increment to support LPM Z+ instruction. Add support for 'E'
	335	constraint for DES instruction.
	336	(print_insn_avr): Adjust calls to avr_operand. Rename variable.
	337
34e77a92 RS	338	2011-03-14 Richard Sandiford <richard.sandiford@linaro.org>
	339
	340	* arm-dis.c (get_sym_code_type): Treat STT_GNU_IFUNCs as code.
	341
35fc36a8 RS	342	2011-03-14 Richard Sandiford <richard.sandiford@linaro.org>
	343
	344	* arm-dis.c (get_sym_code_type): Don't check for STT_ARM_TFUNC.
	345	Use branch types instead.
	346	(print_insn): Likewise.
	347
0067d8fc MR	348	2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
	349
	350	* mips-opc.c (mips_builtin_opcodes): Correct register use
	351	annotation of "alnv.ps".
	352
3eebd5eb MR	353	2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
	354
	355	* mips-opc.c (mips_builtin_opcodes): Add "pref" macro.
	356
500cccad MF	357	2011-02-22 Mike Frysinger <vapier@gentoo.org>
	358
	359	* bfin-dis.c (OUTS): Remove p NULL check and txt NUL check.
	360
f5caf9f4 MF	361	2011-02-22 Mike Frysinger <vapier@gentoo.org>
	362
	363	* bfin-dis.c (print_insn_bfin): Change outf->fprintf_func to OUTS.
	364
e5bc4265 MF	365	2011-02-19 Mike Frysinger <vapier@gentoo.org>
	366
	367	* bfin-dis.c (saved_state): Mark static. Change a[01]x to ax[] and
	368	a[01]w to aw[]. Delete ac0, ac0_copy, ac1, an, aq, av0, av0s, av1,
	369	av1s, az, cc, v, v_copy, vs, rnd_mod, v_internal, pc, ticks, insts,
	370	exception, end_of_registers, msize, memory, bfd_mach.
	371	(CCREG, PCREG, A0XREG, A0WREG, A1XREG, A1WREG, LC0REG, LT0REG,
	372	LB0REG, LC1REG, LT1REG, LB1REG): Delete
	373	(AXREG, AWREG, LCREG, LTREG, LBREG): Define.
	374	(get_allreg): Change to new defines. Fallback to abort().
	375
602427c4 MF	376	2011-02-14 Mike Frysinger <vapier@gentoo.org>
	377
	378	* bfin-dis.c: Add whitespace/parenthesis where needed.
	379
298c1ec2 MF	380	2011-02-14 Mike Frysinger <vapier@gentoo.org>
	381
	382	* bfin-dis.c (decode_LoopSetup_0): Return when reg is greater
	383	than 7.
	384
822ce8ee RW	385	2011-02-13 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
	386
	387	* configure: Regenerate.
	388
13c02f06 MF	389	2011-02-13 Mike Frysinger <vapier@gentoo.org>
	390
	391	* bfin-dis.c (decode_dsp32alu_0): Fix typo with A1 reg.
	392
4db66394 MF	393	2011-02-13 Mike Frysinger <vapier@gentoo.org>
	394
	395	* bfin-dis.c (decode_dsp32mult_0): Add 1 to dst for mac1. Output
	396	dregs only when P is set, and dregs_lo otherwise.
	397
36f44611 MF	398	2011-02-13 Mike Frysinger <vapier@gentoo.org>
	399
	400	* bfin-dis.c (decode_dsp32alu_0): Delete BYTEOP2M code.
	401
9805c0a5 MF	402	2011-02-12 Mike Frysinger <vapier@gentoo.org>
	403
	404	* bfin-dis.c (decode_pseudoDEBUG_0): Add space after PRNT.
	405
43a6aa65 MF	406	2011-02-12 Mike Frysinger <vapier@gentoo.org>
	407
	408	* bfin-dis.c (machine_registers): Delete REG_GP.
	409	(reg_names): Delete "GP".
	410	(decode_allregs): Change REG_GP to REG_LASTREG.
	411
26bb3ddd MF	412	2011-02-12 Mike Frysinger <vapier@gentoo.org>
26bb3ddd MF	413
89c0d58c MR	414	* bfin-dis.c (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2,
89c0d58c MR	415	M_IH, M_IU): Delete.
26bb3ddd	416
69b8ea4a MF	417	2011-02-11 Mike Frysinger <vapier@gentoo.org>
	418
	419	* bfin-dis.c (reg_names): Add const.
	420	(decode_dregs_lo, decode_dregs_hi, decode_dregs, decode_dregs_byte,
	421	decode_pregs, decode_iregs, decode_mregs, decode_dpregs, decode_gregs,
	422	decode_regs, decode_regs_lo, decode_regs_hi, decode_statbits,
	423	decode_counters, decode_allregs): Likewise.
	424
42d5f9c6 MS	425	2011-02-09 Michael Snyder <msnyder@vmware.com>
42d5f9c6 MS	426
56300268	427	* i386-dis.c (OP_J): Parenthesize expression to prevent
42d5f9c6 MS	428	truncated addresses.
	429	(print_insn): Fix indentation off-by-one.
	430
4be0c941 NC	431	2011-02-01 Nick Clifton <nickc@redhat.com>
	432
	433	* po/da.po: Updated Danish translation.
	434
6b069ee7 AM	435	2011-01-21 Dave Murphy <davem@devkitpro.org>
	436
	437	* ppc-opc.c (NON32, NO371): Remove PPC_OPCODE_PPCPS.
	438
e3949f17 L	439	2011-01-18 H.J. Lu <hongjiu.lu@intel.com>
	440
	441	* i386-dis.c (sIbT): New.
	442	(b_T_mode): Likewise.
	443	(dis386): Replace sIb with sIbT on "pushT".
	444	(x86_64_table): Replace sIb with Ib on "aam" and "aad".
	445	(OP_sI): Handle b_T_mode. Properly sign-extend byte.
	446
752573b2 JK	447	2011-01-18 Jan Kratochvil <jan.kratochvil@redhat.com>
	448
	449	* i386-init.h: Regenerated.
	450	* i386-tbl.h: Regenerated
	451
2a2a0f38 QN	452	2011-01-17 Quentin Neill <quentin.neill@amd.com>
	453
	454	* i386-dis.c (REG_XOP_TBM_01): New.
	455	(REG_XOP_TBM_02): New.
	456	(reg_table): Add REG_XOP_TBM_01 and REG_XOP_TBM_02 tables.
	457	(xop_table): Redirect to REG_XOP_TBM_01 and REG_XOP_TBM_02
	458	entries, and add bextr instruction.
	459
	460	* i386-gen.c (cpu_flag_init): Add CPU_TBM_FLAGS, CpuTBM.
	461	(cpu_flags): Add CpuTBM.
	462
	463	* i386-opc.h (CpuTBM) New.
	464	(i386_cpu_flags): Add bit cputbm.
	465
	466	* i386-opc.tbl: Add bextr, blcfill, blci, blcic, blcmsk,
	467	blcs, blsfill, blsic, t1mskc, and tzmsk.
	468
90d6ff62 DD	469	2011-01-12 DJ Delorie <dj@redhat.com>
	470
	471	* rx-dis.c (print_insn_rx): Support RX_Operand_TwoReg.
	472
c95354ed MX	473	2011-01-11 Mingjie Xing <mingjie.xing@gmail.com>
	474
	475	* mips-dis.c (print_insn_args): Adjust the value to print the real
	476	offset for "+c" argument.
	477
f7465604 NC	478	2011-01-10 Nick Clifton <nickc@redhat.com>
	479
	480	* po/da.po: Updated Danish translation.
	481
639e30d2 NS	482	2011-01-05 Nathan Sidwell <nathan@codesourcery.com>
	483
	484	* arm-dis.c (thumb32_opcodes): BLX must have bit zero clear.
	485
f12dc422 L	486	2011-01-04 H.J. Lu <hongjiu.lu@intel.com>
	487
	488	* i386-dis.c (REG_VEX_38F3): New.
	489	(PREFIX_0FBC): Likewise.
	490	(PREFIX_VEX_38F2): Likewise.
	491	(PREFIX_VEX_38F3_REG_1): Likewise.
	492	(PREFIX_VEX_38F3_REG_2): Likewise.
	493	(PREFIX_VEX_38F3_REG_3): Likewise.
	494	(PREFIX_VEX_38F7): Likewise.
	495	(VEX_LEN_38F2_P_0): Likewise.
	496	(VEX_LEN_38F3_R_1_P_0): Likewise.
	497	(VEX_LEN_38F3_R_2_P_0): Likewise.
	498	(VEX_LEN_38F3_R_3_P_0): Likewise.
	499	(VEX_LEN_38F7_P_0): Likewise.
	500	(dis386_twobyte): Use PREFIX_0FBC.
	501	(reg_table): Add REG_VEX_38F3.
	502	(prefix_table): Add PREFIX_0FBC, PREFIX_VEX_38F2,
	503	PREFIX_VEX_38F3_REG_1, PREFIX_VEX_38F3_REG_2,
	504	PREFIX_VEX_38F3_REG_3 and PREFIX_VEX_38F7.
	505	(vex_table): Use PREFIX_VEX_38F2, REG_VEX_38F3 and
	506	PREFIX_VEX_38F7.
	507	(vex_len_table): Add VEX_LEN_38F2_P_0, VEX_LEN_38F3_R_1_P_0,
	508	VEX_LEN_38F3_R_2_P_0, VEX_LEN_38F3_R_3_P_0 and
	509	VEX_LEN_38F7_P_0.
	510
	511	* i386-gen.c (cpu_flag_init): Add CPU_BMI_FLAGS.
	512	(cpu_flags): Add CpuBMI.
	513
	514	* i386-opc.h (CpuBMI): New.
	515	(i386_cpu_flags): Add cpubmi.
	516
	517	* i386-opc.tbl: Add andn, bextr, blsi, blsmsk, blsr and tzcnt.
	518	* i386-init.h: Regenerated.
	519	* i386-tbl.h: Likewise.
	520
cb21baef L	521	2011-01-04 H.J. Lu <hongjiu.lu@intel.com>
	522
	523	* i386-dis.c (VexGdq): New.
	524	(OP_VEX): Handle dq_mode.
	525
0db46eb4 L	526	2011-01-01 H.J. Lu <hongjiu.lu@intel.com>
	527
	528	* i386-gen.c (process_copyright): Update copyright to 2011.
	529
9e9e0820	530	For older changes see ChangeLog-2010
252b5132 RH	531	\f
252b5132 RH	532	Local Variables:
2f6d2f85 NC	533	mode: change-log
	534	left-margin: 8
	535	fill-column: 74
252b5132 RH	536	version-control: never
252b5132 RH	537	End: