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ubsan: or1k: left shift of negative value
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
bcd9f578
AM		 12019-12-20 Alan Modra <amodra@gmail.com>
2
3 * or1k-ibld.c: Regenerate.
4
15d2859f
AM		 52019-12-20 Alan Modra <amodra@gmail.com>
6
7 * hppa-dis.c (extract_16, extract_21, print_insn_hppa): Use
8 unsigned variables.
9
000fe1a7
AM		 102019-12-20 Alan Modra <amodra@gmail.com>
11
12 * m68hc11-dis.c (read_memory): Delete forward decls.
13 (print_indexed_operand, print_insn): Likewise.
14 (print_indexed_operand): Formatting. Don't rely on short being
15 exactly 16 bits, make sign extension explicit.
16 (print_insn): Likewise. Avoid signed overflow.
17
f0090188
AM		 182019-12-19 Alan Modra <amodra@gmail.com>
19
20 * vax-dis.c (print_insn_mode): Stop index mode recursion.
21
1d29ab86
DF		 222019-12-19 Dr N.W. Filardo <nwf20@cam.ac.uk>
23
24 PR 25277
25 * microblaze-opcm.h (enum microblaze_instr): Prefix fadd, fmul and
26 fdiv with "mbi_".
27 * microblaze-opc.h (opcodes): Adjust to suit.
28
2480b6fa
AM		 292019-12-18 Alan Modra <amodra@gmail.com>
30
31 * alpha-opc.c (OP): Avoid signed overflow.
32 * arm-dis.c (print_insn): Likewise.
33 * mcore-dis.c (print_insn_mcore): Likewise.
34 * pj-dis.c (get_int): Likewise.
35 * ppc-opc.c (EBD15, EBD15BI): Likewise.
36 * score7-dis.c (s7_print_insn): Likewise.
37 * tic30-dis.c (print_insn_tic30): Likewise.
38 * v850-opc.c (insert_SELID): Likewise.
39 * vax-dis.c (print_insn_vax): Likewise.
40 * arc-ext.c (create_map): Likewise.
41 (struct ExtAuxRegister): Make "address" field unsigned int.
42 (arcExtMap_auxRegName): Pass unsigned address.
43 (dump_ARC_extmap): Adjust.
44 * arc-ext.h (arcExtMap_auxRegName): Update prototype.
45
eb7b5046
AM		 462019-12-17 Alan Modra <amodra@gmail.com>
47
48 * visium-dis.c (print_insn_visium): Avoid signed overflow.
49
29298bf6
AM		 502019-12-17 Alan Modra <amodra@gmail.com>
51
52 * aarch64-opc.c (value_fit_signed_field_p): Avoid signed overflow.
53 (value_fit_unsigned_field_p): Likewise.
54 (aarch64_wide_constant_p): Likewise.
55 (operand_general_constraint_met_p): Likewise.
56 * aarch64-opc.h (aarch64_wide_constant_p): Update prototype.
57
e46d79a7
AM		 582019-12-17 Alan Modra <amodra@gmail.com>
59
60 * nds32-dis.c (nds32_mask_opcode): Avoid signed overflow.
61 (print_insn_nds32): Use uint64_t for "given" and "given1".
62
5b660084
AM		 632019-12-17 Alan Modra <amodra@gmail.com>
64
65 * tic80-dis.c: Delete file.
66 * tic80-opc.c: Delete file.
67 * disassemble.c: Remove tic80 support.
68 * disassemble.h: Likewise.
69 * Makefile.am: Likewise.
70 * configure.ac: Likewise.
71 * Makefile.in: Regenerate.
72 * configure: Regenerate.
73 * po/POTFILES.in: Regenerate.
74
62e65990
AM		 752019-12-17 Alan Modra <amodra@gmail.com>
76
77 * bpf-ibld.c: Regenerate.
78
f81e7e2d
AM		 792019-12-16 Alan Modra <amodra@gmail.com>
80
81 * aarch64-dis.c (sign_extend): Return uint64_t. Rewrite without
82 conditional.
83 (aarch64_ext_imm): Avoid signed overflow.
84
488d02fe
AM		 852019-12-16 Alan Modra <amodra@gmail.com>
86
87 * microblaze-dis.c (read_insn_microblaze): Avoid signed overflow.
88
8a92faab
AM		 892019-12-16 Alan Modra <amodra@gmail.com>
90
91 * nios2-dis.c (nios2_print_insn_arg): Avoid signed overflow
92
e6ced26a
AM		 932019-12-16 Alan Modra <amodra@gmail.com>
94
95 * xstormy16-ibld.c: Regenerate.
96
84e098cd
AM		 972019-12-16 Alan Modra <amodra@gmail.com>
98
99 * score-dis.c (print_insn_score16): Move rpush/rpop imm field
100 value adjustment so that it doesn't affect reg field too.
101
36bd8ea7
AM		 1022019-12-16 Alan Modra <amodra@gmail.com>
103
104 * crx-dis.c (EXTRACT, SBM): Avoid signed overflow.
105 (get_number_of_operands, getargtype, getbits, getregname),
106 (getcopregname, getprocregname, gettrapstring, getcinvstring),
107 (getregliststring, get_word_at_PC, get_words_at_PC, build_mask),
108 (powerof2, match_opcode, make_instruction, print_arguments),
109 (print_arg): Delete forward declarations, moving static to..
110 (getregname, getcopregname, getregliststring): ..these definitions.
111 (build_mask): Return unsigned int mask.
112 (match_opcode): Use unsigned int vars.
113
cedfc774
AM		 1142019-12-16 Alan Modra <amodra@gmail.com>
115
116 * bfin-dis.c (fmtconst, fmtconst_val): Avoid signed overflow.
117
4bdb25fe
AM		 1182019-12-16 Alan Modra <amodra@gmail.com>
119
120 * nds32-dis.c (print_insn16, print_insn32): Remove forward decls.
121 (struct objdump_disasm_info): Delete.
122 (nds32_parse_audio_ext, nds32_parse_opcode): Cast result of
123 N32_IMMS to unsigned before shifting left.
124
cf950fd4
AM		 1252019-12-16 Alan Modra <amodra@gmail.com>
126
127 * moxie-dis.c (INST2OFFSET): Don't left shift a signed value.
128 (print_insn_moxie): Remove unnecessary cast.
129
967354c3
AM		 1302019-12-12 Alan Modra <amodra@gmail.com>
131
132 * csky-dis.c (csky_chars_to_number): Remove abort and unnecessary
133 mask.
134
1d61b032
AM		 1352019-12-11 Alan Modra <amodra@gmail.com>
136
137 * arc-dis.c (BITS): Don't truncate high bits with shifts.
138 * nios2-dis.c (nios2_print_insn_arg): Don't sign extend with shifts.
139 * tic54x-dis.c (print_instruction): Likewise.
140 * tilegx-opc.c (parse_insn_tilegx): Likewise.
141 * tilepro-opc.c (parse_insn_tilepro): Likewise.
142 * visium-dis.c (disassem_class0): Likewise.
143 * pdp11-dis.c (sign_extend): Likewise.
144 (SIGN_BITS): Delete.
145 * epiphany-ibld.c: Regenerate.
146 * lm32-ibld.c: Regenerate.
147 * m32c-ibld.c: Regenerate.
148
5afa80e9
AM		 1492019-12-11 Alan Modra <amodra@gmail.com>
150
151 * ns32k-dis.c (sign_extend): Correct last patch.
152
5c05618a
AM		 1532019-12-11 Alan Modra <amodra@gmail.com>
154
155 * vax-dis.c (NEXTLONG): Avoid signed overflow.
156
2a81ccbb
AM		 1572019-12-11 Alan Modra <amodra@gmail.com>
158
159 * v850-dis.c (get_operand_value): Use unsigned arithmetic. Don't
160 sign extend using shifts.
161
b84f6152
AM		 1622019-12-11 Alan Modra <amodra@gmail.com>
163
164 * tic6x-dis.c (tic6x_extract_32): Avoid signed overflow.
165
66152f16
AM		 1662019-12-11 Alan Modra <amodra@gmail.com>
167
168 * tic4x-dis.c (tic4x_print_register): Formatting. Don't segfault
169 on NULL registertable entry.
170 (tic4x_hash_opcode): Use unsigned arithmetic.
171
205c426a
AM		 1722019-12-11 Alan Modra <amodra@gmail.com>
173
174 * s12z-opc.c (z_decode_signed_value): Avoid signed overflow.
175
fb4cb4e2
AM		 1762019-12-11 Alan Modra <amodra@gmail.com>
177
178 * ns32k-dis.c (bit_extract): Use unsigned arithmetic.
179 (bit_extract_simple, sign_extend): Likewise.
180
96f1f604
AM		 1812019-12-11 Alan Modra <amodra@gmail.com>
182
183 * nios2-dis.c (nios2_print_insn_arg): Use 1u << 31.
184
8c9b4171
AM		 1852019-12-11 Alan Modra <amodra@gmail.com>
186
187 * moxie-dis.c (INST2OFFSET): Don't sign extend using shifts.
188
334175b6
AM		 1892019-12-11 Alan Modra <amodra@gmail.com>
190
191 * m68k-dis.c (COERCE32): Cast value first.
192 (NEXTLONG, NEXTULONG): Avoid signed overflow.
193
f8a87c78
AM		 1942019-12-11 Alan Modra <amodra@gmail.com>
195
196 * h8300-dis.c (extract_immediate): Avoid signed overflow.
197 (bfd_h8_disassemble): Likewise.
198
159653d8
AM		 1992019-12-11 Alan Modra <amodra@gmail.com>
200
201 * d30v-dis.c (print_insn): Make opind unsigned. Don't access
202 past end of operands array.
203
d93bba9e
AM		 2042019-12-11 Alan Modra <amodra@gmail.com>
205
206 * csky-dis.c (csky_chars_to_number): Rewrite. Avoid signed
207 overflow when collecting bytes of a number.
208
c202f69e
AM		 2092019-12-11 Alan Modra <amodra@gmail.com>
210
211 * cris-dis.c (print_with_operands): Avoid signed integer
212 overflow when collecting bytes of a 32-bit integer.
213
0ef562a4
AM		 2142019-12-11 Alan Modra <amodra@gmail.com>
215
216 * cr16-dis.c (EXTRACT, SBM): Rewrite.
217 (cr16_match_opcode): Delete duplicate bcond test.
218
2fd2b153
AM		 2192019-12-11 Alan Modra <amodra@gmail.com>
220
221 * bfin-dis.c (HOST_LONG_WORD_SIZE, XFIELD): Delete.
222 (SIGNBIT): New.
223 (MASKBITS, SIGNEXTEND): Rewrite.
224 (fmtconst): Don't use ? expression now that SIGNEXTEND uses
225 unsigned arithmetic, instead assign result of SIGNEXTEND back
226 to x.
227 (fmtconst_val): Use 1u in shift expression.
228
a11db3e9
AM		 2292019-12-11 Alan Modra <amodra@gmail.com>
230
231 * arc-dis.c (find_format_from_table): Use ull constant when
232 shifting by up to 32.
233
9d48687b
AM		 2342019-12-11 Alan Modra <amodra@gmail.com>
235
236 PR 25270
237 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Return
238 false when field is zero for sve_size_tsz_bhs.
239
b8e61daa
AM		 2402019-12-11 Alan Modra <amodra@gmail.com>
241
242 * epiphany-ibld.c: Regenerate.
243
20135676
AM		 2442019-12-10 Alan Modra <amodra@gmail.com>
245
246 PR 24960
247 * disassemble.c (disassemble_free_target): New function.
248
103ebbc3
AM		 2492019-12-10 Alan Modra <amodra@gmail.com>
250
251 * cgen-dis.in (print_insn_@arch@): Replace insn_sets with private_data.
252 * disassemble.c (disassemble_init_for_target): Likewise.
253 * bpf-dis.c: Regenerate.
254 * epiphany-dis.c: Regenerate.
255 * fr30-dis.c: Regenerate.
256 * frv-dis.c: Regenerate.
257 * ip2k-dis.c: Regenerate.
258 * iq2000-dis.c: Regenerate.
259 * lm32-dis.c: Regenerate.
260 * m32c-dis.c: Regenerate.
261 * m32r-dis.c: Regenerate.
262 * mep-dis.c: Regenerate.
263 * mt-dis.c: Regenerate.
264 * or1k-dis.c: Regenerate.
265 * xc16x-dis.c: Regenerate.
266 * xstormy16-dis.c: Regenerate.
267
6f0e0752
AM		 2682019-12-10 Alan Modra <amodra@gmail.com>
269
270 * ppc-dis.c (private): Delete variable.
271 (get_powerpc_dialect): Don't segfault on NULL info->private_data.
272 (powerpc_init_dialect): Don't use global private.
273
e7c22a69
AM		 2742019-12-10 Alan Modra <amodra@gmail.com>
275
276 * s12z-opc.c: Formatting.
277
0a6aef6b
AM		 2782019-12-08 Alan Modra <amodra@gmail.com>
279
280 * s12z-opc.c (exg_sex_discrim): Don't leak memory on invalid
281 registers.
282
2dc4b12f
JB		 2832019-12-05 Jan Beulich <jbeulich@suse.com>
284
285 * aarch64-tbl.h (aarch64_feature_crypto,
286 aarch64_feature_crypto_v8_2, CRYPTO, CRYPTO_V8_2, CRYP_INSN,
287 CRYPTO_V8_2_INSN): Delete.
288
378fd436
AM		 2892019-12-05 Alan Modra <amodra@gmail.com>
290
291 PR 25249
292 * microblaze-dis.c (NUM_STRBUFS, STRBUF_SIZE): Define.
293 (struct string_buf): New.
294 (strbuf): New function.
295 (get_field): Use strbuf rather than strdup of local temp.
296 (get_field_imm, get_field_imm5, get_field_imm5_mbar): Likewise.
297 (get_field_rfsl, get_field_imm15): Likewise.
298 (get_field_rd, get_field_r1, get_field_r2): Update macros.
299 (get_field_special): Likewise. Don't strcpy spr. Formatting.
300 (print_insn_microblaze): Formatting. Init and pass string_buf to
301 get_field functions.
302
0ba59a29
JB		 3032019-12-04 Jan Beulich <jbeulich@suse.com>
304
305 * i386-opc.tbl (lfs, lgs, lss): Drop No_qSuf.
306 * i386-tbl.h: Re-generate.
307
77ad8092
JB		 3082019-12-04 Jan Beulich <jbeulich@suse.com>
309
310 * i386-dis.c (mod_table): Use Ev instead of Em for movdiri.
311
3036c899
JB		 3122019-12-04 Jan Beulich <jbeulich@suse.com>
313
314 * i386-opc.tbl (push, pop): Drop DefaultSize from GPR-only
315 forms.
316 (xbegin): Drop DefaultSize.
317 * i386-tbl.h: Re-generate.
318
8b301fbb
MI		 3192019-11-22 Mihail Ionescu <mihail.ionescu@arm.com>
320
321 * opcodes/arm-dis.c (arm_opcodes, thumb32_opcodes):
322 Change the coproc CRC conditions to use the extension
323 feature set, second word, base on ARM_EXT2_CRC.
324
6aa385b9
JB		 3252019-11-14 Jan Beulich <jbeulich@suse.com>
326
327 * i386-opc.tbl (syscall, sysret): Drop Cpu64 forms.
328 * i386-tbl.h: Re-generate.
329
0cfa3eb3
JB		 3302019-11-14 Jan Beulich <jbeulich@suse.com>
331
332 * i386-gen.c (opcode_modifiers): Remove JumpDword, JumpByte,
333 JumpInterSegment, and JumpAbsolute entries.
334 * i386-opc.h (JUMP, JUMP_DWORD, JUMP_BYTE, JUMP_INTERSEGMENT,
335 JUMP_ABSOLUTE): Define.
336 (struct i386_opcode_modifier): Extend jump field to 3 bits.
337 Remove jumpdword, jumpbyte, jumpintersegment, and jumpabsolute
338 fields.
339 * i386-opc.tbl (JumpByte, JumpDword, JumpAbsolute,
340 JumpInterSegment): Define.
341 * i386-tbl.h: Re-generate.
342
6f2f06be
JB		 3432019-11-14 Jan Beulich <jbeulich@suse.com>
344
345 * i386-gen.c (operand_type_init): Remove
346 OPERAND_TYPE_JUMPABSOLUTE entry.
347 (opcode_modifiers): Add JumpAbsolute entry.
348 (operand_types): Remove JumpAbsolute entry.
349 * i386-opc.h (JumpAbsolute): Move between enums.
350 (struct i386_opcode_modifier): Add jumpabsolute field.
351 (union i386_operand_type): Remove jumpabsolute field.
352 * i386-opc.tbl (call, lcall, jmp, ljmp): Move JumpAbsolute.
353 * i386-init.h, i386-tbl.h: Re-generate.
354
601e8564
JB		 3552019-11-14 Jan Beulich <jbeulich@suse.com>
356
357 * i386-gen.c (opcode_modifiers): Add AnySize entry.
358 (operand_types): Remove AnySize entry.
359 * i386-opc.h (AnySize): Move between enums.
360 (struct i386_opcode_modifier): Add anysize field.
361 (OTUnused): Un-comment.
362 (union i386_operand_type): Remove anysize field.
363 * i386-opc.tbl (lea, invlpg, clflush, prefetchnta, prefetcht0,
364 prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
365 bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote): Move
366 AnySize.
367 * i386-tbl.h: Re-generate.
368
7722d40a
JW		 3692019-11-12 Nelson Chu <nelson.chu@sifive.com>
370
371 * riscv-opc.c (riscv_insn_types): Replace the INSN_CLASS_I with
372 INSN_CLASS_F and the INSN_CLASS_C with INSN_CLASS_F_AND_C if we
373 use the floating point register (FPR).
374
ce760a76
MI		 3752019-11-12 Mihail Ionescu <mihail.ionescu@arm.com>
376
377 * opcodes/arm-dis.c (mve_opcodes): Enable VMOV imm to vec with
378 cmode 1101.
379 (is_mve_encoding_conflict): Update cmode conflict checks for
380 MVE_VMVN_IMM.
381
51c8edf6
JB		 3822019-11-12 Jan Beulich <jbeulich@suse.com>
383
384 * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_ESSEG
385 entry.
386 (operand_types): Remove EsSeg entry.
387 (main): Replace stale use of OTMax.
388 * i386-opc.h (IS_STRING_ES_OP0, IS_STRING_ES_OP1): Define.
389 (struct i386_opcode_modifier): Expand isstring field to 2 bits.
390 (EsSeg): Delete.
391 (OTUnused): Comment out.
392 (union i386_operand_type): Remove esseg field.
393 * i386-opc.tbl (IsStringEsOp0, IsStringEsOp1): Define.
394 (cmps, scmp, scas, ssca, cmpsd): Add IsStringEsOp0.
395 (ins, movs, smov, movsd): Add IsStringEsOpOp1.
396 (stos, ssto): Add IsStringEsOp0/IsStringEsOpOp1.
397 * i386-init.h, i386-tbl.h: Re-generate.
398
474da251
JB		 3992019-11-12 Jan Beulich <jbeulich@suse.com>
400
401 * i386-gen.c (operand_instances): Add RegB entry.
402 * i386-opc.h (enum operand_instance): Add RegB.
403 * i386-opc.tbl (RegC, RegD, RegB): Define.
404 (Acc, ShiftCount, InOutPortReg): Adjust definitions.
405 (monitor, mwait, invlpga, skinit, vmload, vmrun, vmsave, clzero,
406 monitorx, mwaitx): Drop ImmExt and convert encodings
407 accordingly.
408 * i386-reg.tbl (ecx, rcx): Add Instance=RegC.
409 (edx, rdx): Add Instance=RegD.
410 (ebx, rbx): Add Instance=RegB.
411 * i386-tbl.h: Re-generate.
412
75e5731b
JB		 4132019-11-12 Jan Beulich <jbeulich@suse.com>
414
415 * i386-gen.c (operand_type_init): Adjust
416 OPERAND_TYPE_INOUTPORTREG, OPERAND_TYPE_SHIFTCOUNT,
417 OPERAND_TYPE_FLOATACC, OPERAND_TYPE_ACC8, OPERAND_TYPE_ACC16,
418 OPERAND_TYPE_ACC32, and OPERAND_TYPE_ACC64 entries.
419 (operand_instances): New.
420 (operand_types): Drop InOutPortReg, ShiftCount, and Acc entries.
421 (output_operand_type): New parameter "instance". Process it.
422 (process_i386_operand_type): New local variable "instance".
423 (main): Adjust static assertions.
424 * i386-opc.h (INSTANCE_WIDTH): Define.
425 (enum operand_instance): New.
426 (Acc, InOutPortReg, ShiftCount): Replace by ClassInstance.
427 (union i386_operand_type): Replace acc, inoutportreg, and
428 shiftcount by instance.
429 * i386-opc.tbl (Acc, InOutPortReg, ShiftCount): Define.
430 * i386-reg.tbl (st, al, cl, ax, dx, eax, rax, xmm0, st(0)):
431 Add Instance=.
432 * i386-init.h, i386-tbl.h: Re-generate.
433
91802f3c
JB		 4342019-11-11 Jan Beulich <jbeulich@suse.com>
435
436 * aarch64-tbl.h (aarch64_opcode_table): Switch SVE2's
437 smaxp/sminp entries' "tied_operand" field to 2.
438
4f5fc85d
JB		 4392019-11-11 Jan Beulich <jbeulich@suse.com>
440
441 * aarch64-opc.c (operand_general_constraint_met_p): Replace
442 "index" local variable by that of the already existing "num".
443
dc2be329
L		 4442019-11-08 H.J. Lu <hongjiu.lu@intel.com>
445
446 PR gas/25167
447 * i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd.
448 * i386-tbl.h: Regenerated.
449
f74a6307
JB		 4502019-11-08 Jan Beulich <jbeulich@suse.com>
451
452 * i386-gen.c (operand_type_init): Add Class= to
453 OPERAND_TYPE_REGMASK and OPERAND_TYPE_REGBND entries. Move up
454 OPERAND_TYPE_REGBND entry.
455 (operand_classes): Add RegMask and RegBND entries.
456 (operand_types): Drop RegMask and RegBND entry.
457 * i386-opc.h (enum operand_class): Add RegMask and RegBND.
458 (RegMask, RegBND): Delete.
459 (union i386_operand_type): Remove regmask and regbnd fields.
460 * i386-opc.tbl (RegMask, RegBND): Define.
461 * i386-reg.tbl: Replace RegMask by Class=RegMask and RegBND by
462 Class=RegBND.
463 * i386-init.h, i386-tbl.h: Re-generate.
464
3528c362
JB		 4652019-11-08 Jan Beulich <jbeulich@suse.com>
466
467 * i386-gen.c (operand_type_init): Add Class= to
468 OPERAND_TYPE_REGMMX, OPERAND_TYPE_REGXMM, OPERAND_TYPE_REGYMM, and
469 OPERAND_TYPE_REGZMM entries.
470 (operand_classes): Add RegMMX and RegSIMD entries.
471 (operand_types): Drop RegMMX and RegSIMD entries.
472 * i386-opc.h (enum operand_class): Add RegMMX and RegSIMD.
473 (RegMMX, RegSIMD): Delete.
474 (union i386_operand_type): Remove regmmx and regsimd fields.
475 * i386-opc.tbl (RegMMX): Define.
476 (RegXMM, RegYMM, RegZMM): Add Class=.
477 * i386-reg.tbl: Replace RegMMX by Class=RegMMX and RegSIMD by
478 Class=RegSIMD.
479 * i386-init.h, i386-tbl.h: Re-generate.
480
4a5c67ed
JB		 4812019-11-08 Jan Beulich <jbeulich@suse.com>
482
483 * i386-gen.c (operand_type_init): Add Class= to
484 OPERAND_TYPE_CONTROL, OPERAND_TYPE_TEST, and OPERAND_TYPE_DEBUG
485 entries.
486 (operand_classes): Add RegCR, RegDR, and RegTR entries.
487 (operand_types): Drop Control, Debug, and Test entries.
488 * i386-opc.h (enum operand_class): Add RegCR, RegDR, and RegTR.
489 (Control, Debug, Test): Delete.
490 (union i386_operand_type): Remove control, debug, and test
491 fields.
492 * i386-opc.tbl (Control, Debug, Test): Define.
493 * i386-reg.tbl: Replace Control by Class=RegCR, Debug by
494 Class=RegDR, and Test by Class=RegTR.
495 * i386-init.h, i386-tbl.h: Re-generate.
496
00cee14f
JB		 4972019-11-08 Jan Beulich <jbeulich@suse.com>
498
499 * i386-gen.c (operand_type_init): Add Class= to
500 OPERAND_TYPE_SREG entry.
501 (operand_classes): Add SReg entry.
502 (operand_types): Drop SReg entry.
503 * i386-opc.h (enum operand_class): Add SReg.
504 (SReg): Delete.
505 (union i386_operand_type): Remove sreg field.
506 * i386-opc.tbl (SReg): Define.
507 * i386-reg.tbl: Replace SReg by Class=SReg.
508 * i386-init.h, i386-tbl.h: Re-generate.
509
bab6aec1
JB		 5102019-11-08 Jan Beulich <jbeulich@suse.com>
511
512 * i386-gen.c (operand_type_init): Add Class=. New
513 OPERAND_TYPE_ANYIMM entry.
514 (operand_classes): New.
515 (operand_types): Drop Reg entry.
516 (output_operand_type): New parameter "class". Process it.
517 (process_i386_operand_type): New local variable "class".
518 (main): Adjust static assertions.
519 * i386-opc.h (CLASS_WIDTH): Define.
520 (enum operand_class): New.
521 (Reg): Replace by Class. Adjust comment.
522 (union i386_operand_type): Replace reg by class.
523 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add
524 Class=.
525 * i386-reg.tbl: Replace Reg by Class=Reg.
526 * i386-init.h: Re-generate.
527
1f4cd317
MM		 5282019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
529
530 * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
531 (aarch64_opcode_table): Add data gathering hint mnemonic.
532 * opcodes/aarch64-dis-2.c: Account for new instruction.
533
616ce08e
MM		 5342019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
535
536 * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.
537
538
8382113f
MM		 5392019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
540
541 * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
542 aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
543 aarch64_feature_f64mm): New feature sets.
544 (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
545 F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
546 instructions.
547 (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
548 macros.
549 (QL_MMLA64, OP_SVE_SBB): New qualifiers.
550 (OP_SVE_QQQ): New qualifier.
551 (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
552 F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
553 the movprfx constraint.
554 (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
555 (aarch64_opcode_table): Define new instructions smmla,
556 ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod,
557 uzip{1/2}, trn{1/2}.
558 * aarch64-opc.c (operand_general_constraint_met_p): Handle
559 AARCH64_OPND_SVE_ADDR_RI_S4x32.
560 (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
561 * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
562 Account for new instructions.
563 * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
564 S4x32 operand.
565 * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
566
aab2c27d
MM		 5672019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
5682019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
569
570 * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
571 Armv8.6-A.
572 (coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
573 (neon_opcodes): Add bfloat SIMD instructions.
574 (print_insn_coprocessor): Add new control character %b to print
575 condition code without checking cp_num.
576 (print_insn_neon): Account for BFloat16 instructions that have no
577 special top-byte handling.
578
33593eaf
MM		 5792019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
5802019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
581
582 * arm-dis.c (print_insn_coprocessor,
583 print_insn_generic_coprocessor): Create wrapper functions around
584 the implementation of the print_insn_coprocessor control codes.
585 (print_insn_coprocessor_1): Original print_insn_coprocessor
586 function that now takes which array to look at as an argument.
587 (print_insn_arm): Use both print_insn_coprocessor and
588 print_insn_generic_coprocessor.
589 (print_insn_thumb32): As above.
590
df678013
MM		 5912019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
5922019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
593
594 * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
595 in reglane special case.
596 * aarch64-dis-2.c (aarch64_opcode_lookup_1,
597 aarch64_find_next_opcode): Account for new instructions.
598 * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
599 in reglane special case.
600 * aarch64-opc.c (struct operand_qualifier_data): Add data for
601 new AARCH64_OPND_QLF_S_2H qualifier.
602 * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
603 QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
604 (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
605 sets.
606 (BFLOAT_SVE, BFLOAT): New feature set macros.
607 (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
608 instructions.
609 (aarch64_opcode_table): Define new instructions bfdot,
610 bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
611 bfcvtn2, bfcvt.
612
8ae2d3d9
MM		 6132019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
6142019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
615
616 * aarch64-tbl.h (ARMV8_6): New macro.
617
142861df
JB		 6182019-11-07 Jan Beulich <jbeulich@suse.com>
619
620 * i386-dis.c (prefix_table): Add mcommit.
621 (rm_table): Add rdpru.
622 * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
623 CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
624 (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
625 * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
626 (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
627 * i386-opc.tbl (mcommit, rdpru): New.
628 * i386-init.h, i386-tbl.h: Re-generate.
629
081e283f
JB		 6302019-11-07 Jan Beulich <jbeulich@suse.com>
631
632 * i386-dis.c (OP_Mwait): Drop local variable "names", use
633 "names32" instead.
634 (OP_Monitor): Drop local variable "op1_names", re-purpose
635 "names" for it instead, and replace former "names" uses by
636 "names32" ones.
637
c050c89a
JB		 6382019-11-07 Jan Beulich <jbeulich@suse.com>
639
640 PR/gas 25167
641 * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
642 operand-less forms.
643 * opcodes/i386-tbl.h: Re-generate.
644
7abb8d81
JB		 6452019-11-05 Jan Beulich <jbeulich@suse.com>
646
647 * i386-dis.c (OP_Mwaitx): Delete.
648 (prefix_table): Use OP_Mwait for mwaitx entry.
649 (OP_Mwait): Also handle mwaitx.
650
267b8516
JB		 6512019-11-05 Jan Beulich <jbeulich@suse.com>
652
653 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
654 PREFIX_0F01_REG_7_MOD_3_RM_3): New.
655 (prefix_table): Add respective entries.
656 (rm_table): Link to those entries.
657
f8687e93
JB		 6582019-11-05 Jan Beulich <jbeulich@suse.com>
659
660 * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
661 (REG_0F1C_P_0_MOD_0): ... this.
662 (REG_0F1E_MOD_3): Rename to ...
663 (REG_0F1E_P_1_MOD_3): ... this.
664 (RM_0F01_REG_5): Rename to ...
665 (RM_0F01_REG_5_MOD_3): ... this.
666 (RM_0F01_REG_7): Rename to ...
667 (RM_0F01_REG_7_MOD_3): ... this.
668 (RM_0F1E_MOD_3_REG_7): Rename to ...
669 (RM_0F1E_P_1_MOD_3_REG_7): ... this.
670 (RM_0FAE_REG_6): Rename to ...
671 (RM_0FAE_REG_6_MOD_3_P_0): ... this.
672 (RM_0FAE_REG_7): Rename to ...
673 (RM_0FAE_REG_7_MOD_3): ... this.
674 (PREFIX_MOD_0_0F01_REG_5): Rename to ...
675 (PREFIX_0F01_REG_5_MOD_0): ... this.
676 (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
677 (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
678 (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
679 (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
680 (PREFIX_0FAE_REG_0): Rename to ...
681 (PREFIX_0FAE_REG_0_MOD_3): ... this.
682 (PREFIX_0FAE_REG_1): Rename to ...
683 (PREFIX_0FAE_REG_1_MOD_3): ... this.
684 (PREFIX_0FAE_REG_2): Rename to ...
685 (PREFIX_0FAE_REG_2_MOD_3): ... this.
686 (PREFIX_0FAE_REG_3): Rename to ...
687 (PREFIX_0FAE_REG_3_MOD_3): ... this.
688 (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
689 (PREFIX_0FAE_REG_4_MOD_0): ... this.
690 (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
691 (PREFIX_0FAE_REG_4_MOD_3): ... this.
692 (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
693 (PREFIX_0FAE_REG_5_MOD_0): ... this.
694 (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
695 (PREFIX_0FAE_REG_5_MOD_3): ... this.
696 (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
697 (PREFIX_0FAE_REG_6_MOD_0): ... this.
698 (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
699 (PREFIX_0FAE_REG_6_MOD_3): ... this.
700 (PREFIX_0FAE_REG_7): Rename to ...
701 (PREFIX_0FAE_REG_7_MOD_0): ... this.
702 (PREFIX_MOD_0_0FC3): Rename to ...
703 (PREFIX_0FC3_MOD_0): ... this.
704 (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
705 (PREFIX_0FC7_REG_6_MOD_0): ... this.
706 (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
707 (PREFIX_0FC7_REG_6_MOD_3): ... this.
708 (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
709 (PREFIX_0FC7_REG_7_MOD_3): ... this.
710 (reg_table, prefix_table, mod_table, rm_table): Adjust
711 accordingly.
712
5103274f
NC		 7132019-11-04 Nick Clifton <nickc@redhat.com>
714
715 * v850-dis.c (get_v850_sreg_name): New function. Returns the name
716 of a v850 system register. Move the v850_sreg_names array into
717 this function.
718 (get_v850_reg_name): Likewise for ordinary register names.
719 (get_v850_vreg_name): Likewise for vector register names.
720 (get_v850_cc_name): Likewise for condition codes.
721 * get_v850_float_cc_name): Likewise for floating point condition
722 codes.
723 (get_v850_cacheop_name): Likewise for cache-ops.
724 (get_v850_prefop_name): Likewise for pref-ops.
725 (disassemble): Use the new accessor functions.
726
1820262b
DB		 7272019-10-30 Delia Burduv <delia.burduv@arm.com>
728
729 * aarch64-opc.c (print_immediate_offset_address): Don't print the
730 immediate for the writeback form of ldraa/ldrab if it is 0.
731 * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
732 * aarch64-opc-2.c: Regenerated.
733
3cc17af5
JB		 7342019-10-30 Jan Beulich <jbeulich@suse.com>
735
736 * i386-gen.c (operand_type_shorthands): Delete.
737 (operand_type_init): Expand previous shorthands.
738 (set_bitfield_from_shorthand): Rename back to ...
739 (set_bitfield_from_cpu_flag_init): ... this. Drop processing
740 of operand_type_init[].
741 (set_bitfield): Adjust call to the above function.
742 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
743 RegXMM, RegYMM, RegZMM): Define.
744 * i386-reg.tbl: Expand prior shorthands.
745
a2cebd03
JB		 7462019-10-30 Jan Beulich <jbeulich@suse.com>
747
748 * i386-gen.c (output_i386_opcode): Change order of fields
749 emitted to output.
750 * i386-opc.h (struct insn_template): Move operands field.
751 Convert extension_opcode field to unsigned short.
752 * i386-tbl.h: Re-generate.
753
507916b8
JB		 7542019-10-30 Jan Beulich <jbeulich@suse.com>
755
756 * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
757 of W.
758 * i386-opc.h (W): Extend comment.
759 * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
760 general purpose variants not allowing for byte operands.
761 * i386-tbl.h: Re-generate.
762
efea62b4
NC		 7632019-10-29 Nick Clifton <nickc@redhat.com>
764
765 * tic30-dis.c (print_branch): Correct size of operand array.
766
9adb2591
NC		 7672019-10-29 Nick Clifton <nickc@redhat.com>
768
769 * d30v-dis.c (print_insn): Check that operand index is valid
770 before attempting to access the operands array.
771
993a00a9
NC		 7722019-10-29 Nick Clifton <nickc@redhat.com>
773
774 * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
775 locating the bit to be tested.
776
66a66a17
NC		 7772019-10-29 Nick Clifton <nickc@redhat.com>
778
779 * s12z-dis.c (opr_emit_disassembly): Check for illegal register
780 values.
781 (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
782 (print_insn_s12z): Check for illegal size values.
783
1ee3542c
NC		 7842019-10-28 Nick Clifton <nickc@redhat.com>
785
786 * csky-dis.c (csky_chars_to_number): Check for a negative
787 count. Use an unsigned integer to construct the return value.
788
bbf9a0b5
NC		 7892019-10-28 Nick Clifton <nickc@redhat.com>
790
791 * tic30-dis.c (OPERAND_BUFFER_LEN): Define. Use as length of
792 operand buffer. Set value to 15 not 13.
793 (get_register_operand): Use OPERAND_BUFFER_LEN.
794 (get_indirect_operand): Likewise.
795 (print_two_operand): Likewise.
796 (print_three_operand): Likewise.
797 (print_oar_insn): Likewise.
798
d1e304bc
NC		 7992019-10-28 Nick Clifton <nickc@redhat.com>
800
801 * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
802 (bit_extract_simple): Likewise.
803 (bit_copy): Likewise.
804 (pirnt_insn_ns32k): Ensure that uninitialised elements in the
805 index_offset array are not accessed.
806
dee33451
NC		 8072019-10-28 Nick Clifton <nickc@redhat.com>
808
809 * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
810 operand.
811
27cee81d
NC		 8122019-10-25 Nick Clifton <nickc@redhat.com>
813
814 * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
815 access to opcodes.op array element.
816
de6d8dc2
NC		 8172019-10-23 Nick Clifton <nickc@redhat.com>
818
819 * rx-dis.c (get_register_name): Fix spelling typo in error
820 message.
821 (get_condition_name, get_flag_name, get_double_register_name)
822 (get_double_register_high_name, get_double_register_low_name)
823 (get_double_control_register_name, get_double_condition_name)
824 (get_opsize_name, get_size_name): Likewise.
825
6207ed28
NC		 8262019-10-22 Nick Clifton <nickc@redhat.com>
827
828 * rx-dis.c (get_size_name): New function. Provides safe
829 access to name array.
830 (get_opsize_name): Likewise.
831 (print_insn_rx): Use the accessor functions.
832
12234dfd
NC		 8332019-10-16 Nick Clifton <nickc@redhat.com>
834
835 * rx-dis.c (get_register_name): New function. Provides safe
836 access to name array.
837 (get_condition_name, get_flag_name, get_double_register_name)
838 (get_double_register_high_name, get_double_register_low_name)
839 (get_double_control_register_name, get_double_condition_name):
840 Likewise.
841 (print_insn_rx): Use the accessor functions.
842
1d378749
NC		 8432019-10-09 Nick Clifton <nickc@redhat.com>
844
845 PR 25041
846 * avr-dis.c (avr_operand): Fix construction of address for lds/sts
847 instructions.
848
d241b910
JB		 8492019-10-07 Jan Beulich <jbeulich@suse.com>
850
851 * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
852 (cmpsd): Likewise. Move EsSeg to other operand.
853 * opcodes/i386-tbl.h: Re-generate.
854
f5c5b7c1
AM		 8552019-09-23 Alan Modra <amodra@gmail.com>
856
857 * m68k-dis.c: Include cpu-m68k.h
858
7beeaeb8
AM		 8592019-09-23 Alan Modra <amodra@gmail.com>
860
861 * mips-dis.c: Include elfxx-mips.h. Move "elf-bfd.h" and
862 "elf/mips.h" earlier.
863
3f9aad11
JB		 8642018-09-20 Jan Beulich <jbeulich@suse.com>
865
866 PR gas/25012
867 * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
868 with SReg operand.
869 * i386-tbl.h: Re-generate.
870
fd361982
AM		 8712019-09-18 Alan Modra <amodra@gmail.com>
872
873 * arc-ext.c: Update throughout for bfd section macro changes.
874
e0b2a78c
SM		 8752019-09-18 Simon Marchi <simon.marchi@polymtl.ca>
876
877 * Makefile.in: Re-generate.
878 * configure: Re-generate.
879
7e9ad3a3
JW		 8802019-09-17 Maxim Blinov <maxim.blinov@embecosm.com>
881
882 * riscv-opc.c (riscv_opcodes): Change subset field
883 to insn_class field for all instructions.
884 (riscv_insn_types): Likewise.
885
bb695960
PB		 8862019-09-16 Phil Blundell <pb@pbcl.net>
887
888 * configure: Regenerated.
889
8063ab7e
MV		 8902019-09-10 Miod Vallat <miod@online.fr>
891
892 PR 24982
893 * m68k-opc.c: Correct aliases for tdivsl and tdivul.
894
60391a25
PB		 8952019-09-09 Phil Blundell <pb@pbcl.net>
896
897 binutils 2.33 branch created.
898
f44b758d
NC		 8992019-09-03 Nick Clifton <nickc@redhat.com>
900
901 PR 24961
902 * tic30-dis.c (get_indirect_operand): Check for bufcnt being
903 greater than zero before indexing via (bufcnt -1).
904
1e4b5e7d
NC		 9052019-09-03 Nick Clifton <nickc@redhat.com>
906
907 PR 24958
908 * mmix-dis.c (MAX_REG_NAME_LEN): Define.
909 (MAX_SPEC_REG_NAME_LEN): Define.
910 (struct mmix_dis_info): Use defined constants for array lengths.
911 (get_reg_name): New function.
912 (get_sprec_reg_name): New function.
913 (print_insn_mmix): Use new functions.
914
c4a23bf8
SP		 9152019-08-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
916
917 * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
918 (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
919 (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
920
a051e2f3
KT		 9212019-08-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
922
923 * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
924 tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
925 (aarch64_sys_reg_supported_p): Update checks for the above.
926
08132bdd
SP		 9272019-08-12 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
928
929 * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
930 cases MVE_SQRSHRL and MVE_UQRSHLL.
931 (print_insn_mve): Add case for specifier 'k' to check
932 specific bit of the instruction.
933
d88bdcb4
PA		 9342019-08-07 Phillipe Antoine <p.antoine@catenacyber.fr>
935
936 PR 24854
937 * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
938 encountering an unknown machine type.
939 (print_insn_arc): Handle arc_insn_length returning 0. In error
940 cases return -1 rather than calling abort.
941
bc750500
JB		 9422019-08-07 Jan Beulich <jbeulich@suse.com>
943
944 * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
945 (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
946 IgnoreSize.
947 * i386-tbl.h: Re-generate.
948
23d188c7
BW		 9492019-08-05 Barnaby Wilks <barnaby.wilks@arm.com>
950
951 * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
952 instructions.
953
c0d6f62f
JW		 9542019-07-30 Mel Chen <mel.chen@sifive.com>
955
956 * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
957 fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
958
959 * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
960 fscsr.
961
0f3f7167
CZ		 9622019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
963
964 * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
965 and MPY class instructions.
966 (parse_option): Add nps400 option.
967 (print_arc_disassembler_options): Add nps400 info.
968
7e126ba3
CZ		 9692019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
970
971 * arc-ext-tbl.h (bspeek): Remove it, added to main table.
972 (bspop): Likewise.
973 (modapp): Likewise.
974 * arc-opc.c (RAD_CHK): Add.
975 * arc-tbl.h: Regenerate.
976
a028026d
KT		 9772019-07-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
978
979 * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
980 (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
981
ac79ff9e
NC		 9822019-07-22 Barnaby Wilks <barnaby.wilks@arm.com>
983
984 * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
985 instructions as UNPREDICTABLE.
986
231097b0
JM		 9872019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
988
989 * bpf-desc.c: Regenerated.
990
1d942ae9
JB		 9912019-07-17 Jan Beulich <jbeulich@suse.com>
992
993 * i386-gen.c (static_assert): Define.
994 (main): Use it.
995 * i386-opc.h (Opcode_Modifier_Max): Rename to ...
996 (Opcode_Modifier_Num): ... this.
997 (Mem): Delete.
998
dfd69174
JB		 9992019-07-16 Jan Beulich <jbeulich@suse.com>
1000
1001 * i386-gen.c (operand_types): Move RegMem ...
1002 (opcode_modifiers): ... here.
1003 * i386-opc.h (RegMem): Move to opcode modifer enum.
1004 (union i386_operand_type): Move regmem field ...
1005 (struct i386_opcode_modifier): ... here.
1006 * i386-opc.tbl (RegMem): Define.
1007 (mov, movq): Move RegMem on segment, control, debug, and test
1008 register flavors.
1009 (pextrb): Move RegMem on register only flavors. Add IgnoreSize
1010 to non-SSE2AVX flavor.
1011 (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
1012 Move RegMem on register only flavors. Drop IgnoreSize from
1013 legacy encoding flavors.
1014 (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
1015 flavors.
1016 (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
1017 register only flavors.
1018 (vmovd): Move RegMem and drop IgnoreSize on register only
1019 flavor. Change opcode and operand order to store form.
1020 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
1021
21df382b
JB		 10222019-07-16 Jan Beulich <jbeulich@suse.com>
1023
1024 * i386-gen.c (operand_type_init, operand_types): Replace SReg
1025 entries.
1026 * i386-opc.h (SReg2, SReg3): Replace by ...
1027 (SReg): ... this.
1028 (union i386_operand_type): Replace sreg fields.
1029 * i386-opc.tbl (mov, ): Use SReg.
1030 (push, pop): Likewies. Drop i386 and x86-64 specific segment
1031 register flavors.
1032 * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
1033 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
1034
3719fd55
JM		 10352019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
1036
1037 * bpf-desc.c: Regenerate.
1038 * bpf-opc.c: Likewise.
1039 * bpf-opc.h: Likewise.
1040
92434a14
JM		 10412019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
1042
1043 * bpf-desc.c: Regenerate.
1044 * bpf-opc.c: Likewise.
1045
43dd7626
HPN		 10462019-07-10 Hans-Peter Nilsson <hp@bitrange.com>
1047
1048 * arm-dis.c (print_insn_coprocessor): Rename index to
1049 index_operand.
1050
98602811
JW		 10512019-07-05 Kito Cheng <kito.cheng@sifive.com>
1052
1053 * riscv-opc.c (riscv_insn_types): Add r4 type.
1054
1055 * riscv-opc.c (riscv_insn_types): Add b and j type.
1056
1057 * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
1058 format for sb type and correct s type.
1059
01c1ee4a
RS		 10602019-07-02 Richard Sandiford <richard.sandiford@arm.com>
1061
1062 * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
1063 SVE FMOV alias of FCPY.
1064
83adff69
RS		 10652019-07-02 Richard Sandiford <richard.sandiford@arm.com>
1066
1067 * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
1068 to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
1069
89418844
RS		 10702019-07-02 Richard Sandiford <richard.sandiford@arm.com>
1071
1072 * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
1073 registers in an instruction prefixed by MOVPRFX.
1074
41be57ca
MM		 10752019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
1076
1077 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
1078 sve_size_13 icode to account for variant behaviour of
1079 pmull{t,b}.
1080 * aarch64-dis-2.c: Regenerate.
1081 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
1082 sve_size_13 icode to account for variant behaviour of
1083 pmull{t,b}.
1084 * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
1085 (OP_SVE_VVV_Q_D): Add new qualifier.
1086 (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
1087 (struct aarch64_opcode): Split pmull{t,b} into those requiring
1088 AES and those not.
1089
9d3bf266
JB		 10902019-07-01 Jan Beulich <jbeulich@suse.com>
1091
1092 * opcodes/i386-gen.c (operand_type_init): Remove
1093 OPERAND_TYPE_VEC_IMM4 entry.
1094 (operand_types): Remove Vec_Imm4.
1095 * opcodes/i386-opc.h (Vec_Imm4): Delete.
1096 (union i386_operand_type): Remove vec_imm4.
1097 * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
1098 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
1099
c3949f43
JB		 11002019-07-01 Jan Beulich <jbeulich@suse.com>
1101
1102 * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
1103 vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
1104 rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
1105 vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
1106 xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
1107 monitorx, mwaitx): Drop ImmExt from operand-less forms.
1108 * i386-tbl.h: Re-generate.
1109
5641ec01
JB		 11102019-07-01 Jan Beulich <jbeulich@suse.com>
1111
1112 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
1113 register operands.
1114 * i386-tbl.h: Re-generate.
1115
79dec6b7
JB		 11162019-07-01 Jan Beulich <jbeulich@suse.com>
1117
1118 * i386-opc.tbl (C): New.
1119 (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
1120 pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
1121 por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
1122 cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
1123 pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
1124 cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
1125 cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
1126 vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
1127 vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
1128 vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
1129 vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
1130 vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
1131 vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
1132 vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
1133 vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
1134 vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
1135 vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
1136 vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
1137 vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
1138 vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
1139 vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
1140 vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
1141 vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
1142 vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
1143 vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
1144 vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
1145 flavors.
1146 * i386-tbl.h: Re-generate.
1147
a0a1771e
JB		 11482019-07-01 Jan Beulich <jbeulich@suse.com>
1149
1150 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
1151 register operands.
1152 * i386-tbl.h: Re-generate.
1153
cd546e7b
JB		 11542019-07-01 Jan Beulich <jbeulich@suse.com>
1155
1156 * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
1157 * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
1158 vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
1159 * i386-tbl.h: Re-generate.
1160
e3bba3fc
JB		 11612019-07-01 Jan Beulich <jbeulich@suse.com>
1162
1163 * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
1164 Disp8MemShift from register only templates.
1165 * i386-tbl.h: Re-generate.
1166
36cc073e
JB		 11672019-07-01 Jan Beulich <jbeulich@suse.com>
1168
1169 * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
1170 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
1171 MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
1172 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
1173 EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
1174 EVEX_W_0F11_P_3_M_1): Delete.
1175 (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
1176 EVEX_W_0F11_P_3): New.
1177 * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
1178 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
1179 MOD_EVEX_0F11_PREFIX_3 table entries.
1180 * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
1181 PREFIX_EVEX_0F11 table entries.
1182 * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
1183 EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
1184 EVEX_W_0F11_P_3_M_{0,1} table entries.
1185
219920a7
JB		 11862019-07-01 Jan Beulich <jbeulich@suse.com>
1187
1188 * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
1189 Delete.
1190
e395f487
L		 11912019-06-27 H.J. Lu <hongjiu.lu@intel.com>
1192
1193 PR binutils/24719
1194 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1195 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1196 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1197 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1198 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1199 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1200 EVEX_LEN_0F38C7_R_6_P_2_W_1.
1201 * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
1202 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
1203 PREFIX_EVEX_0F38C6_REG_6 entries.
1204 * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
1205 EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
1206 EVEX_W_0F38C7_R_6_P_2 entries.
1207 * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1208 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1209 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1210 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1211 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1212 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1213 EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
1214
2b7bcc87
JB		 12152019-06-27 Jan Beulich <jbeulich@suse.com>
1216
1217 * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
1218 VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
1219 VEX_LEN_0F2D_P_3): Delete.
1220 (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
1221 vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
1222 (prefix_table): ... here.
1223
c1dc7af5
JB		 12242019-06-27 Jan Beulich <jbeulich@suse.com>
1225
1226 * i386-dis.c (Iq): Delete.
1227 (Id): New.
1228 (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
1229 TBM insns.
1230 (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
1231 vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
1232 (OP_E_memory): Also honor needindex when deciding whether an
1233 address size prefix needs printing.
1234 (OP_I): Remove handling of q_mode. Add handling of d_mode.
1235
d7560e2d
JW		 12362019-06-26 Jim Wilson <jimw@sifive.com>
1237
1238 PR binutils/24739
1239 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
1240 Set info->display_endian to info->endian_code.
1241
2c703856
JB		 12422019-06-25 Jan Beulich <jbeulich@suse.com>
1243
1244 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
1245 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
1246 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
1247 OPERAND_TYPE_ACC64 entries.
1248 * i386-init.h: Re-generate.
1249
54fbadc0
JB		 12502019-06-25 Jan Beulich <jbeulich@suse.com>
1251
1252 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
1253 Delete.
1254 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
1255 of dqa_mode.
1256 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
1257 entries here.
1258 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
1259 entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
1260
a280ab8e
JB		 12612019-06-25 Jan Beulich <jbeulich@suse.com>
1262
1263 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
1264 variables.
1265
e1a1babd
JB		 12662019-06-25 Jan Beulich <jbeulich@suse.com>
1267
1268 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
1269 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
1270 movnti.
d7560e2d 1271 * i386-opc.tbl (movnti): Add IgnoreSize.
e1a1babd
JB		 1272 * i386-tbl.h: Re-generate.
1273
b8364fa7
JB		 12742019-06-25 Jan Beulich <jbeulich@suse.com>
1275
1276 * i386-opc.tbl (and): Mark Imm8S form for optimization.
1277 * i386-tbl.h: Re-generate.
1278
ad692897
L		 12792019-06-21 H.J. Lu <hongjiu.lu@intel.com>
1280
1281 * i386-dis-evex.h: Break into ...
1282 * i386-dis-evex-len.h: New file.
1283 * i386-dis-evex-mod.h: Likewise.
1284 * i386-dis-evex-prefix.h: Likewise.
1285 * i386-dis-evex-reg.h: Likewise.
1286 * i386-dis-evex-w.h: Likewise.
1287 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
1288 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
1289 i386-dis-evex-mod.h.
1290
f0a6222e
L		 12912019-06-19 H.J. Lu <hongjiu.lu@intel.com>
1292
1293 PR binutils/24700
1294 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
1295 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
1296 EVEX_W_0F385B_P_2.
1297 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
1298 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
1299 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
1300 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
1301 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
1302 EVEX_LEN_0F385B_P_2_W_1.
1303 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
1304 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
1305 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
1306 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
1307 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
1308 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
1309 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
1310 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
1311 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
1312 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
1313
6e1c90b7
L		 13142019-06-17 H.J. Lu <hongjiu.lu@intel.com>
1315
1316 PR binutils/24691
1317 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
1318 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
1319 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
1320 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
1321 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
1322 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
1323 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
1324 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
1325 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
1326 EVEX_LEN_0F3A43_P_2_W_1.
1327 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
1328 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
1329 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
1330 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
1331 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
1332 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
1333 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
1334 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
1335 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
1336 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
1337 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
1338 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
1339
bcc5a6eb
NC		 13402019-06-14 Nick Clifton <nickc@redhat.com>
1341
1342 * po/fr.po; Updated French translation.
1343
e4c4ac46
SH		 13442019-06-13 Stafford Horne <shorne@gmail.com>
1345
1346 * or1k-asm.c: Regenerated.
1347 * or1k-desc.c: Regenerated.
1348 * or1k-desc.h: Regenerated.
1349 * or1k-dis.c: Regenerated.
1350 * or1k-ibld.c: Regenerated.
1351 * or1k-opc.c: Regenerated.
1352 * or1k-opc.h: Regenerated.
1353 * or1k-opinst.c: Regenerated.
1354
a0e44ef5
PB		 13552019-06-12 Peter Bergner <bergner@linux.ibm.com>
1356
1357 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
1358
12efd68d
L		 13592019-06-05 H.J. Lu <hongjiu.lu@intel.com>
1360
1361 PR binutils/24633
1362 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
1363 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
1364 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
1365 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
1366 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
1367 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
1368 EVEX_LEN_0F3A1B_P_2_W_1.
1369 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
1370 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
1371 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
1372 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
1373 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
1374 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
1375 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
1376 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
1377
63c6fc6c
L		 13782019-06-04 H.J. Lu <hongjiu.lu@intel.com>
1379
1380 PR binutils/24626
1381 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
1382 EVEX.vvvv when disassembling VEX and EVEX instructions.
1383 (OP_VEX): Set vex.register_specifier to 0 after readding
1384 vex.register_specifier.
1385 (OP_Vex_2src_1): Likewise.
1386 (OP_Vex_2src_2): Likewise.
1387 (OP_LWP_E): Likewise.
1388 (OP_EX_Vex): Don't check vex.register_specifier.
1389 (OP_XMM_Vex): Likewise.
1390
9186c494
L		 13912019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1392 Lili Cui <lili.cui@intel.com>
1393
1394 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
1395 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
1396 instructions.
1397 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
1398 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
1399 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
1400 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
1401 (i386_cpu_flags): Add cpuavx512_vp2intersect.
1402 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
1403 * i386-init.h: Regenerated.
1404 * i386-tbl.h: Likewise.
1405
5d79adc4
L		 14062019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
1407 Lili Cui <lili.cui@intel.com>
1408
1409 * doc/c-i386.texi: Document enqcmd.
1410 * testsuite/gas/i386/enqcmd-intel.d: New file.
1411 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
1412 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
1413 * testsuite/gas/i386/enqcmd.d: Likewise.
1414 * testsuite/gas/i386/enqcmd.s: Likewise.
1415 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
1416 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
1417 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
1418 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
1419 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
1420 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
1421 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
1422 and x86-64-enqcmd.
1423
a9d96ab9
AH		 14242019-06-04 Alan Hayward <alan.hayward@arm.com>
1425
1426 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
1427
4f6d070a
AM		 14282019-06-03 Alan Modra <amodra@gmail.com>
1429
1430 * ppc-dis.c (prefix_opcd_indices): Correct size.
1431
a2f4b66c
L		 14322019-05-28 H.J. Lu <hongjiu.lu@intel.com>
1433
1434 PR gas/24625
1435 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
1436 Disp8ShiftVL.
1437 * i386-tbl.h: Regenerated.
1438
405b5bd8
AM		 14392019-05-24 Alan Modra <amodra@gmail.com>
1440
1441 * po/POTFILES.in: Regenerate.
1442
8acf1435
PB		 14432019-05-24 Peter Bergner <bergner@linux.ibm.com>
1444 Alan Modra <amodra@gmail.com>
1445
1446 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
1447 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
1448 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
1449 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
1450 XTOP>): Define and add entries.
1451 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
1452 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
1453 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
1454 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
1455
dd7efa79
PB		 14562019-05-24 Peter Bergner <bergner@linux.ibm.com>
1457 Alan Modra <amodra@gmail.com>
1458
1459 * ppc-dis.c (ppc_opts): Add "future" entry.
1460 (PREFIX_OPCD_SEGS): Define.
1461 (prefix_opcd_indices): New array.
1462 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
1463 (lookup_prefix): New function.
1464 (print_insn_powerpc): Handle 64-bit prefix instructions.
1465 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
1466 (PMRR, POWERXX): Define.
1467 (prefix_opcodes): New instruction table.
1468 (prefix_num_opcodes): New constant.
1469
79472b45
JM		 14702019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
1471
1472 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
1473 * configure: Regenerated.
1474 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
1475 and cpu/bpf.opc.
1476 (HFILES): Add bpf-desc.h and bpf-opc.h.
1477 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
1478 bpf-ibld.c and bpf-opc.c.
1479 (BPF_DEPS): Define.
1480 * Makefile.in: Regenerated.
1481 * disassemble.c (ARCH_bpf): Define.
1482 (disassembler): Add case for bfd_arch_bpf.
1483 (disassemble_init_for_target): Likewise.
1484 (enum epbf_isa_attr): Define.
1485 * disassemble.h: extern print_insn_bpf.
1486 * bpf-asm.c: Generated.
1487 * bpf-opc.h: Likewise.
1488 * bpf-opc.c: Likewise.
1489 * bpf-ibld.c: Likewise.
1490 * bpf-dis.c: Likewise.
1491 * bpf-desc.h: Likewise.
1492 * bpf-desc.c: Likewise.
1493
ba6cd17f
SD		 14942019-05-21 Sudakshina Das <sudi.das@arm.com>
1495
1496 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
1497 and VMSR with the new operands.
1498
e39c1607
SD		 14992019-05-21 Sudakshina Das <sudi.das@arm.com>
1500
1501 * arm-dis.c (enum mve_instructions): New enum
1502 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
1503 and cneg.
1504 (mve_opcodes): New instructions as above.
1505 (is_mve_encoding_conflict): Add cases for csinc, csinv,
1506 csneg and csel.
1507 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
1508
23d00a41
SD		 15092019-05-21 Sudakshina Das <sudi.das@arm.com>
1510
1511 * arm-dis.c (emun mve_instructions): Updated for new instructions.
1512 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
1513 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
1514 uqshl, urshrl and urshr.
1515 (is_mve_okay_in_it): Add new instructions to TRUE list.
1516 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
1517 (print_insn_mve): Updated to accept new %j,
1518 %<bitfield>m and %<bitfield>n patterns.
1519
cd4797ee
FS		 15202019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
1521
1522 * mips-opc.c (mips_builtin_opcodes): Change source register
1523 constraint for DAUI.
1524
999b073b
NC		 15252019-05-20 Nick Clifton <nickc@redhat.com>
1526
1527 * po/fr.po: Updated French translation.
1528
14b456f2
AV		 15292019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1530 Michael Collison <michael.collison@arm.com>
1531
1532 * arm-dis.c (thumb32_opcodes): Add new instructions.
1533 (enum mve_instructions): Likewise.
1534 (enum mve_undefined): Add new reasons.
1535 (is_mve_encoding_conflict): Handle new instructions.
1536 (is_mve_undefined): Likewise.
1537 (is_mve_unpredictable): Likewise.
1538 (print_mve_undefined): Likewise.
1539 (print_mve_size): Likewise.
1540
f49bb598
AV		 15412019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1542 Michael Collison <michael.collison@arm.com>
1543
1544 * arm-dis.c (thumb32_opcodes): Add new instructions.
1545 (enum mve_instructions): Likewise.
1546 (is_mve_encoding_conflict): Handle new instructions.
1547 (is_mve_undefined): Likewise.
1548 (is_mve_unpredictable): Likewise.
1549 (print_mve_size): Likewise.
1550
56858bea
AV		 15512019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1552 Michael Collison <michael.collison@arm.com>
1553
1554 * arm-dis.c (thumb32_opcodes): Add new instructions.
1555 (enum mve_instructions): Likewise.
1556 (is_mve_encoding_conflict): Likewise.
1557 (is_mve_unpredictable): Likewise.
1558 (print_mve_size): Likewise.
1559
e523f101
AV		 15602019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1561 Michael Collison <michael.collison@arm.com>
1562
1563 * arm-dis.c (thumb32_opcodes): Add new instructions.
1564 (enum mve_instructions): Likewise.
1565 (is_mve_encoding_conflict): Handle new instructions.
1566 (is_mve_undefined): Likewise.
1567 (is_mve_unpredictable): Likewise.
1568 (print_mve_size): Likewise.
1569
66dcaa5d
AV		 15702019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1571 Michael Collison <michael.collison@arm.com>
1572
1573 * arm-dis.c (thumb32_opcodes): Add new instructions.
1574 (enum mve_instructions): Likewise.
1575 (is_mve_encoding_conflict): Handle new instructions.
1576 (is_mve_undefined): Likewise.
1577 (is_mve_unpredictable): Likewise.
1578 (print_mve_size): Likewise.
1579 (print_insn_mve): Likewise.
1580
d052b9b7
AV		 15812019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1582 Michael Collison <michael.collison@arm.com>
1583
1584 * arm-dis.c (thumb32_opcodes): Add new instructions.
1585 (print_insn_thumb32): Handle new instructions.
1586
ed63aa17
AV		 15872019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1588 Michael Collison <michael.collison@arm.com>
1589
1590 * arm-dis.c (enum mve_instructions): Add new instructions.
1591 (enum mve_undefined): Add new reasons.
1592 (is_mve_encoding_conflict): Handle new instructions.
1593 (is_mve_undefined): Likewise.
1594 (is_mve_unpredictable): Likewise.
1595 (print_mve_undefined): Likewise.
1596 (print_mve_size): Likewise.
1597 (print_mve_shift_n): Likewise.
1598 (print_insn_mve): Likewise.
1599
897b9bbc
AV		 16002019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1601 Michael Collison <michael.collison@arm.com>
1602
1603 * arm-dis.c (enum mve_instructions): Add new instructions.
1604 (is_mve_encoding_conflict): Handle new instructions.
1605 (is_mve_unpredictable): Likewise.
1606 (print_mve_rotate): Likewise.
1607 (print_mve_size): Likewise.
1608 (print_insn_mve): Likewise.
1609
1c8f2df8
AV		 16102019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1611 Michael Collison <michael.collison@arm.com>
1612
1613 * arm-dis.c (enum mve_instructions): Add new instructions.
1614 (is_mve_encoding_conflict): Handle new instructions.
1615 (is_mve_unpredictable): Likewise.
1616 (print_mve_size): Likewise.
1617 (print_insn_mve): Likewise.
1618
d3b63143
AV		 16192019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1620 Michael Collison <michael.collison@arm.com>
1621
1622 * arm-dis.c (enum mve_instructions): Add new instructions.
1623 (enum mve_undefined): Add new reasons.
1624 (is_mve_encoding_conflict): Handle new instructions.
1625 (is_mve_undefined): Likewise.
1626 (is_mve_unpredictable): Likewise.
1627 (print_mve_undefined): Likewise.
1628 (print_mve_size): Likewise.
1629 (print_insn_mve): Likewise.
1630
14925797
AV		 16312019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1632 Michael Collison <michael.collison@arm.com>
1633
1634 * arm-dis.c (enum mve_instructions): Add new instructions.
1635 (is_mve_encoding_conflict): Handle new instructions.
1636 (is_mve_undefined): Likewise.
1637 (is_mve_unpredictable): Likewise.
1638 (print_mve_size): Likewise.
1639 (print_insn_mve): Likewise.
1640
c507f10b
AV		 16412019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1642 Michael Collison <michael.collison@arm.com>
1643
1644 * arm-dis.c (enum mve_instructions): Add new instructions.
1645 (enum mve_unpredictable): Add new reasons.
1646 (enum mve_undefined): Likewise.
1647 (is_mve_okay_in_it): Handle new isntructions.
1648 (is_mve_encoding_conflict): Likewise.
1649 (is_mve_undefined): Likewise.
1650 (is_mve_unpredictable): Likewise.
1651 (print_mve_vmov_index): Likewise.
1652 (print_simd_imm8): Likewise.
1653 (print_mve_undefined): Likewise.
1654 (print_mve_unpredictable): Likewise.
1655 (print_mve_size): Likewise.
1656 (print_insn_mve): Likewise.
1657
bf0b396d
AV		 16582019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1659 Michael Collison <michael.collison@arm.com>
1660
1661 * arm-dis.c (enum mve_instructions): Add new instructions.
1662 (enum mve_unpredictable): Add new reasons.
1663 (enum mve_undefined): Likewise.
1664 (is_mve_encoding_conflict): Handle new instructions.
1665 (is_mve_undefined): Likewise.
1666 (is_mve_unpredictable): Likewise.
1667 (print_mve_undefined): Likewise.
1668 (print_mve_unpredictable): Likewise.
1669 (print_mve_rounding_mode): Likewise.
1670 (print_mve_vcvt_size): Likewise.
1671 (print_mve_size): Likewise.
1672 (print_insn_mve): Likewise.
1673
ef1576a1
AV		 16742019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1675 Michael Collison <michael.collison@arm.com>
1676
1677 * arm-dis.c (enum mve_instructions): Add new instructions.
1678 (enum mve_unpredictable): Add new reasons.
1679 (enum mve_undefined): Likewise.
1680 (is_mve_undefined): Handle new instructions.
1681 (is_mve_unpredictable): Likewise.
1682 (print_mve_undefined): Likewise.
1683 (print_mve_unpredictable): Likewise.
1684 (print_mve_size): Likewise.
1685 (print_insn_mve): Likewise.
1686
aef6d006
AV		 16872019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1688 Michael Collison <michael.collison@arm.com>
1689
1690 * arm-dis.c (enum mve_instructions): Add new instructions.
1691 (enum mve_undefined): Add new reasons.
1692 (insns): Add new instructions.
1693 (is_mve_encoding_conflict):
1694 (print_mve_vld_str_addr): New print function.
1695 (is_mve_undefined): Handle new instructions.
1696 (is_mve_unpredictable): Likewise.
1697 (print_mve_undefined): Likewise.
1698 (print_mve_size): Likewise.
1699 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1700 (print_insn_mve): Handle new operands.
1701
04d54ace
AV		 17022019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1703 Michael Collison <michael.collison@arm.com>
1704
1705 * arm-dis.c (enum mve_instructions): Add new instructions.
1706 (enum mve_unpredictable): Add new reasons.
1707 (is_mve_encoding_conflict): Handle new instructions.
1708 (is_mve_unpredictable): Likewise.
1709 (mve_opcodes): Add new instructions.
1710 (print_mve_unpredictable): Handle new reasons.
1711 (print_mve_register_blocks): New print function.
1712 (print_mve_size): Handle new instructions.
1713 (print_insn_mve): Likewise.
1714
9743db03
AV		 17152019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1716 Michael Collison <michael.collison@arm.com>
1717
1718 * arm-dis.c (enum mve_instructions): Add new instructions.
1719 (enum mve_unpredictable): Add new reasons.
1720 (enum mve_undefined): Likewise.
1721 (is_mve_encoding_conflict): Handle new instructions.
1722 (is_mve_undefined): Likewise.
1723 (is_mve_unpredictable): Likewise.
1724 (coprocessor_opcodes): Move NEON VDUP from here...
1725 (neon_opcodes): ... to here.
1726 (mve_opcodes): Add new instructions.
1727 (print_mve_undefined): Handle new reasons.
1728 (print_mve_unpredictable): Likewise.
1729 (print_mve_size): Handle new instructions.
1730 (print_insn_neon): Handle vdup.
1731 (print_insn_mve): Handle new operands.
1732
143275ea
AV		 17332019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1734 Michael Collison <michael.collison@arm.com>
1735
1736 * arm-dis.c (enum mve_instructions): Add new instructions.
1737 (enum mve_unpredictable): Add new values.
1738 (mve_opcodes): Add new instructions.
1739 (vec_condnames): New array with vector conditions.
1740 (mve_predicatenames): New array with predicate suffixes.
1741 (mve_vec_sizename): New array with vector sizes.
1742 (enum vpt_pred_state): New enum with vector predication states.
1743 (struct vpt_block): New struct type for vpt blocks.
1744 (vpt_block_state): Global struct to keep track of state.
1745 (mve_extract_pred_mask): New helper function.
1746 (num_instructions_vpt_block): Likewise.
1747 (mark_outside_vpt_block): Likewise.
1748 (mark_inside_vpt_block): Likewise.
1749 (invert_next_predicate_state): Likewise.
1750 (update_next_predicate_state): Likewise.
1751 (update_vpt_block_state): Likewise.
1752 (is_vpt_instruction): Likewise.
1753 (is_mve_encoding_conflict): Add entries for new instructions.
1754 (is_mve_unpredictable): Likewise.
1755 (print_mve_unpredictable): Handle new cases.
1756 (print_instruction_predicate): Likewise.
1757 (print_mve_size): New function.
1758 (print_vec_condition): New function.
1759 (print_insn_mve): Handle vpt blocks and new print operands.
1760
f08d8ce3
AV		 17612019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1762
1763 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1764 8, 14 and 15 for Armv8.1-M Mainline.
1765
73cd51e5
AV		 17662019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1767 Michael Collison <michael.collison@arm.com>
1768
1769 * arm-dis.c (enum mve_instructions): New enum.
1770 (enum mve_unpredictable): Likewise.
1771 (enum mve_undefined): Likewise.
1772 (struct mopcode32): New struct.
1773 (is_mve_okay_in_it): New function.
1774 (is_mve_architecture): Likewise.
1775 (arm_decode_field): Likewise.
1776 (arm_decode_field_multiple): Likewise.
1777 (is_mve_encoding_conflict): Likewise.
1778 (is_mve_undefined): Likewise.
1779 (is_mve_unpredictable): Likewise.
1780 (print_mve_undefined): Likewise.
1781 (print_mve_unpredictable): Likewise.
1782 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1783 (print_insn_mve): New function.
1784 (print_insn_thumb32): Handle MVE architecture.
1785 (select_arm_features): Force thumb for Armv8.1-m Mainline.
1786
3076e594
NC		 17872019-05-10 Nick Clifton <nickc@redhat.com>
1788
1789 PR 24538
1790 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1791 end of the table prematurely.
1792
387e7624
FS		 17932019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
1794
1795 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1796 macros for R6.
1797
0067be51
AM		 17982019-05-11 Alan Modra <amodra@gmail.com>
1799
1800 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1801 when -Mraw is in effect.
1802
42e6288f
MM		 18032019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1804
1805 * aarch64-dis-2.c: Regenerate.
1806 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1807 (OP_SVE_BBB): New variant set.
1808 (OP_SVE_DDDD): New variant set.
1809 (OP_SVE_HHH): New variant set.
1810 (OP_SVE_HHHU): New variant set.
1811 (OP_SVE_SSS): New variant set.
1812 (OP_SVE_SSSU): New variant set.
1813 (OP_SVE_SHH): New variant set.
1814 (OP_SVE_SBBU): New variant set.
1815 (OP_SVE_DSS): New variant set.
1816 (OP_SVE_DHHU): New variant set.
1817 (OP_SVE_VMV_HSD_BHS): New variant set.
1818 (OP_SVE_VVU_HSD_BHS): New variant set.
1819 (OP_SVE_VVVU_SD_BH): New variant set.
1820 (OP_SVE_VVVU_BHSD): New variant set.
1821 (OP_SVE_VVV_QHD_DBS): New variant set.
1822 (OP_SVE_VVV_HSD_BHS): New variant set.
1823 (OP_SVE_VVV_HSD_BHS2): New variant set.
1824 (OP_SVE_VVV_BHS_HSD): New variant set.
1825 (OP_SVE_VV_BHS_HSD): New variant set.
1826 (OP_SVE_VVV_SD): New variant set.
1827 (OP_SVE_VVU_BHS_HSD): New variant set.
1828 (OP_SVE_VZVV_SD): New variant set.
1829 (OP_SVE_VZVV_BH): New variant set.
1830 (OP_SVE_VZV_SD): New variant set.
1831 (aarch64_opcode_table): Add sve2 instructions.
1832
28ed815a
MM		 18332019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1834
1835 * aarch64-asm-2.c: Regenerated.
1836 * aarch64-dis-2.c: Regenerated.
1837 * aarch64-opc-2.c: Regenerated.
1838 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1839 for SVE_SHLIMM_UNPRED_22.
1840 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1841 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1842 operand.
1843
fd1dc4a0
MM		 18442019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1845
1846 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1847 sve_size_tsz_bhs iclass encode.
1848 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1849 sve_size_tsz_bhs iclass decode.
1850
31e36ab3
MM		 18512019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1852
1853 * aarch64-asm-2.c: Regenerated.
1854 * aarch64-dis-2.c: Regenerated.
1855 * aarch64-opc-2.c: Regenerated.
1856 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1857 for SVE_Zm4_11_INDEX.
1858 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1859 (fields): Handle SVE_i2h field.
1860 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1861 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1862
1be5f94f
MM		 18632019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1864
1865 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1866 sve_shift_tsz_bhsd iclass encode.
1867 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1868 sve_shift_tsz_bhsd iclass decode.
1869
3c17238b
MM		 18702019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1871
1872 * aarch64-asm-2.c: Regenerated.
1873 * aarch64-dis-2.c: Regenerated.
1874 * aarch64-opc-2.c: Regenerated.
1875 * aarch64-asm.c (aarch64_ins_sve_shrimm):
1876 (aarch64_encode_variant_using_iclass): Handle
1877 sve_shift_tsz_hsd iclass encode.
1878 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1879 sve_shift_tsz_hsd iclass decode.
1880 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1881 for SVE_SHRIMM_UNPRED_22.
1882 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1883 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1884 operand.
1885
cd50a87a
MM		 18862019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1887
1888 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1889 sve_size_013 iclass encode.
1890 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1891 sve_size_013 iclass decode.
1892
3c705960
MM		 18932019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1894
1895 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1896 sve_size_bh iclass encode.
1897 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1898 sve_size_bh iclass decode.
1899
0a57e14f
MM		 19002019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1901
1902 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1903 sve_size_sd2 iclass encode.
1904 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1905 sve_size_sd2 iclass decode.
1906 * aarch64-opc.c (fields): Handle SVE_sz2 field.
1907 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1908
c469c864
MM		 19092019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1910
1911 * aarch64-asm-2.c: Regenerated.
1912 * aarch64-dis-2.c: Regenerated.
1913 * aarch64-opc-2.c: Regenerated.
1914 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1915 for SVE_ADDR_ZX.
1916 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1917 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1918
116adc27
MM		 19192019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1920
1921 * aarch64-asm-2.c: Regenerated.
1922 * aarch64-dis-2.c: Regenerated.
1923 * aarch64-opc-2.c: Regenerated.
1924 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1925 for SVE_Zm3_11_INDEX.
1926 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1927 (fields): Handle SVE_i3l and SVE_i3h2 fields.
1928 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1929 fields.
1930 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1931
3bd82c86
MM		 19322019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1933
1934 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1935 sve_size_hsd2 iclass encode.
1936 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1937 sve_size_hsd2 iclass decode.
1938 * aarch64-opc.c (fields): Handle SVE_size field.
1939 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1940
adccc507
MM		 19412019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1942
1943 * aarch64-asm-2.c: Regenerated.
1944 * aarch64-dis-2.c: Regenerated.
1945 * aarch64-opc-2.c: Regenerated.
1946 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1947 for SVE_IMM_ROT3.
1948 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1949 (fields): Handle SVE_rot3 field.
1950 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1951 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1952
5cd99750
MM		 19532019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1954
1955 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1956 instructions.
1957
7ce2460a
MM		 19582019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1959
1960 * aarch64-tbl.h
1961 (aarch64_feature_sve2, aarch64_feature_sve2aes,
1962 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1963 aarch64_feature_sve2bitperm): New feature sets.
1964 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1965 for feature set addresses.
1966 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1967 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1968
41cee089
FS		 19692019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
1970 Faraz Shahbazker <fshahbazker@wavecomp.com>
1971
1972 * mips-dis.c (mips_calculate_combination_ases): Add ISA
1973 argument and set ASE_EVA_R6 appropriately.
1974 (set_default_mips_dis_options): Pass ISA to above.
1975 (parse_mips_dis_option): Likewise.
1976 * mips-opc.c (EVAR6): New macro.
1977 (mips_builtin_opcodes): Add llwpe, scwpe.
1978
b83b4b13
SD		 19792019-05-01 Sudakshina Das <sudi.das@arm.com>
1980
1981 * aarch64-asm-2.c: Regenerated.
1982 * aarch64-dis-2.c: Regenerated.
1983 * aarch64-opc-2.c: Regenerated.
1984 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1985 AARCH64_OPND_TME_UIMM16.
1986 (aarch64_print_operand): Likewise.
1987 * aarch64-tbl.h (QL_IMM_NIL): New.
1988 (TME): New.
1989 (_TME_INSN): New.
1990 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1991
4a90ce95
JD		 19922019-04-29 John Darrington <john@darrington.wattle.id.au>
1993
1994 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1995
a45328b9
AB		 19962019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
1997 Faraz Shahbazker <fshahbazker@wavecomp.com>
1998
1999 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
2000
d10be0cb
JD		 20012019-04-24 John Darrington <john@darrington.wattle.id.au>
2002
2003 * s12z-opc.h: Add extern "C" bracketing to help
2004 users who wish to use this interface in c++ code.
2005
a679f24e
JD		 20062019-04-24 John Darrington <john@darrington.wattle.id.au>
2007
2008 * s12z-opc.c (bm_decode): Handle bit map operations with the
2009 "reserved0" mode.
2010
32c36c3c
AV		 20112019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
2012
2013 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
2014 specifier. Add entries for VLDR and VSTR of system registers.
2015 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
2016 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
2017 of %J and %K format specifier.
2018
efd6b359
AV		 20192019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
2020
2021 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
2022 Add new entries for VSCCLRM instruction.
2023 (print_insn_coprocessor): Handle new %C format control code.
2024
6b0dd094
AV		 20252019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
2026
2027 * arm-dis.c (enum isa): New enum.
2028 (struct sopcode32): New structure.
2029 (coprocessor_opcodes): change type of entries to struct sopcode32 and
2030 set isa field of all current entries to ANY.
2031 (print_insn_coprocessor): Change type of insn to struct sopcode32.
2032 Only match an entry if its isa field allows the current mode.
2033
4b5a202f
AV		 20342019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
2035
2036 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
2037 CLRM.
2038 (print_insn_thumb32): Add logic to print %n CLRM register list.
2039
60f993ce
AV		 20402019-04-15 Sudakshina Das <sudi.das@arm.com>
2041
2042 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
2043 and %Q patterns.
2044
f6b2b12d
AV		 20452019-04-15 Sudakshina Das <sudi.das@arm.com>
2046
2047 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
2048 (print_insn_thumb32): Edit the switch case for %Z.
2049
1889da70
AV		 20502019-04-15 Sudakshina Das <sudi.das@arm.com>
2051
2052 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
2053
65d1bc05
AV		 20542019-04-15 Sudakshina Das <sudi.das@arm.com>
2055
2056 * arm-dis.c (thumb32_opcodes): New instruction bfl.
2057
1caf72a5
AV		 20582019-04-15 Sudakshina Das <sudi.das@arm.com>
2059
2060 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
2061
f1c7f421
AV		 20622019-04-15 Sudakshina Das <sudi.das@arm.com>
2063
2064 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
2065 Arm register with r13 and r15 unpredictable.
2066 (thumb32_opcodes): New instructions for bfx and bflx.
2067
4389b29a
AV		 20682019-04-15 Sudakshina Das <sudi.das@arm.com>
2069
2070 * arm-dis.c (thumb32_opcodes): New instructions for bf.
2071
e5d6e09e
AV		 20722019-04-15 Sudakshina Das <sudi.das@arm.com>
2073
2074 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
2075
e12437dc
AV		 20762019-04-15 Sudakshina Das <sudi.das@arm.com>
2077
2078 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
2079
031254f2
AV		 20802019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
2081
2082 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
2083
e5a557ac
JD		 20842019-04-12 John Darrington <john@darrington.wattle.id.au>
2085
2086 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
2087 "optr". ("operator" is a reserved word in c++).
2088
bd7ceb8d
SD		 20892019-04-11 Sudakshina Das <sudi.das@arm.com>
2090
2091 * aarch64-opc.c (aarch64_print_operand): Add case for
2092 AARCH64_OPND_Rt_SP.
2093 (verify_constraints): Likewise.
2094 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
2095 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
2096 to accept Rt|SP as first operand.
2097 (AARCH64_OPERANDS): Add new Rt_SP.
2098 * aarch64-asm-2.c: Regenerated.
2099 * aarch64-dis-2.c: Regenerated.
2100 * aarch64-opc-2.c: Regenerated.
2101
e54010f1
SD		 21022019-04-11 Sudakshina Das <sudi.das@arm.com>
2103
2104 * aarch64-asm-2.c: Regenerated.
2105 * aarch64-dis-2.c: Likewise.
2106 * aarch64-opc-2.c: Likewise.
2107 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
2108
7e96e219
RS		 21092019-04-09 Robert Suchanek <robert.suchanek@mips.com>
2110
2111 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
2112
6f2791d5
L		 21132019-04-08 H.J. Lu <hongjiu.lu@intel.com>
2114
2115 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
2116 * i386-init.h: Regenerated.
2117
e392bad3
AM		 21182019-04-07 Alan Modra <amodra@gmail.com>
2119
2120 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
2121 op_separator to control printing of spaces, comma and parens
2122 rather than need_comma, need_paren and spaces vars.
2123
dffaa15c
AM		 21242019-04-07 Alan Modra <amodra@gmail.com>
2125
2126 PR 24421
2127 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
2128 (print_insn_neon, print_insn_arm): Likewise.
2129
d6aab7a1
XG		 21302019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
2131
2132 * i386-dis-evex.h (evex_table): Updated to support BF16
2133 instructions.
2134 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
2135 and EVEX_W_0F3872_P_3.
2136 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
2137 (cpu_flags): Add bitfield for CpuAVX512_BF16.
2138 * i386-opc.h (enum): Add CpuAVX512_BF16.
2139 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
2140 * i386-opc.tbl: Add AVX512 BF16 instructions.
2141 * i386-init.h: Regenerated.
2142 * i386-tbl.h: Likewise.
2143
66e85460
AM		 21442019-04-05 Alan Modra <amodra@gmail.com>
2145
2146 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
2147 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
2148 to favour printing of "-" branch hint when using the "y" bit.
2149 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
2150
c2b1c275
AM		 21512019-04-05 Alan Modra <amodra@gmail.com>
2152
2153 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
2154 opcode until first operand is output.
2155
aae9718e
PB		 21562019-04-04 Peter Bergner <bergner@linux.ibm.com>
2157
2158 PR gas/24349
2159 * ppc-opc.c (valid_bo_pre_v2): Add comments.
2160 (valid_bo_post_v2): Add support for 'at' branch hints.
2161 (insert_bo): Only error on branch on ctr.
2162 (get_bo_hint_mask): New function.
2163 (insert_boe): Add new 'branch_taken' formal argument. Add support
2164 for inserting 'at' branch hints.
2165 (extract_boe): Add new 'branch_taken' formal argument. Add support
2166 for extracting 'at' branch hints.
2167 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
2168 (BOE): Delete operand.
2169 (BOM, BOP): New operands.
2170 (RM): Update value.
2171 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
2172 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
2173 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
2174 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
2175 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
2176 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
2177 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
2178 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
2179 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
2180 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
2181 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
2182 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
2183 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
2184 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
2185 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
2186 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
2187 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
2188 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
2189 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
2190 bttarl+>: New extended mnemonics.
2191
96a86c01
AM		 21922019-03-28 Alan Modra <amodra@gmail.com>
2193
2194 PR 24390
2195 * ppc-opc.c (BTF): Define.
2196 (powerpc_opcodes): Use for mtfsb*.
2197 * ppc-dis.c (print_insn_powerpc): Print fields with both
2198 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
2199
796d6298
TC		 22002019-03-25 Tamar Christina <tamar.christina@arm.com>
2201
2202 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
2203 (mapping_symbol_for_insn): Implement new algorithm.
2204 (print_insn): Remove duplicate code.
2205
60df3720
TC		 22062019-03-25 Tamar Christina <tamar.christina@arm.com>
2207
2208 * aarch64-dis.c (print_insn_aarch64):
2209 Implement override.
2210
51457761
TC		 22112019-03-25 Tamar Christina <tamar.christina@arm.com>
2212
2213 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
2214 order.
2215
53b2f36b
TC		 22162019-03-25 Tamar Christina <tamar.christina@arm.com>
2217
2218 * aarch64-dis.c (last_stop_offset): New.
2219 (print_insn_aarch64): Use stop_offset.
2220
89199bb5
L		 22212019-03-19 H.J. Lu <hongjiu.lu@intel.com>
2222
2223 PR gas/24359
2224 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
2225 CPU_ANY_AVX2_FLAGS.
2226 * i386-init.h: Regenerated.
2227
97ed31ae
L		 22282019-03-18 H.J. Lu <hongjiu.lu@intel.com>
2229
2230 PR gas/24348
2231 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
2232 vmovdqu16, vmovdqu32 and vmovdqu64.
2233 * i386-tbl.h: Regenerated.
2234
0919bfe9
AK		 22352019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
2236
2237 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
2238 from vstrszb, vstrszh, and vstrszf.
2239
22402019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
2241
2242 * s390-opc.txt: Add instruction descriptions.
2243
21820ebe
JW		 22442019-02-08 Jim Wilson <jimw@sifive.com>
2245
2246 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
2247 <bne>: Likewise.
2248
f7dd2fb2
TC		 22492019-02-07 Tamar Christina <tamar.christina@arm.com>
2250
2251 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
2252
6456d318
TC		 22532019-02-07 Tamar Christina <tamar.christina@arm.com>
2254
2255 PR binutils/23212
2256 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
2257 * aarch64-opc.c (verify_elem_sd): New.
2258 (fields): Add FLD_sz entr.
2259 * aarch64-tbl.h (_SIMD_INSN): New.
2260 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
2261 fmulx scalar and vector by element isns.
2262
4a83b610
NC		 22632019-02-07 Nick Clifton <nickc@redhat.com>
2264
2265 * po/sv.po: Updated Swedish translation.
2266
fc60b8c8
AK		 22672019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
2268
2269 * s390-mkopc.c (main): Accept arch13 as cpu string.
2270 * s390-opc.c: Add new instruction formats and instruction opcode
2271 masks.
2272 * s390-opc.txt: Add new arch13 instructions.
2273
e10620d3
TC		 22742019-01-25 Sudakshina Das <sudi.das@arm.com>
2275
2276 * aarch64-tbl.h (QL_LDST_AT): Update macro.
2277 (aarch64_opcode): Change encoding for stg, stzg
2278 st2g and st2zg.
2279 * aarch64-asm-2.c: Regenerated.
2280 * aarch64-dis-2.c: Regenerated.
2281 * aarch64-opc-2.c: Regenerated.
2282
20a4ca55
SD		 22832019-01-25 Sudakshina Das <sudi.das@arm.com>
2284
2285 * aarch64-asm-2.c: Regenerated.
2286 * aarch64-dis-2.c: Likewise.
2287 * aarch64-opc-2.c: Likewise.
2288 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
2289
550fd7bf
SD		 22902019-01-25 Sudakshina Das <sudi.das@arm.com>
2291 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
2292
2293 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
2294 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
2295 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
2296 * aarch64-dis.h (ext_addr_simple_2): Likewise.
2297 * aarch64-opc.c (operand_general_constraint_met_p): Remove
2298 case for ldstgv_indexed.
2299 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
2300 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
2301 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
2302 * aarch64-asm-2.c: Regenerated.
2303 * aarch64-dis-2.c: Regenerated.
2304 * aarch64-opc-2.c: Regenerated.
2305
d9938630
NC		 23062019-01-23 Nick Clifton <nickc@redhat.com>
2307
2308 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2309
375cd423
NC		 23102019-01-21 Nick Clifton <nickc@redhat.com>
2311
2312 * po/de.po: Updated German translation.
2313 * po/uk.po: Updated Ukranian translation.
2314
57299f48
CX		 23152019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
2316 * mips-dis.c (mips_arch_choices): Fix typo in
2317 gs464, gs464e and gs264e descriptors.
2318
f48dfe41
NC		 23192019-01-19 Nick Clifton <nickc@redhat.com>
2320
2321 * configure: Regenerate.
2322 * po/opcodes.pot: Regenerate.
2323
f974f26c
NC		 23242018-06-24 Nick Clifton <nickc@redhat.com>
2325
2326 2.32 branch created.
2327
39f286cd
JD		 23282019-01-09 John Darrington <john@darrington.wattle.id.au>
2329
448b8ca8
JD		 2330 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
2331 if it is null.
2332 -dis.c (opr_emit_disassembly): Do not omit an index if it is
39f286cd
JD		 2333 zero.
2334
3107326d
AP		 23352019-01-09 Andrew Paprocki <andrew@ishiboo.com>
2336
2337 * configure: Regenerate.
2338
7e9ca91e
AM		 23392019-01-07 Alan Modra <amodra@gmail.com>
2340
2341 * configure: Regenerate.
2342 * po/POTFILES.in: Regenerate.
2343
ef1ad42b
JD		 23442019-01-03 John Darrington <john@darrington.wattle.id.au>
2345
2346 * s12z-opc.c: New file.
2347 * s12z-opc.h: New file.
2348 * s12z-dis.c: Removed all code not directly related to display
2349 of instructions. Used the interface provided by the new files
2350 instead.
2351 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
7e9ca91e 2352 * Makefile.in: Regenerate.
ef1ad42b 2353 * configure.ac (bfd_s12z_arch): Correct the dependencies.
7e9ca91e 2354 * configure: Regenerate.
ef1ad42b 2355
82704155
AM		 23562019-01-01 Alan Modra <amodra@gmail.com>
2357
2358 Update year range in copyright notice of all files.
2359
d5c04e1b 2360For older changes see ChangeLog-2018
3499769a 2361\f
d5c04e1b 2362Copyright (C) 2019 Free Software Foundation, Inc.
3499769a
AM		 2363
2364Copying and distribution of this file, with or without modification,
2365are permitted in any medium without royalty provided the copyright
2366notice and this notice are preserved.
2367
2368Local Variables:
2369mode: change-log
2370left-margin: 8
2371fill-column: 74
2372version-control: never
2373End:
GDB Binutils - Deliverables
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