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[ARM] Add ARMv8.3 VCMLA and VCADD instructions
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
c28eeff2
SN		 12016-12-05 Szabolcs Nagy <szabolcs.nagy@arm.com>
2
3 * arm-dis.c (coprocessor_opcodes): Add vcmla and vcadd.
4 (print_insn_coprocessor): Add 'V' format for neon D or Q regs.
5
49e8a725
SN		 62016-12-05 Szabolcs Nagy <szabolcs.nagy@arm.com>
7
8 * arm-dis.c (coprocessor_opcodes): Add vjcvt.
9
a37a2806
NC		 102016-12-01 Nick Clifton <nickc@redhat.com>
11
12 PR binutils/20893
13 * i386-dis.c (OP_VEX): Replace call to abort with a append of bad
14 opcode designator.
15
abe7c33b
CZ		 162016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
17
18 * arc-opc.c (insert_ra_chk): New function.
19 (insert_rb_chk): Likewise.
20 (insert_rad): Update text error message.
21 (insert_rcd): Likewise.
22 (insert_rhv2): Likewise.
23 (insert_r0): Likewise.
24 (insert_r1): Likewise.
25 (insert_r2): Likewise.
26 (insert_r3): Likewise.
27 (insert_sp): Likewise.
28 (insert_gp): Likewise.
29 (insert_pcl): Likewise.
30 (insert_blink): Likewise.
31 (insert_ilink1): Likewise.
32 (insert_ilink2): Likewise.
33 (insert_ras): Likewise.
34 (insert_rbs): Likewise.
35 (insert_rcs): Likewise.
36 (insert_simm3s): Likewise.
37 (insert_rrange): Likewise.
38 (insert_fpel): Likewise.
39 (insert_blinkel): Likewise.
40 (insert_pcel): Likewise.
41 (insert_nps_3bit_dst): Likewise.
42 (insert_nps_3bit_dst_short): Likewise.
43 (insert_nps_3bit_src2_short): Likewise.
44 (insert_nps_bitop_size_2b): Likewise.
45 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Likewise.
46 (RA_CHK): Define.
47 (RB): Adjust.
48 (RB_CHK): Define.
49 (RC): Adjust.
50 * arc-dis.c (print_insn_arc): Add LOAD and STORE class.
51 * arc-tbl.h (div, divu): All instructions are DIVREM class.
52 Change first insn argument to check for LP_COUNT usage.
53 (rem): Likewise.
54 (ld, ldd): All instructions are LOAD class. Change first insn
55 argument to check for LP_COUNT usage.
56 (st, std): All instructions are STORE class.
57 (mac, mpy, dmac, mul, dmpy): All instructions are MPY class.
58 Change first insn argument to check for LP_COUNT usage.
59 (mov): All instructions are MOVE class. Change first insn
60 argument to check for LP_COUNT usage.
61
ee881e5d
CZ		 622016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
63
64 * arc-dis.c (is_compatible_p): Remove function.
65 (skip_this_opcode): Don't add any decoding class to decode list.
66 Remove warning.
67 (find_format_from_table): Go through all opcodes, and warn if we
68 use a guessed mnemonic.
69
abfcb414
AP		 702016-11-28 Ramiro Polla <ramiro@hex-rays.com>
71 Amit Pawar <amit.pawar@amd.com>
72
73 PR binutils/20637
74 * i386-dis.c (get_valid_dis386): Ignore REX_B for 32-bit XOP
75 instructions.
76
96fe4562
AM		 772016-11-22 Ambrogino Modigliani <ambrogino.modigliani@gmail.com>
78
79 * configure: Regenerate.
80
6884417a
JM		 812016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com>
82
83 * sparc-opc.c (HWS_V8): Definition moved from
84 gas/config/tc-sparc.c.
85 (HWS_V9): Likewise.
86 (HWS_VA): Likewise.
87 (HWS_VB): Likewise.
88 (HWS_VC): Likewise.
89 (HWS_VD): Likewise.
90 (HWS_VE): Likewise.
91 (HWS_VV): Likewise.
92 (HWS_VM): Likewise.
93 (HWS2_VM): Likewise.
94 (sparc_opcode_archs): Initialize hwcaps and hwcaps2 fields of
95 existing entries.
96
c4b943d7
CZ		 972016-11-22 Claudiu Zissulescu <claziss@synopsys.com>
98
99 * arc-tbl.h: Reorder conditional flags with delay flags for 'b'
100 instructions.
101
c2c4ff8d
SN		 1022016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
103
104 * aarch64-tbl.h (QL_V3SAMEHSD_ROT, QL_ELEMENT_ROT): Define.
105 (aarch64_feature_simd_v8_3, SIMD_V8_3): Define.
106 (aarch64_opcode_table): Add fcmla and fcadd.
107 (AARCH64_OPERANDS): Add IMM_ROT{1,2,3}.
108 * aarch64-asm.h (aarch64_ins_imm_rotate): Declare.
109 * aarch64-asm.c (aarch64_ins_imm_rotate): Define.
110 * aarch64-dis.h (aarch64_ext_imm_rotate): Declare.
111 * aarch64-dis.c (aarch64_ext_imm_rotate): Define.
112 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_rotate{1,2,3}.
113 * aarch64-opc.c (fields): Add FLD_rotate{1,2,3}.
114 (operand_general_constraint_met_p): Rotate and index range check.
115 (aarch64_print_operand): Handle rotate operand.
116 * aarch64-asm-2.c: Regenerate.
117 * aarch64-dis-2.c: Likewise.
118 * aarch64-opc-2.c: Likewise.
119
28617675
SN		 1202016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
121
122 * aarch64-tbl.h (arch64_opcode_table): Add ldaprb, ldaprh, ldapr.
123 * aarch64-asm-2.c: Regenerate.
124 * aarch64-dis-2.c: Regenerate.
125 * aarch64-opc-2.c: Regenerate.
126
ccfc90a3
SN		 1272016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
128
129 * aarch64-tbl.h (arch64_opcode_table): Add fjcvtzs.
130 (QL_FP2INT_W_D, aarch64_feature_fp_v8_3, FP_V8_3): Define.
131 * aarch64-asm-2.c: Regenerate.
132 * aarch64-dis-2.c: Regenerate.
133 * aarch64-opc-2.c: Regenerate.
134
3f06e550
SN		 1352016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
136
137 * aarch64-tbl.h (QL_X1NIL): New.
138 (arch64_opcode_table): Add ldraa, ldrab.
139 (AARCH64_OPERANDS): Add "ADDR_SIMM10".
140 * aarch64-asm.h (aarch64_ins_addr_simm10): Declare.
141 * aarch64-asm.c (aarch64_ins_addr_simm10): Define.
142 * aarch64-dis.h (aarch64_ext_addr_simm10): Declare.
143 * aarch64-dis.c (aarch64_ext_addr_simm10): Define.
144 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_S_simm10.
145 * aarch64-opc.c (fields): Add data for FLD_S_simm10.
146 (operand_general_constraint_met_p): Handle AARCH64_OPND_ADDR_SIMM10.
147 (aarch64_print_operand): Likewise.
148 * aarch64-asm-2.c: Regenerate.
149 * aarch64-dis-2.c: Regenerate.
150 * aarch64-opc-2.c: Regenerate.
151
74f5402d
SN		 1522016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
153
154 * aarch64-tbl.h (arch64_opcode_table): Add braa, brab, blraa, blrab, braaz,
155 brabz, blraaz, blrabz, retaa, retab, eretaa, eretab.
156 * aarch64-asm-2.c: Regenerate.
157 * aarch64-dis-2.c: Regenerate.
158 * aarch64-opc-2.c: Regenerate.
159
c84364ec
SN		 1602016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
161
162 * aarch64-tbl.h (arch64_opcode_table): Add pacga.
163 (AARCH64_OPERANDS): Add Rm_SP.
164 * aarch64-opc.c (aarch64_print_operand): Handle AARCH64_OPND_Rm_SP.
165 * aarch64-asm-2.c: Regenerate.
166 * aarch64-dis-2.c: Regenerate.
167 * aarch64-opc-2.c: Regenerate.
168
a2cfc830
SN		 1692016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
170
171 * aarch64-tbl.h (arch64_opcode_table): Add pacia, pacib, pacda, pacdb, autia,
172 autib, autda, autdb, paciza, pacizb, pacdza, pacdzb, autiza, autizb, autdza,
173 autdzb, xpaci, xpacd.
174 * aarch64-asm-2.c: Regenerate.
175 * aarch64-dis-2.c: Regenerate.
176 * aarch64-opc-2.c: Regenerate.
177
b0bfa7b5
SN		 1782016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
179
180 * aarch64-opc.c (aarch64_sys_regs): Add apiakeylo_el1, apiakeyhi_el1,
181 apibkeylo_el1, apibkeyhi_el1, apdakeylo_el1, apdakeyhi_el1,
182 apdbkeylo_el1, apdbkeyhi_el1, apgakeylo_el1 and apgakeyhi_el1.
183 (aarch64_sys_reg_supported_p): Add feature test for new registers.
184
8787d804
SN		 1852016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
186
187 * aarch64-tbl.h (aarch64_feature_v8_3, ARMV8_3, V8_3_INSN): New.
188 (arch64_opcode_table): Add xpaclri, pacia1716, pacib1716, autia1716,
189 autib1716, paciaz, paciasp, pacibz, pacibsp, autiaz, autiasp, autibz,
190 autibsp.
191 * aarch64-asm-2.c: Regenerate.
192 * aarch64-dis-2.c: Regenerate.
193
3d731f69
SN		 1942016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
195
196 * aarch64-gen.c (find_alias_opcode): Increase max_num_aliases to 32.
197
60227d64
L		 1982016-11-09 H.J. Lu <hongjiu.lu@intel.com>
199
200 PR binutils/20799
201 * i386-dis-evex.h (evex_table): Replace EdqwS with Edqw.
202 * i386-dis.c (EdqwS): Removed.
203 (dqw_swap_mode): Likewise.
204 (intel_operand_size): Don't check dqw_swap_mode.
205 (OP_E_register): Likewise.
206 (OP_E_memory): Likewise.
207 (OP_G): Likewise.
208 (OP_EX): Likewise.
209 * i386-opc.tbl: Remove "S" from EVEX vpextrw.
210 * i386-tbl.h: Regerated.
211
7efeed17
L		 2122016-11-09 H.J. Lu <hongjiu.lu@intel.com>
213
214 * i386-opc.tbl: Merge AVX512F vmovq.
1032d6eb 215 * i386-tbl.h: Regerated.
7efeed17 216
1f334aeb
L		 2172016-11-08 H.J. Lu <hongjiu.lu@intel.com>
218
219 PR binutils/20701
220 * i386-dis.c (THREE_BYTE_0F7A): Removed.
221 (dis386_twobyte): Don't use THREE_BYTE_0F7A.
222 (three_byte_table): Remove THREE_BYTE_0F7A.
223
48c97fa1
L		 2242016-11-07 H.J. Lu <hongjiu.lu@intel.com>
225
226 PR binutils/20775
227 * i386-dis.c (FGRPd9_2): Replace 0 with 1.
228 (FGRPd9_4): Replace 1 with 2.
229 (FGRPd9_5): Replace 2 with 3.
230 (FGRPd9_6): Replace 3 with 4.
231 (FGRPd9_7): Replace 4 with 5.
232 (FGRPda_5): Replace 5 with 6.
233 (FGRPdb_4): Replace 6 with 7.
234 (FGRPde_3): Replace 7 with 8.
235 (FGRPdf_4): Replace 8 with 9.
236 (fgrps): Add an entry for Bad_Opcode.
237
b437d035
AB		 2382016-11-04 Andrew Burgess <andrew.burgess@embecosm.com>
239
240 * arc-opc.c (arc_flag_operands): Add F_DI14.
241 (arc_flag_classes): Add C_DI14.
242 * arc-nps400-tbl.h: Add new exc instructions.
243
5a736821
GM		 2442016-11-03 Graham Markall <graham.markall@embecosm.com>
245
246 * arc-dis.c (arc_insn_length): Return length 8 for instructions with
247 major opcode 0xa.
248 * arc-nps-400-tbl.h: Add dcmac instruction.
249 * arc-opc.c (arc_operands): Added operands for dcmac instruction.
250 (insert_nps_rbdouble_64): Added.
251 (extract_nps_rbdouble_64): Added.
252 (insert_nps_proto_size): Added.
253 (extract_nps_proto_size): Added.
254
bdfe53e3
AB		 2552016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
256
257 * arc-dis.c (struct arc_operand_iterator): Remove all fields
258 relating to long instruction processing, add new limm field.
259 (OPCODE): Rename to...
260 (OPCODE_32BIT_INSN): ...this.
261 (OPCODE_AC): Delete.
262 (skip_this_opcode): Handle different instruction lengths, update
263 macro name.
264 (special_flag_p): Update parameter type.
265 (find_format_from_table): Update for more instruction lengths.
266 (find_format_long_instructions): Delete.
267 (find_format): Update for more instruction lengths.
268 (arc_insn_length): Likewise.
269 (extract_operand_value): Update for more instruction lengths.
270 (operand_iterator_next): Remove code relating to long
271 instructions.
272 (arc_opcode_to_insn_type): New function.
273 (print_insn_arc):Update for more instructions lengths.
274 * arc-ext.c (extInstruction_t): Change argument type.
275 * arc-ext.h (extInstruction_t): Change argument type.
276 * arc-fxi.h: Change type unsigned to unsigned long long
277 extensively throughout.
278 * arc-nps400-tbl.h: Add long instructions taken from
279 arc_long_opcodes table in arc-opc.c.
280 * arc-opc.c: Update parameter types on insert/extract handlers.
281 (arc_long_opcodes): Delete.
282 (arc_num_long_opcodes): Delete.
283 (arc_opcode_len): Update for more instruction lengths.
284
90f61cce
GM		 2852016-11-03 Graham Markall <graham.markall@embecosm.com>
286
287 * arc-dis.c (print_insn_arc): Swap highbyte and lowbyte.
288
06fe285f
GM		 2892016-11-03 Graham Markall <graham.markall@embecosm.com>
290
291 * arc-dis.c (find_format_from_table): Replace use of ARC_SHORT
292 with arc_opcode_len.
293 (find_format_long_instructions): Likewise.
294 * arc-opc.c (arc_opcode_len): New function.
295
ecf64ec6
AB		 2962016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
297
298 * arc-nps400-tbl.h: Fix some instruction masks.
299
d039fef3
L		 3002016-11-03 H.J. Lu <hongjiu.lu@intel.com>
301
302 * i386-dis.c (REG_82): Removed.
303 (X86_64_82_REG_0): Likewise.
304 (X86_64_82_REG_1): Likewise.
305 (X86_64_82_REG_2): Likewise.
306 (X86_64_82_REG_3): Likewise.
307 (X86_64_82_REG_4): Likewise.
308 (X86_64_82_REG_5): Likewise.
309 (X86_64_82_REG_6): Likewise.
310 (X86_64_82_REG_7): Likewise.
311 (X86_64_82): New.
312 (dis386): Use X86_64_82 instead of REG_82.
313 (reg_table): Remove REG_82.
314 (x86_64_table): Add X86_64_82. Remove X86_64_82_REG_0,
315 X86_64_82_REG_1, X86_64_82_REG_2, X86_64_82_REG_3,
316 X86_64_82_REG_4, X86_64_82_REG_5, X86_64_82_REG_6 and
317 X86_64_82_REG_7.
318
8b89fe14
L		 3192016-11-03 H.J. Lu <hongjiu.lu@intel.com>
320
321 PR binutils/20754
322 * i386-dis.c (REG_82): New.
323 (X86_64_82_REG_0): Likewise.
324 (X86_64_82_REG_1): Likewise.
325 (X86_64_82_REG_2): Likewise.
326 (X86_64_82_REG_3): Likewise.
327 (X86_64_82_REG_4): Likewise.
328 (X86_64_82_REG_5): Likewise.
329 (X86_64_82_REG_6): Likewise.
330 (X86_64_82_REG_7): Likewise.
331 (dis386): Use REG_82.
332 (reg_table): Add REG_82.
333 (x86_64_table): Add X86_64_82_REG_0, X86_64_82_REG_1,
334 X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4,
335 X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7.
336
7148c369
L		 3372016-11-03 H.J. Lu <hongjiu.lu@intel.com>
338
339 * i386-dis.c (REG_82): Renamed to ...
340 (REG_83): This.
341 (dis386): Updated.
342 (reg_table): Likewise.
343
47acf0bd
IT		 3442016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
345
346 * i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853.
347 * i386-dis-evex.h (evex_table): Updated.
348 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS,
349 CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
350 (cpu_flags): Add CpuAVX512_4VNNIW.
351 * i386-opc.h (enum): (AVX512_4VNNIW): New.
352 (i386_cpu_flags): Add cpuavx512_4vnniw.
353 * i386-opc.tbl: Add Intel AVX512_4VNNIW instructions.
354 * i386-init.h: Regenerate.
355 * i386-tbl.h: Ditto.
356
920d2ddc
IT		 3572016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
358
359 * i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,
360 PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.
361 * i386-dis-evex.h (evex_table): Updated.
362 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,
363 CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
364 (cpu_flags): Add CpuAVX512_4FMAPS.
365 (opcode_modifiers): Add ImplicitQuadGroup modifier.
366 * i386-opc.h (AVX512_4FMAP): New.
367 (i386_cpu_flags): Add cpuavx512_4fmaps.
368 (ImplicitQuadGroup): New.
369 (i386_opcode_modifier): Add implicitquadgroup.
370 * i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.
371 * i386-init.h: Regenerate.
372 * i386-tbl.h: Ditto.
373
e23eba97
NC		 3742016-11-01 Palmer Dabbelt <palmer@dabbelt.com>
375 Andrew Waterman <andrew@sifive.com>
376
377 Add support for RISC-V architecture.
378 * configure.ac: Add entry for bfd_riscv_arch.
379 * configure: Regenerate.
380 * disassemble.c (disassembler): Add support for riscv.
381 (disassembler_usage): Likewise.
382 * riscv-dis.c: New file.
383 * riscv-opc.c: New file.
384
b5cefcca
L		 3852016-10-21 H.J. Lu <hongjiu.lu@intel.com>
386
387 * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
388 (prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
389 (rm_table): Update the RM_0FAE_REG_7 entry.
390 * i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
391 (cpu_flags): Remove CpuPCOMMIT.
392 * i386-opc.h (CpuPCOMMIT): Removed.
393 (i386_cpu_flags): Remove cpupcommit.
394 * i386-opc.tbl: Remove pcommit.
395 * i386-init.h: Regenerated.
396 * i386-tbl.h: Likewise.
397
9889cbb1
L		 3982016-10-20 H.J. Lu <hongjiu.lu@intel.com>
399
400 PR binutis/20705
401 * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
402 the highest bit in VEX.vvvv for the 3-byte VEX prefix in
403 32-bit mode. Don't check vex.register_specifier in 32-bit
404 mode.
405 (OP_VEX): Check for invalid mask registers.
406
28596323
L		 4072016-10-18 H.J. Lu <hongjiu.lu@intel.com>
408
409 PR binutis/20699
410 * i386-dis.c (OP_E_memory): Check addr32flag in stead of
411 sizeflag.
412
da8d7d66
L		 4132016-10-18 H.J. Lu <hongjiu.lu@intel.com>
414
415 PR binutis/20704
416 * i386-dis.c (three_byte_table): Remove the remaining SSE5 support.
417
eaf02703
MR		 4182016-10-18 Maciej W. Rozycki <macro@imgtec.com>
419
420 * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'
421 local variable to `index_regno'.
422
decf5bd1
CM		 4232016-10-17 Cupertino Miranda <cmiranda@synopsys.com>
424
425 * arc-tbl.h: Removed any "inv.+" instructions from the table.
426
e5b06ef0
CZ		 4272016-10-14 Claudiu Zissulescu <claziss@synopsys.com>
428
429 * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
430 usage on ISA basis.
431
93562a34
JW		 4322016-10-11 Jiong Wang <jiong.wang@arm.com>
433
434 PR target/20666
435 * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
436
362c0c4d
JW		 4372016-10-07 Jiong Wang <jiong.wang@arm.com>
438
439 PR target/20667
440 * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
441 available.
442
1047201f
AM		 4432016-10-07 Alan Modra <amodra@gmail.com>
444
445 * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
446
1a0670f3
AM		 4472016-10-06 Alan Modra <amodra@gmail.com>
448
449 * aarch64-opc.c: Spell fall through comments consistently.
450 * i386-dis.c: Likewise.
451 * aarch64-dis.c: Add missing fall through comments.
452 * aarch64-opc.c: Likewise.
453 * arc-dis.c: Likewise.
454 * arm-dis.c: Likewise.
455 * i386-dis.c: Likewise.
456 * m68k-dis.c: Likewise.
457 * mep-asm.c: Likewise.
458 * ns32k-dis.c: Likewise.
459 * sh-dis.c: Likewise.
460 * tic4x-dis.c: Likewise.
461 * tic6x-dis.c: Likewise.
462 * vax-dis.c: Likewise.
463
2b804145
AM		 4642016-10-06 Alan Modra <amodra@gmail.com>
465
466 * arc-ext.c (create_map): Add missing break.
467 * msp430-decode.opc (encode_as): Likewise.
468 * msp430-decode.c: Regenerate.
469
616ec358
AM		 4702016-10-06 Alan Modra <amodra@gmail.com>
471
472 * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
473 * crx-dis.c (print_insn_crx): Likewise.
474
72da393d
L		 4752016-09-30 H.J. Lu <hongjiu.lu@intel.com>
476
477 PR binutils/20657
478 * i386-dis.c (putop): Don't assign alt twice.
479
744ce302
JW		 4802016-09-29 Jiong Wang <jiong.wang@arm.com>
481
482 PR target/20553
483 * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
484
a5721ba2
AM		 4852016-09-29 Alan Modra <amodra@gmail.com>
486
487 * ppc-opc.c (L): Make compulsory.
488 (LOPT): New, optional form of L.
489 (HTM_R): Define as LOPT.
490 (L0, L1): Delete.
491 (L32OPT): New, optional for 32-bit L.
492 (L2OPT): New, 2-bit L for dcbf.
493 (SVC_LEC): Update.
494 (L2): Define.
495 (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
496 (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
497 <dcbf>: Use L2OPT.
498 <tlbiel, tlbie>: Use LOPT.
499 <wclr, wclrall>: Use L2.
500
c5da1932
VZ		 5012016-09-26 Vlad Zakharov <vzakhar@synopsys.com>
502
503 * Makefile.in: Regenerate.
504 * configure: Likewise.
505
2b848ebd
CZ		 5062016-09-26 Claudiu Zissulescu <claziss@synopsys.com>
507
508 * arc-ext-tbl.h (EXTINSN2OPF): Define.
509 (EXTINSN2OP): Use EXTINSN2OPF.
510 (bspeekm, bspop, modapp): New extension instructions.
511 * arc-opc.c (F_DNZ_ND): Define.
512 (F_DNZ_D): Likewise.
513 (F_SIZEB1): Changed.
514 (C_DNZ_D): Define.
515 (C_HARD): Changed.
516 * arc-tbl.h (dbnz): New instruction.
517 (prealloc): Allow it for ARC EM.
518 (xbfu): Likewise.
519
ad43e107
RS		 5202016-09-21 Richard Sandiford <richard.sandiford@arm.com>
521
522 * aarch64-opc.c (print_immediate_offset_address): Print spaces
523 after commas in addresses.
524 (aarch64_print_operand): Likewise.
525
ab3b8fcf
RS		 5262016-09-21 Richard Sandiford <richard.sandiford@arm.com>
527
528 * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
529 rather than "should be" or "expected to be" in error messages.
530
bb7eff52
RS		 5312016-09-21 Richard Sandiford <richard.sandiford@arm.com>
532
533 * aarch64-dis.c (remove_dot_suffix): New function, split out from...
534 (print_mnemonic_name): ...here.
535 (print_comment): New function.
536 (print_aarch64_insn): Call it.
537 * aarch64-opc.c (aarch64_conds): Add SVE names.
538 (aarch64_print_operand): Print alternative condition names in
539 a comment.
540
c0890d26
RS		 5412016-09-21 Richard Sandiford <richard.sandiford@arm.com>
542
543 * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
544 (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
545 (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
546 (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
547 (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
548 (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
549 (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
550 (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
551 (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
552 (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
553 (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
554 (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
555 (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
556 (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
557 (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
558 (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
559 (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
560 (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
561 (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
562 (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
563 (OP_SVE_XWU, OP_SVE_XXU): New macros.
564 (aarch64_feature_sve): New variable.
565 (SVE): New macro.
566 (_SVE_INSN): Likewise.
567 (aarch64_opcode_table): Add SVE instructions.
568 * aarch64-opc.h (extract_fields): Declare.
569 * aarch64-opc-2.c: Regenerate.
570 * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
571 * aarch64-asm-2.c: Regenerate.
572 * aarch64-dis.c (extract_fields): Make global.
573 (do_misc_decoding): Handle the new SVE aarch64_ops.
574 * aarch64-dis-2.c: Regenerate.
575
116b6019
RS		 5762016-09-21 Richard Sandiford <richard.sandiford@arm.com>
577
578 * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
579 (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
580 aarch64_field_kinds.
581 * aarch64-opc.c (fields): Add corresponding entries.
582 * aarch64-asm.c (aarch64_get_variant): New function.
583 (aarch64_encode_variant_using_iclass): Likewise.
584 (aarch64_opcode_encode): Call it.
585 * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
586 (aarch64_opcode_decode): Call it.
587
047cd301
RS		 5882016-09-21 Richard Sandiford <richard.sandiford@arm.com>
589
590 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
591 and FP register operands.
592 * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
593 (FLD_SVE_Vn): New aarch64_field_kinds.
594 * aarch64-opc.c (fields): Add corresponding entries.
595 (aarch64_print_operand): Handle the new SVE core and FP register
596 operands.
597 * aarch64-opc-2.c: Regenerate.
598 * aarch64-asm-2.c: Likewise.
599 * aarch64-dis-2.c: Likewise.
600
165d4950
RS		 6012016-09-21 Richard Sandiford <richard.sandiford@arm.com>
602
603 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
604 immediate operands.
605 * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
606 * aarch64-opc.c (fields): Add corresponding entry.
607 (operand_general_constraint_met_p): Handle the new SVE FP immediate
608 operands.
609 (aarch64_print_operand): Likewise.
610 * aarch64-opc-2.c: Regenerate.
611 * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
612 (ins_sve_float_zero_one): New inserters.
613 * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
614 (aarch64_ins_sve_float_half_two): Likewise.
615 (aarch64_ins_sve_float_zero_one): Likewise.
616 * aarch64-asm-2.c: Regenerate.
617 * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
618 (ext_sve_float_zero_one): New extractors.
619 * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
620 (aarch64_ext_sve_float_half_two): Likewise.
621 (aarch64_ext_sve_float_zero_one): Likewise.
622 * aarch64-dis-2.c: Regenerate.
623
e950b345
RS		 6242016-09-21 Richard Sandiford <richard.sandiford@arm.com>
625
626 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
627 integer immediate operands.
628 * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
629 (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
630 (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
631 * aarch64-opc.c (fields): Add corresponding entries.
632 (operand_general_constraint_met_p): Handle the new SVE integer
633 immediate operands.
634 (aarch64_print_operand): Likewise.
635 (aarch64_sve_dupm_mov_immediate_p): New function.
636 * aarch64-opc-2.c: Regenerate.
637 * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
638 (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
639 * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
640 (aarch64_ins_limm): ...here.
641 (aarch64_ins_inv_limm): New function.
642 (aarch64_ins_sve_aimm): Likewise.
643 (aarch64_ins_sve_asimm): Likewise.
644 (aarch64_ins_sve_limm_mov): Likewise.
645 (aarch64_ins_sve_shlimm): Likewise.
646 (aarch64_ins_sve_shrimm): Likewise.
647 * aarch64-asm-2.c: Regenerate.
648 * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
649 (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
650 * aarch64-dis.c (decode_limm): New function, split out from...
651 (aarch64_ext_limm): ...here.
652 (aarch64_ext_inv_limm): New function.
653 (decode_sve_aimm): Likewise.
654 (aarch64_ext_sve_aimm): Likewise.
655 (aarch64_ext_sve_asimm): Likewise.
656 (aarch64_ext_sve_limm_mov): Likewise.
657 (aarch64_top_bit): Likewise.
658 (aarch64_ext_sve_shlimm): Likewise.
659 (aarch64_ext_sve_shrimm): Likewise.
660 * aarch64-dis-2.c: Regenerate.
661
98907a70
RS		 6622016-09-21 Richard Sandiford <richard.sandiford@arm.com>
663
664 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
665 operands.
666 * aarch64-opc.c (aarch64_operand_modifiers): Initialize
667 the AARCH64_MOD_MUL_VL entry.
668 (value_aligned_p): Cope with non-power-of-two alignments.
669 (operand_general_constraint_met_p): Handle the new MUL VL addresses.
670 (print_immediate_offset_address): Likewise.
671 (aarch64_print_operand): Likewise.
672 * aarch64-opc-2.c: Regenerate.
673 * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
674 (ins_sve_addr_ri_s9xvl): New inserters.
675 * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
676 (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
677 (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
678 * aarch64-asm-2.c: Regenerate.
679 * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
680 (ext_sve_addr_ri_s9xvl): New extractors.
681 * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
682 (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
683 (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
684 (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
685 * aarch64-dis-2.c: Regenerate.
686
4df068de
RS		 6872016-09-21 Richard Sandiford <richard.sandiford@arm.com>
688
689 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
690 address operands.
691 * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
692 (FLD_SVE_xs_22): New aarch64_field_kinds.
693 (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
694 (get_operand_specific_data): New function.
695 * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
696 FLD_SVE_xs_14 and FLD_SVE_xs_22.
697 (operand_general_constraint_met_p): Handle the new SVE address
698 operands.
699 (sve_reg): New array.
700 (get_addr_sve_reg_name): New function.
701 (aarch64_print_operand): Handle the new SVE address operands.
702 * aarch64-opc-2.c: Regenerate.
703 * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
704 (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
705 (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
706 * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
707 (aarch64_ins_sve_addr_rr_lsl): Likewise.
708 (aarch64_ins_sve_addr_rz_xtw): Likewise.
709 (aarch64_ins_sve_addr_zi_u5): Likewise.
710 (aarch64_ins_sve_addr_zz): Likewise.
711 (aarch64_ins_sve_addr_zz_lsl): Likewise.
712 (aarch64_ins_sve_addr_zz_sxtw): Likewise.
713 (aarch64_ins_sve_addr_zz_uxtw): Likewise.
714 * aarch64-asm-2.c: Regenerate.
715 * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
716 (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
717 (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
718 * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
719 (aarch64_ext_sve_addr_ri_u6): Likewise.
720 (aarch64_ext_sve_addr_rr_lsl): Likewise.
721 (aarch64_ext_sve_addr_rz_xtw): Likewise.
722 (aarch64_ext_sve_addr_zi_u5): Likewise.
723 (aarch64_ext_sve_addr_zz): Likewise.
724 (aarch64_ext_sve_addr_zz_lsl): Likewise.
725 (aarch64_ext_sve_addr_zz_sxtw): Likewise.
726 (aarch64_ext_sve_addr_zz_uxtw): Likewise.
727 * aarch64-dis-2.c: Regenerate.
728
2442d846
RS		 7292016-09-21 Richard Sandiford <richard.sandiford@arm.com>
730
731 * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
732 AARCH64_OPND_SVE_PATTERN_SCALED.
733 * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
734 * aarch64-opc.c (fields): Add a corresponding entry.
735 (set_multiplier_out_of_range_error): New function.
736 (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
737 (operand_general_constraint_met_p): Handle
738 AARCH64_OPND_SVE_PATTERN_SCALED.
739 (print_register_offset_address): Use PRIi64 to print the
740 shift amount.
741 (aarch64_print_operand): Likewise. Handle
742 AARCH64_OPND_SVE_PATTERN_SCALED.
743 * aarch64-opc-2.c: Regenerate.
744 * aarch64-asm.h (ins_sve_scale): New inserter.
745 * aarch64-asm.c (aarch64_ins_sve_scale): New function.
746 * aarch64-asm-2.c: Regenerate.
747 * aarch64-dis.h (ext_sve_scale): New inserter.
748 * aarch64-dis.c (aarch64_ext_sve_scale): New function.
749 * aarch64-dis-2.c: Regenerate.
750
245d2e3f
RS		 7512016-09-21 Richard Sandiford <richard.sandiford@arm.com>
752
753 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
754 AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
755 * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
756 (FLD_SVE_prfop): Likewise.
757 * aarch64-opc.c: Include libiberty.h.
758 (aarch64_sve_pattern_array): New variable.
759 (aarch64_sve_prfop_array): Likewise.
760 (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
761 (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
762 AARCH64_OPND_SVE_PRFOP.
763 * aarch64-asm-2.c: Regenerate.
764 * aarch64-dis-2.c: Likewise.
765 * aarch64-opc-2.c: Likewise.
766
d50c751e
RS		 7672016-09-21 Richard Sandiford <richard.sandiford@arm.com>
768
769 * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
770 AARCH64_OPND_QLF_P_[ZM].
771 (aarch64_print_operand): Print /z and /m where appropriate.
772
f11ad6bc
RS		 7732016-09-21 Richard Sandiford <richard.sandiford@arm.com>
774
775 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
776 * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
777 (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
778 (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
779 (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
780 * aarch64-opc.c (fields): Add corresponding entries here.
781 (operand_general_constraint_met_p): Check that SVE register lists
782 have the correct length. Check the ranges of SVE index registers.
783 Check for cases where p8-p15 are used in 3-bit predicate fields.
784 (aarch64_print_operand): Handle the new SVE operands.
785 * aarch64-opc-2.c: Regenerate.
786 * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
787 * aarch64-asm.c (aarch64_ins_sve_index): New function.
788 (aarch64_ins_sve_reglist): Likewise.
789 * aarch64-asm-2.c: Regenerate.
790 * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
791 * aarch64-dis.c (aarch64_ext_sve_index): New function.
792 (aarch64_ext_sve_reglist): Likewise.
793 * aarch64-dis-2.c: Regenerate.
794
0c608d6b
RS		 7952016-09-21 Richard Sandiford <richard.sandiford@arm.com>
796
797 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
798 (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
799 (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
800 * aarch64-opc.c (aarch64_match_operands_constraint): Check for
801 tied operands.
802
01dbfe4c
RS		 8032016-09-21 Richard Sandiford <richard.sandiford@arm.com>
804
805 * aarch64-opc.c (get_offset_int_reg_name): New function.
806 (print_immediate_offset_address): Likewise.
807 (print_register_offset_address): Take the base and offset
808 registers as parameters.
809 (aarch64_print_operand): Update caller accordingly. Use
810 print_immediate_offset_address.
811
72e9f319
RS		 8122016-09-21 Richard Sandiford <richard.sandiford@arm.com>
813
814 * aarch64-opc.c (BANK): New macro.
815 (R32, R64): Take a register number as argument
816 (int_reg): Use BANK.
817
8a7f0c1b
RS		 8182016-09-21 Richard Sandiford <richard.sandiford@arm.com>
819
820 * aarch64-opc.c (print_register_list): Add a prefix parameter.
821 (aarch64_print_operand): Update accordingly.
822
aa2aa4c6
RS		 8232016-09-21 Richard Sandiford <richard.sandiford@arm.com>
824
825 * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
826 for FPIMM.
827 * aarch64-asm.h (ins_fpimm): New inserter.
828 * aarch64-asm.c (aarch64_ins_fpimm): New function.
829 * aarch64-asm-2.c: Regenerate.
830 * aarch64-dis.h (ext_fpimm): New extractor.
831 * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
832 (aarch64_ext_fpimm): New function.
833 * aarch64-dis-2.c: Regenerate.
834
b5464a68
RS		 8352016-09-21 Richard Sandiford <richard.sandiford@arm.com>
836
837 * aarch64-asm.c: Include libiberty.h.
838 (insert_fields): New function.
839 (aarch64_ins_imm): Use it.
840 * aarch64-dis.c (extract_fields): New function.
841 (aarch64_ext_imm): Use it.
842
42408347
RS		 8432016-09-21 Richard Sandiford <richard.sandiford@arm.com>
844
845 * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
846 with an esize parameter.
847 (operand_general_constraint_met_p): Update accordingly.
848 Fix misindented code.
849 * aarch64-asm.c (aarch64_ins_limm): Update call to
850 aarch64_logical_immediate_p.
851
4989adac
RS		 8522016-09-21 Richard Sandiford <richard.sandiford@arm.com>
853
854 * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
855
bd11d5d8
RS		 8562016-09-21 Richard Sandiford <richard.sandiford@arm.com>
857
858 * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
859
f807f43d
CZ		 8602016-09-15 Claudiu Zissulescu <claziss@synopsys.com>
861
862 * arc-dis.c (find_format): Walk the linked list pointed by einsn.
863
fd486b63
PB		 8642016-09-14 Peter Bergner <bergner@vnet.ibm.com>
865
866 * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
867 <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
868 xor3>: Delete mnemonics.
869 <cp_abort>: Rename mnemonic from ...
870 <cpabort>: ...to this.
871 <setb>: Change to a X form instruction.
872 <sync>: Change to 1 operand form.
873 <copy>: Delete mnemonic.
874 <copy_first>: Rename mnemonic from ...
875 <copy>: ...to this.
876 <paste, paste.>: Delete mnemonics.
877 <paste_last>: Rename mnemonic from ...
878 <paste.>: ...to this.
879
dce08442
AK		 8802016-09-14 Anton Kolesov <Anton.Kolesov@synopsys.com>
881
882 * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
883
952c3f51
AK		 8842016-09-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
885
886 * s390-mkopc.c (main): Support alternate arch strings.
887
8b71537b
PS		 8882016-09-12 Patrick Steuer <steuer@linux.vnet.ibm.com>
889
890 * s390-opc.txt: Fix kmctr instruction type.
891
5b64d091
L		 8922016-09-07 H.J. Lu <hongjiu.lu@intel.com>
893
894 * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
895 * i386-init.h: Regenerated.
896
7763838e
CM		 8972016-08-30 Cupertino Miranda <cmiranda@synopsys.com>
898
899 * opcodes/arc-dis.c (print_insn_arc): Changed.
900
1b8b6532
JM		 9012016-08-26 Jose E. Marchesi <jose.marchesi@oracle.com>
902
903 * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
904 camellia_fl.
905
1a336194
TP		 9062016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
907
908 * arm-dis.c (psr_name): Use hex as case labels. Add detection for
909 MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
910 FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
911
6b40c462
L		 9122016-08-24 H.J. Lu <hongjiu.lu@intel.com>
913
914 * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
915 (PREFIX_MOD_3_0FAE_REG_4): Likewise.
916 (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
917 PREFIX_MOD_3_0FAE_REG_4.
918 (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
919 PREFIX_MOD_3_0FAE_REG_4.
920 * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
921 (cpu_flags): Add CpuPTWRITE.
922 * i386-opc.h (CpuPTWRITE): New.
923 (i386_cpu_flags): Add cpuptwrite.
924 * i386-opc.tbl: Add ptwrite instruction.
925 * i386-init.h: Regenerated.
926 * i386-tbl.h: Likewise.
927
ab548d2d
AK		 9282016-08-24 Anton Kolesov <Anton.Kolesov@synopsys.com>
929
930 * arc-dis.h: Wrap around in extern "C".
931
344bde0a
RS		 9322016-08-23 Richard Sandiford <richard.sandiford@arm.com>
933
934 * aarch64-tbl.h (V8_2_INSN): New macro.
935 (aarch64_opcode_table): Use it.
936
5ce912d8
RS		 9372016-08-23 Richard Sandiford <richard.sandiford@arm.com>
938
939 * aarch64-tbl.h (aarch64_opcode_table): Make more use of
940 CORE_INSN, __FP_INSN and SIMD_INSN.
941
9d30b0bd
RS		 9422016-08-23 Richard Sandiford <richard.sandiford@arm.com>
943
944 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
945 (aarch64_opcode_table): Update uses accordingly.
946
dfdaec14
AJ		 9472016-07-25 Andrew Jenner <andrew@codesourcery.com>
948 Kwok Cheung Yeung <kcy@codesourcery.com>
949
950 opcodes/
951 * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
952 'e_cmplwi' to 'e_cmpli' instead.
953 (OPVUPRT, OPVUPRT_MASK): Define.
954 (powerpc_opcodes): Add E200Z4 insns.
955 (vle_opcodes): Add context save/restore insns.
956
7bd374a4
MR		 9572016-07-27 Maciej W. Rozycki <macro@imgtec.com>
958
959 * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
960 "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
961 "j".
962
db18dbab
GM		 9632016-07-27 Graham Markall <graham.markall@embecosm.com>
964
965 * arc-nps400-tbl.h: Change block comments to GNU format.
966 * arc-dis.c: Add new globals addrtypenames,
967 addrtypenames_max, and addtypeunknown.
968 (get_addrtype): New function.
969 (print_insn_arc): Print colons and address types when
970 required.
971 * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
972 define insert and extract functions for all address types.
973 (arc_operands): Add operands for colon and all address
974 types.
975 * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
976 * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
977 insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
978 * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
979 * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
980 insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
981
fecd57f9
L		 9822016-07-21 H.J. Lu <hongjiu.lu@intel.com>
983
984 * configure: Regenerated.
985
37fd5ef3
CZ		 9862016-07-20 Claudiu Zissulescu <claziss@synopsys.com>
987
988 * arc-dis.c (skipclass): New structure.
989 (decodelist): New variable.
990 (is_compatible_p): New function.
991 (new_element): Likewise.
992 (skip_class_p): Likewise.
993 (find_format_from_table): Use skip_class_p function.
994 (find_format): Decode first the extension instructions.
995 (print_insn_arc): Select either ARCEM or ARCHS based on elf
996 e_flags.
997 (parse_option): New function.
998 (parse_disassembler_options): Likewise.
999 (print_arc_disassembler_options): Likewise.
1000 (print_insn_arc): Use parse_disassembler_options function. Proper
1001 select ARCv2 cpu variant.
1002 * disassemble.c (disassembler_usage): Add ARC disassembler
1003 options.
1004
92281a5b
MR		 10052016-07-13 Maciej W. Rozycki <macro@imgtec.com>
1006
1007 * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
1008 annotation from the "nal" entry and reorder it beyond "bltzal".
1009
6e7ced37
JM		 10102016-07-12 Jose E. Marchesi <jose.marchesi@oracle.com>
1011
1012 * sparc-opc.c (ldtxa): New macro.
1013 (sparc_opcodes): Use the macro defined above to add entries for
1014 the LDTXA instructions.
1015 (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
1016 instruction.
1017
2f831b9a 10182016-07-07 James Bowman <james.bowman@ftdichip.com>
1019
1020 * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
1021 and "jmpc".
1022
c07315e0
JB		 10232016-07-01 Jan Beulich <jbeulich@suse.com>
1024
1025 * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
1026 (movzb): Adjust to cover all permitted suffixes.
1027 (movzw): New.
1028 * i386-tbl.h: Re-generate.
1029
9243100a
JB		 10302016-07-01 Jan Beulich <jbeulich@suse.com>
1031
1032 * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
1033 (lgdt): Remove Tbyte from non-64-bit variant.
1034 (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
1035 xsaves64, xsavec64): Remove Disp16.
1036 (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
1037 Remove Disp32S from non-64-bit variants. Remove Disp16 from
1038 64-bit variants.
1039 (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
1040 vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
1041 vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
1042 64-bit variants.
1043 * i386-tbl.h: Re-generate.
1044
8325cc63
JB		 10452016-07-01 Jan Beulich <jbeulich@suse.com>
1046
1047 * i386-opc.tbl (xlat): Remove RepPrefixOk.
1048 * i386-tbl.h: Re-generate.
1049
838441e4
YQ		 10502016-06-30 Yao Qi <yao.qi@linaro.org>
1051
1052 * arm-dis.c (print_insn): Fix typo in comment.
1053
dab26bf4
RS		 10542016-06-28 Richard Sandiford <richard.sandiford@arm.com>
1055
1056 * aarch64-opc.c (operand_general_constraint_met_p): Check the
1057 range of ldst_elemlist operands.
1058 (print_register_list): Use PRIi64 to print the index.
1059 (aarch64_print_operand): Likewise.
1060
5703197e
TS		 10612016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1062
1063 * mcore-opc.h: Remove sentinal.
1064 * mcore-dis.c (print_insn_mcore): Adjust.
1065
ce440d63
GM		 10662016-06-23 Graham Markall <graham.markall@embecosm.com>
1067
1068 * arc-opc.c: Correct description of availability of NPS400
1069 features.
1070
6fd3a02d
PB		 10712016-06-22 Peter Bergner <bergner@vnet.ibm.com>
1072
1073 * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
1074 (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
1075 mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
1076 xor3>: New mnemonics.
1077 <setb>: Change to a VX form instruction.
1078 (insert_sh6): Add support for rldixor.
1079 (extract_sh6): Likewise.
1080
6b477896
TS		 10812016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1082
1083 * arc-ext.h: Wrap in extern C.
1084
bdd582db
GM		 10852016-06-21 Graham Markall <graham.markall@embecosm.com>
1086
1087 * arc-dis.c (arc_insn_length): Add comment on instruction length.
1088 Use same method for determining instruction length on ARC700 and
1089 NPS-400.
1090 (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
1091 * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
1092 with the NPS400 subclass.
1093 * arc-opc.c: Likewise.
1094
96074adc
JM		 10952016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
1096
1097 * sparc-opc.c (rdasr): New macro.
1098 (wrasr): Likewise.
1099 (rdpr): Likewise.
1100 (wrpr): Likewise.
1101 (rdhpr): Likewise.
1102 (wrhpr): Likewise.
1103 (sparc_opcodes): Use the macros above to fix and expand the
1104 definition of read/write instructions from/to
1105 asr/privileged/hyperprivileged instructions.
1106 * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
1107 %hva_mask_nz. Prefer softint_set and softint_clear over
1108 set_softint and clear_softint.
1109 (print_insn_sparc): Support %ver in Rd.
1110
7a10c22f
JM		 11112016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
1112
1113 * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
1114 architecture according to the hardware capabilities they require.
1115
4f26fb3a
JM		 11162016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
1117
1118 * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
1119 (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
1120 bfd_mach_sparc_v9{c,d,e,v,m}.
1121 * sparc-opc.c (MASK_V9C): Define.
1122 (MASK_V9D): Likewise.
1123 (MASK_V9E): Likewise.
1124 (MASK_V9V): Likewise.
1125 (MASK_V9M): Likewise.
1126 (v6): Add MASK_V9{C,D,E,V,M}.
1127 (v6notlet): Likewise.
1128 (v7): Likewise.
1129 (v8): Likewise.
1130 (v9): Likewise.
1131 (v9andleon): Likewise.
1132 (v9a): Likewise.
1133 (v9b): Likewise.
1134 (v9c): Define.
1135 (v9d): Likewise.
1136 (v9e): Likewise.
1137 (v9v): Likewise.
1138 (v9m): Likewise.
1139 (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
1140
3ee6e4fb
NC		 11412016-06-15 Nick Clifton <nickc@redhat.com>
1142
1143 * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
1144 constants to match expected behaviour.
1145 (nds32_parse_opcode): Likewise. Also for whitespace.
1146
02f3be19
AB		 11472016-06-15 Andrew Burgess <andrew.burgess@embecosm.com>
1148
1149 * arc-opc.c (extract_rhv1): Extract value from insn.
1150
6f9f37ed 11512016-06-14 Graham Markall <graham.markall@embecosm.com>
28215275
GM		 1152
1153 * arc-nps400-tbl.h: Add ldbit instruction.
1154 * arc-opc.c: Add flag classes required for ldbit.
1155
6f9f37ed 11562016-06-14 Graham Markall <graham.markall@embecosm.com>
9ba75c88
GM		 1157
1158 * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
1159 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1160 support the above instructions.
1161
6f9f37ed 11622016-06-14 Graham Markall <graham.markall@embecosm.com>
14053c19
GM		 1163
1164 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
1165 imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
1166 csma, cbba, zncv, and hofs.
1167 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1168 support the above instructions.
1169
11702016-06-06 Graham Markall <graham.markall@embecosm.com>
1171
1172 * arc-nps400-tbl.h: Add andab and orab instructions.
1173
11742016-06-06 Graham Markall <graham.markall@embecosm.com>
1175
1176 * arc-nps400-tbl.h: Add addl-like instructions.
1177
11782016-06-06 Graham Markall <graham.markall@embecosm.com>
1179
1180 * arc-nps400-tbl.h: Add mxb and imxb instructions.
1181
11822016-06-06 Graham Markall <graham.markall@embecosm.com>
1183
1184 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
1185 instructions.
1186
b2cc3f6f
AK		 11872016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1188
1189 * s390-dis.c (option_use_insn_len_bits_p): New file scope
1190 variable.
1191 (init_disasm): Handle new command line option "insnlength".
1192 (print_s390_disassembler_options): Mention new option in help
1193 output.
1194 (print_insn_s390): Use the encoded insn length when dumping
1195 unknown instructions.
1196
1857fe72
DC		 11972016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
1198
1199 * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
1200 to the address and set as symbol address for LDS/ STS immediate operands.
1201
14b57c7c
AM		 12022016-06-07 Alan Modra <amodra@gmail.com>
1203
1204 * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
1205 cpu for "vle" to e500.
1206 * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
1207 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
1208 (PPCNONE): Delete, substitute throughout.
1209 (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
1210 except for major opcode 4 and 31.
1211 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
1212
4d1464f2
MW		 12132016-06-07 Matthew Wahab <matthew.wahab@arm.com>
1214
1215 * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
1216 ARM_EXT_RAS in relevant entries.
1217
026122a6
PB		 12182016-06-03 Peter Bergner <bergner@vnet.ibm.com>
1219
1220 PR binutils/20196
1221 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
1222 opcodes for E6500.
1223
07f5af7d
L		 12242016-06-03 H.J. Lu <hongjiu.lu@intel.com>
1225
1226 PR binutis/18386
1227 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
1228 (indir_v_mode): New.
1229 Add comments for '&'.
1230 (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
1231 (putop): Handle '&'.
1232 (intel_operand_size): Handle indir_v_mode.
1233 (OP_E_register): Likewise.
1234 * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
1235 64-bit indirect call/jmp for AMD64.
1236 * i386-tbl.h: Regenerated
1237
4eb6f892
AB		 12382016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
1239
1240 * arc-dis.c (struct arc_operand_iterator): New structure.
1241 (find_format_from_table): All the old content from find_format,
1242 with some minor adjustments, and parameter renaming.
1243 (find_format_long_instructions): New function.
1244 (find_format): Rewritten.
1245 (arc_insn_length): Add LSB parameter.
1246 (extract_operand_value): New function.
1247 (operand_iterator_next): New function.
1248 (print_insn_arc): Use new functions to find opcode, and iterator
1249 over operands.
1250 * arc-opc.c (insert_nps_3bit_dst_short): New function.
1251 (extract_nps_3bit_dst_short): New function.
1252 (insert_nps_3bit_src2_short): New function.
1253 (extract_nps_3bit_src2_short): New function.
1254 (insert_nps_bitop1_size): New function.
1255 (extract_nps_bitop1_size): New function.
1256 (insert_nps_bitop2_size): New function.
1257 (extract_nps_bitop2_size): New function.
1258 (insert_nps_bitop_mod4_msb): New function.
1259 (extract_nps_bitop_mod4_msb): New function.
1260 (insert_nps_bitop_mod4_lsb): New function.
1261 (extract_nps_bitop_mod4_lsb): New function.
1262 (insert_nps_bitop_dst_pos3_pos4): New function.
1263 (extract_nps_bitop_dst_pos3_pos4): New function.
1264 (insert_nps_bitop_ins_ext): New function.
1265 (extract_nps_bitop_ins_ext): New function.
1266 (arc_operands): Add new operands.
1267 (arc_long_opcodes): New global array.
1268 (arc_num_long_opcodes): New global.
1269 * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
1270
1fe0971e
TS		 12712016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1272
1273 * nds32-asm.h: Add extern "C".
1274 * sh-opc.h: Likewise.
1275
315f180f
GM		 12762016-06-01 Graham Markall <graham.markall@embecosm.com>
1277
1278 * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
1279 0,b,limm to the rflt instruction.
1280
a2b5fccc
TS		 12812016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1282
1283 * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
1284 constant.
1285
0cbd0046
L		 12862016-05-29 H.J. Lu <hongjiu.lu@intel.com>
1287
1288 PR gas/20145
1289 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
1290 CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
1291 CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
1292 CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
1293 CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
1294 * i386-init.h: Regenerated.
1295
1848e567
L		 12962016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1297
1298 PR gas/20145
1299 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
1300 CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
1301 CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
1302 Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
1303 CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
1304 CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
1305 CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
1306 Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
1307 CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
1308 CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
1309 CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
1310 for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
1311 CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
1312 CpuRegMask for AVX512.
1313 (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
1314 and CpuRegMask.
1315 (set_bitfield_from_cpu_flag_init): New function.
1316 (set_bitfield): Remove const on f. Call
1317 set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
1318 * i386-opc.h (CpuRegMMX): New.
1319 (CpuRegXMM): Likewise.
1320 (CpuRegYMM): Likewise.
1321 (CpuRegZMM): Likewise.
1322 (CpuRegMask): Likewise.
1323 (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
1324 and cpuregmask.
1325 * i386-init.h: Regenerated.
1326 * i386-tbl.h: Likewise.
1327
e92bae62
L		 13282016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1329
1330 PR gas/20154
1331 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
1332 (opcode_modifiers): Add AMD64 and Intel64.
1333 (main): Properly verify CpuMax.
1334 * i386-opc.h (CpuAMD64): Removed.
1335 (CpuIntel64): Likewise.
1336 (CpuMax): Set to CpuNo64.
1337 (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
1338 (AMD64): New.
1339 (Intel64): Likewise.
1340 (i386_opcode_modifier): Add amd64 and intel64.
1341 (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
1342 on call and jmp.
1343 * i386-init.h: Regenerated.
1344 * i386-tbl.h: Likewise.
1345
e89c5eaa
L		 13462016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1347
1348 PR gas/20154
1349 * i386-gen.c (main): Fail if CpuMax is incorrect.
1350 * i386-opc.h (CpuMax): Set to CpuIntel64.
1351 * i386-tbl.h: Regenerated.
1352
77d66e7b
NC		 13532016-05-27 Nick Clifton <nickc@redhat.com>
1354
1355 PR target/20150
1356 * msp430-dis.c (msp430dis_read_two_bytes): New function.
1357 (msp430dis_opcode_unsigned): New function.
1358 (msp430dis_opcode_signed): New function.
1359 (msp430_singleoperand): Use the new opcode reading functions.
1360 Only disassenmble bytes if they were successfully read.
1361 (msp430_doubleoperand): Likewise.
1362 (msp430_branchinstr): Likewise.
1363 (msp430x_callx_instr): Likewise.
1364 (print_insn_msp430): Check that it is safe to read bytes before
1365 attempting disassembly. Use the new opcode reading functions.
1366
19dfcc89
PB		 13672016-05-26 Peter Bergner <bergner@vnet.ibm.com>
1368
1369 * ppc-opc.c (CY): New define. Document it.
1370 (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
1371
f3ad7637
L		 13722016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1373
1374 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
1375 CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
1376 and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
1377 CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
1378 CPU_ANY_AVX_FLAGS.
1379 * i386-init.h: Regenerated.
1380
f1360d58
L		 13812016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1382
1383 PR gas/20141
1384 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
1385 CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
1386 * i386-init.h: Regenerated.
1387
293f5f65
L		 13882016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1389
1390 * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
1391 CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
1392 * i386-init.h: Regenerated.
1393
d9eca1df
CZ		 13942016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1395
1396 * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
1397 information.
1398 (print_insn_arc): Set insn_type information.
1399 * arc-opc.c (C_CC): Add F_CLASS_COND.
1400 * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
1401 (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
1402 (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
1403 (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
1404 (brne, brne_s, jeq_s, jne_s): Likewise.
1405
87789e08
CZ		 14062016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1407
1408 * arc-tbl.h (neg): New instruction variant.
1409
c810e0b8
CZ		 14102016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
1411
1412 * arc-dis.c (find_format, find_format, get_auxreg)
1413 (print_insn_arc): Changed.
1414 * arc-ext.h (INSERT_XOP): Likewise.
1415
3d207518
TS		 14162016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1417
1418 * tic54x-dis.c (sprint_mmr): Adjust.
1419 * tic54x-opc.c: Likewise.
1420
514e58b7
AM		 14212016-05-19 Alan Modra <amodra@gmail.com>
1422
1423 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
1424
e43de63c
AM		 14252016-05-19 Alan Modra <amodra@gmail.com>
1426
1427 * ppc-opc.c: Formatting.
1428 (NSISIGNOPT): Define.
1429 (powerpc_opcodes <subis>): Use NSISIGNOPT.
1430
1401d2fe
MR		 14312016-05-18 Maciej W. Rozycki <macro@imgtec.com>
1432
1433 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
1434 replacing references to `micromips_ase' throughout.
1435 (_print_insn_mips): Don't use file-level microMIPS annotation to
1436 determine the disassembly mode with the symbol table.
1437
1178da44
PB		 14382016-05-13 Peter Bergner <bergner@vnet.ibm.com>
1439
1440 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
1441
8f4f9071
MF		 14422016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
1443
1444 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
1445 mips64r6.
1446 * mips-opc.c (D34): New macro.
1447 (mips_builtin_opcodes): Define bposge32c for DSPr3.
1448
8bc52696
AF		 14492016-05-10 Alexander Fomin <alexander.fomin@intel.com>
1450
1451 * i386-dis.c (prefix_table): Add RDPID instruction.
1452 * i386-gen.c (cpu_flag_init): Add RDPID flag.
1453 (cpu_flags): Add RDPID bitfield.
1454 * i386-opc.h (enum): Add RDPID element.
1455 (i386_cpu_flags): Add RDPID field.
1456 * i386-opc.tbl: Add RDPID instruction.
1457 * i386-init.h: Regenerate.
1458 * i386-tbl.h: Regenerate.
1459
39d911fc
TP		 14602016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1461
1462 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
1463 branch type of a symbol.
1464 (print_insn): Likewise.
1465
16a1fa25
TP		 14662016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1467
1468 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1469 Mainline Security Extensions instructions.
1470 (thumb_opcodes): Add entries for narrow ARMv8-M Security
1471 Extensions instructions.
1472 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1473 instructions.
1474 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1475 special registers.
1476
d751b79e
JM		 14772016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
1478
1479 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1480
945e0f82
CZ		 14812016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
1482
1483 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1484 (arcExtMap_genOpcode): Likewise.
1485 * arc-opc.c (arg_32bit_rc): Define new variable.
1486 (arg_32bit_u6): Likewise.
1487 (arg_32bit_limm): Likewise.
1488
20f55f38
SN		 14892016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
1490
1491 * aarch64-gen.c (VERIFIER): Define.
1492 * aarch64-opc.c (VERIFIER): Define.
1493 (verify_ldpsw): Use static linkage.
1494 * aarch64-opc.h (verify_ldpsw): Remove.
1495 * aarch64-tbl.h: Use VERIFIER for verifiers.
1496
4bd13cde
NC		 14972016-04-28 Nick Clifton <nickc@redhat.com>
1498
1499 PR target/19722
1500 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1501 * aarch64-opc.c (verify_ldpsw): New function.
1502 * aarch64-opc.h (verify_ldpsw): New prototype.
1503 * aarch64-tbl.h: Add initialiser for verifier field.
1504 (LDPSW): Set verifier to verify_ldpsw.
1505
c0f92bf9
L		 15062016-04-23 H.J. Lu <hongjiu.lu@intel.com>
1507
1508 PR binutils/19983
1509 PR binutils/19984
1510 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1511 smaller than address size.
1512
e6c7cdec
TS		 15132016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1514
1515 * alpha-dis.c: Regenerate.
1516 * crx-dis.c: Likewise.
1517 * disassemble.c: Likewise.
1518 * epiphany-opc.c: Likewise.
1519 * fr30-opc.c: Likewise.
1520 * frv-opc.c: Likewise.
1521 * ip2k-opc.c: Likewise.
1522 * iq2000-opc.c: Likewise.
1523 * lm32-opc.c: Likewise.
1524 * lm32-opinst.c: Likewise.
1525 * m32c-opc.c: Likewise.
1526 * m32r-opc.c: Likewise.
1527 * m32r-opinst.c: Likewise.
1528 * mep-opc.c: Likewise.
1529 * mt-opc.c: Likewise.
1530 * or1k-opc.c: Likewise.
1531 * or1k-opinst.c: Likewise.
1532 * tic80-opc.c: Likewise.
1533 * xc16x-opc.c: Likewise.
1534 * xstormy16-opc.c: Likewise.
1535
537aefaf
AB		 15362016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1537
1538 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1539 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1540 calcsd, and calcxd instructions.
1541 * arc-opc.c (insert_nps_bitop_size): Delete.
1542 (extract_nps_bitop_size): Delete.
1543 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1544 (extract_nps_qcmp_m3): Define.
1545 (extract_nps_qcmp_m2): Define.
1546 (extract_nps_qcmp_m1): Define.
1547 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1548 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1549 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1550 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1551 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1552 NPS_QCMP_M3.
1553
c8f785f2
AB		 15542016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1555
1556 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1557
6fd8e7c2
L		 15582016-04-15 H.J. Lu <hongjiu.lu@intel.com>
1559
1560 * Makefile.in: Regenerated with automake 1.11.6.
1561 * aclocal.m4: Likewise.
1562
4b0c052e
AB		 15632016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1564
1565 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1566 instructions.
1567 * arc-opc.c (insert_nps_cmem_uimm16): New function.
1568 (extract_nps_cmem_uimm16): New function.
1569 (arc_operands): Add NPS_XLDST_UIMM16 operand.
1570
cb040366
AB		 15712016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1572
1573 * arc-dis.c (arc_insn_length): New function.
1574 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1575 (find_format): Change insnLen parameter to unsigned.
1576
accc0180
NC		 15772016-04-13 Nick Clifton <nickc@redhat.com>
1578
1579 PR target/19937
1580 * v850-opc.c (v850_opcodes): Correct masks for long versions of
1581 the LD.B and LD.BU instructions.
1582
f36e33da
CZ		 15832016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1584
1585 * arc-dis.c (find_format): Check for extension flags.
1586 (print_flags): New function.
1587 (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1588 .extAuxRegister.
1589 * arc-ext.c (arcExtMap_coreRegName): Use
1590 LAST_EXTENSION_CORE_REGISTER.
1591 (arcExtMap_coreReadWrite): Likewise.
1592 (dump_ARC_extmap): Update printing.
1593 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1594 (arc_aux_regs): Add cpu field.
1595 * arc-regs.h: Add cpu field, lower case name aux registers.
1596
1c2e355e
CZ		 15972016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1598
1599 * arc-tbl.h: Add rtsc, sleep with no arguments.
1600
b99747ae
CZ		 16012016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1602
1603 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1604 Initialize.
1605 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1606 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1607 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1608 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1609 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1610 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1611 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1612 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1613 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1614 (arc_opcode arc_opcodes): Null terminate the array.
1615 (arc_num_opcodes): Remove.
1616 * arc-ext.h (INSERT_XOP): Define.
1617 (extInstruction_t): Likewise.
1618 (arcExtMap_instName): Delete.
1619 (arcExtMap_insn): New function.
1620 (arcExtMap_genOpcode): Likewise.
1621 * arc-ext.c (ExtInstruction): Remove.
1622 (create_map): Zero initialize instruction fields.
1623 (arcExtMap_instName): Remove.
1624 (arcExtMap_insn): New function.
1625 (dump_ARC_extmap): More info while debuging.
1626 (arcExtMap_genOpcode): New function.
1627 * arc-dis.c (find_format): New function.
1628 (print_insn_arc): Use find_format.
1629 (arc_get_disassembler): Enable dump_ARC_extmap only when
1630 debugging.
1631
92708cec
MR		 16322016-04-11 Maciej W. Rozycki <macro@imgtec.com>
1633
1634 * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1635 instruction bits out.
1636
a42a4f84
AB		 16372016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1638
1639 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1640 * arc-opc.c (arc_flag_operands): Add new flags.
1641 (arc_flag_classes): Add new classes.
1642
1328504b
AB		 16432016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1644
1645 * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1646
820f03ff
AB		 16472016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
1648
1649 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1650 encode1, rflt, crc16, and crc32 instructions.
1651 * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1652 (arc_flag_classes): Add C_NPS_R.
1653 (insert_nps_bitop_size_2b): New function.
1654 (extract_nps_bitop_size_2b): Likewise.
1655 (insert_nps_bitop_uimm8): Likewise.
1656 (extract_nps_bitop_uimm8): Likewise.
1657 (arc_operands): Add new operand entries.
1658
8ddf6b2a
CZ		 16592016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
1660
b99747ae
CZ		 1661 * arc-regs.h: Add a new subclass field. Add double assist
1662 accumulator register values.
1663 * arc-tbl.h: Use DPA subclass to mark the double assist
1664 instructions. Use DPX/SPX subclas to mark the FPX instructions.
1665 * arc-opc.c (RSP): Define instead of SP.
1666 (arc_aux_regs): Add the subclass field.
8ddf6b2a 1667
589a7d88
JW		 16682016-04-05 Jiong Wang <jiong.wang@arm.com>
1669
1670 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1671
0a191de9 16722016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
2cce10e7
AB		 1673
1674 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1675 NPS_R_SRC1.
1676
0a106562
AB		 16772016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
1678
1679 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1680 issues. No functional changes.
1681
bd05ac5f
CZ		 16822016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
1683
b99747ae
CZ		 1684 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1685 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1686 (RTT): Remove duplicate.
1687 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1688 (PCT_CONFIG*): Remove.
1689 (D1L, D1H, D2H, D2L): Define.
bd05ac5f 1690
9885948f
CZ		 16912016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1692
b99747ae 1693 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
9885948f 1694
f2dd8838
CZ		 16952016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1696
b99747ae
CZ		 1697 * arc-tbl.h (invld07): Remove.
1698 * arc-ext-tbl.h: New file.
1699 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1700 * arc-opc.c (arc_opcodes): Add ext-tbl include.
f2dd8838 1701
0d2f91fe
JK		 17022016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
1703
1704 Fix -Wstack-usage warnings.
1705 * aarch64-dis.c (print_operands): Substitute size.
1706 * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1707
a6b71f42
JM		 17082016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
1709
1710 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1711 to get a proper diagnostic when an invalid ASR register is used.
1712
9780e045
NC		 17132016-03-22 Nick Clifton <nickc@redhat.com>
1714
1715 * configure: Regenerate.
1716
e23e8ebe
AB		 17172016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1718
1719 * arc-nps400-tbl.h: New file.
1720 * arc-opc.c: Add top level comment.
1721 (insert_nps_3bit_dst): New function.
1722 (extract_nps_3bit_dst): New function.
1723 (insert_nps_3bit_src2): New function.
1724 (extract_nps_3bit_src2): New function.
1725 (insert_nps_bitop_size): New function.
1726 (extract_nps_bitop_size): New function.
1727 (arc_flag_operands): Add nps400 entries.
1728 (arc_flag_classes): Add nps400 entries.
1729 (arc_operands): Add nps400 entries.
1730 (arc_opcodes): Add nps400 include.
1731
1ae8ab47
AB		 17322016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1733
1734 * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1735 the new class enum values.
1736
8699fc3e
AB		 17372016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1738
1739 * arc-dis.c (print_insn_arc): Handle nps400.
1740
24740d83
AB		 17412016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1742
1743 * arc-opc.c (BASE): Delete.
1744
8678914f
NC		 17452016-03-18 Nick Clifton <nickc@redhat.com>
1746
1747 PR target/19721
1748 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1749 of MOV insn that aliases an ORR insn.
1750
cc933301
JW		 17512016-03-16 Jiong Wang <jiong.wang@arm.com>
1752
1753 * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1754
f86f5863
TS		 17552016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1756
1757 * mcore-opc.h: Add const qualifiers.
1758 * microblaze-opc.h (struct op_code_struct): Likewise.
1759 * sh-opc.h: Likewise.
1760 * tic4x-dis.c (tic4x_print_indirect): Likewise.
1761 (tic4x_print_op): Likewise.
1762
62de1c63
AM		 17632016-03-02 Alan Modra <amodra@gmail.com>
1764
d11698cd 1765 * or1k-desc.h: Regenerate.
62de1c63 1766 * fr30-ibld.c: Regenerate.
c697cf0b 1767 * rl78-decode.c: Regenerate.
62de1c63 1768
020efce5
NC		 17692016-03-01 Nick Clifton <nickc@redhat.com>
1770
1771 PR target/19747
1772 * rl78-dis.c (print_insn_rl78_common): Fix typo.
1773
b0c11777
RL		 17742016-02-24 Renlin Li <renlin.li@arm.com>
1775
1776 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1777 (print_insn_coprocessor): Support fp16 instructions.
1778
3e309328
RL		 17792016-02-24 Renlin Li <renlin.li@arm.com>
1780
1781 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1782 vminnm, vrint(mpna).
1783
8afc7bea
RL		 17842016-02-24 Renlin Li <renlin.li@arm.com>
1785
1786 * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1787 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1788
4fd7268a
L		 17892016-02-15 H.J. Lu <hongjiu.lu@intel.com>
1790
1791 * i386-dis.c (print_insn): Parenthesize expression to prevent
1792 truncated addresses.
1793 (OP_J): Likewise.
1794
4670103e
CZ		 17952016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
1796 Janek van Oirschot <jvanoirs@synopsys.com>
1797
b99747ae
CZ		 1798 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1799 variable.
4670103e 1800
c1d9289f
NC		 18012016-02-04 Nick Clifton <nickc@redhat.com>
1802
1803 PR target/19561
1804 * msp430-dis.c (print_insn_msp430): Add a special case for
1805 decoding an RRC instruction with the ZC bit set in the extension
1806 word.
1807
a143b004
AB		 18082016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1809
1810 * cgen-ibld.in (insert_normal): Rework calculation of shift.
1811 * epiphany-ibld.c: Regenerate.
1812 * fr30-ibld.c: Regenerate.
1813 * frv-ibld.c: Regenerate.
1814 * ip2k-ibld.c: Regenerate.
1815 * iq2000-ibld.c: Regenerate.
1816 * lm32-ibld.c: Regenerate.
1817 * m32c-ibld.c: Regenerate.
1818 * m32r-ibld.c: Regenerate.
1819 * mep-ibld.c: Regenerate.
1820 * mt-ibld.c: Regenerate.
1821 * or1k-ibld.c: Regenerate.
1822 * xc16x-ibld.c: Regenerate.
1823 * xstormy16-ibld.c: Regenerate.
1824
b89807c6
AB		 18252016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1826
1827 * epiphany-dis.c: Regenerated from latest cpu files.
1828
d8c823c8
MM		 18292016-02-01 Michael McConville <mmcco@mykolab.com>
1830
1831 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1832 test bit.
1833
5bc5ae88
RL		 18342016-01-25 Renlin Li <renlin.li@arm.com>
1835
1836 * arm-dis.c (mapping_symbol_for_insn): New function.
1837 (find_ifthen_state): Call mapping_symbol_for_insn().
1838
0bff6e2d
MW		 18392016-01-20 Matthew Wahab <matthew.wahab@arm.com>
1840
1841 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1842 of MSR UAO immediate operand.
1843
100b4f2e
MR		 18442016-01-18 Maciej W. Rozycki <macro@imgtec.com>
1845
1846 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1847 instruction support.
1848
5c14705f
AM		 18492016-01-17 Alan Modra <amodra@gmail.com>
1850
1851 * configure: Regenerate.
1852
4d82fe66
NC		 18532016-01-14 Nick Clifton <nickc@redhat.com>
1854
1855 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1856 instructions that can support stack pointer operations.
1857 * rl78-decode.c: Regenerate.
1858 * rl78-dis.c: Fix display of stack pointer in MOVW based
1859 instructions.
1860
651657fa
MW		 18612016-01-14 Matthew Wahab <matthew.wahab@arm.com>
1862
1863 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1864 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
1865 erxtatus_el1 and erxaddr_el1.
1866
105bde57
MW		 18672016-01-12 Matthew Wahab <matthew.wahab@arm.com>
1868
1869 * arm-dis.c (arm_opcodes): Add "esb".
1870 (thumb_opcodes): Likewise.
1871
afa8d405
PB		 18722016-01-11 Peter Bergner <bergner@vnet.ibm.com>
1873
1874 * ppc-opc.c <xscmpnedp>: Delete.
1875 <xvcmpnedp>: Likewise.
1876 <xvcmpnedp.>: Likewise.
1877 <xvcmpnesp>: Likewise.
1878 <xvcmpnesp.>: Likewise.
1879
83c3256e
AS		 18802016-01-08 Andreas Schwab <schwab@linux-m68k.org>
1881
1882 PR gas/13050
1883 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1884 addition to ISA_A.
1885
6f2750fe
AM		 18862016-01-01 Alan Modra <amodra@gmail.com>
1887
1888 Update year range in copyright notice of all files.
1889
3499769a
AM		 1890For older changes see ChangeLog-2015
1891\f
1892Copyright (C) 2016 Free Software Foundation, Inc.
1893
1894Copying and distribution of this file, with or without modification,
1895are permitted in any medium without royalty provided the copyright
1896notice and this notice are preserved.
1897
1898Local Variables:
1899mode: change-log
1900left-margin: 8
1901fill-column: 74
1902version-control: never
1903End:
GDB Binutils - Deliverables
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