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[AArch64] Add ARMv8.3 FCMLA and FCADD instructions
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
c2c4ff8d
SN		 12016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
2
3 * aarch64-tbl.h (QL_V3SAMEHSD_ROT, QL_ELEMENT_ROT): Define.
4 (aarch64_feature_simd_v8_3, SIMD_V8_3): Define.
5 (aarch64_opcode_table): Add fcmla and fcadd.
6 (AARCH64_OPERANDS): Add IMM_ROT{1,2,3}.
7 * aarch64-asm.h (aarch64_ins_imm_rotate): Declare.
8 * aarch64-asm.c (aarch64_ins_imm_rotate): Define.
9 * aarch64-dis.h (aarch64_ext_imm_rotate): Declare.
10 * aarch64-dis.c (aarch64_ext_imm_rotate): Define.
11 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_rotate{1,2,3}.
12 * aarch64-opc.c (fields): Add FLD_rotate{1,2,3}.
13 (operand_general_constraint_met_p): Rotate and index range check.
14 (aarch64_print_operand): Handle rotate operand.
15 * aarch64-asm-2.c: Regenerate.
16 * aarch64-dis-2.c: Likewise.
17 * aarch64-opc-2.c: Likewise.
18
28617675
SN		 192016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
20
21 * aarch64-tbl.h (arch64_opcode_table): Add ldaprb, ldaprh, ldapr.
22 * aarch64-asm-2.c: Regenerate.
23 * aarch64-dis-2.c: Regenerate.
24 * aarch64-opc-2.c: Regenerate.
25
ccfc90a3
SN		 262016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
27
28 * aarch64-tbl.h (arch64_opcode_table): Add fjcvtzs.
29 (QL_FP2INT_W_D, aarch64_feature_fp_v8_3, FP_V8_3): Define.
30 * aarch64-asm-2.c: Regenerate.
31 * aarch64-dis-2.c: Regenerate.
32 * aarch64-opc-2.c: Regenerate.
33
3f06e550
SN		 342016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
35
36 * aarch64-tbl.h (QL_X1NIL): New.
37 (arch64_opcode_table): Add ldraa, ldrab.
38 (AARCH64_OPERANDS): Add "ADDR_SIMM10".
39 * aarch64-asm.h (aarch64_ins_addr_simm10): Declare.
40 * aarch64-asm.c (aarch64_ins_addr_simm10): Define.
41 * aarch64-dis.h (aarch64_ext_addr_simm10): Declare.
42 * aarch64-dis.c (aarch64_ext_addr_simm10): Define.
43 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_S_simm10.
44 * aarch64-opc.c (fields): Add data for FLD_S_simm10.
45 (operand_general_constraint_met_p): Handle AARCH64_OPND_ADDR_SIMM10.
46 (aarch64_print_operand): Likewise.
47 * aarch64-asm-2.c: Regenerate.
48 * aarch64-dis-2.c: Regenerate.
49 * aarch64-opc-2.c: Regenerate.
50
74f5402d
SN		 512016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
52
53 * aarch64-tbl.h (arch64_opcode_table): Add braa, brab, blraa, blrab, braaz,
54 brabz, blraaz, blrabz, retaa, retab, eretaa, eretab.
55 * aarch64-asm-2.c: Regenerate.
56 * aarch64-dis-2.c: Regenerate.
57 * aarch64-opc-2.c: Regenerate.
58
c84364ec
SN		 592016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
60
61 * aarch64-tbl.h (arch64_opcode_table): Add pacga.
62 (AARCH64_OPERANDS): Add Rm_SP.
63 * aarch64-opc.c (aarch64_print_operand): Handle AARCH64_OPND_Rm_SP.
64 * aarch64-asm-2.c: Regenerate.
65 * aarch64-dis-2.c: Regenerate.
66 * aarch64-opc-2.c: Regenerate.
67
a2cfc830
SN		 682016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
69
70 * aarch64-tbl.h (arch64_opcode_table): Add pacia, pacib, pacda, pacdb, autia,
71 autib, autda, autdb, paciza, pacizb, pacdza, pacdzb, autiza, autizb, autdza,
72 autdzb, xpaci, xpacd.
73 * aarch64-asm-2.c: Regenerate.
74 * aarch64-dis-2.c: Regenerate.
75 * aarch64-opc-2.c: Regenerate.
76
b0bfa7b5
SN		 772016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
78
79 * aarch64-opc.c (aarch64_sys_regs): Add apiakeylo_el1, apiakeyhi_el1,
80 apibkeylo_el1, apibkeyhi_el1, apdakeylo_el1, apdakeyhi_el1,
81 apdbkeylo_el1, apdbkeyhi_el1, apgakeylo_el1 and apgakeyhi_el1.
82 (aarch64_sys_reg_supported_p): Add feature test for new registers.
83
8787d804
SN		 842016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
85
86 * aarch64-tbl.h (aarch64_feature_v8_3, ARMV8_3, V8_3_INSN): New.
87 (arch64_opcode_table): Add xpaclri, pacia1716, pacib1716, autia1716,
88 autib1716, paciaz, paciasp, pacibz, pacibsp, autiaz, autiasp, autibz,
89 autibsp.
90 * aarch64-asm-2.c: Regenerate.
91 * aarch64-dis-2.c: Regenerate.
92
3d731f69
SN		 932016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
94
95 * aarch64-gen.c (find_alias_opcode): Increase max_num_aliases to 32.
96
60227d64
L		 972016-11-09 H.J. Lu <hongjiu.lu@intel.com>
98
99 PR binutils/20799
100 * i386-dis-evex.h (evex_table): Replace EdqwS with Edqw.
101 * i386-dis.c (EdqwS): Removed.
102 (dqw_swap_mode): Likewise.
103 (intel_operand_size): Don't check dqw_swap_mode.
104 (OP_E_register): Likewise.
105 (OP_E_memory): Likewise.
106 (OP_G): Likewise.
107 (OP_EX): Likewise.
108 * i386-opc.tbl: Remove "S" from EVEX vpextrw.
109 * i386-tbl.h: Regerated.
110
7efeed17
L		 1112016-11-09 H.J. Lu <hongjiu.lu@intel.com>
112
113 * i386-opc.tbl: Merge AVX512F vmovq.
1032d6eb 114 * i386-tbl.h: Regerated.
7efeed17 115
1f334aeb
L		 1162016-11-08 H.J. Lu <hongjiu.lu@intel.com>
117
118 PR binutils/20701
119 * i386-dis.c (THREE_BYTE_0F7A): Removed.
120 (dis386_twobyte): Don't use THREE_BYTE_0F7A.
121 (three_byte_table): Remove THREE_BYTE_0F7A.
122
48c97fa1
L		 1232016-11-07 H.J. Lu <hongjiu.lu@intel.com>
124
125 PR binutils/20775
126 * i386-dis.c (FGRPd9_2): Replace 0 with 1.
127 (FGRPd9_4): Replace 1 with 2.
128 (FGRPd9_5): Replace 2 with 3.
129 (FGRPd9_6): Replace 3 with 4.
130 (FGRPd9_7): Replace 4 with 5.
131 (FGRPda_5): Replace 5 with 6.
132 (FGRPdb_4): Replace 6 with 7.
133 (FGRPde_3): Replace 7 with 8.
134 (FGRPdf_4): Replace 8 with 9.
135 (fgrps): Add an entry for Bad_Opcode.
136
b437d035
AB		 1372016-11-04 Andrew Burgess <andrew.burgess@embecosm.com>
138
139 * arc-opc.c (arc_flag_operands): Add F_DI14.
140 (arc_flag_classes): Add C_DI14.
141 * arc-nps400-tbl.h: Add new exc instructions.
142
5a736821
GM		 1432016-11-03 Graham Markall <graham.markall@embecosm.com>
144
145 * arc-dis.c (arc_insn_length): Return length 8 for instructions with
146 major opcode 0xa.
147 * arc-nps-400-tbl.h: Add dcmac instruction.
148 * arc-opc.c (arc_operands): Added operands for dcmac instruction.
149 (insert_nps_rbdouble_64): Added.
150 (extract_nps_rbdouble_64): Added.
151 (insert_nps_proto_size): Added.
152 (extract_nps_proto_size): Added.
153
bdfe53e3
AB		 1542016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
155
156 * arc-dis.c (struct arc_operand_iterator): Remove all fields
157 relating to long instruction processing, add new limm field.
158 (OPCODE): Rename to...
159 (OPCODE_32BIT_INSN): ...this.
160 (OPCODE_AC): Delete.
161 (skip_this_opcode): Handle different instruction lengths, update
162 macro name.
163 (special_flag_p): Update parameter type.
164 (find_format_from_table): Update for more instruction lengths.
165 (find_format_long_instructions): Delete.
166 (find_format): Update for more instruction lengths.
167 (arc_insn_length): Likewise.
168 (extract_operand_value): Update for more instruction lengths.
169 (operand_iterator_next): Remove code relating to long
170 instructions.
171 (arc_opcode_to_insn_type): New function.
172 (print_insn_arc):Update for more instructions lengths.
173 * arc-ext.c (extInstruction_t): Change argument type.
174 * arc-ext.h (extInstruction_t): Change argument type.
175 * arc-fxi.h: Change type unsigned to unsigned long long
176 extensively throughout.
177 * arc-nps400-tbl.h: Add long instructions taken from
178 arc_long_opcodes table in arc-opc.c.
179 * arc-opc.c: Update parameter types on insert/extract handlers.
180 (arc_long_opcodes): Delete.
181 (arc_num_long_opcodes): Delete.
182 (arc_opcode_len): Update for more instruction lengths.
183
90f61cce
GM		 1842016-11-03 Graham Markall <graham.markall@embecosm.com>
185
186 * arc-dis.c (print_insn_arc): Swap highbyte and lowbyte.
187
06fe285f
GM		 1882016-11-03 Graham Markall <graham.markall@embecosm.com>
189
190 * arc-dis.c (find_format_from_table): Replace use of ARC_SHORT
191 with arc_opcode_len.
192 (find_format_long_instructions): Likewise.
193 * arc-opc.c (arc_opcode_len): New function.
194
ecf64ec6
AB		 1952016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
196
197 * arc-nps400-tbl.h: Fix some instruction masks.
198
d039fef3
L		 1992016-11-03 H.J. Lu <hongjiu.lu@intel.com>
200
201 * i386-dis.c (REG_82): Removed.
202 (X86_64_82_REG_0): Likewise.
203 (X86_64_82_REG_1): Likewise.
204 (X86_64_82_REG_2): Likewise.
205 (X86_64_82_REG_3): Likewise.
206 (X86_64_82_REG_4): Likewise.
207 (X86_64_82_REG_5): Likewise.
208 (X86_64_82_REG_6): Likewise.
209 (X86_64_82_REG_7): Likewise.
210 (X86_64_82): New.
211 (dis386): Use X86_64_82 instead of REG_82.
212 (reg_table): Remove REG_82.
213 (x86_64_table): Add X86_64_82. Remove X86_64_82_REG_0,
214 X86_64_82_REG_1, X86_64_82_REG_2, X86_64_82_REG_3,
215 X86_64_82_REG_4, X86_64_82_REG_5, X86_64_82_REG_6 and
216 X86_64_82_REG_7.
217
8b89fe14
L		 2182016-11-03 H.J. Lu <hongjiu.lu@intel.com>
219
220 PR binutils/20754
221 * i386-dis.c (REG_82): New.
222 (X86_64_82_REG_0): Likewise.
223 (X86_64_82_REG_1): Likewise.
224 (X86_64_82_REG_2): Likewise.
225 (X86_64_82_REG_3): Likewise.
226 (X86_64_82_REG_4): Likewise.
227 (X86_64_82_REG_5): Likewise.
228 (X86_64_82_REG_6): Likewise.
229 (X86_64_82_REG_7): Likewise.
230 (dis386): Use REG_82.
231 (reg_table): Add REG_82.
232 (x86_64_table): Add X86_64_82_REG_0, X86_64_82_REG_1,
233 X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4,
234 X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7.
235
7148c369
L		 2362016-11-03 H.J. Lu <hongjiu.lu@intel.com>
237
238 * i386-dis.c (REG_82): Renamed to ...
239 (REG_83): This.
240 (dis386): Updated.
241 (reg_table): Likewise.
242
47acf0bd
IT		 2432016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
244
245 * i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853.
246 * i386-dis-evex.h (evex_table): Updated.
247 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS,
248 CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
249 (cpu_flags): Add CpuAVX512_4VNNIW.
250 * i386-opc.h (enum): (AVX512_4VNNIW): New.
251 (i386_cpu_flags): Add cpuavx512_4vnniw.
252 * i386-opc.tbl: Add Intel AVX512_4VNNIW instructions.
253 * i386-init.h: Regenerate.
254 * i386-tbl.h: Ditto.
255
920d2ddc
IT		 2562016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
257
258 * i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,
259 PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.
260 * i386-dis-evex.h (evex_table): Updated.
261 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,
262 CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
263 (cpu_flags): Add CpuAVX512_4FMAPS.
264 (opcode_modifiers): Add ImplicitQuadGroup modifier.
265 * i386-opc.h (AVX512_4FMAP): New.
266 (i386_cpu_flags): Add cpuavx512_4fmaps.
267 (ImplicitQuadGroup): New.
268 (i386_opcode_modifier): Add implicitquadgroup.
269 * i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.
270 * i386-init.h: Regenerate.
271 * i386-tbl.h: Ditto.
272
e23eba97
NC		 2732016-11-01 Palmer Dabbelt <palmer@dabbelt.com>
274 Andrew Waterman <andrew@sifive.com>
275
276 Add support for RISC-V architecture.
277 * configure.ac: Add entry for bfd_riscv_arch.
278 * configure: Regenerate.
279 * disassemble.c (disassembler): Add support for riscv.
280 (disassembler_usage): Likewise.
281 * riscv-dis.c: New file.
282 * riscv-opc.c: New file.
283
b5cefcca
L		 2842016-10-21 H.J. Lu <hongjiu.lu@intel.com>
285
286 * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
287 (prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
288 (rm_table): Update the RM_0FAE_REG_7 entry.
289 * i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
290 (cpu_flags): Remove CpuPCOMMIT.
291 * i386-opc.h (CpuPCOMMIT): Removed.
292 (i386_cpu_flags): Remove cpupcommit.
293 * i386-opc.tbl: Remove pcommit.
294 * i386-init.h: Regenerated.
295 * i386-tbl.h: Likewise.
296
9889cbb1
L		 2972016-10-20 H.J. Lu <hongjiu.lu@intel.com>
298
299 PR binutis/20705
300 * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
301 the highest bit in VEX.vvvv for the 3-byte VEX prefix in
302 32-bit mode. Don't check vex.register_specifier in 32-bit
303 mode.
304 (OP_VEX): Check for invalid mask registers.
305
28596323
L		 3062016-10-18 H.J. Lu <hongjiu.lu@intel.com>
307
308 PR binutis/20699
309 * i386-dis.c (OP_E_memory): Check addr32flag in stead of
310 sizeflag.
311
da8d7d66
L		 3122016-10-18 H.J. Lu <hongjiu.lu@intel.com>
313
314 PR binutis/20704
315 * i386-dis.c (three_byte_table): Remove the remaining SSE5 support.
316
eaf02703
MR		 3172016-10-18 Maciej W. Rozycki <macro@imgtec.com>
318
319 * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'
320 local variable to `index_regno'.
321
decf5bd1
CM		 3222016-10-17 Cupertino Miranda <cmiranda@synopsys.com>
323
324 * arc-tbl.h: Removed any "inv.+" instructions from the table.
325
e5b06ef0
CZ		 3262016-10-14 Claudiu Zissulescu <claziss@synopsys.com>
327
328 * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
329 usage on ISA basis.
330
93562a34
JW		 3312016-10-11 Jiong Wang <jiong.wang@arm.com>
332
333 PR target/20666
334 * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
335
362c0c4d
JW		 3362016-10-07 Jiong Wang <jiong.wang@arm.com>
337
338 PR target/20667
339 * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
340 available.
341
1047201f
AM		 3422016-10-07 Alan Modra <amodra@gmail.com>
343
344 * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
345
1a0670f3
AM		 3462016-10-06 Alan Modra <amodra@gmail.com>
347
348 * aarch64-opc.c: Spell fall through comments consistently.
349 * i386-dis.c: Likewise.
350 * aarch64-dis.c: Add missing fall through comments.
351 * aarch64-opc.c: Likewise.
352 * arc-dis.c: Likewise.
353 * arm-dis.c: Likewise.
354 * i386-dis.c: Likewise.
355 * m68k-dis.c: Likewise.
356 * mep-asm.c: Likewise.
357 * ns32k-dis.c: Likewise.
358 * sh-dis.c: Likewise.
359 * tic4x-dis.c: Likewise.
360 * tic6x-dis.c: Likewise.
361 * vax-dis.c: Likewise.
362
2b804145
AM		 3632016-10-06 Alan Modra <amodra@gmail.com>
364
365 * arc-ext.c (create_map): Add missing break.
366 * msp430-decode.opc (encode_as): Likewise.
367 * msp430-decode.c: Regenerate.
368
616ec358
AM		 3692016-10-06 Alan Modra <amodra@gmail.com>
370
371 * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
372 * crx-dis.c (print_insn_crx): Likewise.
373
72da393d
L		 3742016-09-30 H.J. Lu <hongjiu.lu@intel.com>
375
376 PR binutils/20657
377 * i386-dis.c (putop): Don't assign alt twice.
378
744ce302
JW		 3792016-09-29 Jiong Wang <jiong.wang@arm.com>
380
381 PR target/20553
382 * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
383
a5721ba2
AM		 3842016-09-29 Alan Modra <amodra@gmail.com>
385
386 * ppc-opc.c (L): Make compulsory.
387 (LOPT): New, optional form of L.
388 (HTM_R): Define as LOPT.
389 (L0, L1): Delete.
390 (L32OPT): New, optional for 32-bit L.
391 (L2OPT): New, 2-bit L for dcbf.
392 (SVC_LEC): Update.
393 (L2): Define.
394 (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
395 (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
396 <dcbf>: Use L2OPT.
397 <tlbiel, tlbie>: Use LOPT.
398 <wclr, wclrall>: Use L2.
399
c5da1932
VZ		 4002016-09-26 Vlad Zakharov <vzakhar@synopsys.com>
401
402 * Makefile.in: Regenerate.
403 * configure: Likewise.
404
2b848ebd
CZ		 4052016-09-26 Claudiu Zissulescu <claziss@synopsys.com>
406
407 * arc-ext-tbl.h (EXTINSN2OPF): Define.
408 (EXTINSN2OP): Use EXTINSN2OPF.
409 (bspeekm, bspop, modapp): New extension instructions.
410 * arc-opc.c (F_DNZ_ND): Define.
411 (F_DNZ_D): Likewise.
412 (F_SIZEB1): Changed.
413 (C_DNZ_D): Define.
414 (C_HARD): Changed.
415 * arc-tbl.h (dbnz): New instruction.
416 (prealloc): Allow it for ARC EM.
417 (xbfu): Likewise.
418
ad43e107
RS		 4192016-09-21 Richard Sandiford <richard.sandiford@arm.com>
420
421 * aarch64-opc.c (print_immediate_offset_address): Print spaces
422 after commas in addresses.
423 (aarch64_print_operand): Likewise.
424
ab3b8fcf
RS		 4252016-09-21 Richard Sandiford <richard.sandiford@arm.com>
426
427 * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
428 rather than "should be" or "expected to be" in error messages.
429
bb7eff52
RS		 4302016-09-21 Richard Sandiford <richard.sandiford@arm.com>
431
432 * aarch64-dis.c (remove_dot_suffix): New function, split out from...
433 (print_mnemonic_name): ...here.
434 (print_comment): New function.
435 (print_aarch64_insn): Call it.
436 * aarch64-opc.c (aarch64_conds): Add SVE names.
437 (aarch64_print_operand): Print alternative condition names in
438 a comment.
439
c0890d26
RS		 4402016-09-21 Richard Sandiford <richard.sandiford@arm.com>
441
442 * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
443 (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
444 (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
445 (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
446 (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
447 (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
448 (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
449 (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
450 (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
451 (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
452 (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
453 (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
454 (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
455 (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
456 (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
457 (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
458 (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
459 (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
460 (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
461 (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
462 (OP_SVE_XWU, OP_SVE_XXU): New macros.
463 (aarch64_feature_sve): New variable.
464 (SVE): New macro.
465 (_SVE_INSN): Likewise.
466 (aarch64_opcode_table): Add SVE instructions.
467 * aarch64-opc.h (extract_fields): Declare.
468 * aarch64-opc-2.c: Regenerate.
469 * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
470 * aarch64-asm-2.c: Regenerate.
471 * aarch64-dis.c (extract_fields): Make global.
472 (do_misc_decoding): Handle the new SVE aarch64_ops.
473 * aarch64-dis-2.c: Regenerate.
474
116b6019
RS		 4752016-09-21 Richard Sandiford <richard.sandiford@arm.com>
476
477 * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
478 (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
479 aarch64_field_kinds.
480 * aarch64-opc.c (fields): Add corresponding entries.
481 * aarch64-asm.c (aarch64_get_variant): New function.
482 (aarch64_encode_variant_using_iclass): Likewise.
483 (aarch64_opcode_encode): Call it.
484 * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
485 (aarch64_opcode_decode): Call it.
486
047cd301
RS		 4872016-09-21 Richard Sandiford <richard.sandiford@arm.com>
488
489 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
490 and FP register operands.
491 * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
492 (FLD_SVE_Vn): New aarch64_field_kinds.
493 * aarch64-opc.c (fields): Add corresponding entries.
494 (aarch64_print_operand): Handle the new SVE core and FP register
495 operands.
496 * aarch64-opc-2.c: Regenerate.
497 * aarch64-asm-2.c: Likewise.
498 * aarch64-dis-2.c: Likewise.
499
165d4950
RS		 5002016-09-21 Richard Sandiford <richard.sandiford@arm.com>
501
502 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
503 immediate operands.
504 * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
505 * aarch64-opc.c (fields): Add corresponding entry.
506 (operand_general_constraint_met_p): Handle the new SVE FP immediate
507 operands.
508 (aarch64_print_operand): Likewise.
509 * aarch64-opc-2.c: Regenerate.
510 * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
511 (ins_sve_float_zero_one): New inserters.
512 * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
513 (aarch64_ins_sve_float_half_two): Likewise.
514 (aarch64_ins_sve_float_zero_one): Likewise.
515 * aarch64-asm-2.c: Regenerate.
516 * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
517 (ext_sve_float_zero_one): New extractors.
518 * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
519 (aarch64_ext_sve_float_half_two): Likewise.
520 (aarch64_ext_sve_float_zero_one): Likewise.
521 * aarch64-dis-2.c: Regenerate.
522
e950b345
RS		 5232016-09-21 Richard Sandiford <richard.sandiford@arm.com>
524
525 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
526 integer immediate operands.
527 * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
528 (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
529 (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
530 * aarch64-opc.c (fields): Add corresponding entries.
531 (operand_general_constraint_met_p): Handle the new SVE integer
532 immediate operands.
533 (aarch64_print_operand): Likewise.
534 (aarch64_sve_dupm_mov_immediate_p): New function.
535 * aarch64-opc-2.c: Regenerate.
536 * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
537 (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
538 * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
539 (aarch64_ins_limm): ...here.
540 (aarch64_ins_inv_limm): New function.
541 (aarch64_ins_sve_aimm): Likewise.
542 (aarch64_ins_sve_asimm): Likewise.
543 (aarch64_ins_sve_limm_mov): Likewise.
544 (aarch64_ins_sve_shlimm): Likewise.
545 (aarch64_ins_sve_shrimm): Likewise.
546 * aarch64-asm-2.c: Regenerate.
547 * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
548 (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
549 * aarch64-dis.c (decode_limm): New function, split out from...
550 (aarch64_ext_limm): ...here.
551 (aarch64_ext_inv_limm): New function.
552 (decode_sve_aimm): Likewise.
553 (aarch64_ext_sve_aimm): Likewise.
554 (aarch64_ext_sve_asimm): Likewise.
555 (aarch64_ext_sve_limm_mov): Likewise.
556 (aarch64_top_bit): Likewise.
557 (aarch64_ext_sve_shlimm): Likewise.
558 (aarch64_ext_sve_shrimm): Likewise.
559 * aarch64-dis-2.c: Regenerate.
560
98907a70
RS		 5612016-09-21 Richard Sandiford <richard.sandiford@arm.com>
562
563 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
564 operands.
565 * aarch64-opc.c (aarch64_operand_modifiers): Initialize
566 the AARCH64_MOD_MUL_VL entry.
567 (value_aligned_p): Cope with non-power-of-two alignments.
568 (operand_general_constraint_met_p): Handle the new MUL VL addresses.
569 (print_immediate_offset_address): Likewise.
570 (aarch64_print_operand): Likewise.
571 * aarch64-opc-2.c: Regenerate.
572 * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
573 (ins_sve_addr_ri_s9xvl): New inserters.
574 * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
575 (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
576 (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
577 * aarch64-asm-2.c: Regenerate.
578 * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
579 (ext_sve_addr_ri_s9xvl): New extractors.
580 * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
581 (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
582 (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
583 (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
584 * aarch64-dis-2.c: Regenerate.
585
4df068de
RS		 5862016-09-21 Richard Sandiford <richard.sandiford@arm.com>
587
588 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
589 address operands.
590 * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
591 (FLD_SVE_xs_22): New aarch64_field_kinds.
592 (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
593 (get_operand_specific_data): New function.
594 * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
595 FLD_SVE_xs_14 and FLD_SVE_xs_22.
596 (operand_general_constraint_met_p): Handle the new SVE address
597 operands.
598 (sve_reg): New array.
599 (get_addr_sve_reg_name): New function.
600 (aarch64_print_operand): Handle the new SVE address operands.
601 * aarch64-opc-2.c: Regenerate.
602 * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
603 (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
604 (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
605 * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
606 (aarch64_ins_sve_addr_rr_lsl): Likewise.
607 (aarch64_ins_sve_addr_rz_xtw): Likewise.
608 (aarch64_ins_sve_addr_zi_u5): Likewise.
609 (aarch64_ins_sve_addr_zz): Likewise.
610 (aarch64_ins_sve_addr_zz_lsl): Likewise.
611 (aarch64_ins_sve_addr_zz_sxtw): Likewise.
612 (aarch64_ins_sve_addr_zz_uxtw): Likewise.
613 * aarch64-asm-2.c: Regenerate.
614 * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
615 (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
616 (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
617 * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
618 (aarch64_ext_sve_addr_ri_u6): Likewise.
619 (aarch64_ext_sve_addr_rr_lsl): Likewise.
620 (aarch64_ext_sve_addr_rz_xtw): Likewise.
621 (aarch64_ext_sve_addr_zi_u5): Likewise.
622 (aarch64_ext_sve_addr_zz): Likewise.
623 (aarch64_ext_sve_addr_zz_lsl): Likewise.
624 (aarch64_ext_sve_addr_zz_sxtw): Likewise.
625 (aarch64_ext_sve_addr_zz_uxtw): Likewise.
626 * aarch64-dis-2.c: Regenerate.
627
2442d846
RS		 6282016-09-21 Richard Sandiford <richard.sandiford@arm.com>
629
630 * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
631 AARCH64_OPND_SVE_PATTERN_SCALED.
632 * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
633 * aarch64-opc.c (fields): Add a corresponding entry.
634 (set_multiplier_out_of_range_error): New function.
635 (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
636 (operand_general_constraint_met_p): Handle
637 AARCH64_OPND_SVE_PATTERN_SCALED.
638 (print_register_offset_address): Use PRIi64 to print the
639 shift amount.
640 (aarch64_print_operand): Likewise. Handle
641 AARCH64_OPND_SVE_PATTERN_SCALED.
642 * aarch64-opc-2.c: Regenerate.
643 * aarch64-asm.h (ins_sve_scale): New inserter.
644 * aarch64-asm.c (aarch64_ins_sve_scale): New function.
645 * aarch64-asm-2.c: Regenerate.
646 * aarch64-dis.h (ext_sve_scale): New inserter.
647 * aarch64-dis.c (aarch64_ext_sve_scale): New function.
648 * aarch64-dis-2.c: Regenerate.
649
245d2e3f
RS		 6502016-09-21 Richard Sandiford <richard.sandiford@arm.com>
651
652 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
653 AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
654 * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
655 (FLD_SVE_prfop): Likewise.
656 * aarch64-opc.c: Include libiberty.h.
657 (aarch64_sve_pattern_array): New variable.
658 (aarch64_sve_prfop_array): Likewise.
659 (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
660 (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
661 AARCH64_OPND_SVE_PRFOP.
662 * aarch64-asm-2.c: Regenerate.
663 * aarch64-dis-2.c: Likewise.
664 * aarch64-opc-2.c: Likewise.
665
d50c751e
RS		 6662016-09-21 Richard Sandiford <richard.sandiford@arm.com>
667
668 * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
669 AARCH64_OPND_QLF_P_[ZM].
670 (aarch64_print_operand): Print /z and /m where appropriate.
671
f11ad6bc
RS		 6722016-09-21 Richard Sandiford <richard.sandiford@arm.com>
673
674 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
675 * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
676 (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
677 (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
678 (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
679 * aarch64-opc.c (fields): Add corresponding entries here.
680 (operand_general_constraint_met_p): Check that SVE register lists
681 have the correct length. Check the ranges of SVE index registers.
682 Check for cases where p8-p15 are used in 3-bit predicate fields.
683 (aarch64_print_operand): Handle the new SVE operands.
684 * aarch64-opc-2.c: Regenerate.
685 * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
686 * aarch64-asm.c (aarch64_ins_sve_index): New function.
687 (aarch64_ins_sve_reglist): Likewise.
688 * aarch64-asm-2.c: Regenerate.
689 * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
690 * aarch64-dis.c (aarch64_ext_sve_index): New function.
691 (aarch64_ext_sve_reglist): Likewise.
692 * aarch64-dis-2.c: Regenerate.
693
0c608d6b
RS		 6942016-09-21 Richard Sandiford <richard.sandiford@arm.com>
695
696 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
697 (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
698 (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
699 * aarch64-opc.c (aarch64_match_operands_constraint): Check for
700 tied operands.
701
01dbfe4c
RS		 7022016-09-21 Richard Sandiford <richard.sandiford@arm.com>
703
704 * aarch64-opc.c (get_offset_int_reg_name): New function.
705 (print_immediate_offset_address): Likewise.
706 (print_register_offset_address): Take the base and offset
707 registers as parameters.
708 (aarch64_print_operand): Update caller accordingly. Use
709 print_immediate_offset_address.
710
72e9f319
RS		 7112016-09-21 Richard Sandiford <richard.sandiford@arm.com>
712
713 * aarch64-opc.c (BANK): New macro.
714 (R32, R64): Take a register number as argument
715 (int_reg): Use BANK.
716
8a7f0c1b
RS		 7172016-09-21 Richard Sandiford <richard.sandiford@arm.com>
718
719 * aarch64-opc.c (print_register_list): Add a prefix parameter.
720 (aarch64_print_operand): Update accordingly.
721
aa2aa4c6
RS		 7222016-09-21 Richard Sandiford <richard.sandiford@arm.com>
723
724 * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
725 for FPIMM.
726 * aarch64-asm.h (ins_fpimm): New inserter.
727 * aarch64-asm.c (aarch64_ins_fpimm): New function.
728 * aarch64-asm-2.c: Regenerate.
729 * aarch64-dis.h (ext_fpimm): New extractor.
730 * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
731 (aarch64_ext_fpimm): New function.
732 * aarch64-dis-2.c: Regenerate.
733
b5464a68
RS		 7342016-09-21 Richard Sandiford <richard.sandiford@arm.com>
735
736 * aarch64-asm.c: Include libiberty.h.
737 (insert_fields): New function.
738 (aarch64_ins_imm): Use it.
739 * aarch64-dis.c (extract_fields): New function.
740 (aarch64_ext_imm): Use it.
741
42408347
RS		 7422016-09-21 Richard Sandiford <richard.sandiford@arm.com>
743
744 * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
745 with an esize parameter.
746 (operand_general_constraint_met_p): Update accordingly.
747 Fix misindented code.
748 * aarch64-asm.c (aarch64_ins_limm): Update call to
749 aarch64_logical_immediate_p.
750
4989adac
RS		 7512016-09-21 Richard Sandiford <richard.sandiford@arm.com>
752
753 * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
754
bd11d5d8
RS		 7552016-09-21 Richard Sandiford <richard.sandiford@arm.com>
756
757 * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
758
f807f43d
CZ		 7592016-09-15 Claudiu Zissulescu <claziss@synopsys.com>
760
761 * arc-dis.c (find_format): Walk the linked list pointed by einsn.
762
fd486b63
PB		 7632016-09-14 Peter Bergner <bergner@vnet.ibm.com>
764
765 * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
766 <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
767 xor3>: Delete mnemonics.
768 <cp_abort>: Rename mnemonic from ...
769 <cpabort>: ...to this.
770 <setb>: Change to a X form instruction.
771 <sync>: Change to 1 operand form.
772 <copy>: Delete mnemonic.
773 <copy_first>: Rename mnemonic from ...
774 <copy>: ...to this.
775 <paste, paste.>: Delete mnemonics.
776 <paste_last>: Rename mnemonic from ...
777 <paste.>: ...to this.
778
dce08442
AK		 7792016-09-14 Anton Kolesov <Anton.Kolesov@synopsys.com>
780
781 * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
782
952c3f51
AK		 7832016-09-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
784
785 * s390-mkopc.c (main): Support alternate arch strings.
786
8b71537b
PS		 7872016-09-12 Patrick Steuer <steuer@linux.vnet.ibm.com>
788
789 * s390-opc.txt: Fix kmctr instruction type.
790
5b64d091
L		 7912016-09-07 H.J. Lu <hongjiu.lu@intel.com>
792
793 * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
794 * i386-init.h: Regenerated.
795
7763838e
CM		 7962016-08-30 Cupertino Miranda <cmiranda@synopsys.com>
797
798 * opcodes/arc-dis.c (print_insn_arc): Changed.
799
1b8b6532
JM		 8002016-08-26 Jose E. Marchesi <jose.marchesi@oracle.com>
801
802 * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
803 camellia_fl.
804
1a336194
TP		 8052016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
806
807 * arm-dis.c (psr_name): Use hex as case labels. Add detection for
808 MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
809 FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
810
6b40c462
L		 8112016-08-24 H.J. Lu <hongjiu.lu@intel.com>
812
813 * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
814 (PREFIX_MOD_3_0FAE_REG_4): Likewise.
815 (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
816 PREFIX_MOD_3_0FAE_REG_4.
817 (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
818 PREFIX_MOD_3_0FAE_REG_4.
819 * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
820 (cpu_flags): Add CpuPTWRITE.
821 * i386-opc.h (CpuPTWRITE): New.
822 (i386_cpu_flags): Add cpuptwrite.
823 * i386-opc.tbl: Add ptwrite instruction.
824 * i386-init.h: Regenerated.
825 * i386-tbl.h: Likewise.
826
ab548d2d
AK		 8272016-08-24 Anton Kolesov <Anton.Kolesov@synopsys.com>
828
829 * arc-dis.h: Wrap around in extern "C".
830
344bde0a
RS		 8312016-08-23 Richard Sandiford <richard.sandiford@arm.com>
832
833 * aarch64-tbl.h (V8_2_INSN): New macro.
834 (aarch64_opcode_table): Use it.
835
5ce912d8
RS		 8362016-08-23 Richard Sandiford <richard.sandiford@arm.com>
837
838 * aarch64-tbl.h (aarch64_opcode_table): Make more use of
839 CORE_INSN, __FP_INSN and SIMD_INSN.
840
9d30b0bd
RS		 8412016-08-23 Richard Sandiford <richard.sandiford@arm.com>
842
843 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
844 (aarch64_opcode_table): Update uses accordingly.
845
dfdaec14
AJ		 8462016-07-25 Andrew Jenner <andrew@codesourcery.com>
847 Kwok Cheung Yeung <kcy@codesourcery.com>
848
849 opcodes/
850 * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
851 'e_cmplwi' to 'e_cmpli' instead.
852 (OPVUPRT, OPVUPRT_MASK): Define.
853 (powerpc_opcodes): Add E200Z4 insns.
854 (vle_opcodes): Add context save/restore insns.
855
7bd374a4
MR		 8562016-07-27 Maciej W. Rozycki <macro@imgtec.com>
857
858 * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
859 "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
860 "j".
861
db18dbab
GM		 8622016-07-27 Graham Markall <graham.markall@embecosm.com>
863
864 * arc-nps400-tbl.h: Change block comments to GNU format.
865 * arc-dis.c: Add new globals addrtypenames,
866 addrtypenames_max, and addtypeunknown.
867 (get_addrtype): New function.
868 (print_insn_arc): Print colons and address types when
869 required.
870 * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
871 define insert and extract functions for all address types.
872 (arc_operands): Add operands for colon and all address
873 types.
874 * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
875 * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
876 insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
877 * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
878 * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
879 insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
880
fecd57f9
L		 8812016-07-21 H.J. Lu <hongjiu.lu@intel.com>
882
883 * configure: Regenerated.
884
37fd5ef3
CZ		 8852016-07-20 Claudiu Zissulescu <claziss@synopsys.com>
886
887 * arc-dis.c (skipclass): New structure.
888 (decodelist): New variable.
889 (is_compatible_p): New function.
890 (new_element): Likewise.
891 (skip_class_p): Likewise.
892 (find_format_from_table): Use skip_class_p function.
893 (find_format): Decode first the extension instructions.
894 (print_insn_arc): Select either ARCEM or ARCHS based on elf
895 e_flags.
896 (parse_option): New function.
897 (parse_disassembler_options): Likewise.
898 (print_arc_disassembler_options): Likewise.
899 (print_insn_arc): Use parse_disassembler_options function. Proper
900 select ARCv2 cpu variant.
901 * disassemble.c (disassembler_usage): Add ARC disassembler
902 options.
903
92281a5b
MR		 9042016-07-13 Maciej W. Rozycki <macro@imgtec.com>
905
906 * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
907 annotation from the "nal" entry and reorder it beyond "bltzal".
908
6e7ced37
JM		 9092016-07-12 Jose E. Marchesi <jose.marchesi@oracle.com>
910
911 * sparc-opc.c (ldtxa): New macro.
912 (sparc_opcodes): Use the macro defined above to add entries for
913 the LDTXA instructions.
914 (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
915 instruction.
916
2f831b9a 9172016-07-07 James Bowman <james.bowman@ftdichip.com>
918
919 * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
920 and "jmpc".
921
c07315e0
JB		 9222016-07-01 Jan Beulich <jbeulich@suse.com>
923
924 * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
925 (movzb): Adjust to cover all permitted suffixes.
926 (movzw): New.
927 * i386-tbl.h: Re-generate.
928
9243100a
JB		 9292016-07-01 Jan Beulich <jbeulich@suse.com>
930
931 * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
932 (lgdt): Remove Tbyte from non-64-bit variant.
933 (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
934 xsaves64, xsavec64): Remove Disp16.
935 (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
936 Remove Disp32S from non-64-bit variants. Remove Disp16 from
937 64-bit variants.
938 (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
939 vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
940 vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
941 64-bit variants.
942 * i386-tbl.h: Re-generate.
943
8325cc63
JB		 9442016-07-01 Jan Beulich <jbeulich@suse.com>
945
946 * i386-opc.tbl (xlat): Remove RepPrefixOk.
947 * i386-tbl.h: Re-generate.
948
838441e4
YQ		 9492016-06-30 Yao Qi <yao.qi@linaro.org>
950
951 * arm-dis.c (print_insn): Fix typo in comment.
952
dab26bf4
RS		 9532016-06-28 Richard Sandiford <richard.sandiford@arm.com>
954
955 * aarch64-opc.c (operand_general_constraint_met_p): Check the
956 range of ldst_elemlist operands.
957 (print_register_list): Use PRIi64 to print the index.
958 (aarch64_print_operand): Likewise.
959
5703197e
TS		 9602016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
961
962 * mcore-opc.h: Remove sentinal.
963 * mcore-dis.c (print_insn_mcore): Adjust.
964
ce440d63
GM		 9652016-06-23 Graham Markall <graham.markall@embecosm.com>
966
967 * arc-opc.c: Correct description of availability of NPS400
968 features.
969
6fd3a02d
PB		 9702016-06-22 Peter Bergner <bergner@vnet.ibm.com>
971
972 * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
973 (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
974 mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
975 xor3>: New mnemonics.
976 <setb>: Change to a VX form instruction.
977 (insert_sh6): Add support for rldixor.
978 (extract_sh6): Likewise.
979
6b477896
TS		 9802016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
981
982 * arc-ext.h: Wrap in extern C.
983
bdd582db
GM		 9842016-06-21 Graham Markall <graham.markall@embecosm.com>
985
986 * arc-dis.c (arc_insn_length): Add comment on instruction length.
987 Use same method for determining instruction length on ARC700 and
988 NPS-400.
989 (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
990 * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
991 with the NPS400 subclass.
992 * arc-opc.c: Likewise.
993
96074adc
JM		 9942016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
995
996 * sparc-opc.c (rdasr): New macro.
997 (wrasr): Likewise.
998 (rdpr): Likewise.
999 (wrpr): Likewise.
1000 (rdhpr): Likewise.
1001 (wrhpr): Likewise.
1002 (sparc_opcodes): Use the macros above to fix and expand the
1003 definition of read/write instructions from/to
1004 asr/privileged/hyperprivileged instructions.
1005 * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
1006 %hva_mask_nz. Prefer softint_set and softint_clear over
1007 set_softint and clear_softint.
1008 (print_insn_sparc): Support %ver in Rd.
1009
7a10c22f
JM		 10102016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
1011
1012 * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
1013 architecture according to the hardware capabilities they require.
1014
4f26fb3a
JM		 10152016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
1016
1017 * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
1018 (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
1019 bfd_mach_sparc_v9{c,d,e,v,m}.
1020 * sparc-opc.c (MASK_V9C): Define.
1021 (MASK_V9D): Likewise.
1022 (MASK_V9E): Likewise.
1023 (MASK_V9V): Likewise.
1024 (MASK_V9M): Likewise.
1025 (v6): Add MASK_V9{C,D,E,V,M}.
1026 (v6notlet): Likewise.
1027 (v7): Likewise.
1028 (v8): Likewise.
1029 (v9): Likewise.
1030 (v9andleon): Likewise.
1031 (v9a): Likewise.
1032 (v9b): Likewise.
1033 (v9c): Define.
1034 (v9d): Likewise.
1035 (v9e): Likewise.
1036 (v9v): Likewise.
1037 (v9m): Likewise.
1038 (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
1039
3ee6e4fb
NC		 10402016-06-15 Nick Clifton <nickc@redhat.com>
1041
1042 * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
1043 constants to match expected behaviour.
1044 (nds32_parse_opcode): Likewise. Also for whitespace.
1045
02f3be19
AB		 10462016-06-15 Andrew Burgess <andrew.burgess@embecosm.com>
1047
1048 * arc-opc.c (extract_rhv1): Extract value from insn.
1049
6f9f37ed 10502016-06-14 Graham Markall <graham.markall@embecosm.com>
28215275
GM		 1051
1052 * arc-nps400-tbl.h: Add ldbit instruction.
1053 * arc-opc.c: Add flag classes required for ldbit.
1054
6f9f37ed 10552016-06-14 Graham Markall <graham.markall@embecosm.com>
9ba75c88
GM		 1056
1057 * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
1058 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1059 support the above instructions.
1060
6f9f37ed 10612016-06-14 Graham Markall <graham.markall@embecosm.com>
14053c19
GM		 1062
1063 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
1064 imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
1065 csma, cbba, zncv, and hofs.
1066 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1067 support the above instructions.
1068
10692016-06-06 Graham Markall <graham.markall@embecosm.com>
1070
1071 * arc-nps400-tbl.h: Add andab and orab instructions.
1072
10732016-06-06 Graham Markall <graham.markall@embecosm.com>
1074
1075 * arc-nps400-tbl.h: Add addl-like instructions.
1076
10772016-06-06 Graham Markall <graham.markall@embecosm.com>
1078
1079 * arc-nps400-tbl.h: Add mxb and imxb instructions.
1080
10812016-06-06 Graham Markall <graham.markall@embecosm.com>
1082
1083 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
1084 instructions.
1085
b2cc3f6f
AK		 10862016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1087
1088 * s390-dis.c (option_use_insn_len_bits_p): New file scope
1089 variable.
1090 (init_disasm): Handle new command line option "insnlength".
1091 (print_s390_disassembler_options): Mention new option in help
1092 output.
1093 (print_insn_s390): Use the encoded insn length when dumping
1094 unknown instructions.
1095
1857fe72
DC		 10962016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
1097
1098 * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
1099 to the address and set as symbol address for LDS/ STS immediate operands.
1100
14b57c7c
AM		 11012016-06-07 Alan Modra <amodra@gmail.com>
1102
1103 * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
1104 cpu for "vle" to e500.
1105 * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
1106 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
1107 (PPCNONE): Delete, substitute throughout.
1108 (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
1109 except for major opcode 4 and 31.
1110 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
1111
4d1464f2
MW		 11122016-06-07 Matthew Wahab <matthew.wahab@arm.com>
1113
1114 * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
1115 ARM_EXT_RAS in relevant entries.
1116
026122a6
PB		 11172016-06-03 Peter Bergner <bergner@vnet.ibm.com>
1118
1119 PR binutils/20196
1120 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
1121 opcodes for E6500.
1122
07f5af7d
L		 11232016-06-03 H.J. Lu <hongjiu.lu@intel.com>
1124
1125 PR binutis/18386
1126 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
1127 (indir_v_mode): New.
1128 Add comments for '&'.
1129 (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
1130 (putop): Handle '&'.
1131 (intel_operand_size): Handle indir_v_mode.
1132 (OP_E_register): Likewise.
1133 * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
1134 64-bit indirect call/jmp for AMD64.
1135 * i386-tbl.h: Regenerated
1136
4eb6f892
AB		 11372016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
1138
1139 * arc-dis.c (struct arc_operand_iterator): New structure.
1140 (find_format_from_table): All the old content from find_format,
1141 with some minor adjustments, and parameter renaming.
1142 (find_format_long_instructions): New function.
1143 (find_format): Rewritten.
1144 (arc_insn_length): Add LSB parameter.
1145 (extract_operand_value): New function.
1146 (operand_iterator_next): New function.
1147 (print_insn_arc): Use new functions to find opcode, and iterator
1148 over operands.
1149 * arc-opc.c (insert_nps_3bit_dst_short): New function.
1150 (extract_nps_3bit_dst_short): New function.
1151 (insert_nps_3bit_src2_short): New function.
1152 (extract_nps_3bit_src2_short): New function.
1153 (insert_nps_bitop1_size): New function.
1154 (extract_nps_bitop1_size): New function.
1155 (insert_nps_bitop2_size): New function.
1156 (extract_nps_bitop2_size): New function.
1157 (insert_nps_bitop_mod4_msb): New function.
1158 (extract_nps_bitop_mod4_msb): New function.
1159 (insert_nps_bitop_mod4_lsb): New function.
1160 (extract_nps_bitop_mod4_lsb): New function.
1161 (insert_nps_bitop_dst_pos3_pos4): New function.
1162 (extract_nps_bitop_dst_pos3_pos4): New function.
1163 (insert_nps_bitop_ins_ext): New function.
1164 (extract_nps_bitop_ins_ext): New function.
1165 (arc_operands): Add new operands.
1166 (arc_long_opcodes): New global array.
1167 (arc_num_long_opcodes): New global.
1168 * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
1169
1fe0971e
TS		 11702016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1171
1172 * nds32-asm.h: Add extern "C".
1173 * sh-opc.h: Likewise.
1174
315f180f
GM		 11752016-06-01 Graham Markall <graham.markall@embecosm.com>
1176
1177 * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
1178 0,b,limm to the rflt instruction.
1179
a2b5fccc
TS		 11802016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1181
1182 * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
1183 constant.
1184
0cbd0046
L		 11852016-05-29 H.J. Lu <hongjiu.lu@intel.com>
1186
1187 PR gas/20145
1188 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
1189 CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
1190 CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
1191 CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
1192 CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
1193 * i386-init.h: Regenerated.
1194
1848e567
L		 11952016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1196
1197 PR gas/20145
1198 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
1199 CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
1200 CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
1201 Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
1202 CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
1203 CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
1204 CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
1205 Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
1206 CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
1207 CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
1208 CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
1209 for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
1210 CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
1211 CpuRegMask for AVX512.
1212 (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
1213 and CpuRegMask.
1214 (set_bitfield_from_cpu_flag_init): New function.
1215 (set_bitfield): Remove const on f. Call
1216 set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
1217 * i386-opc.h (CpuRegMMX): New.
1218 (CpuRegXMM): Likewise.
1219 (CpuRegYMM): Likewise.
1220 (CpuRegZMM): Likewise.
1221 (CpuRegMask): Likewise.
1222 (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
1223 and cpuregmask.
1224 * i386-init.h: Regenerated.
1225 * i386-tbl.h: Likewise.
1226
e92bae62
L		 12272016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1228
1229 PR gas/20154
1230 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
1231 (opcode_modifiers): Add AMD64 and Intel64.
1232 (main): Properly verify CpuMax.
1233 * i386-opc.h (CpuAMD64): Removed.
1234 (CpuIntel64): Likewise.
1235 (CpuMax): Set to CpuNo64.
1236 (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
1237 (AMD64): New.
1238 (Intel64): Likewise.
1239 (i386_opcode_modifier): Add amd64 and intel64.
1240 (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
1241 on call and jmp.
1242 * i386-init.h: Regenerated.
1243 * i386-tbl.h: Likewise.
1244
e89c5eaa
L		 12452016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1246
1247 PR gas/20154
1248 * i386-gen.c (main): Fail if CpuMax is incorrect.
1249 * i386-opc.h (CpuMax): Set to CpuIntel64.
1250 * i386-tbl.h: Regenerated.
1251
77d66e7b
NC		 12522016-05-27 Nick Clifton <nickc@redhat.com>
1253
1254 PR target/20150
1255 * msp430-dis.c (msp430dis_read_two_bytes): New function.
1256 (msp430dis_opcode_unsigned): New function.
1257 (msp430dis_opcode_signed): New function.
1258 (msp430_singleoperand): Use the new opcode reading functions.
1259 Only disassenmble bytes if they were successfully read.
1260 (msp430_doubleoperand): Likewise.
1261 (msp430_branchinstr): Likewise.
1262 (msp430x_callx_instr): Likewise.
1263 (print_insn_msp430): Check that it is safe to read bytes before
1264 attempting disassembly. Use the new opcode reading functions.
1265
19dfcc89
PB		 12662016-05-26 Peter Bergner <bergner@vnet.ibm.com>
1267
1268 * ppc-opc.c (CY): New define. Document it.
1269 (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
1270
f3ad7637
L		 12712016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1272
1273 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
1274 CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
1275 and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
1276 CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
1277 CPU_ANY_AVX_FLAGS.
1278 * i386-init.h: Regenerated.
1279
f1360d58
L		 12802016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1281
1282 PR gas/20141
1283 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
1284 CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
1285 * i386-init.h: Regenerated.
1286
293f5f65
L		 12872016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1288
1289 * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
1290 CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
1291 * i386-init.h: Regenerated.
1292
d9eca1df
CZ		 12932016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1294
1295 * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
1296 information.
1297 (print_insn_arc): Set insn_type information.
1298 * arc-opc.c (C_CC): Add F_CLASS_COND.
1299 * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
1300 (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
1301 (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
1302 (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
1303 (brne, brne_s, jeq_s, jne_s): Likewise.
1304
87789e08
CZ		 13052016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1306
1307 * arc-tbl.h (neg): New instruction variant.
1308
c810e0b8
CZ		 13092016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
1310
1311 * arc-dis.c (find_format, find_format, get_auxreg)
1312 (print_insn_arc): Changed.
1313 * arc-ext.h (INSERT_XOP): Likewise.
1314
3d207518
TS		 13152016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1316
1317 * tic54x-dis.c (sprint_mmr): Adjust.
1318 * tic54x-opc.c: Likewise.
1319
514e58b7
AM		 13202016-05-19 Alan Modra <amodra@gmail.com>
1321
1322 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
1323
e43de63c
AM		 13242016-05-19 Alan Modra <amodra@gmail.com>
1325
1326 * ppc-opc.c: Formatting.
1327 (NSISIGNOPT): Define.
1328 (powerpc_opcodes <subis>): Use NSISIGNOPT.
1329
1401d2fe
MR		 13302016-05-18 Maciej W. Rozycki <macro@imgtec.com>
1331
1332 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
1333 replacing references to `micromips_ase' throughout.
1334 (_print_insn_mips): Don't use file-level microMIPS annotation to
1335 determine the disassembly mode with the symbol table.
1336
1178da44
PB		 13372016-05-13 Peter Bergner <bergner@vnet.ibm.com>
1338
1339 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
1340
8f4f9071
MF		 13412016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
1342
1343 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
1344 mips64r6.
1345 * mips-opc.c (D34): New macro.
1346 (mips_builtin_opcodes): Define bposge32c for DSPr3.
1347
8bc52696
AF		 13482016-05-10 Alexander Fomin <alexander.fomin@intel.com>
1349
1350 * i386-dis.c (prefix_table): Add RDPID instruction.
1351 * i386-gen.c (cpu_flag_init): Add RDPID flag.
1352 (cpu_flags): Add RDPID bitfield.
1353 * i386-opc.h (enum): Add RDPID element.
1354 (i386_cpu_flags): Add RDPID field.
1355 * i386-opc.tbl: Add RDPID instruction.
1356 * i386-init.h: Regenerate.
1357 * i386-tbl.h: Regenerate.
1358
39d911fc
TP		 13592016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1360
1361 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
1362 branch type of a symbol.
1363 (print_insn): Likewise.
1364
16a1fa25
TP		 13652016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1366
1367 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1368 Mainline Security Extensions instructions.
1369 (thumb_opcodes): Add entries for narrow ARMv8-M Security
1370 Extensions instructions.
1371 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1372 instructions.
1373 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1374 special registers.
1375
d751b79e
JM		 13762016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
1377
1378 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1379
945e0f82
CZ		 13802016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
1381
1382 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1383 (arcExtMap_genOpcode): Likewise.
1384 * arc-opc.c (arg_32bit_rc): Define new variable.
1385 (arg_32bit_u6): Likewise.
1386 (arg_32bit_limm): Likewise.
1387
20f55f38
SN		 13882016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
1389
1390 * aarch64-gen.c (VERIFIER): Define.
1391 * aarch64-opc.c (VERIFIER): Define.
1392 (verify_ldpsw): Use static linkage.
1393 * aarch64-opc.h (verify_ldpsw): Remove.
1394 * aarch64-tbl.h: Use VERIFIER for verifiers.
1395
4bd13cde
NC		 13962016-04-28 Nick Clifton <nickc@redhat.com>
1397
1398 PR target/19722
1399 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1400 * aarch64-opc.c (verify_ldpsw): New function.
1401 * aarch64-opc.h (verify_ldpsw): New prototype.
1402 * aarch64-tbl.h: Add initialiser for verifier field.
1403 (LDPSW): Set verifier to verify_ldpsw.
1404
c0f92bf9
L		 14052016-04-23 H.J. Lu <hongjiu.lu@intel.com>
1406
1407 PR binutils/19983
1408 PR binutils/19984
1409 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1410 smaller than address size.
1411
e6c7cdec
TS		 14122016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1413
1414 * alpha-dis.c: Regenerate.
1415 * crx-dis.c: Likewise.
1416 * disassemble.c: Likewise.
1417 * epiphany-opc.c: Likewise.
1418 * fr30-opc.c: Likewise.
1419 * frv-opc.c: Likewise.
1420 * ip2k-opc.c: Likewise.
1421 * iq2000-opc.c: Likewise.
1422 * lm32-opc.c: Likewise.
1423 * lm32-opinst.c: Likewise.
1424 * m32c-opc.c: Likewise.
1425 * m32r-opc.c: Likewise.
1426 * m32r-opinst.c: Likewise.
1427 * mep-opc.c: Likewise.
1428 * mt-opc.c: Likewise.
1429 * or1k-opc.c: Likewise.
1430 * or1k-opinst.c: Likewise.
1431 * tic80-opc.c: Likewise.
1432 * xc16x-opc.c: Likewise.
1433 * xstormy16-opc.c: Likewise.
1434
537aefaf
AB		 14352016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1436
1437 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1438 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1439 calcsd, and calcxd instructions.
1440 * arc-opc.c (insert_nps_bitop_size): Delete.
1441 (extract_nps_bitop_size): Delete.
1442 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1443 (extract_nps_qcmp_m3): Define.
1444 (extract_nps_qcmp_m2): Define.
1445 (extract_nps_qcmp_m1): Define.
1446 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1447 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1448 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1449 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1450 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1451 NPS_QCMP_M3.
1452
c8f785f2
AB		 14532016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1454
1455 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1456
6fd8e7c2
L		 14572016-04-15 H.J. Lu <hongjiu.lu@intel.com>
1458
1459 * Makefile.in: Regenerated with automake 1.11.6.
1460 * aclocal.m4: Likewise.
1461
4b0c052e
AB		 14622016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1463
1464 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1465 instructions.
1466 * arc-opc.c (insert_nps_cmem_uimm16): New function.
1467 (extract_nps_cmem_uimm16): New function.
1468 (arc_operands): Add NPS_XLDST_UIMM16 operand.
1469
cb040366
AB		 14702016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1471
1472 * arc-dis.c (arc_insn_length): New function.
1473 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1474 (find_format): Change insnLen parameter to unsigned.
1475
accc0180
NC		 14762016-04-13 Nick Clifton <nickc@redhat.com>
1477
1478 PR target/19937
1479 * v850-opc.c (v850_opcodes): Correct masks for long versions of
1480 the LD.B and LD.BU instructions.
1481
f36e33da
CZ		 14822016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1483
1484 * arc-dis.c (find_format): Check for extension flags.
1485 (print_flags): New function.
1486 (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1487 .extAuxRegister.
1488 * arc-ext.c (arcExtMap_coreRegName): Use
1489 LAST_EXTENSION_CORE_REGISTER.
1490 (arcExtMap_coreReadWrite): Likewise.
1491 (dump_ARC_extmap): Update printing.
1492 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1493 (arc_aux_regs): Add cpu field.
1494 * arc-regs.h: Add cpu field, lower case name aux registers.
1495
1c2e355e
CZ		 14962016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1497
1498 * arc-tbl.h: Add rtsc, sleep with no arguments.
1499
b99747ae
CZ		 15002016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1501
1502 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1503 Initialize.
1504 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1505 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1506 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1507 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1508 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1509 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1510 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1511 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1512 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1513 (arc_opcode arc_opcodes): Null terminate the array.
1514 (arc_num_opcodes): Remove.
1515 * arc-ext.h (INSERT_XOP): Define.
1516 (extInstruction_t): Likewise.
1517 (arcExtMap_instName): Delete.
1518 (arcExtMap_insn): New function.
1519 (arcExtMap_genOpcode): Likewise.
1520 * arc-ext.c (ExtInstruction): Remove.
1521 (create_map): Zero initialize instruction fields.
1522 (arcExtMap_instName): Remove.
1523 (arcExtMap_insn): New function.
1524 (dump_ARC_extmap): More info while debuging.
1525 (arcExtMap_genOpcode): New function.
1526 * arc-dis.c (find_format): New function.
1527 (print_insn_arc): Use find_format.
1528 (arc_get_disassembler): Enable dump_ARC_extmap only when
1529 debugging.
1530
92708cec
MR		 15312016-04-11 Maciej W. Rozycki <macro@imgtec.com>
1532
1533 * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1534 instruction bits out.
1535
a42a4f84
AB		 15362016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1537
1538 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1539 * arc-opc.c (arc_flag_operands): Add new flags.
1540 (arc_flag_classes): Add new classes.
1541
1328504b
AB		 15422016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1543
1544 * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1545
820f03ff
AB		 15462016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
1547
1548 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1549 encode1, rflt, crc16, and crc32 instructions.
1550 * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1551 (arc_flag_classes): Add C_NPS_R.
1552 (insert_nps_bitop_size_2b): New function.
1553 (extract_nps_bitop_size_2b): Likewise.
1554 (insert_nps_bitop_uimm8): Likewise.
1555 (extract_nps_bitop_uimm8): Likewise.
1556 (arc_operands): Add new operand entries.
1557
8ddf6b2a
CZ		 15582016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
1559
b99747ae
CZ		 1560 * arc-regs.h: Add a new subclass field. Add double assist
1561 accumulator register values.
1562 * arc-tbl.h: Use DPA subclass to mark the double assist
1563 instructions. Use DPX/SPX subclas to mark the FPX instructions.
1564 * arc-opc.c (RSP): Define instead of SP.
1565 (arc_aux_regs): Add the subclass field.
8ddf6b2a 1566
589a7d88
JW		 15672016-04-05 Jiong Wang <jiong.wang@arm.com>
1568
1569 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1570
0a191de9 15712016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
2cce10e7
AB		 1572
1573 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1574 NPS_R_SRC1.
1575
0a106562
AB		 15762016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
1577
1578 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1579 issues. No functional changes.
1580
bd05ac5f
CZ		 15812016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
1582
b99747ae
CZ		 1583 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1584 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1585 (RTT): Remove duplicate.
1586 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1587 (PCT_CONFIG*): Remove.
1588 (D1L, D1H, D2H, D2L): Define.
bd05ac5f 1589
9885948f
CZ		 15902016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1591
b99747ae 1592 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
9885948f 1593
f2dd8838
CZ		 15942016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1595
b99747ae
CZ		 1596 * arc-tbl.h (invld07): Remove.
1597 * arc-ext-tbl.h: New file.
1598 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1599 * arc-opc.c (arc_opcodes): Add ext-tbl include.
f2dd8838 1600
0d2f91fe
JK		 16012016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
1602
1603 Fix -Wstack-usage warnings.
1604 * aarch64-dis.c (print_operands): Substitute size.
1605 * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1606
a6b71f42
JM		 16072016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
1608
1609 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1610 to get a proper diagnostic when an invalid ASR register is used.
1611
9780e045
NC		 16122016-03-22 Nick Clifton <nickc@redhat.com>
1613
1614 * configure: Regenerate.
1615
e23e8ebe
AB		 16162016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1617
1618 * arc-nps400-tbl.h: New file.
1619 * arc-opc.c: Add top level comment.
1620 (insert_nps_3bit_dst): New function.
1621 (extract_nps_3bit_dst): New function.
1622 (insert_nps_3bit_src2): New function.
1623 (extract_nps_3bit_src2): New function.
1624 (insert_nps_bitop_size): New function.
1625 (extract_nps_bitop_size): New function.
1626 (arc_flag_operands): Add nps400 entries.
1627 (arc_flag_classes): Add nps400 entries.
1628 (arc_operands): Add nps400 entries.
1629 (arc_opcodes): Add nps400 include.
1630
1ae8ab47
AB		 16312016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1632
1633 * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1634 the new class enum values.
1635
8699fc3e
AB		 16362016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1637
1638 * arc-dis.c (print_insn_arc): Handle nps400.
1639
24740d83
AB		 16402016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1641
1642 * arc-opc.c (BASE): Delete.
1643
8678914f
NC		 16442016-03-18 Nick Clifton <nickc@redhat.com>
1645
1646 PR target/19721
1647 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1648 of MOV insn that aliases an ORR insn.
1649
cc933301
JW		 16502016-03-16 Jiong Wang <jiong.wang@arm.com>
1651
1652 * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1653
f86f5863
TS		 16542016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1655
1656 * mcore-opc.h: Add const qualifiers.
1657 * microblaze-opc.h (struct op_code_struct): Likewise.
1658 * sh-opc.h: Likewise.
1659 * tic4x-dis.c (tic4x_print_indirect): Likewise.
1660 (tic4x_print_op): Likewise.
1661
62de1c63
AM		 16622016-03-02 Alan Modra <amodra@gmail.com>
1663
d11698cd 1664 * or1k-desc.h: Regenerate.
62de1c63 1665 * fr30-ibld.c: Regenerate.
c697cf0b 1666 * rl78-decode.c: Regenerate.
62de1c63 1667
020efce5
NC		 16682016-03-01 Nick Clifton <nickc@redhat.com>
1669
1670 PR target/19747
1671 * rl78-dis.c (print_insn_rl78_common): Fix typo.
1672
b0c11777
RL		 16732016-02-24 Renlin Li <renlin.li@arm.com>
1674
1675 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1676 (print_insn_coprocessor): Support fp16 instructions.
1677
3e309328
RL		 16782016-02-24 Renlin Li <renlin.li@arm.com>
1679
1680 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1681 vminnm, vrint(mpna).
1682
8afc7bea
RL		 16832016-02-24 Renlin Li <renlin.li@arm.com>
1684
1685 * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1686 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1687
4fd7268a
L		 16882016-02-15 H.J. Lu <hongjiu.lu@intel.com>
1689
1690 * i386-dis.c (print_insn): Parenthesize expression to prevent
1691 truncated addresses.
1692 (OP_J): Likewise.
1693
4670103e
CZ		 16942016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
1695 Janek van Oirschot <jvanoirs@synopsys.com>
1696
b99747ae
CZ		 1697 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1698 variable.
4670103e 1699
c1d9289f
NC		 17002016-02-04 Nick Clifton <nickc@redhat.com>
1701
1702 PR target/19561
1703 * msp430-dis.c (print_insn_msp430): Add a special case for
1704 decoding an RRC instruction with the ZC bit set in the extension
1705 word.
1706
a143b004
AB		 17072016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1708
1709 * cgen-ibld.in (insert_normal): Rework calculation of shift.
1710 * epiphany-ibld.c: Regenerate.
1711 * fr30-ibld.c: Regenerate.
1712 * frv-ibld.c: Regenerate.
1713 * ip2k-ibld.c: Regenerate.
1714 * iq2000-ibld.c: Regenerate.
1715 * lm32-ibld.c: Regenerate.
1716 * m32c-ibld.c: Regenerate.
1717 * m32r-ibld.c: Regenerate.
1718 * mep-ibld.c: Regenerate.
1719 * mt-ibld.c: Regenerate.
1720 * or1k-ibld.c: Regenerate.
1721 * xc16x-ibld.c: Regenerate.
1722 * xstormy16-ibld.c: Regenerate.
1723
b89807c6
AB		 17242016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1725
1726 * epiphany-dis.c: Regenerated from latest cpu files.
1727
d8c823c8
MM		 17282016-02-01 Michael McConville <mmcco@mykolab.com>
1729
1730 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1731 test bit.
1732
5bc5ae88
RL		 17332016-01-25 Renlin Li <renlin.li@arm.com>
1734
1735 * arm-dis.c (mapping_symbol_for_insn): New function.
1736 (find_ifthen_state): Call mapping_symbol_for_insn().
1737
0bff6e2d
MW		 17382016-01-20 Matthew Wahab <matthew.wahab@arm.com>
1739
1740 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1741 of MSR UAO immediate operand.
1742
100b4f2e
MR		 17432016-01-18 Maciej W. Rozycki <macro@imgtec.com>
1744
1745 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1746 instruction support.
1747
5c14705f
AM		 17482016-01-17 Alan Modra <amodra@gmail.com>
1749
1750 * configure: Regenerate.
1751
4d82fe66
NC		 17522016-01-14 Nick Clifton <nickc@redhat.com>
1753
1754 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1755 instructions that can support stack pointer operations.
1756 * rl78-decode.c: Regenerate.
1757 * rl78-dis.c: Fix display of stack pointer in MOVW based
1758 instructions.
1759
651657fa
MW		 17602016-01-14 Matthew Wahab <matthew.wahab@arm.com>
1761
1762 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1763 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
1764 erxtatus_el1 and erxaddr_el1.
1765
105bde57
MW		 17662016-01-12 Matthew Wahab <matthew.wahab@arm.com>
1767
1768 * arm-dis.c (arm_opcodes): Add "esb".
1769 (thumb_opcodes): Likewise.
1770
afa8d405
PB		 17712016-01-11 Peter Bergner <bergner@vnet.ibm.com>
1772
1773 * ppc-opc.c <xscmpnedp>: Delete.
1774 <xvcmpnedp>: Likewise.
1775 <xvcmpnedp.>: Likewise.
1776 <xvcmpnesp>: Likewise.
1777 <xvcmpnesp.>: Likewise.
1778
83c3256e
AS		 17792016-01-08 Andreas Schwab <schwab@linux-m68k.org>
1780
1781 PR gas/13050
1782 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1783 addition to ISA_A.
1784
6f2750fe
AM		 17852016-01-01 Alan Modra <amodra@gmail.com>
1786
1787 Update year range in copyright notice of all files.
1788
3499769a
AM		 1789For older changes see ChangeLog-2015
1790\f
1791Copyright (C) 2016 Free Software Foundation, Inc.
1792
1793Copying and distribution of this file, with or without modification,
1794are permitted in any medium without royalty provided the copyright
1795notice and this notice are preserved.
1796
1797Local Variables:
1798mode: change-log
1799left-margin: 8
1800fill-column: 74
1801version-control: never
1802End:
GDB Binutils - Deliverables
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