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* gdb.cp/formatted-ref.exp: Add equality test.
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
9f7678f6
AS		 12008-11-26 Andreas Schwab <schwab@suse.de>
2
3 * m68k-dis.c (NEXTBYTE, NEXTWORD, NEXTLONG, NEXTULONG, NEXTSINGLE)
4 (NEXTDOUBLE, NEXTEXTEND, NEXTPACKED): Fix error handling.
5 (save_printer, save_print_address): Remove.
6 (fetch_data): Don't use them.
7 (match_insn_m68k): Always restore printing functions.
8 (print_insn_m68k): Don't save/restore printing functions.
9
62443ade
NC		 102008-11-25 Nick Clifton <nickc@redhat.com>
11
12 * m68k-dis.c: Rewrite to remove use of setjmp/longjmp.
13
8e79c3df
CM		 142008-11-18 Catherine Moore <clm@codesourcery.com>
15
16 * arm-dis.c (coprocessor_opcodes): Add half-precision vcvt
17 instructions.
18 (neon_opcodes): Likewise.
19 (print_insn_coprocessor): Print 't' or 'b' for vcvt
20 instructions.
21
d387240a
TG		 222008-11-14 Tristan Gingold <gingold@adacore.com>
23
24 * makefile.vms (OBJS): Update list of objects.
25 (DEFS): Update
26 (CFLAGS): Update.
27
4dc48ef6
CF		 282008-11-06 Chao-ying Fu <fu@mips.com>
29
30 * mips-opc.c (synciobdma, syncs, syncw, syncws): Move these
31 before sync.
32 (sync): New instruction with 5-bit sync type.
3c6528a8 33 * mips-dis.c (print_insn_args): Add case '1' to print 5-bit values.
4dc48ef6 34
c8941035
NC		 352008-11-06 Nick Clifton <nickc@redhat.com>
36
37 * avr-dis.c: Replace uses of sprintf without a format string with
38 calls to strcpy.
39
a7bea99d
L		 402008-11-03 H.J. Lu <hongjiu.lu@intel.com>
41
42 * i386-opc.tbl: Add cmovpe and cmovpo.
43 * i386-tbl.h: Regenerated.
44
4267b19f
NC		 452008-10-22 Nick Clifton <nickc@redhat.com>
46
47 PR 6937
48 * configure.in (SHARED_LIBADD): Revert previous change.
49 Add a comment explaining why.
50 (SHARED_DEPENDENCIES): Revert previous change.
51 * configure: Regenerate.
52
8a9629d0
NC		 532008-10-10 Nick Clifton <nickc@redhat.com>
54
55 PR 6937
56 * configure.in (SHARED_LIBADD): Add libiberty.a.
57 (SHARED_DEPENDENCIES): Add libiberty.a.
58
c587b3f9
L		 592008-09-30 H.J. Lu <hongjiu.lu@intel.com>
60
61 * i386-gen.c: Include "hashtab.h".
62 (next_field): Take a new argument, last. Check last.
63 (process_i386_cpu_flag): Updated.
64 (process_i386_opcode_modifier): Likewise.
65 (process_i386_operand_type): Likewise.
66 (process_i386_registers): Likewise.
67 (output_i386_opcode): New.
68 (opcode_hash_entry): Likewise.
69 (opcode_hash_table): Likewise.
70 (opcode_hash_hash): Likewise.
71 (opcode_hash_eq): Likewise.
72 (process_i386_opcodes): Use opcode hash table and opcode array.
73
34b23dab
AK		 742008-09-30 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
75
76 * s390-opc.txt (stdy, stey): Fix description
77
782e11fd
AM		 782008-09-30 Alan Modra <amodra@bigpond.net.au>
79
80 * Makefile.am: Run "make dep-am".
81 * Makefile.in: Regenerate.
82
1927a18f
L		 832008-09-29 H.J. Lu <hongjiu.lu@intel.com>
84
85 * aclocal.m4: Regenerated.
86 * configure: Likewise.
87 * Makefile.in: Likewise.
88
afac680a
NC		 892008-09-29 Nick Clifton <nickc@redhat.com>
90
91 * po/vi.po: Updated Vietnamese translation.
92 * po/fr.po: Updated French translation.
93
b40d5eb9
AK		 942008-09-26 Florian Krohm <fkrohm@us.ibm.com>
95
96 * s390-opc.txt (thder, thdr): Change RRE_RR to RRE_FF.
97 (cfxr, cfdr, cfer, clclu): Add esa flag.
98 (sqd): Instruction added.
99 (qadtr, qaxtr): Change RRF_FFFU to RRF_FUFF.
100 * s390-opc.c: (INSTR_RRF_FFFU, MASK_RRF_FFFU): Removed.
101
d0411736
AM		 1022008-09-14 Arnold Metselaar <arnold.metselaar@planet.nl>
103
104 * z80-dis.c (prt_rr_nn): Fix register pair for two byte opcodes.
105 (tab_elt opc_ed): Add "ld r,a" and "ld r,a" instructions.
106
3e126784
L		 1072008-09-11 H.J. Lu <hongjiu.lu@intel.com>
108
109 * i386-opc.tbl: Fix memory operand size for cmpXXXs[sd].
110 * i386-tbl.h: Regenerated.
111
ddab3d59
JB		 1122008-08-28 Jan Beulich <jbeulich@novell.com>
113
114 * i386-dis.c (dis386): Adjust far return mnemonics.
115 * i386-opc.tbl: Add retf.
116 * i386-tbl.h: Re-generate.
117
b19d5385
JB		 1182008-08-28 Jan Beulich <jbeulich@novell.com>
119
120 * i386-dis.c (dis386_twobyte): Adjust cmovXX mnemonics.
121
1ca35711
L		 1222008-08-28 H.J. Lu <hongjiu.lu@intel.com>
123
124 * ia64-dis.c (print_insn_ia64): Handle cr.iib0 and cr.iib1.
125 * ia64-gen.c (lookup_specifier): Likewise.
126
127 * ia64-ic.tbl: Add support for cr.iib0 and cr.iib1.
128 * ia64-raw.tbl: Likewise.
129 * ia64-waw.tbl: Likewise.
130 * ia64-asmtab.c: Regenerated.
131
515c56e7
L		 1322008-08-27 H.J. Lu <hongjiu.lu@intel.com>
133
134 * i386-opc.tbl: Correct fidivr operand size.
135
136 * i386-tbl.h: Regenerated.
137
da594c4a
AM		 1382008-08-24 Alan Modra <amodra@bigpond.net.au>
139
140 * configure.in: Update a number of obsolete autoconf macros.
141 * aclocal.m4: Regenerate.
142
a5ff0eb2
L		 1432008-08-20 H.J. Lu <hongjiu.lu@intel.com>
144
145 AVX Programming Reference (August, 2008)
146 * i386-dis.c (PREFIX_VEX_38DB): New.
147 (PREFIX_VEX_38DC): Likewise.
148 (PREFIX_VEX_38DD): Likewise.
149 (PREFIX_VEX_38DE): Likewise.
150 (PREFIX_VEX_38DF): Likewise.
151 (PREFIX_VEX_3ADF): Likewise.
152 (VEX_LEN_38DB_P_2): Likewise.
153 (VEX_LEN_38DC_P_2): Likewise.
154 (VEX_LEN_38DD_P_2): Likewise.
155 (VEX_LEN_38DE_P_2): Likewise.
156 (VEX_LEN_38DF_P_2): Likewise.
157 (VEX_LEN_3ADF_P_2): Likewise.
158 (PREFIX_VEX_3A04): Updated.
159 (VEX_LEN_3A06_P_2): Likewise.
160 (prefix_table): Add PREFIX_VEX_38DB, PREFIX_VEX_38DC,
161 PREFIX_VEX_38DD, PREFIX_VEX_38DE and PREFIX_VEX_3ADF.
162 (x86_64_table): Likewise.
163 (vex_len_table): Add VEX_LEN_38DB_P_2, VEX_LEN_38DC_P_2,
164 VEX_LEN_38DD_P_2, VEX_LEN_38DE_P_2, VEX_LEN_38DF_P_2 and
165 VEX_LEN_3ADF_P_2.
166
167 * i386-opc.tbl: Add AES + AVX instructions.
168 * i386-init.h: Regenerated.
169 * i386-tbl.h: Likewise.
170
7dc6076f
AK		 1712008-08-15 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
172
173 * s390-opc.c (INSTR_RRF_FFRU, MASK_RRF_FFRU): New instruction format.
174 * s390-opc.txt (lxr, rrdtr, rrxtr): Fix instruction format.
175
7357c5b6
AM		 1762008-08-15 Alan Modra <amodra@bigpond.net.au>
177
178 PR 6526
179 * configure.in: Invoke AC_USE_SYSTEM_EXTENSIONS.
180 * Makefile.in: Regenerate.
181 * aclocal.m4: Regenerate.
182 * config.in: Regenerate.
183 * configure: Regenerate.
184
899d85be
AM		 1852008-08-14 Sebastian Huber <sebastian.huber@embedded-brains.de>
186
187 PR 6825
188 * ppc-opc.c (powerpc_opcodes): Enable rfci, mfpmr, mtpmr for e300.
189
dfb07592
L		 1902008-08-12 H.J. Lu <hongjiu.lu@intel.com>
191
192 * i386-opc.tbl: Add syscall and sysret for Cpu64.
193
194 * i386-tbl.h: Regenerated.
195
323ee3f4
AM		 1962008-08-04 Alan Modra <amodra@bigpond.net.au>
197
198 * Makefile.am (POTFILES.in): Set LC_ALL=C.
199 * Makefile.in: Regenerate.
200 * po/POTFILES.in: Regenerate.
201
9b4e5766
PB		 2022008-08-01 Peter Bergner <bergner@vnet.ibm.com>
203
204 * ppc-dis.c (powerpc_init_dialect): Handle power7 and vsx options.
205 (print_insn_powerpc): Prepend 'vs' when printing VSX registers.
206 (print_ppc_disassembler_options): Document -Mpower7 and -Mvsx.
207 * ppc-opc.c (insert_xt6): New static function.
208 (extract_xt6): Likewise.
209 (insert_xa6): Likewise.
210 (extract_xa6: Likewise.
211 (insert_xb6): Likewise.
212 (extract_xb6): Likewise.
213 (insert_xb6s): Likewise.
214 (extract_xb6s): Likewise.
215 (XS6, XT6, XA6, XB6, XB6S, DM, XX3, XX3DM, XX1_MASK, XX3_MASK,
216 XX3DM_MASK, PPCVSX): New.
217 (powerpc_opcodes): Add opcodes "lxvd2x", "lxvd2ux", "stxvd2x",
218 "stxvd2ux", "xxmrghd", "xxmrgld", "xxpermdi", "xvmovdp", "xvcpsgndp".
219
20fd6e2e
PA		 2202008-08-01 Pedro Alves <pedro@codesourcery.com>
221
222 * Makefile.am ($(srcdir)/ia64-asmtab.c): Remove line continuation.
223 * Makefile.in: Regenerate.
224
a656ed5b
L		 2252008-08-01 H.J. Lu <hongjiu.lu@intel.com>
226
227 * i386-reg.tbl: Use Dw2Inval on AVX registers.
228 * i386-tbl.h: Regenerated.
229
081ba1b3
AM		 2302008-07-30 Michael J. Eager <eager@eagercon.com>
231
232 * ppc-dis.c (print_insn_powerpc): Disassemble FSL/FCR/UDI fields.
233 * ppc-opc.c (powerpc_operands): Add Xilinx APU related operands.
234 (insert_sprg, PPC405): Use PPC_OPCODE_405.
235 (powerpc_opcodes): Add Xilinx APU related opcodes.
236
0af1713e
AM		 2372008-07-30 Alan Modra <amodra@bigpond.net.au>
238
239 * bfin-dis.c, cris-dis.c, i386-dis.c, or32-opc.c: Silence gcc warnings.
240
30c09090
RS		 2412008-07-10 Richard Sandiford <rdsandiford@googlemail.com>
242
243 * mips-dis.c (_print_insn_mips): Use ELF_ST_IS_MIPS16.
244
c27e721e
AN		 2452008-07-07 Adam Nemet <anemet@caviumnetworks.com>
246
247 * mips-opc.c (CP): New macro.
248 (mips_builtin_opcodes): Mark c0, c2 and c3 as CP. Add Octeon to the
249 membership of di, dmfc0, dmtc0, ei, mfc0 and mtc0. Add dmfc2 and
250 dmtc2 Octeon instructions.
251
bd2e2557
SS		 2522008-07-07 Stan Shebs <stan@codesourcery.com>
253
254 * dis-init.c (init_disassemble_info): Init endian_code field.
255 * arm-dis.c (print_insn): Disassemble code according to
256 setting of endian_code.
257 (print_insn_big_arm): Detect when BE8 extension flag has been set.
258
6ba2a415
RS		 2592008-06-30 Richard Sandiford <rdsandiford@googlemail.com>
260
261 * mips-dis.c (_print_insn_mips): Use bfd_asymbol_flavour to check
262 for ELF symbols.
263
c8187e15
PB		 2642008-06-25 Peter Bergner <bergner@vnet.ibm.com>
265
266 * ppc-dis.c (powerpc_init_dialect): Handle -M464.
267 (print_ppc_disassembler_options): Likewise.
268 * ppc-opc.c (PPC464): Define.
269 (powerpc_opcodes): Add mfdcrux and mtdcrux.
270
7a283e07
RW		 2712008-06-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
272
273 * configure: Regenerate.
274
fa452fa6
PB		 2752008-06-13 Peter Bergner <bergner@vnet.ibm.com>
276
277 * ppc-dis.c (print_insn_powerpc): Update prototye to use new
278 ppc_cpu_t typedef.
279 (struct dis_private): New.
280 (POWERPC_DIALECT): New define.
281 (powerpc_dialect): Renamed to...
282 (powerpc_init_dialect): This. Update to use ppc_cpu_t and
283 struct dis_private.
284 (print_insn_big_powerpc): Update for using structure in
285 info->private_data.
286 (print_insn_little_powerpc): Likewise.
287 (operand_value_powerpc): Change type of dialect param to ppc_cpu_t.
288 (skip_optional_operands): Likewise.
289 (print_insn_powerpc): Likewise. Remove initialization of dialect.
290 * ppc-opc.c (extract_bat, extract_bba, extract_bdm, extract_bdp,
291 extract_bo, extract_boe, extract_fxm, extract_mb6, extract_mbe,
292 extract_nb, extract_nsi, extract_rbs, extract_sh6, extract_spr,
293 extract_sprg, extract_tbr insert_bat, insert_bba, insert_bdm,
294 insert_bdp, insert_bo, insert_boe, insert_fxm, insert_mb6, insert_mbe,
295 insert_nsi, insert_ral, insert_ram, insert_raq, insert_ras, insert_rbs,
296 insert_sh6, insert_spr, insert_sprg, insert_tbr): Change the dialect
297 param to be of type ppc_cpu_t. Update prototype.
298
bb35fb24
NC		 2992008-06-12 Adam Nemet <anemet@caviumnetworks.com>
300
301 * mips-dis.c (print_insn_args): Handle field descriptors +x, +p,
302 +s, +S.
303 * mips-opc.c (mips_builtin_opcodes): Add Octeon instructions
304 baddu, bbit*, cins*, dmul, pop, dpop, exts*, mtm*, mtp*, syncs,
305 syncw, syncws, vm3mulu, vm0 and vmulu.
306
dd3cbb7e
NC		 307 * mips-dis.c (print_insn_args): Handle field descriptor +Q.
308 * mips-opc.c (mips_builtin_opcodes): Add Octeon instructions seq,
309 seqi, sne and snei.
310
a5dabbb0
L		 3112008-05-30 H.J. Lu <hongjiu.lu@intel.com>
312
313 * i386-opc.tbl: Add vmovd with 64bit operand.
314 * i386-tbl.h: Regenerated.
315
725a9891
MS		 3162008-05-27 Martin Schwidefsky <schwidefsky@de.ibm.com>
317
318 * s390-opc.c (INSTR_RRF_R0RR): Fix RRF_R0RR operand format.
319
cbc80391
L		 3202008-05-22 H.J. Lu <hongjiu.lu@intel.com>
321
322 * i386-opc.tbl: Add NoAVX to cvtpd2pi, cvtpi2pd and cvttpd2pi.
323 * i386-tbl.h: Regenerated.
324
116615c5
L		 3252008-05-22 H.J. Lu <hongjiu.lu@intel.com>
326
327 PR gas/6517
328 * i386-opc.tbl: Break cvtsi2ss/cvtsi2sd/vcvtsi2sd/vcvtsi2ss
3c6528a8 329 into 32bit and 64bit. Remove Reg64|Qword and add
116615c5
L		 330 IgnoreSize|No_qSuf on 32bit version.
331 * i386-tbl.h: Regenerated.
332
d9479f2d
L		 3332008-05-21 H.J. Lu <hongjiu.lu@intel.com>
334
335 * i386-opc.tbl: Add NoAVX to movdq2q and movq2dq.
336 * i386-tbl.h: Regenerated.
337
3ce6fddb
NC		 3382008-05-21 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
339
340 * cr16-dis.c (build_mask): Adjust the mask for 32-bit bcond.
341
8944f3c2
AM		 3422008-05-14 Alan Modra <amodra@bigpond.net.au>
343
344 * Makefile.am: Run "make dep-am".
345 * Makefile.in: Regenerate.
346
f1f8f695
L		 3472008-05-02 H.J. Lu <hongjiu.lu@intel.com>
348
349 * i386-dis.c (MOVBE_Fixup): New.
350 (Mo): Likewise.
351 (PREFIX_0F3880): Likewise.
352 (PREFIX_0F3881): Likewise.
353 (PREFIX_0F38F0): Updated.
354 (prefix_table): Add PREFIX_0F3880 and PREFIX_0F3881. Update
355 PREFIX_0F38F0 and PREFIX_0F38F1 for movbe.
356 (three_byte_table): Use PREFIX_0F3880 and PREFIX_0F3881.
357
358 * i386-gen.c (cpu_flag_init): Add CPU_MOVBE_FLAGS and
359 CPU_EPT_FLAGS.
360 (cpu_flags): Add CpuMovbe and CpuEPT.
361
362 * i386-opc.h (CpuMovbe): New.
363 (CpuEPT): Likewise.
364 (CpuLM): Updated.
365 (i386_cpu_flags): Add cpumovbe and cpuept.
366
367 * i386-opc.tbl: Add entries for movbe and EPT instructions.
368 * i386-init.h: Regenerated.
369 * i386-tbl.h: Likewise.
370
89aa3097
AN		 3712008-04-29 Adam Nemet <anemet@caviumnetworks.com>
372
373 * mips-opc.c (mips_builtin_opcodes): Set field `match' to 0 for
374 the two drem and the two dremu macros.
375
39c5c168
AN		 3762008-04-28 Adam Nemet <anemet@caviumnetworks.com>
377
378 * mips-opc.c (mips_builtin_opcodes): Mark prefx and c1
379 instructions FP_S. Mark l.s, li.s, lwc1, swc1, s.s, trunc.w.s and
380 cop1 macros INSN2_M_FP_S. Mark l.d, li.d, ldc1 and sdc1 macros
381 INSN2_M_FP_D. Mark trunc.w.d macro INSN2_M_FP_S and INSN2_M_FP_D.
382
f04d18b7
DM		 3832008-04-25 David S. Miller <davem@davemloft.net>
384
385 * sparc-dis.c: Emit %stick instead of %sys_tick, and %stick_cmpr
386 instead of %sys_tick_cmpr, as suggested in architecture manuals.
387
6194aaab
L		 3882008-04-23 Paolo Bonzini <bonzini@gnu.org>
389
390 * aclocal.m4: Regenerate.
391 * configure: Regenerate.
392
1a6b486f
DM		 3932008-04-23 David S. Miller <davem@davemloft.net>
394
395 * sparc-opc.c (asi_table): Add UltraSPARC and Niagara
396 extended values.
397 (prefetch_table): Add missing values.
398
81f8a913
L		 3992008-04-22 H.J. Lu <hongjiu.lu@intel.com>
400
401 * i386-gen.c (opcode_modifiers): Add NoAVX.
402
403 * i386-opc.h (NoAVX): New.
404 (OldGcc): Updated.
405 (i386_opcode_modifier): Add noavx.
406
407 * i386-opc.tbl: Add NoAVX to SSE, SSE2, SSE3 and SSSE3
408 instructions which don't have AVX equivalent.
409 * i386-tbl.h: Regenerated.
410
dae39acc
L		 4112008-04-18 H.J. Lu <hongjiu.lu@intel.com>
412
413 * i386-dis.c (OP_VEX_FMA): New.
414 (OP_EX_VexImmW): Likewise.
415 (VexFMA): Likewise.
416 (Vex128FMA): Likewise.
417 (EXVexImmW): Likewise.
418 (get_vex_imm8): Likewise.
419 (OP_EX_VexReg): Likewise.
420 (vex_i4_done): Renamed to ...
421 (vex_w_done): This.
422 (prefix_table): Replace EXVexW with EXVexImmW on vpermil2ps
423 and vpermil2pd. Replace Vex/Vex128 with VexFMA/Vex128FMA on
424 FMA instructions.
425 (print_insn): Updated.
426 (OP_EX_VexW): Rewrite to swap register in VEX with EX.
427 (OP_REG_VexI4): Check invalid high registers.
428
ce886ab1
DR		 4292008-04-16 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
430 Michael Meissner <michael.meissner@amd.com>
431
432 * i386-opc.tbl: Fix protX to allow memory in the middle operand.
433 * i386-tbl.h: Regenerate from i386-opc.tbl.
8944f3c2 434
19a6653c
AM		 4352008-04-14 Edmar Wienskoski <edmar@freescale.com>
436
437 * ppc-dis.c (powerpc_dialect): Handle "e500mc". Extend "e500" to
438 accept Power E500MC instructions.
439 (print_ppc_disassembler_options): Document -Me500mc.
440 * ppc-opc.c (DUIS, DUI, T): New.
441 (XRT, XRTRA): Likewise.
442 (E500MC): Likewise.
443 (powerpc_opcodes): Add new Power E500MC instructions.
444
112b7c50
AK		 4452008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
446
447 * s390-dis.c (init_disasm): Evaluate disassembler_options.
448 (print_s390_disassembler_options): New function.
449 * disassemble.c (disassembler_usage): Invoke
450 print_s390_disassembler_options.
451
7ff42648
AK		 4522008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
453
454 * s390-mkopc.c (insertExpandedMnemonic): Expand string sizes
455 of local variables used for mnemonic parsing: prefix, suffix and
456 number.
457
45a5551e
AK		 4582008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
459
460 * s390-mkopc.c (s390_cond_ext_format): Add back the mnemonic
461 extensions for conditional jumps (o, p, m, nz, z, nm, np, no).
462 (s390_crb_extensions): New extensions table.
463 (insertExpandedMnemonic): Handle '$' tag.
464 * s390-opc.txt: Remove conditional jump variants which can now
465 be expanded automatically.
466 Replace '*' tag with '$' in the compare and branch instructions.
467
06c8514a
L		 4682008-04-07 H.J. Lu <hongjiu.lu@intel.com>
469
470 * i386-dis.c (PREFIX_VEX_38XX): Add a tab.
471 (PREFIX_VEX_3AXX): Likewis.
472
b122c285
L		 4732008-04-07 H.J. Lu <hongjiu.lu@intel.com>
474
475 * i386-opc.tbl: Remove 4 extra blank lines.
476
594ab6a3
L		 4772008-04-04 H.J. Lu <hongjiu.lu@intel.com>
478
479 * i386-gen.c (cpu_flag_init): Replace CPU_CLMUL_FLAGS/CpuCLMUL
480 with CPU_PCLMUL_FLAGS/CpuPCLMUL.
481 (cpu_flags): Replace CpuCLMUL with CpuPCLMUL.
482 * i386-opc.tbl: Likewise.
483
484 * i386-opc.h (CpuCLMUL): Renamed to ...
485 (CpuPCLMUL): This.
486 (CpuFMA): Updated.
487 (i386_cpu_flags): Replace cpuclmul with cpupclmul.
488
489 * i386-init.h: Regenerated.
490
c0f3af97
L		 4912008-04-03 H.J. Lu <hongjiu.lu@intel.com>
492
493 * i386-dis.c (OP_E_register): New.
494 (OP_E_memory): Likewise.
495 (OP_VEX): Likewise.
496 (OP_EX_Vex): Likewise.
497 (OP_EX_VexW): Likewise.
498 (OP_XMM_Vex): Likewise.
499 (OP_XMM_VexW): Likewise.
500 (OP_REG_VexI4): Likewise.
501 (PCLMUL_Fixup): Likewise.
502 (VEXI4_Fixup): Likewise.
503 (VZERO_Fixup): Likewise.
504 (VCMP_Fixup): Likewise.
505 (VPERMIL2_Fixup): Likewise.
506 (rex_original): Likewise.
507 (rex_ignored): Likewise.
508 (Mxmm): Likewise.
509 (XMM): Likewise.
510 (EXxmm): Likewise.
511 (EXxmmq): Likewise.
512 (EXymmq): Likewise.
513 (Vex): Likewise.
514 (Vex128): Likewise.
515 (Vex256): Likewise.
516 (VexI4): Likewise.
517 (EXdVex): Likewise.
518 (EXqVex): Likewise.
519 (EXVexW): Likewise.
520 (EXdVexW): Likewise.
521 (EXqVexW): Likewise.
522 (XMVex): Likewise.
523 (XMVexW): Likewise.
524 (XMVexI4): Likewise.
525 (PCLMUL): Likewise.
526 (VZERO): Likewise.
527 (VCMP): Likewise.
528 (VPERMIL2): Likewise.
529 (xmm_mode): Likewise.
530 (xmmq_mode): Likewise.
531 (ymmq_mode): Likewise.
532 (vex_mode): Likewise.
533 (vex128_mode): Likewise.
534 (vex256_mode): Likewise.
535 (USE_VEX_C4_TABLE): Likewise.
536 (USE_VEX_C5_TABLE): Likewise.
537 (USE_VEX_LEN_TABLE): Likewise.
538 (VEX_C4_TABLE): Likewise.
539 (VEX_C5_TABLE): Likewise.
540 (VEX_LEN_TABLE): Likewise.
541 (REG_VEX_XX): Likewise.
542 (MOD_VEX_XXX): Likewise.
543 (PREFIX_0F38DB..PREFIX_0F38DF): Likewise.
544 (PREFIX_0F3A44): Likewise.
545 (PREFIX_0F3ADF): Likewise.
546 (PREFIX_VEX_XXX): Likewise.
547 (VEX_OF): Likewise.
548 (VEX_OF38): Likewise.
549 (VEX_OF3A): Likewise.
550 (VEX_LEN_XXX): Likewise.
551 (vex): Likewise.
552 (need_vex): Likewise.
553 (need_vex_reg): Likewise.
554 (vex_i4_done): Likewise.
555 (vex_table): Likewise.
556 (vex_len_table): Likewise.
557 (OP_REG_VexI4): Likewise.
558 (vex_cmp_op): Likewise.
559 (pclmul_op): Likewise.
560 (vpermil2_op): Likewise.
561 (m_mode): Updated.
562 (es_reg): Likewise.
563 (PREFIX_0F38F0): Likewise.
564 (PREFIX_0F3A60): Likewise.
565 (reg_table): Add REG_VEX_71...REG_VEX_73 and REG_VEX_AE.
566 (prefix_table): Add PREFIX_0F38DB..PREFIX_0F38DF, PREFIX_0F3ADF
567 and PREFIX_VEX_XXX entries.
568 (x86_64_table): Use VEX_C4_TABLE and VEX_C5_TABLE.
569 (three_byte_table): Use PREFIX_0F38DB..PREFIX_0F38DF and
570 PREFIX_0F3ADF.
571 (mod_table): Use VEX_C4_TABLE, VEX_C5_TABLE and VEX_LEN_TABLE.
572 Add MOD_VEX_XXX entries.
573 (ckprefix): Initialize rex_original and rex_ignored. Store the
574 REX byte in rex_original.
575 (get_valid_dis386): Handle the implicit prefix in VEX prefix
576 bytes and USE_VEX_LEN_TABLE/USE_VEX_C4_TABLE/USE_VEX_C5_TABLE.
577 (print_insn): Set need_vex/need_vex_reg/vex_i4_done to 0 before
578 calling get_valid_dis386. Use rex_original and rex_ignored when
579 printing out REX.
580 (putop): Handle "XY".
581 (intel_operand_size): Handle VEX, xmm_mode, xmmq_mode and
582 ymmq_mode.
583 (OP_E_extended): Updated to use OP_E_register and
584 OP_E_memory.
585 (OP_XMM): Handle VEX.
586 (OP_EX): Likewise.
587 (XMM_Fixup): Likewise.
588 (CMP_Fixup): Use ARRAY_SIZE.
589
590 * i386-gen.c (cpu_flag_init): Add CpuAES, CPU_CLMUL_FLAGS,
591 CPU_FMA_FLAGS and CPU_AVX_FLAGS.
592 (operand_type_init): Add OPERAND_TYPE_REGYMM and
593 OPERAND_TYPE_VEX_IMM4.
594 (cpu_flags): Add CpuAVX, CpuAES, CpuCLMUL and CpuFMA.
595 (opcode_modifiers): Add Implicit1stXmm0, Vex, Vex256, VexNDD,
596 VexNDS, VexW0, VexW1, Vex0F, Vex0F38, Vex0F3A, Vex3Sources,
597 VexImmExt and SSE2AVX.
598 (operand_types): Add RegYMM, Ymmword and Vex_Imm4.
599
600 * i386-opc.h (CpuAVX): New.
601 (CpuAES): Likewise.
602 (CpuCLMUL): Likewise.
603 (CpuFMA): Likewise.
604 (Vex): Likewise.
605 (Vex256): Likewise.
606 (VexNDS): Likewise.
607 (VexNDD): Likewise.
608 (VexW0): Likewise.
609 (VexW1): Likewise.
610 (Vex0F): Likewise.
611 (Vex0F38): Likewise.
612 (Vex0F3A): Likewise.
613 (Vex3Sources): Likewise.
614 (VexImmExt): Likewise.
615 (SSE2AVX): Likewise.
616 (RegYMM): Likewise.
617 (Ymmword): Likewise.
618 (Vex_Imm4): Likewise.
619 (Implicit1stXmm0): Likewise.
620 (CpuXsave): Updated.
621 (CpuLM): Likewise.
622 (ByteOkIntel): Likewise.
623 (OldGcc): Likewise.
624 (Control): Likewise.
625 (Unspecified): Likewise.
626 (OTMax): Likewise.
627 (i386_cpu_flags): Add cpuavx, cpuaes, cpuclmul and cpufma.
628 (i386_opcode_modifier): Add implicit1stxmm0, vex, vex256,
629 vexnds, vexndd, vexw0, vexw1, vex0f, vex0f38, vex0f3a,
630 vex3sources, veximmext and sse2avx.
631 (i386_operand_type): Add regymm, ymmword and vex_imm4.
632
633 * i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions.
634
635 * i386-reg.tbl: Add AVX registers, ymm0..ymm15.
636
637 * i386-init.h: Regenerated.
638 * i386-tbl.h: Likewise.
639
b21c9cb4
BS		 6402008-03-26 Bernd Schmidt <bernd.schmidt@analog.com>
641
642 From Robin Getz <robin.getz@analog.com>
643 * bfin-dis.c (bu32): Typedef.
644 (enum const_forms_t): Add c_uimm32 and c_huimm32.
645 (constant_formats[]): Add uimm32 and huimm16.
646 (fmtconst_val): New.
647 (uimm32): Define.
648 (huimm32): Define.
649 (imm16_val): Define.
650 (luimm16_val): Define.
651 (struct saved_state): Define.
652 (GREG, DPREG, DREG, PREG, SPREG, FPREG, IREG, MREG, BREG, LREG,
653 A0XREG, A0WREG, A1XREG, A1WREG,CCREG, LC0REG, LT0REG, LB0REG,
654 LC1REG, LT1REG, LB1REG, RETSREG, PCREG): Define.
655 (get_allreg): New.
656 (decode_LDIMMhalf_0): Print out the whole register value.
657
ee171c8f
BS		 658 From Jie Zhang <jie.zhang@analog.com>
659 * bfin-dis.c (decode_dsp32mac_0): Decode (IU) option for
660 multiply and multiply-accumulate to data register instruction.
661
086134ec
BS		 662 * bfin-dis.c: (c_uimm4s4d, c_imm5d, c_imm7d, c_imm16d, c_uimm16s4d,
663 c_imm32, c_huimm32e): Define.
664 (constant_formats): Add flags for printing decimal, leading spaces, and
665 exact symbols.
666 (comment, parallel): Add global flags in all disassembly.
667 (fmtconst): Take advantage of new flags, and print default in hex.
668 (fmtconst_val): Likewise.
669 (decode_macfunc): Be consistant with spaces, tabs, comments,
670 capitalization in disassembly, fix minor coding style issues.
671 (reg_names, amod0, amod1, amod0amod2, aligndir, get_allreg): Likewise.
672 (decode_ProgCtrl_0, decode_PushPopMultiple_0, decode_CCflag_0,
673 decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0,
674 decode_REGMV_0, decode_ALU2op_0, decode_PTR2op_0, decode_LOGI2op_0,
675 decode_COMP3op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
676 decode_LDSTpmod_0, decode_dagMODim_0, decode_dagMODik_0,
677 decode_dspLDST_0, decode_LDST_0, decode_LDSTiiFP_0, decode_LDSTii_0,
678 decode_LoopSetup_0, decode_LDIMMhalf_0, decode_CALLa_0,
679 decode_LDSTidxI_0, decode_linkage_0, decode_dsp32alu_0,
680 decode_dsp32shift_0, decode_dsp32shiftimm_0, decode_pseudodbg_assert_0,
681 _print_insn_bfin, print_insn_bfin): Likewise.
682
58c85be7
RW		 6832008-03-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
684
685 * aclocal.m4: Regenerate.
686 * configure: Likewise.
687 * Makefile.in: Likewise.
688
50e7d84b
AM		 6892008-03-13 Alan Modra <amodra@bigpond.net.au>
690
691 * Makefile.am: Run "make dep-am".
692 * Makefile.in: Regenerate.
693 * configure: Regenerate.
694
de866fcc
AM		 6952008-03-07 Alan Modra <amodra@bigpond.net.au>
696
697 * ppc-opc.c (powerpc_opcodes): Order and format.
698
28dbc079
L		 6992008-03-01 H.J. Lu <hongjiu.lu@intel.com>
700
701 * i386-opc.tbl: Allow 16-bit near indirect branches for x86-64.
702 * i386-tbl.h: Regenerated.
703
849830bd
L		 7042008-02-23 H.J. Lu <hongjiu.lu@intel.com>
705
706 * i386-opc.tbl: Disallow 16-bit near indirect branches for
707 x86-64.
708 * i386-tbl.h: Regenerated.
709
743ddb6b
JB		 7102008-02-21 Jan Beulich <jbeulich@novell.com>
711
712 * i386-opc.tbl: Allow Dword for far indirect call. Allow Dword
713 and Fword for far indirect jmp. Allow Reg16 and Word for near
714 indirect jmp on x86-64. Disallow Fword for lcall.
715 * i386-tbl.h: Re-generate.
716
796d5313
NC		 7172008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
718
719 * cr16-opc.c (cr16_num_optab): Defined
720
65da13b5
L		 7212008-02-16 H.J. Lu <hongjiu.lu@intel.com>
722
723 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_INOUTPORTREG.
724 * i386-init.h: Regenerated.
725
0e336180
NC		 7262008-02-14 Nick Clifton <nickc@redhat.com>
727
728 PR binutils/5524
729 * configure.in (SHARED_LIBADD): Select the correct host specific
730 file extension for shared libraries.
731 * configure: Regenerate.
732
b7240065
JB		 7332008-02-13 Jan Beulich <jbeulich@novell.com>
734
735 * i386-opc.h (RegFlat): New.
736 * i386-reg.tbl (flat): Add.
737 * i386-tbl.h: Re-generate.
738
34b772a6
JB		 7392008-02-13 Jan Beulich <jbeulich@novell.com>
740
741 * i386-dis.c (a_mode): New.
742 (cond_jump_mode): Adjust.
743 (Ma): Change to a_mode.
744 (intel_operand_size): Handle a_mode.
745 * i386-opc.tbl: Allow Dword and Qword for bound.
746 * i386-tbl.h: Re-generate.
747
a60de03c
JB		 7482008-02-13 Jan Beulich <jbeulich@novell.com>
749
750 * i386-gen.c (process_i386_registers): Process new fields.
751 * i386-opc.h (reg_entry): Shrink reg_flags and reg_num to
752 unsigned char. Add dw2_regnum and Dw2Inval.
753 * i386-reg.tbl: Provide initializers for dw2_regnum. Add pseudo
754 register names.
755 * i386-tbl.h: Re-generate.
756
f03fe4c1
L		 7572008-02-11 H.J. Lu <hongjiu.lu@intel.com>
758
4b6bc8eb 759 * i386-gen.c (cpu_flag_init): Add CPU_XSAVE_FLAGS.
f03fe4c1
L		 760 * i386-init.h: Updated.
761
475a2301
L		 7622008-02-11 H.J. Lu <hongjiu.lu@intel.com>
763
764 * i386-gen.c (cpu_flags): Add CpuXsave.
765
766 * i386-opc.h (CpuXsave): New.
4b6bc8eb 767 (CpuLM): Updated.
475a2301
L		 768 (i386_cpu_flags): Add cpuxsave.
769
770 * i386-dis.c (MOD_0FAE_REG_4): New.
771 (RM_0F01_REG_2): Likewise.
772 (MOD_0FAE_REG_5): Updated.
773 (RM_0F01_REG_3): Likewise.
774 (reg_table): Use MOD_0FAE_REG_4.
775 (mod_table): Use RM_0F01_REG_2. Add MOD_0FAE_REG_4. Updated
776 for xrstor.
777 (rm_table): Add RM_0F01_REG_2.
778
779 * i386-opc.tbl: Add xsave, xrstor, xgetbv and xsetbv.
780 * i386-init.h: Regenerated.
781 * i386-tbl.h: Likewise.
782
595785c6 7832008-02-11 Jan Beulich <jbeulich@novell.com>
041179fc 784
595785c6
JB		 785 * i386-opc.tbl: Remove Disp32S from CpuNo64 opcodes. Remove
786 Disp16 from Cpu64 non-jump opcodes (including loop and j?cxz).
787 * i386-tbl.h: Re-generate.
788
bb8541b9
L		 7892008-02-04 H.J. Lu <hongjiu.lu@intel.com>
790
791 PR 5715
792 * configure: Regenerated.
793
57b592a3
AN		 7942008-02-04 Adam Nemet <anemet@caviumnetworks.com>
795
796 * mips-dis.c: Update copyright.
797 (mips_arch_choices): Add Octeon.
798 * mips-opc.c: Update copyright.
799 (IOCT): New macro.
800 (mips_builtin_opcodes): Add Octeon instruction synciobdma.
801
930bb4cf
AM		 8022008-01-29 Alan Modra <amodra@bigpond.net.au>
803
804 * ppc-opc.c: Support optional L form mtmsr.
805
82c18208
L		 8062008-01-24 H.J. Lu <hongjiu.lu@intel.com>
807
808 * i386-dis.c (OP_E_extended): Handle r12 like rsp.
809
599121aa
L		 8102008-01-23 H.J. Lu <hongjiu.lu@intel.com>
811
812 * i386-gen.c (cpu_flag_init): Add CpuLM to CPU_GENERIC64_FLAGS.
813 * i386-init.h: Regenerated.
814
80098f51
TG		 8152008-01-23 Tristan Gingold <gingold@adacore.com>
816
817 * ia64-dis.c (print_insn_ia64): Display symbolic name of ar.fcr,
818 ar.eflag, ar.csd, ar.ssd, ar.cflg, ar.fsr, ar.fir and ar.fdr.
819
115c7c25
L		 8202008-01-22 H.J. Lu <hongjiu.lu@intel.com>
821
822 * i386-gen.c (cpu_flag_init): Remove CpuMMX2.
823 (cpu_flags): Likewise.
824
825 * i386-opc.h (CpuMMX2): Removed.
826 (CpuSSE): Updated.
827
828 * i386-opc.tbl: Replace CpuMMX2 with CpuSSE|Cpu3dnowA.
829 * i386-init.h: Regenerated.
830 * i386-tbl.h: Likewise.
831
6305a203
L		 8322008-01-22 H.J. Lu <hongjiu.lu@intel.com>
833
834 * i386-gen.c (cpu_flag_init): Add CPU_VMX_FLAGS and
835 CPU_SMX_FLAGS.
836 * i386-init.h: Regenerated.
837
fd07a1c8
L		 8382008-01-15 H.J. Lu <hongjiu.lu@intel.com>
839
840 * i386-opc.tbl: Use Qword on movddup.
841 * i386-tbl.h: Regenerated.
842
321fd21e
L		 8432008-01-15 H.J. Lu <hongjiu.lu@intel.com>
844
845 * i386-opc.tbl: Put back 16bit movsx/movzx for AT&T syntax.
846 * i386-tbl.h: Regenerated.
847
4ee52178
L		 8482008-01-15 H.J. Lu <hongjiu.lu@intel.com>
849
850 * i386-dis.c (Mx): New.
851 (PREFIX_0FC3): Likewise.
852 (PREFIX_0FC7_REG_6): Updated.
853 (dis386_twobyte): Use PREFIX_0FC3.
854 (prefix_table): Add PREFIX_0FC3. Use Mq on movntq and movntsd.
855 Use Mx on movntps, movntpd, movntdq and movntdqa. Use Md on
856 movntss.
857
5c07affc
L		 8582008-01-14 H.J. Lu <hongjiu.lu@intel.com>
859
860 * i386-gen.c (opcode_modifiers): Add IntelSyntax.
861 (operand_types): Add Mem.
862
863 * i386-opc.h (IntelSyntax): New.
864 * i386-opc.h (Mem): New.
865 (Byte): Updated.
866 (Opcode_Modifier_Max): Updated.
867 (i386_opcode_modifier): Add intelsyntax.
868 (i386_operand_type): Add mem.
869
870 * i386-opc.tbl: Remove Reg16 from movnti. Add sizes to more
871 instructions.
872
873 * i386-reg.tbl: Add size for accumulator.
874
875 * i386-init.h: Regenerated.
876 * i386-tbl.h: Likewise.
877
0d6a2f58
L		 8782008-01-13 H.J. Lu <hongjiu.lu@intel.com>
879
880 * i386-opc.h (Byte): Fix a typo.
881
7d5e4556
L		 8822008-01-12 H.J. Lu <hongjiu.lu@intel.com>
883
884 PR gas/5534
885 * i386-gen.c (operand_type_init): Add Dword to
886 OPERAND_TYPE_ACC32. Add Qword to OPERAND_TYPE_ACC64.
887 (opcode_modifiers): Remove CheckSize, Byte, Word, Dword,
888 Qword and Xmmword.
889 (operand_types): Add Byte, Word, Dword, Fword, Qword, Tbyte,
890 Xmmword, Unspecified and Anysize.
891 (set_bitfield): Make Mmword an alias of Qword. Make Oword
892 an alias of Xmmword.
893
894 * i386-opc.h (CheckSize): Removed.
895 (Byte): Updated.
896 (Word): Likewise.
897 (Dword): Likewise.
898 (Qword): Likewise.
899 (Xmmword): Likewise.
900 (FWait): Updated.
901 (OTMax): Likewise.
902 (i386_opcode_modifier): Remove checksize, byte, word, dword,
903 qword and xmmword.
904 (Fword): New.
905 (TBYTE): Likewise.
906 (Unspecified): Likewise.
907 (Anysize): Likewise.
908 (i386_operand_type): Add byte, word, dword, fword, qword,
909 tbyte xmmword, unspecified and anysize.
910
911 * i386-opc.tbl: Updated to use Byte, Word, Dword, Fword, Qword,
912 Tbyte, Xmmword, Unspecified and Anysize.
913
914 * i386-reg.tbl: Add size for accumulator.
915
916 * i386-init.h: Regenerated.
917 * i386-tbl.h: Likewise.
918
b5b1fc4f
L		 9192008-01-10 H.J. Lu <hongjiu.lu@intel.com>
920
921 * i386-dis.c (REG_0F0E): Renamed to REG_0F0D.
922 (REG_0F18): Updated.
923 (reg_table): Updated.
924 (dis386_twobyte): Updated. Use "nopQ" on 0x19 to 0x1e.
925 (twobyte_has_modrm): Set 1 for 0x19 to 0x1e.
926
50e8458f
L		 9272008-01-08 H.J. Lu <hongjiu.lu@intel.com>
928
929 * i386-gen.c (set_bitfield): Use fail () on error.
930
3d4d5afa
L		 9312008-01-08 H.J. Lu <hongjiu.lu@intel.com>
932
933 * i386-gen.c (lineno): New.
934 (filename): Likewise.
935 (set_bitfield): Report filename and line numer on error.
936 (process_i386_opcodes): Set filename and update lineno.
937 (process_i386_registers): Likewise.
938
e1d4d893
L		 9392008-01-05 H.J. Lu <hongjiu.lu@intel.com>
940
941 * i386-gen.c (opcode_modifiers): Rename IntelMnemonic to
942 ATTSyntax.
943
944 * i386-opc.h (IntelMnemonic): Renamed to ..
945 (ATTSyntax): This
946 (Opcode_Modifier_Max): Updated.
947 (i386_opcode_modifier): Remove intelmnemonic. Add attsyntax
948 and intelsyntax.
949
8944f3c2 950 * i386-opc.tbl: Remove IntelMnemonic and update with ATTSyntax
e1d4d893
L		 951 on fsub, fubp, fsubr, fsubrp, div, fdivp, fdivr and fdivrp.
952 * i386-tbl.h: Regenerated.
953
6f143e4d
L		 9542008-01-04 H.J. Lu <hongjiu.lu@intel.com>
955
956 * i386-gen.c: Update copyright to 2008.
957 * i386-opc.h: Likewise.
958 * i386-opc.tbl: Likewise.
959
960 * i386-init.h: Regenerated.
961 * i386-tbl.h: Likewise.
962
c6add537
L		 9632008-01-04 H.J. Lu <hongjiu.lu@intel.com>
964
965 * i386-opc.tbl: Add NoRex64 to extractps, movmskpd, movmskps,
966 pextrb, pextrw, pinsrb, pinsrw and pmovmskb.
967 * i386-tbl.h: Regenerated.
968
3629bb00
L		 9692008-01-03 H.J. Lu <hongjiu.lu@intel.com>
970
971 * i386-gen.c (cpu_flag_init): Remove CpuSSE4_1_Or_5 and
972 CpuSSE4_2_Or_ABM.
973 (cpu_flags): Likewise.
974
975 * i386-opc.h (CpuSSE4_1_Or_5): Removed.
976 (CpuSSE4_2_Or_ABM): Likewise.
977 (CpuLM): Updated.
978 (i386_cpu_flags): Remove cpusse4_1_or_5 and cpusse4_2_or_abm.
979
980 * i386-opc.tbl: Replace CpuSSE4_1_Or_5, CpuSSE4_2_Or_ABM and
981 Cpu686|CpuPadLock with CpuSSE4_1|CpuSSE5, CpuABM|CpuSSE4_2
982 and CpuPadLock, respectively.
983 * i386-init.h: Regenerated.
984 * i386-tbl.h: Likewise.
985
24995bd6
L		 9862008-01-03 H.J. Lu <hongjiu.lu@intel.com>
987
988 * i386-gen.c (opcode_modifiers): Remove No_xSuf.
989
990 * i386-opc.h (No_xSuf): Removed.
991 (CheckSize): Updated.
992
993 * i386-tbl.h: Regenerated.
994
e0329a22
L		 9952008-01-02 H.J. Lu <hongjiu.lu@intel.com>
996
997 * i386-gen.c (cpu_flag_init): Add CpuSSE4_2_Or_ABM to
998 CPU_AMDFAM10_FLAGS, CPU_SSE4_2_FLAGS, CpuABM and
999 CPU_SSE5_FLAGS.
1000 (cpu_flags): Add CpuSSE4_2_Or_ABM.
1001
1002 * i386-opc.h (CpuSSE4_2_Or_ABM): New.
1003 (CpuLM): Updated.
1004 (i386_cpu_flags): Add cpusse4_2_or_abm.
1005
1006 * i386-opc.tbl: Use CpuSSE4_2_Or_ABM instead of
1007 CpuABM|CpuSSE4_2 on popcnt.
1008 * i386-init.h: Regenerated.
1009 * i386-tbl.h: Likewise.
1010
f2a9c676
L		 10112008-01-02 H.J. Lu <hongjiu.lu@intel.com>
1012
1013 * i386-opc.h: Update comments.
1014
d978b5be
L		 10152008-01-02 H.J. Lu <hongjiu.lu@intel.com>
1016
1017 * i386-gen.c (opcode_modifiers): Use Qword instead of QWord.
1018 * i386-opc.h: Likewise.
1019 * i386-opc.tbl: Likewise.
1020
582d5edd
L		 10212008-01-02 H.J. Lu <hongjiu.lu@intel.com>
1022
1023 PR gas/5534
1024 * i386-gen.c (opcode_modifiers): Add No_xSuf, CheckSize,
1025 Byte, Word, Dword, QWord and Xmmword.
1026
1027 * i386-opc.h (No_xSuf): New.
1028 (CheckSize): Likewise.
1029 (Byte): Likewise.
1030 (Word): Likewise.
1031 (Dword): Likewise.
1032 (QWord): Likewise.
1033 (Xmmword): Likewise.
1034 (FWait): Updated.
1035 (i386_opcode_modifier): Add No_xSuf, CheckSize, Byte, Word,
1036 Dword, QWord and Xmmword.
1037
1038 * i386-opc.tbl: Add CheckSize|QWord to movq if IgnoreSize is
1039 used.
1040 * i386-tbl.h: Regenerated.
1041
3fe15143
MK		 10422008-01-02 Mark Kettenis <kettenis@gnu.org>
1043
1044 * m88k-dis.c (instructions): Fix fcvt.* instructions.
1045 From Miod Vallat.
1046
6c7ac64e 1047For older changes see ChangeLog-2007
252b5132
RH		 1048\f
1049Local Variables:
2f6d2f85
NC		 1050mode: change-log
1051left-margin: 8
1052fill-column: 74
252b5132
RH		 1053version-control: never
1054End:
GDB Binutils - Deliverables
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