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x86: move ImmExt processing
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
589958d6
JB		 12020-06-25 Jan Beulich <jbeulich@suse.com>
2
3 * i386-dis.c: Adjust description of "LQ" macro.
4 (dis386_twobyte): Use LQ for sysret.
5 (putop): Adjust handling of LQ.
6
39ff0b81
NC		 72020-06-22 Nelson Chu <nelson.chu@sifive.com>
8
9 * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
10 * riscv-dis.c: Include elfxx-riscv.h.
11
d27c357a
JB		 122020-06-18 H.J. Lu <hongjiu.lu@intel.com>
13
14 * i386-dis.c (prefix_table): Revert the last vmgexit change.
15
6fde587f
CL		 162020-06-17 Lili Cui <lili.cui@intel.com>
17
18 * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
19
efe30057
L		 202020-06-14 H.J. Lu <hongjiu.lu@intel.com>
21
22 PR gas/26115
23 * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
24 * i386-opc.tbl: Likewise.
25 * i386-tbl.h: Regenerated.
26
d8af286f
NC		 272020-06-12 Nelson Chu <nelson.chu@sifive.com>
28
29 * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
30
14962256
AC		 312020-06-11 Alex Coplan <alex.coplan@arm.com>
32
33 * aarch64-opc.c (SYSREG): New macro for describing system registers.
34 (SR_CORE): Likewise.
35 (SR_FEAT): Likewise.
36 (SR_RNG): Likewise.
37 (SR_V8_1): Likewise.
38 (SR_V8_2): Likewise.
39 (SR_V8_3): Likewise.
40 (SR_V8_4): Likewise.
41 (SR_PAN): Likewise.
42 (SR_RAS): Likewise.
43 (SR_SSBS): Likewise.
44 (SR_SVE): Likewise.
45 (SR_ID_PFR2): Likewise.
46 (SR_PROFILE): Likewise.
47 (SR_MEMTAG): Likewise.
48 (SR_SCXTNUM): Likewise.
49 (aarch64_sys_regs): Refactor to store feature information in the table.
50 (aarch64_sys_reg_supported_p): Collapse logic for system registers
51 that now describe their own features.
52 (aarch64_pstatefield_supported_p): Likewise.
53
f9630fa6
L		 542020-06-09 H.J. Lu <hongjiu.lu@intel.com>
55
56 * i386-dis.c (prefix_table): Fix a typo in comments.
57
73239888
JB		 582020-06-09 Jan Beulich <jbeulich@suse.com>
59
60 * i386-dis.c (rex_ignored): Delete.
61 (ckprefix): Drop rex_ignored initialization.
62 (get_valid_dis386): Drop setting of rex_ignored.
63 (print_insn): Drop checking of rex_ignored. Don't record data
64 size prefix as used with VEX-and-alike encodings.
65
18897deb
JB		 662020-06-09 Jan Beulich <jbeulich@suse.com>
67
68 * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
69 MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
70 (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
71 (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
72 (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
73 VEX_0F12, and VEX_0F16.
74 (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
75 VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
76 (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
77 from movlps and movhlps. New MOD_0F12_PREFIX_2,
78 MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
79 MOD_VEX_0F16_PREFIX_2 entries.
80
97e6786a
JB		 812020-06-09 Jan Beulich <jbeulich@suse.com>
82
83 * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
84 MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
85 (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
86 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
87 PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
88 PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
89 EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
90 EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
91 EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
92 EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
93 EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
94 EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
95 EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
96 EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
97 EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
98 EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
99 EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
100 EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
101 EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
102 EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
103 EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
104 EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
105 EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
106 EVEX_W_0FC6_P_2): Delete.
107 (print_insn): Add EVEX.W vs embedded prefix consistency check
108 to prefix validation.
109 * i386-dis-evex.h (evex_table): Don't further descend for
110 vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
111 and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
112 and 0F2B.
113 * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
114 * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
115 vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
116 vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
117 2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
118 Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
119 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
120 PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
121 PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
122 * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
123 EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
124 EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
125 EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
126 EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
127 EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
128 EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
129 EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
130 EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
131 EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
132 EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
133 EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
134 EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
135 EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
136 EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
137 EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
138 EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
139 EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
140
bf926894
JB		 1412020-06-09 Jan Beulich <jbeulich@suse.com>
142
143 * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
144 vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
145 (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
146 vmovmskpX.
147 (print_insn): Drop pointless check against bad_opcode. Split
148 prefix validation into legacy and VEX-and-alike parts.
149 (putop): Re-work 'X' macro handling.
150
a5aaedb9
JB		 1512020-06-09 Jan Beulich <jbeulich@suse.com>
152
153 * i386-dis.c (MOD_0F51): Rename to ...
154 (MOD_0F50): ... this.
155
26417f19
AC		 1562020-06-08 Alex Coplan <alex.coplan@arm.com>
157
158 * arm-dis.c (arm_opcodes): Add dfb.
159 (thumb32_opcodes): Add dfb.
160
8a6fb3f9
JB		 1612020-06-08 Jan Beulich <jbeulich@suse.com>
162
163 * i386-opc.h (reg_entry): Const-qualify reg_name field.
164
1424c35d
AM		 1652020-06-06 Alan Modra <amodra@gmail.com>
166
167 * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
168
d3d1cc7b
AM		 1692020-06-05 Alan Modra <amodra@gmail.com>
170
171 * cgen-dis.c (hash_insn_array): Increase size of buf. Assert
172 size is large enough.
173
d8740be1
JM		 1742020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
175
176 * disassemble.c (disassemble_init_for_target): Set endian_code for
177 bpf targets.
178 * bpf-desc.c: Regenerate.
179 * bpf-opc.c: Likewise.
180 * bpf-dis.c: Likewise.
181
e9bffec9
JM		 1822020-06-03 Jose E. Marchesi <jose.marchesi@oracle.com>
183
184 * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
185 (cgen_put_insn_value): Likewise.
186 (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
187 * cgen-dis.in (print_insn): Likewise.
188 * cgen-ibld.in (insert_1): Likewise.
189 (insert_1): Likewise.
190 (insert_insn_normal): Likewise.
191 (extract_1): Likewise.
192 * bpf-dis.c: Regenerate.
193 * bpf-ibld.c: Likewise.
194 * bpf-ibld.c: Likewise.
195 * cgen-dis.in: Likewise.
196 * cgen-ibld.in: Likewise.
197 * cgen-opc.c: Likewise.
198 * epiphany-dis.c: Likewise.
199 * epiphany-ibld.c: Likewise.
200 * fr30-dis.c: Likewise.
201 * fr30-ibld.c: Likewise.
202 * frv-dis.c: Likewise.
203 * frv-ibld.c: Likewise.
204 * ip2k-dis.c: Likewise.
205 * ip2k-ibld.c: Likewise.
206 * iq2000-dis.c: Likewise.
207 * iq2000-ibld.c: Likewise.
208 * lm32-dis.c: Likewise.
209 * lm32-ibld.c: Likewise.
210 * m32c-dis.c: Likewise.
211 * m32c-ibld.c: Likewise.
212 * m32r-dis.c: Likewise.
213 * m32r-ibld.c: Likewise.
214 * mep-dis.c: Likewise.
215 * mep-ibld.c: Likewise.
216 * mt-dis.c: Likewise.
217 * mt-ibld.c: Likewise.
218 * or1k-dis.c: Likewise.
219 * or1k-ibld.c: Likewise.
220 * xc16x-dis.c: Likewise.
221 * xc16x-ibld.c: Likewise.
222 * xstormy16-dis.c: Likewise.
223 * xstormy16-ibld.c: Likewise.
224
b3db6d07
JM		 2252020-06-04 Jose E. Marchesi <jemarch@gnu.org>
226
227 * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
228 (print_insn_): Handle instruction endian.
229 * bpf-dis.c: Regenerate.
230 * bpf-desc.c: Regenerate.
231 * epiphany-dis.c: Likewise.
232 * epiphany-desc.c: Likewise.
233 * fr30-dis.c: Likewise.
234 * fr30-desc.c: Likewise.
235 * frv-dis.c: Likewise.
236 * frv-desc.c: Likewise.
237 * ip2k-dis.c: Likewise.
238 * ip2k-desc.c: Likewise.
239 * iq2000-dis.c: Likewise.
240 * iq2000-desc.c: Likewise.
241 * lm32-dis.c: Likewise.
242 * lm32-desc.c: Likewise.
243 * m32c-dis.c: Likewise.
244 * m32c-desc.c: Likewise.
245 * m32r-dis.c: Likewise.
246 * m32r-desc.c: Likewise.
247 * mep-dis.c: Likewise.
248 * mep-desc.c: Likewise.
249 * mt-dis.c: Likewise.
250 * mt-desc.c: Likewise.
251 * or1k-dis.c: Likewise.
252 * or1k-desc.c: Likewise.
253 * xc16x-dis.c: Likewise.
254 * xc16x-desc.c: Likewise.
255 * xstormy16-dis.c: Likewise.
256 * xstormy16-desc.c: Likewise.
257
4ee4189f
NC		 2582020-06-03 Nick Clifton <nickc@redhat.com>
259
260 * po/sr.po: Updated Serbian translation.
261
44730156
NC		 2622020-06-03 Nelson Chu <nelson.chu@sifive.com>
263
264 * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
265 (riscv_get_priv_spec_class): Likewise.
266
3c3d0376
AM		 2672020-06-01 Alan Modra <amodra@gmail.com>
268
269 * bpf-desc.c: Regenerate.
270
78c1c354
JM		 2712020-05-28 Jose E. Marchesi <jose.marchesi@oracle.com>
272 David Faust <david.faust@oracle.com>
273
274 * bpf-desc.c: Regenerate.
275 * bpf-opc.h: Likewise.
276 * bpf-opc.c: Likewise.
277 * bpf-dis.c: Likewise.
278
efcf5fb5
AM		 2792020-05-28 Alan Modra <amodra@gmail.com>
280
281 * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
282 values.
283
ab382d64
AM		 2842020-05-28 Alan Modra <amodra@gmail.com>
285
286 * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
287 immediates.
288 (print_insn_ns32k): Revert last change.
289
151f5de4
NC		 2902020-05-28 Nick Clifton <nickc@redhat.com>
291
292 * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
293 static.
294
25e1eca8
SL		 2952020-05-26 Sandra Loosemore <sandra@codesourcery.com>
296
297 Fix extraction of signed constants in nios2 disassembler (again).
298
299 * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
300 extractions of signed fields.
301
57b17940
SSF		 3022020-05-26 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
303
304 * s390-opc.txt: Relocate vector load/store instructions with
305 additional alignment parameter and change architecture level
306 constraint from z14 to z13.
307
d96bf37b
AM		 3082020-05-21 Alan Modra <amodra@gmail.com>
309
310 * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
311 * sparc-dis.c: Likewise.
312 * tic4x-dis.c: Likewise.
313 * xtensa-dis.c: Likewise.
314 * bpf-desc.c: Regenerate.
315 * epiphany-desc.c: Regenerate.
316 * fr30-desc.c: Regenerate.
317 * frv-desc.c: Regenerate.
318 * ip2k-desc.c: Regenerate.
319 * iq2000-desc.c: Regenerate.
320 * lm32-desc.c: Regenerate.
321 * m32c-desc.c: Regenerate.
322 * m32r-desc.c: Regenerate.
323 * mep-asm.c: Regenerate.
324 * mep-desc.c: Regenerate.
325 * mt-desc.c: Regenerate.
326 * or1k-desc.c: Regenerate.
327 * xc16x-desc.c: Regenerate.
328 * xstormy16-desc.c: Regenerate.
329
8f595e9b
NC		 3302020-05-20 Nelson Chu <nelson.chu@sifive.com>
331
332 * riscv-opc.c (riscv_ext_version_table): The table used to store
333 all information about the supported spec and the corresponding ISA
334 versions. Currently, only Zicsr is supported to verify the
335 correctness of Z sub extension settings. Others will be supported
336 in the future patches.
337 (struct isa_spec_t, isa_specs): List for all supported ISA spec
338 classes and the corresponding strings.
339 (riscv_get_isa_spec_class): New function. Get the corresponding ISA
340 spec class by giving a ISA spec string.
341 * riscv-opc.c (struct priv_spec_t): New structure.
342 (struct priv_spec_t priv_specs): List for all supported privilege spec
343 classes and the corresponding strings.
344 (riscv_get_priv_spec_class): New function. Get the corresponding
345 privilege spec class by giving a spec string.
346 (riscv_get_priv_spec_name): New function. Get the corresponding
347 privilege spec string by giving a CSR version class.
348 * riscv-dis.c: Updated since DECLARE_CSR is changed.
349 * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
350 according to the chosen version. Build a hash table riscv_csr_hash to
351 store the valid CSR for the chosen pirv verison. Dump the direct
352 CSR address rather than it's name if it is invalid.
353 (parse_riscv_dis_option_without_args): New function. Parse the options
354 without arguments.
355 (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
356 parse the options without arguments first, and then handle the options
357 with arguments. Add the new option -Mpriv-spec, which has argument.
358 * riscv-dis.c (print_riscv_disassembler_options): Add description
359 about the new OBJDUMP option.
360
3d205eb4
PB		 3612020-05-19 Peter Bergner <bergner@linux.ibm.com>
362
363 * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
364 WC values on POWER10 sync, dcbf and wait instructions.
365 (insert_pl, extract_pl): New functions.
366 (L2OPT, LS, WC): Use insert_ls and extract_ls.
367 (LS3): New , 3-bit L for sync.
368 (LS3, L3OPT): New, 3-bit L for sync and dcbf.
369 (SC2, PL): New, 2-bit SC and PL for sync and wait.
370 (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
371 (XOPL3, XWCPL, XSYNCLS): New opcode macros.
372 (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
373 plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
374 <wait>: Enable PL operand on POWER10.
375 <dcbf>: Enable L3OPT operand on POWER10.
376 <sync>: Enable SC2 operand on POWER10.
377
a501eb44
SH		 3782020-05-19 Stafford Horne <shorne@gmail.com>
379
380 PR 25184
381 * or1k-asm.c: Regenerate.
382 * or1k-desc.c: Regenerate.
383 * or1k-desc.h: Regenerate.
384 * or1k-dis.c: Regenerate.
385 * or1k-ibld.c: Regenerate.
386 * or1k-opc.c: Regenerate.
387 * or1k-opc.h: Regenerate.
388 * or1k-opinst.c: Regenerate.
389
3b646889
AM		 3902020-05-11 Alan Modra <amodra@gmail.com>
391
392 * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
393 xsmaxcqp, xsmincqp.
394
9cc4ce88
AM		 3952020-05-11 Alan Modra <amodra@gmail.com>
396
397 * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
398 stxvrbx, stxvrhx, stxvrwx, stxvrdx.
399
5d57bc3f
AM		 4002020-05-11 Alan Modra <amodra@gmail.com>
401
402 * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
403
66ef5847
AM		 4042020-05-11 Alan Modra <amodra@gmail.com>
405
406 * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
407 vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
408
4f3e9537
PB		 4092020-05-11 Peter Bergner <bergner@linux.ibm.com>
410
411 * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
412 mnemonics.
413
ec40e91c
AM		 4142020-05-11 Alan Modra <amodra@gmail.com>
415
416 * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
417 (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
418 vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
419 (prefix_opcodes): Add xxeval.
420
d7e97a76
AM		 4212020-05-11 Alan Modra <amodra@gmail.com>
422
423 * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
424 xxgenpcvwm, xxgenpcvdm.
425
fdefed7c
AM		 4262020-05-11 Alan Modra <amodra@gmail.com>
427
428 * ppc-opc.c (MP, VXVAM_MASK): Define.
429 (VXVAPS_MASK): Use VXVA_MASK.
430 (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
431 vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
432 vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
433 vcntmbb, vcntmbh, vcntmbw, vcntmbd.
434
aa3c112f
AM		 4352020-05-11 Alan Modra <amodra@gmail.com>
436 Peter Bergner <bergner@linux.ibm.com>
437
438 * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
439 New functions.
440 (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
441 YMSK2, XA6a, XA6ap, XB6a entries.
442 (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
443 (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
444 (PPCVSX4): Define.
445 (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
446 xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
447 xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
448 xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
449 xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
450 xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
451 xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
452 (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
453 pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
454 pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
455 pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
456 pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
457 pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
458 pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
459
6edbfd3b
AM		 4602020-05-11 Alan Modra <amodra@gmail.com>
461
462 * ppc-opc.c (insert_imm32, extract_imm32): New functions.
463 (insert_xts, extract_xts): New functions.
464 (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
465 (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
466 (VXRC_MASK, VXSH_MASK): Define.
467 (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
468 vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
469 vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
470 vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
471 vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
472 (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
473 xxblendvh, xxblendvw, xxblendvd, xxpermx.
474
c7d7aea2
AM		 4752020-05-11 Alan Modra <amodra@gmail.com>
476
477 * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
478 vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
479 vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
480 vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
481 xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
482
94ba9882
AM		 4832020-05-11 Alan Modra <amodra@gmail.com>
484
485 * ppc-opc.c (insert_xtp, extract_xtp): New functions.
486 (XTP, DQXP, DQXP_MASK): Define.
487 (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
488 (prefix_opcodes): Add plxvp and pstxvp.
489
f4791f1a
AM		 4902020-05-11 Alan Modra <amodra@gmail.com>
491
492 * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
493 vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
494 vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
495
3ff0a5ba
PB		 4962020-05-11 Peter Bergner <bergner@linux.ibm.com>
497
498 * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
499
afef4fe9
PB		 5002020-05-11 Peter Bergner <bergner@linux.ibm.com>
501
502 * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
503 (L1OPT): Define.
504 (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
505
1224c05d
PB		 5062020-05-11 Peter Bergner <bergner@linux.ibm.com>
507
508 * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
509
6bbb0c05
AM		 5102020-05-11 Alan Modra <amodra@gmail.com>
511
512 * ppc-dis.c (powerpc_init_dialect): Default to "power10".
513
7c1f4227
AM		 5142020-05-11 Alan Modra <amodra@gmail.com>
515
516 * ppc-dis.c (ppc_opts): Add "power10" entry.
517 (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
518 * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
519
73199c2b
NC		 5202020-05-11 Nick Clifton <nickc@redhat.com>
521
522 * po/fr.po: Updated French translation.
523
09c1e68a
AC		 5242020-04-30 Alex Coplan <alex.coplan@arm.com>
525
526 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
527 * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
528 (operand_general_constraint_met_p): validate
529 AARCH64_OPND_UNDEFINED.
530 * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
531 for FLD_imm16_2.
532 * aarch64-asm-2.c: Regenerated.
533 * aarch64-dis-2.c: Regenerated.
534 * aarch64-opc-2.c: Regenerated.
535
9654d51a
NC		 5362020-04-29 Nick Clifton <nickc@redhat.com>
537
538 PR 22699
539 * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
540 and SETRC insns.
541
c2e71e57
NC		 5422020-04-29 Nick Clifton <nickc@redhat.com>
543
544 * po/sv.po: Updated Swedish translation.
545
5c936ef5
NC		 5462020-04-29 Nick Clifton <nickc@redhat.com>
547
548 PR 22699
549 * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
550 IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
551 * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
552 IMM0_8U case.
553
bb2a1453
AS		 5542020-04-21 Andreas Schwab <schwab@linux-m68k.org>
555
556 PR 25848
557 * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
558 cmpi only on m68020up and cpu32.
559
c2e5c986
SD		 5602020-04-20 Sudakshina Das <sudi.das@arm.com>
561
562 * aarch64-asm.c (aarch64_ins_none): New.
563 * aarch64-asm.h (ins_none): New declaration.
564 * aarch64-dis.c (aarch64_ext_none): New.
565 * aarch64-dis.h (ext_none): New declaration.
566 * aarch64-opc.c (aarch64_print_operand): Update case for
567 AARCH64_OPND_BARRIER_PSB.
568 * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
569 (AARCH64_OPERANDS): Update inserter/extracter for
570 AARCH64_OPND_BARRIER_PSB to use new dummy functions.
571 * aarch64-asm-2.c: Regenerated.
572 * aarch64-dis-2.c: Regenerated.
573 * aarch64-opc-2.c: Regenerated.
574
8a6e1d1d
SD		 5752020-04-20 Sudakshina Das <sudi.das@arm.com>
576
577 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
578 (aarch64_feature_ras, RAS): Likewise.
579 (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
580 (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
581 autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
582 autiaz, autiasp, autibz, autibsp to be CORE_INSN.
583 * aarch64-asm-2.c: Regenerated.
584 * aarch64-dis-2.c: Regenerated.
585 * aarch64-opc-2.c: Regenerated.
586
e409955d
FS		 5872020-04-17 Fredrik Strupe <fredrik@strupe.net>
588
589 * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
590 (print_insn_neon): Support disassembly of conditional
591 instructions.
592
c54a9b56
DF		 5932020-02-16 David Faust <david.faust@oracle.com>
594
595 * bpf-desc.c: Regenerate.
596 * bpf-desc.h: Likewise.
597 * bpf-opc.c: Regenerate.
598 * bpf-opc.h: Likewise.
599
bb651e8b
CL		 6002020-04-07 Lili Cui <lili.cui@intel.com>
601
602 * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
603 (prefix_table): New instructions (see prefixes above).
604 (rm_table): Likewise
605 * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
606 CPU_ANY_TSXLDTRK_FLAGS.
607 (cpu_flags): Add CpuTSXLDTRK.
608 * i386-opc.h (enum): Add CpuTSXLDTRK.
609 (i386_cpu_flags): Add cputsxldtrk.
610 * i386-opc.tbl: Add XSUSPLDTRK insns.
611 * i386-init.h: Regenerate.
612 * i386-tbl.h: Likewise.
613
4b27d27c
L		 6142020-04-02 Lili Cui <lili.cui@intel.com>
615
616 * i386-dis.c (prefix_table): New instructions serialize.
617 * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
618 CPU_ANY_SERIALIZE_FLAGS.
619 (cpu_flags): Add CpuSERIALIZE.
620 * i386-opc.h (enum): Add CpuSERIALIZE.
621 (i386_cpu_flags): Add cpuserialize.
622 * i386-opc.tbl: Add SERIALIZE insns.
623 * i386-init.h: Regenerate.
624 * i386-tbl.h: Likewise.
625
832a5807
AM		 6262020-03-26 Alan Modra <amodra@gmail.com>
627
628 * disassemble.h (opcodes_assert): Declare.
629 (OPCODES_ASSERT): Define.
630 * disassemble.c: Don't include assert.h. Include opintl.h.
631 (opcodes_assert): New function.
632 * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
633 (bfd_h8_disassemble): Reduce size of data array. Correctly
634 calculate maxlen. Omit insn decoding when insn length exceeds
635 maxlen. Exit from nibble loop when looking for E, before
636 accessing next data byte. Move processing of E outside loop.
637 Replace tests of maxlen in loop with assertions.
638
4c4addbe
AM		 6392020-03-26 Alan Modra <amodra@gmail.com>
640
641 * arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
642
a18cd0ca
AM		 6432020-03-25 Alan Modra <amodra@gmail.com>
644
645 * z80-dis.c (suffix): Init mybuf.
646
57cb32b3
AM		 6472020-03-22 Alan Modra <amodra@gmail.com>
648
649 * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
650 successflly read from section.
651
beea5cc1
AM		 6522020-03-22 Alan Modra <amodra@gmail.com>
653
654 * arc-dis.c (find_format): Use ISO C string concatenation rather
655 than line continuation within a string. Don't access needs_limm
656 before testing opcode != NULL.
657
03704c77
AM		 6582020-03-22 Alan Modra <amodra@gmail.com>
659
660 * ns32k-dis.c (print_insn_arg): Update comment.
661 (print_insn_ns32k): Reduce size of index_offset array, and
662 initialize, passing -1 to print_insn_arg for args that are not
663 an index. Don't exit arg loop early. Abort on bad arg number.
664
d1023b5d
AM		 6652020-03-22 Alan Modra <amodra@gmail.com>
666
667 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
668 * s12z-opc.c: Formatting.
669 (operands_f): Return an int.
670 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
671 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
672 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
673 (exg_sex_discrim): Likewise.
674 (create_immediate_operand, create_bitfield_operand),
675 (create_register_operand_with_size, create_register_all_operand),
676 (create_register_all16_operand, create_simple_memory_operand),
677 (create_memory_operand, create_memory_auto_operand): Don't
678 segfault on malloc failure.
679 (z_ext24_decode): Return an int status, negative on fail, zero
680 on success.
681 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
682 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
683 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
684 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
685 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
686 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
687 (loop_primitive_decode, shift_decode, psh_pul_decode),
688 (bit_field_decode): Similarly.
689 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
690 to return value, update callers.
691 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
692 Don't segfault on NULL operand.
693 (decode_operation): Return OP_INVALID on first fail.
694 (decode_s12z): Check all reads, returning -1 on fail.
695
340f3ac8
AM		 6962020-03-20 Alan Modra <amodra@gmail.com>
697
698 * metag-dis.c (print_insn_metag): Don't ignore status from
699 read_memory_func.
700
fe90ae8a
AM		 7012020-03-20 Alan Modra <amodra@gmail.com>
702
703 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
704 Initialize parts of buffer not written when handling a possible
705 2-byte insn at end of section. Don't attempt decoding of such
706 an insn by the 4-byte machinery.
707
833d919c
AM		 7082020-03-20 Alan Modra <amodra@gmail.com>
709
710 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
711 partially filled buffer. Prevent lookup of 4-byte insns when
712 only VLE 2-byte insns are possible due to section size. Print
713 ".word" rather than ".long" for 2-byte leftovers.
714
327ef784
NC		 7152020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
716
717 PR 25641
718 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
719
1673df32
JB		 7202020-03-13 Jan Beulich <jbeulich@suse.com>
721
722 * i386-dis.c (X86_64_0D): Rename to ...
723 (X86_64_0E): ... this.
724
384f3689
L		 7252020-03-09 H.J. Lu <hongjiu.lu@intel.com>
726
727 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
728 * Makefile.in: Regenerated.
729
865e2027
JB		 7302020-03-09 Jan Beulich <jbeulich@suse.com>
731
732 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
733 3-operand pseudos.
734 * i386-tbl.h: Re-generate.
735
2f13234b
JB		 7362020-03-09 Jan Beulich <jbeulich@suse.com>
737
738 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
739 vprot*, vpsha*, and vpshl*.
740 * i386-tbl.h: Re-generate.
741
3fabc179
JB		 7422020-03-09 Jan Beulich <jbeulich@suse.com>
743
744 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
745 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
746 * i386-tbl.h: Re-generate.
747
3677e4c1
JB		 7482020-03-09 Jan Beulich <jbeulich@suse.com>
749
750 * i386-gen.c (set_bitfield): Ignore zero-length field names.
751 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
752 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
753 * i386-tbl.h: Re-generate.
754
4c4898e8
JB		 7552020-03-09 Jan Beulich <jbeulich@suse.com>
756
757 * i386-gen.c (struct template_arg, struct template_instance,
758 struct template_param, struct template, templates,
759 parse_template, expand_templates): New.
760 (process_i386_opcodes): Various local variables moved to
761 expand_templates. Call parse_template and expand_templates.
762 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
763 * i386-tbl.h: Re-generate.
764
bc49bfd8
JB		 7652020-03-06 Jan Beulich <jbeulich@suse.com>
766
767 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
768 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
769 register and memory source templates. Replace VexW= by VexW*
770 where applicable.
771 * i386-tbl.h: Re-generate.
772
4873e243
JB		 7732020-03-06 Jan Beulich <jbeulich@suse.com>
774
775 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
776 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
777 * i386-tbl.h: Re-generate.
778
672a349b
JB		 7792020-03-06 Jan Beulich <jbeulich@suse.com>
780
781 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
782 * i386-tbl.h: Re-generate.
783
4ed21b58
JB		 7842020-03-06 Jan Beulich <jbeulich@suse.com>
785
786 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
787 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
788 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
789 VexW0 on SSE2AVX variants.
790 (vmovq): Drop NoRex64 from XMM/XMM variants.
791 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
792 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
793 applicable use VexW0.
794 * i386-tbl.h: Re-generate.
795
643bb870
JB		 7962020-03-06 Jan Beulich <jbeulich@suse.com>
797
798 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
799 * i386-opc.h (Rex64): Delete.
800 (struct i386_opcode_modifier): Remove rex64 field.
801 * i386-opc.tbl (crc32): Drop Rex64.
802 Replace Rex64 with Size64 everywhere else.
803 * i386-tbl.h: Re-generate.
804
a23b33b3
JB		 8052020-03-06 Jan Beulich <jbeulich@suse.com>
806
807 * i386-dis.c (OP_E_memory): Exclude recording of used address
808 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
809 addressed memory operands for MPX insns.
810
a0497384
JB		 8112020-03-06 Jan Beulich <jbeulich@suse.com>
812
813 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
814 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
815 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
816 (ptwrite): Split into non-64-bit and 64-bit forms.
817 * i386-tbl.h: Re-generate.
818
b630c145
JB		 8192020-03-06 Jan Beulich <jbeulich@suse.com>
820
821 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
822 template.
823 * i386-tbl.h: Re-generate.
824
a847e322
JB		 8252020-03-04 Jan Beulich <jbeulich@suse.com>
826
827 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
828 (prefix_table): Move vmmcall here. Add vmgexit.
829 (rm_table): Replace vmmcall entry by prefix_table[] escape.
830 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
831 (cpu_flags): Add CpuSEV_ES entry.
832 * i386-opc.h (CpuSEV_ES): New.
833 (union i386_cpu_flags): Add cpusev_es field.
834 * i386-opc.tbl (vmgexit): New.
835 * i386-init.h, i386-tbl.h: Re-generate.
836
3cd7f3e3
L		 8372020-03-03 H.J. Lu <hongjiu.lu@intel.com>
838
839 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
840 with MnemonicSize.
841 * i386-opc.h (IGNORESIZE): New.
842 (DEFAULTSIZE): Likewise.
843 (IgnoreSize): Removed.
844 (DefaultSize): Likewise.
845 (MnemonicSize): New.
846 (i386_opcode_modifier): Replace ignoresize/defaultsize with
847 mnemonicsize.
848 * i386-opc.tbl (IgnoreSize): New.
849 (DefaultSize): Likewise.
850 * i386-tbl.h: Regenerated.
851
b8ba1385
SB		 8522020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
853
854 PR 25627
855 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
856 instructions.
857
10d97a0f
L		 8582020-03-03 H.J. Lu <hongjiu.lu@intel.com>
859
860 PR gas/25622
861 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
862 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
863 * i386-tbl.h: Regenerated.
864
dc1e8a47
AM		 8652020-02-26 Alan Modra <amodra@gmail.com>
866
867 * aarch64-asm.c: Indent labels correctly.
868 * aarch64-dis.c: Likewise.
869 * aarch64-gen.c: Likewise.
870 * aarch64-opc.c: Likewise.
871 * alpha-dis.c: Likewise.
872 * i386-dis.c: Likewise.
873 * nds32-asm.c: Likewise.
874 * nfp-dis.c: Likewise.
875 * visium-dis.c: Likewise.
876
265b4673
CZ		 8772020-02-25 Claudiu Zissulescu <claziss@gmail.com>
878
879 * arc-regs.h (int_vector_base): Make it available for all ARC
880 CPUs.
881
bd0cf5a6
NC		 8822020-02-20 Nelson Chu <nelson.chu@sifive.com>
883
884 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
885 changed.
886
fa164239
JW		 8872020-02-19 Nelson Chu <nelson.chu@sifive.com>
888
889 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
890 c.mv/c.li if rs1 is zero.
891
272a84b1
L		 8922020-02-17 H.J. Lu <hongjiu.lu@intel.com>
893
894 * i386-gen.c (cpu_flag_init): Replace CpuABM with
895 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
896 CPU_POPCNT_FLAGS.
897 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
898 * i386-opc.h (CpuABM): Removed.
899 (CpuPOPCNT): New.
900 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
901 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
902 popcnt. Remove CpuABM from lzcnt.
903 * i386-init.h: Regenerated.
904 * i386-tbl.h: Likewise.
905
1f730c46
JB		 9062020-02-17 Jan Beulich <jbeulich@suse.com>
907
908 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
909 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
910 VexW1 instead of open-coding them.
911 * i386-tbl.h: Re-generate.
912
c8f8eebc
JB		 9132020-02-17 Jan Beulich <jbeulich@suse.com>
914
915 * i386-opc.tbl (AddrPrefixOpReg): Define.
916 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
917 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
918 templates. Drop NoRex64.
919 * i386-tbl.h: Re-generate.
920
b9915cbc
JB		 9212020-02-17 Jan Beulich <jbeulich@suse.com>
922
923 PR gas/6518
924 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
925 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
926 into Intel syntax instance (with Unpsecified) and AT&T one
927 (without).
928 (vcvtneps2bf16): Likewise, along with folding the two so far
929 separate ones.
930 * i386-tbl.h: Re-generate.
931
ce504911
L		 9322020-02-16 H.J. Lu <hongjiu.lu@intel.com>
933
934 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
935 CPU_ANY_SSE4A_FLAGS.
936
dabec65d
AM		 9372020-02-17 Alan Modra <amodra@gmail.com>
938
939 * i386-gen.c (cpu_flag_init): Correct last change.
940
af5c13b0
L		 9412020-02-16 H.J. Lu <hongjiu.lu@intel.com>
942
943 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
944 CPU_ANY_SSE4_FLAGS.
945
6867aac0
L		 9462020-02-14 H.J. Lu <hongjiu.lu@intel.com>
947
948 * i386-opc.tbl (movsx): Remove Intel syntax comments.
949 (movzx): Likewise.
950
65fca059
JB		 9512020-02-14 Jan Beulich <jbeulich@suse.com>
952
953 PR gas/25438
954 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
955 destination for Cpu64-only variant.
956 (movzx): Fold patterns.
957 * i386-tbl.h: Re-generate.
958
7deea9aa
JB		 9592020-02-13 Jan Beulich <jbeulich@suse.com>
960
961 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
962 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
963 CPU_ANY_SSE4_FLAGS entry.
964 * i386-init.h: Re-generate.
965
6c0946d0
JB		 9662020-02-12 Jan Beulich <jbeulich@suse.com>
967
968 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
969 with Unspecified, making the present one AT&T syntax only.
970 * i386-tbl.h: Re-generate.
971
ddb56fe6
JB		 9722020-02-12 Jan Beulich <jbeulich@suse.com>
973
974 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
975 * i386-tbl.h: Re-generate.
976
5990e377
JB		 9772020-02-12 Jan Beulich <jbeulich@suse.com>
978
979 PR gas/24546
980 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
981 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
982 Amd64 and Intel64 templates.
983 (call, jmp): Likewise for far indirect variants. Dro
984 Unspecified.
985 * i386-tbl.h: Re-generate.
986
50128d0c
JB		 9872020-02-11 Jan Beulich <jbeulich@suse.com>
988
989 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
990 * i386-opc.h (ShortForm): Delete.
991 (struct i386_opcode_modifier): Remove shortform field.
992 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
993 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
994 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
995 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
996 Drop ShortForm.
997 * i386-tbl.h: Re-generate.
998
1e05b5c4
JB		 9992020-02-11 Jan Beulich <jbeulich@suse.com>
1000
1001 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
1002 fucompi): Drop ShortForm from operand-less templates.
1003 * i386-tbl.h: Re-generate.
1004
2f5dd314
AM		 10052020-02-11 Alan Modra <amodra@gmail.com>
1006
1007 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
1008 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
1009 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
1010 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
1011 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
1012
5aae9ae9
MM		 10132020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
1014
1015 * arm-dis.c (print_insn_cde): Define 'V' parse character.
1016 (cde_opcodes): Add VCX* instructions.
1017
4934a27c
MM		 10182020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
1019 Matthew Malcomson <matthew.malcomson@arm.com>
1020
1021 * arm-dis.c (struct cdeopcode32): New.
1022 (CDE_OPCODE): New macro.
1023 (cde_opcodes): New disassembly table.
1024 (regnames): New option to table.
1025 (cde_coprocs): New global variable.
1026 (print_insn_cde): New
1027 (print_insn_thumb32): Use print_insn_cde.
1028 (parse_arm_disassembler_options): Parse coprocN args.
1029
4b5aaf5f
L		 10302020-02-10 H.J. Lu <hongjiu.lu@intel.com>
1031
1032 PR gas/25516
1033 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
1034 with ISA64.
1035 * i386-opc.h (AMD64): Removed.
1036 (Intel64): Likewose.
1037 (AMD64): New.
1038 (INTEL64): Likewise.
1039 (INTEL64ONLY): Likewise.
1040 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
1041 * i386-opc.tbl (Amd64): New.
1042 (Intel64): Likewise.
1043 (Intel64Only): Likewise.
1044 Replace AMD64 with Amd64. Update sysenter/sysenter with
1045 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
1046 * i386-tbl.h: Regenerated.
1047
9fc0b501
SB		 10482020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
1049
1050 PR 25469
1051 * z80-dis.c: Add support for GBZ80 opcodes.
1052
c5d7be0c
AM		 10532020-02-04 Alan Modra <amodra@gmail.com>
1054
1055 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
1056
44e4546f
AM		 10572020-02-03 Alan Modra <amodra@gmail.com>
1058
1059 * m32c-ibld.c: Regenerate.
1060
b2b1453a
AM		 10612020-02-01 Alan Modra <amodra@gmail.com>
1062
1063 * frv-ibld.c: Regenerate.
1064
4102be5c
JB		 10652020-01-31 Jan Beulich <jbeulich@suse.com>
1066
1067 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
1068 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
1069 (OP_E_memory): Replace xmm_mdq_mode case label by
1070 vex_scalar_w_dq_mode one.
1071 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
1072
825bd36c
JB		 10732020-01-31 Jan Beulich <jbeulich@suse.com>
1074
1075 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
1076 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
1077 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
1078 (intel_operand_size): Drop vex_w_dq_mode case label.
1079
c3036ed0
RS		 10802020-01-31 Richard Sandiford <richard.sandiford@arm.com>
1081
1082 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
1083 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
1084
0c115f84
AM		 10852020-01-30 Alan Modra <amodra@gmail.com>
1086
1087 * m32c-ibld.c: Regenerate.
1088
bd434cc4
JM		 10892020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
1090
1091 * bpf-opc.c: Regenerate.
1092
aeab2b26
JB		 10932020-01-30 Jan Beulich <jbeulich@suse.com>
1094
1095 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
1096 (dis386): Use them to replace C2/C3 table entries.
1097 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
1098 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
1099 ones. Use Size64 instead of DefaultSize on Intel64 ones.
1100 * i386-tbl.h: Re-generate.
1101
62b3f548
JB		 11022020-01-30 Jan Beulich <jbeulich@suse.com>
1103
1104 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
1105 forms.
1106 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
1107 DefaultSize.
1108 * i386-tbl.h: Re-generate.
1109
1bd8ae10
AM		 11102020-01-30 Alan Modra <amodra@gmail.com>
1111
1112 * tic4x-dis.c (tic4x_dp): Make unsigned.
1113
bc31405e
L		 11142020-01-27 H.J. Lu <hongjiu.lu@intel.com>
1115 Jan Beulich <jbeulich@suse.com>
1116
1117 PR binutils/25445
1118 * i386-dis.c (MOVSXD_Fixup): New function.
1119 (movsxd_mode): New enum.
1120 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
1121 (intel_operand_size): Handle movsxd_mode.
1122 (OP_E_register): Likewise.
1123 (OP_G): Likewise.
1124 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
1125 register on movsxd. Add movsxd with 16-bit destination register
1126 for AMD64 and Intel64 ISAs.
1127 * i386-tbl.h: Regenerated.
1128
7568c93b
TC		 11292020-01-27 Tamar Christina <tamar.christina@arm.com>
1130
1131 PR 25403
1132 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
1133 * aarch64-asm-2.c: Regenerate
1134 * aarch64-dis-2.c: Likewise.
1135 * aarch64-opc-2.c: Likewise.
1136
c006a730
JB		 11372020-01-21 Jan Beulich <jbeulich@suse.com>
1138
1139 * i386-opc.tbl (sysret): Drop DefaultSize.
1140 * i386-tbl.h: Re-generate.
1141
c906a69a
JB		 11422020-01-21 Jan Beulich <jbeulich@suse.com>
1143
1144 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
1145 Dword.
1146 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
1147 * i386-tbl.h: Re-generate.
1148
26916852
NC		 11492020-01-20 Nick Clifton <nickc@redhat.com>
1150
1151 * po/de.po: Updated German translation.
1152 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1153 * po/uk.po: Updated Ukranian translation.
1154
4d6cbb64
AM		 11552020-01-20 Alan Modra <amodra@gmail.com>
1156
1157 * hppa-dis.c (fput_const): Remove useless cast.
1158
2bddb71a
AM		 11592020-01-20 Alan Modra <amodra@gmail.com>
1160
1161 * arm-dis.c (print_insn_arm): Wrap 'T' value.
1162
1b1bb2c6
NC		 11632020-01-18 Nick Clifton <nickc@redhat.com>
1164
1165 * configure: Regenerate.
1166 * po/opcodes.pot: Regenerate.
1167
ae774686
NC		 11682020-01-18 Nick Clifton <nickc@redhat.com>
1169
1170 Binutils 2.34 branch created.
1171
07f1f3aa
CB		 11722020-01-17 Christian Biesinger <cbiesinger@google.com>
1173
1174 * opintl.h: Fix spelling error (seperate).
1175
42e04b36
L		 11762020-01-17 H.J. Lu <hongjiu.lu@intel.com>
1177
1178 * i386-opc.tbl: Add {vex} pseudo prefix.
1179 * i386-tbl.h: Regenerated.
1180
2da2eaf4
AV		 11812020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1182
1183 PR 25376
1184 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
1185 (neon_opcodes): Likewise.
1186 (select_arm_features): Make sure we enable MVE bits when selecting
1187 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
1188 any architecture.
1189
d0849eed
JB		 11902020-01-16 Jan Beulich <jbeulich@suse.com>
1191
1192 * i386-opc.tbl: Drop stale comment from XOP section.
1193
9cf70a44
JB		 11942020-01-16 Jan Beulich <jbeulich@suse.com>
1195
1196 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
1197 (extractps): Add VexWIG to SSE2AVX forms.
1198 * i386-tbl.h: Re-generate.
1199
4814632e
JB		 12002020-01-16 Jan Beulich <jbeulich@suse.com>
1201
1202 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
1203 Size64 from and use VexW1 on SSE2AVX forms.
1204 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
1205 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
1206 * i386-tbl.h: Re-generate.
1207
aad09917
AM		 12082020-01-15 Alan Modra <amodra@gmail.com>
1209
1210 * tic4x-dis.c (tic4x_version): Make unsigned long.
1211 (optab, optab_special, registernames): New file scope vars.
1212 (tic4x_print_register): Set up registernames rather than
1213 malloc'd registertable.
1214 (tic4x_disassemble): Delete optable and optable_special. Use
1215 optab and optab_special instead. Throw away old optab,
1216 optab_special and registernames when info->mach changes.
1217
7a6bf3be
SB		 12182020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
1219
1220 PR 25377
1221 * z80-dis.c (suffix): Use .db instruction to generate double
1222 prefix.
1223
ca1eaac0
AM		 12242020-01-14 Alan Modra <amodra@gmail.com>
1225
1226 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
1227 values to unsigned before shifting.
1228
1d67fe3b
TT		 12292020-01-13 Thomas Troeger <tstroege@gmx.de>
1230
1231 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
1232 flow instructions.
1233 (print_insn_thumb16, print_insn_thumb32): Likewise.
1234 (print_insn): Initialize the insn info.
1235 * i386-dis.c (print_insn): Initialize the insn info fields, and
1236 detect jumps.
1237
5e4f7e05
CZ		 12382012-01-13 Claudiu Zissulescu <claziss@gmail.com>
1239
1240 * arc-opc.c (C_NE): Make it required.
1241
b9fe6b8a
CZ		 12422012-01-13 Claudiu Zissulescu <claziss@gmail.com>
1243
1244 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
1245 reserved register name.
1246
90dee485
AM		 12472020-01-13 Alan Modra <amodra@gmail.com>
1248
1249 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
1250 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
1251
febda64f
AM		 12522020-01-13 Alan Modra <amodra@gmail.com>
1253
1254 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
1255 result of wasm_read_leb128 in a uint64_t and check that bits
1256 are not lost when copying to other locals. Use uint32_t for
1257 most locals. Use PRId64 when printing int64_t.
1258
df08b588
AM		 12592020-01-13 Alan Modra <amodra@gmail.com>
1260
1261 * score-dis.c: Formatting.
1262 * score7-dis.c: Formatting.
1263
b2c759ce
AM		 12642020-01-13 Alan Modra <amodra@gmail.com>
1265
1266 * score-dis.c (print_insn_score48): Use unsigned variables for
1267 unsigned values. Don't left shift negative values.
1268 (print_insn_score32): Likewise.
1269 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
1270
5496abe1
AM		 12712020-01-13 Alan Modra <amodra@gmail.com>
1272
1273 * tic4x-dis.c (tic4x_print_register): Remove dead code.
1274
202e762b
AM		 12752020-01-13 Alan Modra <amodra@gmail.com>
1276
1277 * fr30-ibld.c: Regenerate.
1278
7ef412cf
AM		 12792020-01-13 Alan Modra <amodra@gmail.com>
1280
1281 * xgate-dis.c (print_insn): Don't left shift signed value.
1282 (ripBits): Formatting, use 1u.
1283
7f578b95
AM		 12842020-01-10 Alan Modra <amodra@gmail.com>
1285
1286 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
1287 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
1288
441af85b
AM		 12892020-01-10 Alan Modra <amodra@gmail.com>
1290
1291 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
1292 and XRREG value earlier to avoid a shift with negative exponent.
1293 * m10200-dis.c (disassemble): Similarly.
1294
bce58db4
NC		 12952020-01-09 Nick Clifton <nickc@redhat.com>
1296
1297 PR 25224
1298 * z80-dis.c (ld_ii_ii): Use correct cast.
1299
40c75bc8
SB		 13002020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
1301
1302 PR 25224
1303 * z80-dis.c (ld_ii_ii): Use character constant when checking
1304 opcode byte value.
1305
d835a58b
JB		 13062020-01-09 Jan Beulich <jbeulich@suse.com>
1307
1308 * i386-dis.c (SEP_Fixup): New.
1309 (SEP): Define.
1310 (dis386_twobyte): Use it for sysenter/sysexit.
1311 (enum x86_64_isa): Change amd64 enumerator to value 1.
1312 (OP_J): Compare isa64 against intel64 instead of amd64.
1313 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
1314 forms.
1315 * i386-tbl.h: Re-generate.
1316
030a2e78
AM		 13172020-01-08 Alan Modra <amodra@gmail.com>
1318
1319 * z8k-dis.c: Include libiberty.h
1320 (instr_data_s): Make max_fetched unsigned.
1321 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
1322 Don't exceed byte_info bounds.
1323 (output_instr): Make num_bytes unsigned.
1324 (unpack_instr): Likewise for nibl_count and loop.
1325 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
1326 idx unsigned.
1327 * z8k-opc.h: Regenerate.
1328
bb82aefe
SV		 13292020-01-07 Shahab Vahedi <shahab@synopsys.com>
1330
1331 * arc-tbl.h (llock): Use 'LLOCK' as class.
1332 (llockd): Likewise.
1333 (scond): Use 'SCOND' as class.
1334 (scondd): Likewise.
1335 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
1336 (scondd): Likewise.
1337
cc6aa1a6
AM		 13382020-01-06 Alan Modra <amodra@gmail.com>
1339
1340 * m32c-ibld.c: Regenerate.
1341
660e62b1
AM		 13422020-01-06 Alan Modra <amodra@gmail.com>
1343
1344 PR 25344
1345 * z80-dis.c (suffix): Don't use a local struct buffer copy.
1346 Peek at next byte to prevent recursion on repeated prefix bytes.
1347 Ensure uninitialised "mybuf" is not accessed.
1348 (print_insn_z80): Don't zero n_fetch and n_used here,..
1349 (print_insn_z80_buf): ..do it here instead.
1350
c9ae58fe
AM		 13512020-01-04 Alan Modra <amodra@gmail.com>
1352
1353 * m32r-ibld.c: Regenerate.
1354
5f57d4ec
AM		 13552020-01-04 Alan Modra <amodra@gmail.com>
1356
1357 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
1358
2c5c1196
AM		 13592020-01-04 Alan Modra <amodra@gmail.com>
1360
1361 * crx-dis.c (match_opcode): Avoid shift left of signed value.
1362
2e98c6c5
AM		 13632020-01-04 Alan Modra <amodra@gmail.com>
1364
1365 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
1366
567dfba2
JB		 13672020-01-03 Jan Beulich <jbeulich@suse.com>
1368
5437a02a
JB		 1369 * aarch64-tbl.h (aarch64_opcode_table): Use
1370 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
1371
13722020-01-03 Jan Beulich <jbeulich@suse.com>
1373
1374 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
567dfba2
JB		 1375 forms of SUDOT and USDOT.
1376
8c45011a
JB		 13772020-01-03 Jan Beulich <jbeulich@suse.com>
1378
5437a02a 1379 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
8c45011a
JB		 1380 uzip{1,2}.
1381 * opcodes/aarch64-dis-2.c: Re-generate.
1382
f4950f76
JB		 13832020-01-03 Jan Beulich <jbeulich@suse.com>
1384
5437a02a 1385 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
f4950f76
JB		 1386 FMMLA encoding.
1387 * opcodes/aarch64-dis-2.c: Re-generate.
1388
6655dba2
SB		 13892020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
1390
1391 * z80-dis.c: Add support for eZ80 and Z80 instructions.
1392
b14ce8bf
AM		 13932020-01-01 Alan Modra <amodra@gmail.com>
1394
1395 Update year range in copyright notice of all files.
1396
0b114740 1397For older changes see ChangeLog-2019
3499769a 1398\f
0b114740 1399Copyright (C) 2020 Free Software Foundation, Inc.
3499769a
AM		 1400
1401Copying and distribution of this file, with or without modification,
1402are permitted in any medium without royalty provided the copyright
1403notice and this notice are preserved.
1404
1405Local Variables:
1406mode: change-log
1407left-margin: 8
1408fill-column: 74
1409version-control: never
1410End:
GDB Binutils - Deliverables
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