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* options.cc (General_options::parse_dynamic_list): New function.
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
a7bea99d
L		 12008-11-03 H.J. Lu <hongjiu.lu@intel.com>
2
3 * i386-opc.tbl: Add cmovpe and cmovpo.
4 * i386-tbl.h: Regenerated.
5
4267b19f
NC		 62008-10-22 Nick Clifton <nickc@redhat.com>
7
8 PR 6937
9 * configure.in (SHARED_LIBADD): Revert previous change.
10 Add a comment explaining why.
11 (SHARED_DEPENDENCIES): Revert previous change.
12 * configure: Regenerate.
13
8a9629d0
NC		 142008-10-10 Nick Clifton <nickc@redhat.com>
15
16 PR 6937
17 * configure.in (SHARED_LIBADD): Add libiberty.a.
18 (SHARED_DEPENDENCIES): Add libiberty.a.
19
c587b3f9
L		 202008-09-30 H.J. Lu <hongjiu.lu@intel.com>
21
22 * i386-gen.c: Include "hashtab.h".
23 (next_field): Take a new argument, last. Check last.
24 (process_i386_cpu_flag): Updated.
25 (process_i386_opcode_modifier): Likewise.
26 (process_i386_operand_type): Likewise.
27 (process_i386_registers): Likewise.
28 (output_i386_opcode): New.
29 (opcode_hash_entry): Likewise.
30 (opcode_hash_table): Likewise.
31 (opcode_hash_hash): Likewise.
32 (opcode_hash_eq): Likewise.
33 (process_i386_opcodes): Use opcode hash table and opcode array.
34
34b23dab
AK		 352008-09-30 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
36
37 * s390-opc.txt (stdy, stey): Fix description
38
782e11fd
AM		 392008-09-30 Alan Modra <amodra@bigpond.net.au>
40
41 * Makefile.am: Run "make dep-am".
42 * Makefile.in: Regenerate.
43
1927a18f
L		 442008-09-29 H.J. Lu <hongjiu.lu@intel.com>
45
46 * aclocal.m4: Regenerated.
47 * configure: Likewise.
48 * Makefile.in: Likewise.
49
afac680a
NC		 502008-09-29 Nick Clifton <nickc@redhat.com>
51
52 * po/vi.po: Updated Vietnamese translation.
53 * po/fr.po: Updated French translation.
54
b40d5eb9
AK		 552008-09-26 Florian Krohm <fkrohm@us.ibm.com>
56
57 * s390-opc.txt (thder, thdr): Change RRE_RR to RRE_FF.
58 (cfxr, cfdr, cfer, clclu): Add esa flag.
59 (sqd): Instruction added.
60 (qadtr, qaxtr): Change RRF_FFFU to RRF_FUFF.
61 * s390-opc.c: (INSTR_RRF_FFFU, MASK_RRF_FFFU): Removed.
62
d0411736
AM		 632008-09-14 Arnold Metselaar <arnold.metselaar@planet.nl>
64
65 * z80-dis.c (prt_rr_nn): Fix register pair for two byte opcodes.
66 (tab_elt opc_ed): Add "ld r,a" and "ld r,a" instructions.
67
3e126784
L		 682008-09-11 H.J. Lu <hongjiu.lu@intel.com>
69
70 * i386-opc.tbl: Fix memory operand size for cmpXXXs[sd].
71 * i386-tbl.h: Regenerated.
72
ddab3d59
JB		 732008-08-28 Jan Beulich <jbeulich@novell.com>
74
75 * i386-dis.c (dis386): Adjust far return mnemonics.
76 * i386-opc.tbl: Add retf.
77 * i386-tbl.h: Re-generate.
78
b19d5385
JB		 792008-08-28 Jan Beulich <jbeulich@novell.com>
80
81 * i386-dis.c (dis386_twobyte): Adjust cmovXX mnemonics.
82
1ca35711
L		 832008-08-28 H.J. Lu <hongjiu.lu@intel.com>
84
85 * ia64-dis.c (print_insn_ia64): Handle cr.iib0 and cr.iib1.
86 * ia64-gen.c (lookup_specifier): Likewise.
87
88 * ia64-ic.tbl: Add support for cr.iib0 and cr.iib1.
89 * ia64-raw.tbl: Likewise.
90 * ia64-waw.tbl: Likewise.
91 * ia64-asmtab.c: Regenerated.
92
515c56e7
L		 932008-08-27 H.J. Lu <hongjiu.lu@intel.com>
94
95 * i386-opc.tbl: Correct fidivr operand size.
96
97 * i386-tbl.h: Regenerated.
98
da594c4a
AM		 992008-08-24 Alan Modra <amodra@bigpond.net.au>
100
101 * configure.in: Update a number of obsolete autoconf macros.
102 * aclocal.m4: Regenerate.
103
a5ff0eb2
L		 1042008-08-20 H.J. Lu <hongjiu.lu@intel.com>
105
106 AVX Programming Reference (August, 2008)
107 * i386-dis.c (PREFIX_VEX_38DB): New.
108 (PREFIX_VEX_38DC): Likewise.
109 (PREFIX_VEX_38DD): Likewise.
110 (PREFIX_VEX_38DE): Likewise.
111 (PREFIX_VEX_38DF): Likewise.
112 (PREFIX_VEX_3ADF): Likewise.
113 (VEX_LEN_38DB_P_2): Likewise.
114 (VEX_LEN_38DC_P_2): Likewise.
115 (VEX_LEN_38DD_P_2): Likewise.
116 (VEX_LEN_38DE_P_2): Likewise.
117 (VEX_LEN_38DF_P_2): Likewise.
118 (VEX_LEN_3ADF_P_2): Likewise.
119 (PREFIX_VEX_3A04): Updated.
120 (VEX_LEN_3A06_P_2): Likewise.
121 (prefix_table): Add PREFIX_VEX_38DB, PREFIX_VEX_38DC,
122 PREFIX_VEX_38DD, PREFIX_VEX_38DE and PREFIX_VEX_3ADF.
123 (x86_64_table): Likewise.
124 (vex_len_table): Add VEX_LEN_38DB_P_2, VEX_LEN_38DC_P_2,
125 VEX_LEN_38DD_P_2, VEX_LEN_38DE_P_2, VEX_LEN_38DF_P_2 and
126 VEX_LEN_3ADF_P_2.
127
128 * i386-opc.tbl: Add AES + AVX instructions.
129 * i386-init.h: Regenerated.
130 * i386-tbl.h: Likewise.
131
7dc6076f
AK		 1322008-08-15 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
133
134 * s390-opc.c (INSTR_RRF_FFRU, MASK_RRF_FFRU): New instruction format.
135 * s390-opc.txt (lxr, rrdtr, rrxtr): Fix instruction format.
136
7357c5b6
AM		 1372008-08-15 Alan Modra <amodra@bigpond.net.au>
138
139 PR 6526
140 * configure.in: Invoke AC_USE_SYSTEM_EXTENSIONS.
141 * Makefile.in: Regenerate.
142 * aclocal.m4: Regenerate.
143 * config.in: Regenerate.
144 * configure: Regenerate.
145
899d85be
AM		 1462008-08-14 Sebastian Huber <sebastian.huber@embedded-brains.de>
147
148 PR 6825
149 * ppc-opc.c (powerpc_opcodes): Enable rfci, mfpmr, mtpmr for e300.
150
dfb07592
L		 1512008-08-12 H.J. Lu <hongjiu.lu@intel.com>
152
153 * i386-opc.tbl: Add syscall and sysret for Cpu64.
154
155 * i386-tbl.h: Regenerated.
156
323ee3f4
AM		 1572008-08-04 Alan Modra <amodra@bigpond.net.au>
158
159 * Makefile.am (POTFILES.in): Set LC_ALL=C.
160 * Makefile.in: Regenerate.
161 * po/POTFILES.in: Regenerate.
162
9b4e5766
PB		 1632008-08-01 Peter Bergner <bergner@vnet.ibm.com>
164
165 * ppc-dis.c (powerpc_init_dialect): Handle power7 and vsx options.
166 (print_insn_powerpc): Prepend 'vs' when printing VSX registers.
167 (print_ppc_disassembler_options): Document -Mpower7 and -Mvsx.
168 * ppc-opc.c (insert_xt6): New static function.
169 (extract_xt6): Likewise.
170 (insert_xa6): Likewise.
171 (extract_xa6: Likewise.
172 (insert_xb6): Likewise.
173 (extract_xb6): Likewise.
174 (insert_xb6s): Likewise.
175 (extract_xb6s): Likewise.
176 (XS6, XT6, XA6, XB6, XB6S, DM, XX3, XX3DM, XX1_MASK, XX3_MASK,
177 XX3DM_MASK, PPCVSX): New.
178 (powerpc_opcodes): Add opcodes "lxvd2x", "lxvd2ux", "stxvd2x",
179 "stxvd2ux", "xxmrghd", "xxmrgld", "xxpermdi", "xvmovdp", "xvcpsgndp".
180
20fd6e2e
PA		 1812008-08-01 Pedro Alves <pedro@codesourcery.com>
182
183 * Makefile.am ($(srcdir)/ia64-asmtab.c): Remove line continuation.
184 * Makefile.in: Regenerate.
185
a656ed5b
L		 1862008-08-01 H.J. Lu <hongjiu.lu@intel.com>
187
188 * i386-reg.tbl: Use Dw2Inval on AVX registers.
189 * i386-tbl.h: Regenerated.
190
081ba1b3
AM		 1912008-07-30 Michael J. Eager <eager@eagercon.com>
192
193 * ppc-dis.c (print_insn_powerpc): Disassemble FSL/FCR/UDI fields.
194 * ppc-opc.c (powerpc_operands): Add Xilinx APU related operands.
195 (insert_sprg, PPC405): Use PPC_OPCODE_405.
196 (powerpc_opcodes): Add Xilinx APU related opcodes.
197
0af1713e
AM		 1982008-07-30 Alan Modra <amodra@bigpond.net.au>
199
200 * bfin-dis.c, cris-dis.c, i386-dis.c, or32-opc.c: Silence gcc warnings.
201
30c09090
RS		 2022008-07-10 Richard Sandiford <rdsandiford@googlemail.com>
203
204 * mips-dis.c (_print_insn_mips): Use ELF_ST_IS_MIPS16.
205
c27e721e
AN		 2062008-07-07 Adam Nemet <anemet@caviumnetworks.com>
207
208 * mips-opc.c (CP): New macro.
209 (mips_builtin_opcodes): Mark c0, c2 and c3 as CP. Add Octeon to the
210 membership of di, dmfc0, dmtc0, ei, mfc0 and mtc0. Add dmfc2 and
211 dmtc2 Octeon instructions.
212
bd2e2557
SS		 2132008-07-07 Stan Shebs <stan@codesourcery.com>
214
215 * dis-init.c (init_disassemble_info): Init endian_code field.
216 * arm-dis.c (print_insn): Disassemble code according to
217 setting of endian_code.
218 (print_insn_big_arm): Detect when BE8 extension flag has been set.
219
6ba2a415
RS		 2202008-06-30 Richard Sandiford <rdsandiford@googlemail.com>
221
222 * mips-dis.c (_print_insn_mips): Use bfd_asymbol_flavour to check
223 for ELF symbols.
224
c8187e15
PB		 2252008-06-25 Peter Bergner <bergner@vnet.ibm.com>
226
227 * ppc-dis.c (powerpc_init_dialect): Handle -M464.
228 (print_ppc_disassembler_options): Likewise.
229 * ppc-opc.c (PPC464): Define.
230 (powerpc_opcodes): Add mfdcrux and mtdcrux.
231
7a283e07
RW		 2322008-06-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
233
234 * configure: Regenerate.
235
fa452fa6
PB		 2362008-06-13 Peter Bergner <bergner@vnet.ibm.com>
237
238 * ppc-dis.c (print_insn_powerpc): Update prototye to use new
239 ppc_cpu_t typedef.
240 (struct dis_private): New.
241 (POWERPC_DIALECT): New define.
242 (powerpc_dialect): Renamed to...
243 (powerpc_init_dialect): This. Update to use ppc_cpu_t and
244 struct dis_private.
245 (print_insn_big_powerpc): Update for using structure in
246 info->private_data.
247 (print_insn_little_powerpc): Likewise.
248 (operand_value_powerpc): Change type of dialect param to ppc_cpu_t.
249 (skip_optional_operands): Likewise.
250 (print_insn_powerpc): Likewise. Remove initialization of dialect.
251 * ppc-opc.c (extract_bat, extract_bba, extract_bdm, extract_bdp,
252 extract_bo, extract_boe, extract_fxm, extract_mb6, extract_mbe,
253 extract_nb, extract_nsi, extract_rbs, extract_sh6, extract_spr,
254 extract_sprg, extract_tbr insert_bat, insert_bba, insert_bdm,
255 insert_bdp, insert_bo, insert_boe, insert_fxm, insert_mb6, insert_mbe,
256 insert_nsi, insert_ral, insert_ram, insert_raq, insert_ras, insert_rbs,
257 insert_sh6, insert_spr, insert_sprg, insert_tbr): Change the dialect
258 param to be of type ppc_cpu_t. Update prototype.
259
bb35fb24
NC		 2602008-06-12 Adam Nemet <anemet@caviumnetworks.com>
261
262 * mips-dis.c (print_insn_args): Handle field descriptors +x, +p,
263 +s, +S.
264 * mips-opc.c (mips_builtin_opcodes): Add Octeon instructions
265 baddu, bbit*, cins*, dmul, pop, dpop, exts*, mtm*, mtp*, syncs,
266 syncw, syncws, vm3mulu, vm0 and vmulu.
267
dd3cbb7e
NC		 268 * mips-dis.c (print_insn_args): Handle field descriptor +Q.
269 * mips-opc.c (mips_builtin_opcodes): Add Octeon instructions seq,
270 seqi, sne and snei.
271
a5dabbb0
L		 2722008-05-30 H.J. Lu <hongjiu.lu@intel.com>
273
274 * i386-opc.tbl: Add vmovd with 64bit operand.
275 * i386-tbl.h: Regenerated.
276
725a9891
MS		 2772008-05-27 Martin Schwidefsky <schwidefsky@de.ibm.com>
278
279 * s390-opc.c (INSTR_RRF_R0RR): Fix RRF_R0RR operand format.
280
cbc80391
L		 2812008-05-22 H.J. Lu <hongjiu.lu@intel.com>
282
283 * i386-opc.tbl: Add NoAVX to cvtpd2pi, cvtpi2pd and cvttpd2pi.
284 * i386-tbl.h: Regenerated.
285
116615c5
L		 2862008-05-22 H.J. Lu <hongjiu.lu@intel.com>
287
288 PR gas/6517
289 * i386-opc.tbl: Break cvtsi2ss/cvtsi2sd/vcvtsi2sd/vcvtsi2ss
290 into 32bit and 64bit. Remove Reg64|Qword and add
291 IgnoreSize|No_qSuf on 32bit version.
292 * i386-tbl.h: Regenerated.
293
d9479f2d
L		 2942008-05-21 H.J. Lu <hongjiu.lu@intel.com>
295
296 * i386-opc.tbl: Add NoAVX to movdq2q and movq2dq.
297 * i386-tbl.h: Regenerated.
298
3ce6fddb
NC		 2992008-05-21 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
300
301 * cr16-dis.c (build_mask): Adjust the mask for 32-bit bcond.
302
8944f3c2
AM		 3032008-05-14 Alan Modra <amodra@bigpond.net.au>
304
305 * Makefile.am: Run "make dep-am".
306 * Makefile.in: Regenerate.
307
f1f8f695
L		 3082008-05-02 H.J. Lu <hongjiu.lu@intel.com>
309
310 * i386-dis.c (MOVBE_Fixup): New.
311 (Mo): Likewise.
312 (PREFIX_0F3880): Likewise.
313 (PREFIX_0F3881): Likewise.
314 (PREFIX_0F38F0): Updated.
315 (prefix_table): Add PREFIX_0F3880 and PREFIX_0F3881. Update
316 PREFIX_0F38F0 and PREFIX_0F38F1 for movbe.
317 (three_byte_table): Use PREFIX_0F3880 and PREFIX_0F3881.
318
319 * i386-gen.c (cpu_flag_init): Add CPU_MOVBE_FLAGS and
320 CPU_EPT_FLAGS.
321 (cpu_flags): Add CpuMovbe and CpuEPT.
322
323 * i386-opc.h (CpuMovbe): New.
324 (CpuEPT): Likewise.
325 (CpuLM): Updated.
326 (i386_cpu_flags): Add cpumovbe and cpuept.
327
328 * i386-opc.tbl: Add entries for movbe and EPT instructions.
329 * i386-init.h: Regenerated.
330 * i386-tbl.h: Likewise.
331
89aa3097
AN		 3322008-04-29 Adam Nemet <anemet@caviumnetworks.com>
333
334 * mips-opc.c (mips_builtin_opcodes): Set field `match' to 0 for
335 the two drem and the two dremu macros.
336
39c5c168
AN		 3372008-04-28 Adam Nemet <anemet@caviumnetworks.com>
338
339 * mips-opc.c (mips_builtin_opcodes): Mark prefx and c1
340 instructions FP_S. Mark l.s, li.s, lwc1, swc1, s.s, trunc.w.s and
341 cop1 macros INSN2_M_FP_S. Mark l.d, li.d, ldc1 and sdc1 macros
342 INSN2_M_FP_D. Mark trunc.w.d macro INSN2_M_FP_S and INSN2_M_FP_D.
343
f04d18b7
DM		 3442008-04-25 David S. Miller <davem@davemloft.net>
345
346 * sparc-dis.c: Emit %stick instead of %sys_tick, and %stick_cmpr
347 instead of %sys_tick_cmpr, as suggested in architecture manuals.
348
6194aaab
L		 3492008-04-23 Paolo Bonzini <bonzini@gnu.org>
350
351 * aclocal.m4: Regenerate.
352 * configure: Regenerate.
353
1a6b486f
DM		 3542008-04-23 David S. Miller <davem@davemloft.net>
355
356 * sparc-opc.c (asi_table): Add UltraSPARC and Niagara
357 extended values.
358 (prefetch_table): Add missing values.
359
81f8a913
L		 3602008-04-22 H.J. Lu <hongjiu.lu@intel.com>
361
362 * i386-gen.c (opcode_modifiers): Add NoAVX.
363
364 * i386-opc.h (NoAVX): New.
365 (OldGcc): Updated.
366 (i386_opcode_modifier): Add noavx.
367
368 * i386-opc.tbl: Add NoAVX to SSE, SSE2, SSE3 and SSSE3
369 instructions which don't have AVX equivalent.
370 * i386-tbl.h: Regenerated.
371
dae39acc
L		 3722008-04-18 H.J. Lu <hongjiu.lu@intel.com>
373
374 * i386-dis.c (OP_VEX_FMA): New.
375 (OP_EX_VexImmW): Likewise.
376 (VexFMA): Likewise.
377 (Vex128FMA): Likewise.
378 (EXVexImmW): Likewise.
379 (get_vex_imm8): Likewise.
380 (OP_EX_VexReg): Likewise.
381 (vex_i4_done): Renamed to ...
382 (vex_w_done): This.
383 (prefix_table): Replace EXVexW with EXVexImmW on vpermil2ps
384 and vpermil2pd. Replace Vex/Vex128 with VexFMA/Vex128FMA on
385 FMA instructions.
386 (print_insn): Updated.
387 (OP_EX_VexW): Rewrite to swap register in VEX with EX.
388 (OP_REG_VexI4): Check invalid high registers.
389
ce886ab1
DR		 3902008-04-16 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
391 Michael Meissner <michael.meissner@amd.com>
392
393 * i386-opc.tbl: Fix protX to allow memory in the middle operand.
394 * i386-tbl.h: Regenerate from i386-opc.tbl.
8944f3c2 395
19a6653c
AM		 3962008-04-14 Edmar Wienskoski <edmar@freescale.com>
397
398 * ppc-dis.c (powerpc_dialect): Handle "e500mc". Extend "e500" to
399 accept Power E500MC instructions.
400 (print_ppc_disassembler_options): Document -Me500mc.
401 * ppc-opc.c (DUIS, DUI, T): New.
402 (XRT, XRTRA): Likewise.
403 (E500MC): Likewise.
404 (powerpc_opcodes): Add new Power E500MC instructions.
405
112b7c50
AK		 4062008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
407
408 * s390-dis.c (init_disasm): Evaluate disassembler_options.
409 (print_s390_disassembler_options): New function.
410 * disassemble.c (disassembler_usage): Invoke
411 print_s390_disassembler_options.
412
7ff42648
AK		 4132008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
414
415 * s390-mkopc.c (insertExpandedMnemonic): Expand string sizes
416 of local variables used for mnemonic parsing: prefix, suffix and
417 number.
418
45a5551e
AK		 4192008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
420
421 * s390-mkopc.c (s390_cond_ext_format): Add back the mnemonic
422 extensions for conditional jumps (o, p, m, nz, z, nm, np, no).
423 (s390_crb_extensions): New extensions table.
424 (insertExpandedMnemonic): Handle '$' tag.
425 * s390-opc.txt: Remove conditional jump variants which can now
426 be expanded automatically.
427 Replace '*' tag with '$' in the compare and branch instructions.
428
06c8514a
L		 4292008-04-07 H.J. Lu <hongjiu.lu@intel.com>
430
431 * i386-dis.c (PREFIX_VEX_38XX): Add a tab.
432 (PREFIX_VEX_3AXX): Likewis.
433
b122c285
L		 4342008-04-07 H.J. Lu <hongjiu.lu@intel.com>
435
436 * i386-opc.tbl: Remove 4 extra blank lines.
437
594ab6a3
L		 4382008-04-04 H.J. Lu <hongjiu.lu@intel.com>
439
440 * i386-gen.c (cpu_flag_init): Replace CPU_CLMUL_FLAGS/CpuCLMUL
441 with CPU_PCLMUL_FLAGS/CpuPCLMUL.
442 (cpu_flags): Replace CpuCLMUL with CpuPCLMUL.
443 * i386-opc.tbl: Likewise.
444
445 * i386-opc.h (CpuCLMUL): Renamed to ...
446 (CpuPCLMUL): This.
447 (CpuFMA): Updated.
448 (i386_cpu_flags): Replace cpuclmul with cpupclmul.
449
450 * i386-init.h: Regenerated.
451
c0f3af97
L		 4522008-04-03 H.J. Lu <hongjiu.lu@intel.com>
453
454 * i386-dis.c (OP_E_register): New.
455 (OP_E_memory): Likewise.
456 (OP_VEX): Likewise.
457 (OP_EX_Vex): Likewise.
458 (OP_EX_VexW): Likewise.
459 (OP_XMM_Vex): Likewise.
460 (OP_XMM_VexW): Likewise.
461 (OP_REG_VexI4): Likewise.
462 (PCLMUL_Fixup): Likewise.
463 (VEXI4_Fixup): Likewise.
464 (VZERO_Fixup): Likewise.
465 (VCMP_Fixup): Likewise.
466 (VPERMIL2_Fixup): Likewise.
467 (rex_original): Likewise.
468 (rex_ignored): Likewise.
469 (Mxmm): Likewise.
470 (XMM): Likewise.
471 (EXxmm): Likewise.
472 (EXxmmq): Likewise.
473 (EXymmq): Likewise.
474 (Vex): Likewise.
475 (Vex128): Likewise.
476 (Vex256): Likewise.
477 (VexI4): Likewise.
478 (EXdVex): Likewise.
479 (EXqVex): Likewise.
480 (EXVexW): Likewise.
481 (EXdVexW): Likewise.
482 (EXqVexW): Likewise.
483 (XMVex): Likewise.
484 (XMVexW): Likewise.
485 (XMVexI4): Likewise.
486 (PCLMUL): Likewise.
487 (VZERO): Likewise.
488 (VCMP): Likewise.
489 (VPERMIL2): Likewise.
490 (xmm_mode): Likewise.
491 (xmmq_mode): Likewise.
492 (ymmq_mode): Likewise.
493 (vex_mode): Likewise.
494 (vex128_mode): Likewise.
495 (vex256_mode): Likewise.
496 (USE_VEX_C4_TABLE): Likewise.
497 (USE_VEX_C5_TABLE): Likewise.
498 (USE_VEX_LEN_TABLE): Likewise.
499 (VEX_C4_TABLE): Likewise.
500 (VEX_C5_TABLE): Likewise.
501 (VEX_LEN_TABLE): Likewise.
502 (REG_VEX_XX): Likewise.
503 (MOD_VEX_XXX): Likewise.
504 (PREFIX_0F38DB..PREFIX_0F38DF): Likewise.
505 (PREFIX_0F3A44): Likewise.
506 (PREFIX_0F3ADF): Likewise.
507 (PREFIX_VEX_XXX): Likewise.
508 (VEX_OF): Likewise.
509 (VEX_OF38): Likewise.
510 (VEX_OF3A): Likewise.
511 (VEX_LEN_XXX): Likewise.
512 (vex): Likewise.
513 (need_vex): Likewise.
514 (need_vex_reg): Likewise.
515 (vex_i4_done): Likewise.
516 (vex_table): Likewise.
517 (vex_len_table): Likewise.
518 (OP_REG_VexI4): Likewise.
519 (vex_cmp_op): Likewise.
520 (pclmul_op): Likewise.
521 (vpermil2_op): Likewise.
522 (m_mode): Updated.
523 (es_reg): Likewise.
524 (PREFIX_0F38F0): Likewise.
525 (PREFIX_0F3A60): Likewise.
526 (reg_table): Add REG_VEX_71...REG_VEX_73 and REG_VEX_AE.
527 (prefix_table): Add PREFIX_0F38DB..PREFIX_0F38DF, PREFIX_0F3ADF
528 and PREFIX_VEX_XXX entries.
529 (x86_64_table): Use VEX_C4_TABLE and VEX_C5_TABLE.
530 (three_byte_table): Use PREFIX_0F38DB..PREFIX_0F38DF and
531 PREFIX_0F3ADF.
532 (mod_table): Use VEX_C4_TABLE, VEX_C5_TABLE and VEX_LEN_TABLE.
533 Add MOD_VEX_XXX entries.
534 (ckprefix): Initialize rex_original and rex_ignored. Store the
535 REX byte in rex_original.
536 (get_valid_dis386): Handle the implicit prefix in VEX prefix
537 bytes and USE_VEX_LEN_TABLE/USE_VEX_C4_TABLE/USE_VEX_C5_TABLE.
538 (print_insn): Set need_vex/need_vex_reg/vex_i4_done to 0 before
539 calling get_valid_dis386. Use rex_original and rex_ignored when
540 printing out REX.
541 (putop): Handle "XY".
542 (intel_operand_size): Handle VEX, xmm_mode, xmmq_mode and
543 ymmq_mode.
544 (OP_E_extended): Updated to use OP_E_register and
545 OP_E_memory.
546 (OP_XMM): Handle VEX.
547 (OP_EX): Likewise.
548 (XMM_Fixup): Likewise.
549 (CMP_Fixup): Use ARRAY_SIZE.
550
551 * i386-gen.c (cpu_flag_init): Add CpuAES, CPU_CLMUL_FLAGS,
552 CPU_FMA_FLAGS and CPU_AVX_FLAGS.
553 (operand_type_init): Add OPERAND_TYPE_REGYMM and
554 OPERAND_TYPE_VEX_IMM4.
555 (cpu_flags): Add CpuAVX, CpuAES, CpuCLMUL and CpuFMA.
556 (opcode_modifiers): Add Implicit1stXmm0, Vex, Vex256, VexNDD,
557 VexNDS, VexW0, VexW1, Vex0F, Vex0F38, Vex0F3A, Vex3Sources,
558 VexImmExt and SSE2AVX.
559 (operand_types): Add RegYMM, Ymmword and Vex_Imm4.
560
561 * i386-opc.h (CpuAVX): New.
562 (CpuAES): Likewise.
563 (CpuCLMUL): Likewise.
564 (CpuFMA): Likewise.
565 (Vex): Likewise.
566 (Vex256): Likewise.
567 (VexNDS): Likewise.
568 (VexNDD): Likewise.
569 (VexW0): Likewise.
570 (VexW1): Likewise.
571 (Vex0F): Likewise.
572 (Vex0F38): Likewise.
573 (Vex0F3A): Likewise.
574 (Vex3Sources): Likewise.
575 (VexImmExt): Likewise.
576 (SSE2AVX): Likewise.
577 (RegYMM): Likewise.
578 (Ymmword): Likewise.
579 (Vex_Imm4): Likewise.
580 (Implicit1stXmm0): Likewise.
581 (CpuXsave): Updated.
582 (CpuLM): Likewise.
583 (ByteOkIntel): Likewise.
584 (OldGcc): Likewise.
585 (Control): Likewise.
586 (Unspecified): Likewise.
587 (OTMax): Likewise.
588 (i386_cpu_flags): Add cpuavx, cpuaes, cpuclmul and cpufma.
589 (i386_opcode_modifier): Add implicit1stxmm0, vex, vex256,
590 vexnds, vexndd, vexw0, vexw1, vex0f, vex0f38, vex0f3a,
591 vex3sources, veximmext and sse2avx.
592 (i386_operand_type): Add regymm, ymmword and vex_imm4.
593
594 * i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions.
595
596 * i386-reg.tbl: Add AVX registers, ymm0..ymm15.
597
598 * i386-init.h: Regenerated.
599 * i386-tbl.h: Likewise.
600
b21c9cb4
BS		 6012008-03-26 Bernd Schmidt <bernd.schmidt@analog.com>
602
603 From Robin Getz <robin.getz@analog.com>
604 * bfin-dis.c (bu32): Typedef.
605 (enum const_forms_t): Add c_uimm32 and c_huimm32.
606 (constant_formats[]): Add uimm32 and huimm16.
607 (fmtconst_val): New.
608 (uimm32): Define.
609 (huimm32): Define.
610 (imm16_val): Define.
611 (luimm16_val): Define.
612 (struct saved_state): Define.
613 (GREG, DPREG, DREG, PREG, SPREG, FPREG, IREG, MREG, BREG, LREG,
614 A0XREG, A0WREG, A1XREG, A1WREG,CCREG, LC0REG, LT0REG, LB0REG,
615 LC1REG, LT1REG, LB1REG, RETSREG, PCREG): Define.
616 (get_allreg): New.
617 (decode_LDIMMhalf_0): Print out the whole register value.
618
ee171c8f
BS		 619 From Jie Zhang <jie.zhang@analog.com>
620 * bfin-dis.c (decode_dsp32mac_0): Decode (IU) option for
621 multiply and multiply-accumulate to data register instruction.
622
086134ec
BS		 623 * bfin-dis.c: (c_uimm4s4d, c_imm5d, c_imm7d, c_imm16d, c_uimm16s4d,
624 c_imm32, c_huimm32e): Define.
625 (constant_formats): Add flags for printing decimal, leading spaces, and
626 exact symbols.
627 (comment, parallel): Add global flags in all disassembly.
628 (fmtconst): Take advantage of new flags, and print default in hex.
629 (fmtconst_val): Likewise.
630 (decode_macfunc): Be consistant with spaces, tabs, comments,
631 capitalization in disassembly, fix minor coding style issues.
632 (reg_names, amod0, amod1, amod0amod2, aligndir, get_allreg): Likewise.
633 (decode_ProgCtrl_0, decode_PushPopMultiple_0, decode_CCflag_0,
634 decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0,
635 decode_REGMV_0, decode_ALU2op_0, decode_PTR2op_0, decode_LOGI2op_0,
636 decode_COMP3op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
637 decode_LDSTpmod_0, decode_dagMODim_0, decode_dagMODik_0,
638 decode_dspLDST_0, decode_LDST_0, decode_LDSTiiFP_0, decode_LDSTii_0,
639 decode_LoopSetup_0, decode_LDIMMhalf_0, decode_CALLa_0,
640 decode_LDSTidxI_0, decode_linkage_0, decode_dsp32alu_0,
641 decode_dsp32shift_0, decode_dsp32shiftimm_0, decode_pseudodbg_assert_0,
642 _print_insn_bfin, print_insn_bfin): Likewise.
643
58c85be7
RW		 6442008-03-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
645
646 * aclocal.m4: Regenerate.
647 * configure: Likewise.
648 * Makefile.in: Likewise.
649
50e7d84b
AM		 6502008-03-13 Alan Modra <amodra@bigpond.net.au>
651
652 * Makefile.am: Run "make dep-am".
653 * Makefile.in: Regenerate.
654 * configure: Regenerate.
655
de866fcc
AM		 6562008-03-07 Alan Modra <amodra@bigpond.net.au>
657
658 * ppc-opc.c (powerpc_opcodes): Order and format.
659
28dbc079
L		 6602008-03-01 H.J. Lu <hongjiu.lu@intel.com>
661
662 * i386-opc.tbl: Allow 16-bit near indirect branches for x86-64.
663 * i386-tbl.h: Regenerated.
664
849830bd
L		 6652008-02-23 H.J. Lu <hongjiu.lu@intel.com>
666
667 * i386-opc.tbl: Disallow 16-bit near indirect branches for
668 x86-64.
669 * i386-tbl.h: Regenerated.
670
743ddb6b
JB		 6712008-02-21 Jan Beulich <jbeulich@novell.com>
672
673 * i386-opc.tbl: Allow Dword for far indirect call. Allow Dword
674 and Fword for far indirect jmp. Allow Reg16 and Word for near
675 indirect jmp on x86-64. Disallow Fword for lcall.
676 * i386-tbl.h: Re-generate.
677
796d5313
NC		 6782008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
679
680 * cr16-opc.c (cr16_num_optab): Defined
681
65da13b5
L		 6822008-02-16 H.J. Lu <hongjiu.lu@intel.com>
683
684 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_INOUTPORTREG.
685 * i386-init.h: Regenerated.
686
0e336180
NC		 6872008-02-14 Nick Clifton <nickc@redhat.com>
688
689 PR binutils/5524
690 * configure.in (SHARED_LIBADD): Select the correct host specific
691 file extension for shared libraries.
692 * configure: Regenerate.
693
b7240065
JB		 6942008-02-13 Jan Beulich <jbeulich@novell.com>
695
696 * i386-opc.h (RegFlat): New.
697 * i386-reg.tbl (flat): Add.
698 * i386-tbl.h: Re-generate.
699
34b772a6
JB		 7002008-02-13 Jan Beulich <jbeulich@novell.com>
701
702 * i386-dis.c (a_mode): New.
703 (cond_jump_mode): Adjust.
704 (Ma): Change to a_mode.
705 (intel_operand_size): Handle a_mode.
706 * i386-opc.tbl: Allow Dword and Qword for bound.
707 * i386-tbl.h: Re-generate.
708
a60de03c
JB		 7092008-02-13 Jan Beulich <jbeulich@novell.com>
710
711 * i386-gen.c (process_i386_registers): Process new fields.
712 * i386-opc.h (reg_entry): Shrink reg_flags and reg_num to
713 unsigned char. Add dw2_regnum and Dw2Inval.
714 * i386-reg.tbl: Provide initializers for dw2_regnum. Add pseudo
715 register names.
716 * i386-tbl.h: Re-generate.
717
f03fe4c1
L		 7182008-02-11 H.J. Lu <hongjiu.lu@intel.com>
719
4b6bc8eb 720 * i386-gen.c (cpu_flag_init): Add CPU_XSAVE_FLAGS.
f03fe4c1
L		 721 * i386-init.h: Updated.
722
475a2301
L		 7232008-02-11 H.J. Lu <hongjiu.lu@intel.com>
724
725 * i386-gen.c (cpu_flags): Add CpuXsave.
726
727 * i386-opc.h (CpuXsave): New.
4b6bc8eb 728 (CpuLM): Updated.
475a2301
L		 729 (i386_cpu_flags): Add cpuxsave.
730
731 * i386-dis.c (MOD_0FAE_REG_4): New.
732 (RM_0F01_REG_2): Likewise.
733 (MOD_0FAE_REG_5): Updated.
734 (RM_0F01_REG_3): Likewise.
735 (reg_table): Use MOD_0FAE_REG_4.
736 (mod_table): Use RM_0F01_REG_2. Add MOD_0FAE_REG_4. Updated
737 for xrstor.
738 (rm_table): Add RM_0F01_REG_2.
739
740 * i386-opc.tbl: Add xsave, xrstor, xgetbv and xsetbv.
741 * i386-init.h: Regenerated.
742 * i386-tbl.h: Likewise.
743
595785c6 7442008-02-11 Jan Beulich <jbeulich@novell.com>
041179fc 745
595785c6
JB		 746 * i386-opc.tbl: Remove Disp32S from CpuNo64 opcodes. Remove
747 Disp16 from Cpu64 non-jump opcodes (including loop and j?cxz).
748 * i386-tbl.h: Re-generate.
749
bb8541b9
L		 7502008-02-04 H.J. Lu <hongjiu.lu@intel.com>
751
752 PR 5715
753 * configure: Regenerated.
754
57b592a3
AN		 7552008-02-04 Adam Nemet <anemet@caviumnetworks.com>
756
757 * mips-dis.c: Update copyright.
758 (mips_arch_choices): Add Octeon.
759 * mips-opc.c: Update copyright.
760 (IOCT): New macro.
761 (mips_builtin_opcodes): Add Octeon instruction synciobdma.
762
930bb4cf
AM		 7632008-01-29 Alan Modra <amodra@bigpond.net.au>
764
765 * ppc-opc.c: Support optional L form mtmsr.
766
82c18208
L		 7672008-01-24 H.J. Lu <hongjiu.lu@intel.com>
768
769 * i386-dis.c (OP_E_extended): Handle r12 like rsp.
770
599121aa
L		 7712008-01-23 H.J. Lu <hongjiu.lu@intel.com>
772
773 * i386-gen.c (cpu_flag_init): Add CpuLM to CPU_GENERIC64_FLAGS.
774 * i386-init.h: Regenerated.
775
80098f51
TG		 7762008-01-23 Tristan Gingold <gingold@adacore.com>
777
778 * ia64-dis.c (print_insn_ia64): Display symbolic name of ar.fcr,
779 ar.eflag, ar.csd, ar.ssd, ar.cflg, ar.fsr, ar.fir and ar.fdr.
780
115c7c25
L		 7812008-01-22 H.J. Lu <hongjiu.lu@intel.com>
782
783 * i386-gen.c (cpu_flag_init): Remove CpuMMX2.
784 (cpu_flags): Likewise.
785
786 * i386-opc.h (CpuMMX2): Removed.
787 (CpuSSE): Updated.
788
789 * i386-opc.tbl: Replace CpuMMX2 with CpuSSE|Cpu3dnowA.
790 * i386-init.h: Regenerated.
791 * i386-tbl.h: Likewise.
792
6305a203
L		 7932008-01-22 H.J. Lu <hongjiu.lu@intel.com>
794
795 * i386-gen.c (cpu_flag_init): Add CPU_VMX_FLAGS and
796 CPU_SMX_FLAGS.
797 * i386-init.h: Regenerated.
798
fd07a1c8
L		 7992008-01-15 H.J. Lu <hongjiu.lu@intel.com>
800
801 * i386-opc.tbl: Use Qword on movddup.
802 * i386-tbl.h: Regenerated.
803
321fd21e
L		 8042008-01-15 H.J. Lu <hongjiu.lu@intel.com>
805
806 * i386-opc.tbl: Put back 16bit movsx/movzx for AT&T syntax.
807 * i386-tbl.h: Regenerated.
808
4ee52178
L		 8092008-01-15 H.J. Lu <hongjiu.lu@intel.com>
810
811 * i386-dis.c (Mx): New.
812 (PREFIX_0FC3): Likewise.
813 (PREFIX_0FC7_REG_6): Updated.
814 (dis386_twobyte): Use PREFIX_0FC3.
815 (prefix_table): Add PREFIX_0FC3. Use Mq on movntq and movntsd.
816 Use Mx on movntps, movntpd, movntdq and movntdqa. Use Md on
817 movntss.
818
5c07affc
L		 8192008-01-14 H.J. Lu <hongjiu.lu@intel.com>
820
821 * i386-gen.c (opcode_modifiers): Add IntelSyntax.
822 (operand_types): Add Mem.
823
824 * i386-opc.h (IntelSyntax): New.
825 * i386-opc.h (Mem): New.
826 (Byte): Updated.
827 (Opcode_Modifier_Max): Updated.
828 (i386_opcode_modifier): Add intelsyntax.
829 (i386_operand_type): Add mem.
830
831 * i386-opc.tbl: Remove Reg16 from movnti. Add sizes to more
832 instructions.
833
834 * i386-reg.tbl: Add size for accumulator.
835
836 * i386-init.h: Regenerated.
837 * i386-tbl.h: Likewise.
838
0d6a2f58
L		 8392008-01-13 H.J. Lu <hongjiu.lu@intel.com>
840
841 * i386-opc.h (Byte): Fix a typo.
842
7d5e4556
L		 8432008-01-12 H.J. Lu <hongjiu.lu@intel.com>
844
845 PR gas/5534
846 * i386-gen.c (operand_type_init): Add Dword to
847 OPERAND_TYPE_ACC32. Add Qword to OPERAND_TYPE_ACC64.
848 (opcode_modifiers): Remove CheckSize, Byte, Word, Dword,
849 Qword and Xmmword.
850 (operand_types): Add Byte, Word, Dword, Fword, Qword, Tbyte,
851 Xmmword, Unspecified and Anysize.
852 (set_bitfield): Make Mmword an alias of Qword. Make Oword
853 an alias of Xmmword.
854
855 * i386-opc.h (CheckSize): Removed.
856 (Byte): Updated.
857 (Word): Likewise.
858 (Dword): Likewise.
859 (Qword): Likewise.
860 (Xmmword): Likewise.
861 (FWait): Updated.
862 (OTMax): Likewise.
863 (i386_opcode_modifier): Remove checksize, byte, word, dword,
864 qword and xmmword.
865 (Fword): New.
866 (TBYTE): Likewise.
867 (Unspecified): Likewise.
868 (Anysize): Likewise.
869 (i386_operand_type): Add byte, word, dword, fword, qword,
870 tbyte xmmword, unspecified and anysize.
871
872 * i386-opc.tbl: Updated to use Byte, Word, Dword, Fword, Qword,
873 Tbyte, Xmmword, Unspecified and Anysize.
874
875 * i386-reg.tbl: Add size for accumulator.
876
877 * i386-init.h: Regenerated.
878 * i386-tbl.h: Likewise.
879
b5b1fc4f
L		 8802008-01-10 H.J. Lu <hongjiu.lu@intel.com>
881
882 * i386-dis.c (REG_0F0E): Renamed to REG_0F0D.
883 (REG_0F18): Updated.
884 (reg_table): Updated.
885 (dis386_twobyte): Updated. Use "nopQ" on 0x19 to 0x1e.
886 (twobyte_has_modrm): Set 1 for 0x19 to 0x1e.
887
50e8458f
L		 8882008-01-08 H.J. Lu <hongjiu.lu@intel.com>
889
890 * i386-gen.c (set_bitfield): Use fail () on error.
891
3d4d5afa
L		 8922008-01-08 H.J. Lu <hongjiu.lu@intel.com>
893
894 * i386-gen.c (lineno): New.
895 (filename): Likewise.
896 (set_bitfield): Report filename and line numer on error.
897 (process_i386_opcodes): Set filename and update lineno.
898 (process_i386_registers): Likewise.
899
e1d4d893
L		 9002008-01-05 H.J. Lu <hongjiu.lu@intel.com>
901
902 * i386-gen.c (opcode_modifiers): Rename IntelMnemonic to
903 ATTSyntax.
904
905 * i386-opc.h (IntelMnemonic): Renamed to ..
906 (ATTSyntax): This
907 (Opcode_Modifier_Max): Updated.
908 (i386_opcode_modifier): Remove intelmnemonic. Add attsyntax
909 and intelsyntax.
910
8944f3c2 911 * i386-opc.tbl: Remove IntelMnemonic and update with ATTSyntax
e1d4d893
L		 912 on fsub, fubp, fsubr, fsubrp, div, fdivp, fdivr and fdivrp.
913 * i386-tbl.h: Regenerated.
914
6f143e4d
L		 9152008-01-04 H.J. Lu <hongjiu.lu@intel.com>
916
917 * i386-gen.c: Update copyright to 2008.
918 * i386-opc.h: Likewise.
919 * i386-opc.tbl: Likewise.
920
921 * i386-init.h: Regenerated.
922 * i386-tbl.h: Likewise.
923
c6add537
L		 9242008-01-04 H.J. Lu <hongjiu.lu@intel.com>
925
926 * i386-opc.tbl: Add NoRex64 to extractps, movmskpd, movmskps,
927 pextrb, pextrw, pinsrb, pinsrw and pmovmskb.
928 * i386-tbl.h: Regenerated.
929
3629bb00
L		 9302008-01-03 H.J. Lu <hongjiu.lu@intel.com>
931
932 * i386-gen.c (cpu_flag_init): Remove CpuSSE4_1_Or_5 and
933 CpuSSE4_2_Or_ABM.
934 (cpu_flags): Likewise.
935
936 * i386-opc.h (CpuSSE4_1_Or_5): Removed.
937 (CpuSSE4_2_Or_ABM): Likewise.
938 (CpuLM): Updated.
939 (i386_cpu_flags): Remove cpusse4_1_or_5 and cpusse4_2_or_abm.
940
941 * i386-opc.tbl: Replace CpuSSE4_1_Or_5, CpuSSE4_2_Or_ABM and
942 Cpu686|CpuPadLock with CpuSSE4_1|CpuSSE5, CpuABM|CpuSSE4_2
943 and CpuPadLock, respectively.
944 * i386-init.h: Regenerated.
945 * i386-tbl.h: Likewise.
946
24995bd6
L		 9472008-01-03 H.J. Lu <hongjiu.lu@intel.com>
948
949 * i386-gen.c (opcode_modifiers): Remove No_xSuf.
950
951 * i386-opc.h (No_xSuf): Removed.
952 (CheckSize): Updated.
953
954 * i386-tbl.h: Regenerated.
955
e0329a22
L		 9562008-01-02 H.J. Lu <hongjiu.lu@intel.com>
957
958 * i386-gen.c (cpu_flag_init): Add CpuSSE4_2_Or_ABM to
959 CPU_AMDFAM10_FLAGS, CPU_SSE4_2_FLAGS, CpuABM and
960 CPU_SSE5_FLAGS.
961 (cpu_flags): Add CpuSSE4_2_Or_ABM.
962
963 * i386-opc.h (CpuSSE4_2_Or_ABM): New.
964 (CpuLM): Updated.
965 (i386_cpu_flags): Add cpusse4_2_or_abm.
966
967 * i386-opc.tbl: Use CpuSSE4_2_Or_ABM instead of
968 CpuABM|CpuSSE4_2 on popcnt.
969 * i386-init.h: Regenerated.
970 * i386-tbl.h: Likewise.
971
f2a9c676
L		 9722008-01-02 H.J. Lu <hongjiu.lu@intel.com>
973
974 * i386-opc.h: Update comments.
975
d978b5be
L		 9762008-01-02 H.J. Lu <hongjiu.lu@intel.com>
977
978 * i386-gen.c (opcode_modifiers): Use Qword instead of QWord.
979 * i386-opc.h: Likewise.
980 * i386-opc.tbl: Likewise.
981
582d5edd
L		 9822008-01-02 H.J. Lu <hongjiu.lu@intel.com>
983
984 PR gas/5534
985 * i386-gen.c (opcode_modifiers): Add No_xSuf, CheckSize,
986 Byte, Word, Dword, QWord and Xmmword.
987
988 * i386-opc.h (No_xSuf): New.
989 (CheckSize): Likewise.
990 (Byte): Likewise.
991 (Word): Likewise.
992 (Dword): Likewise.
993 (QWord): Likewise.
994 (Xmmword): Likewise.
995 (FWait): Updated.
996 (i386_opcode_modifier): Add No_xSuf, CheckSize, Byte, Word,
997 Dword, QWord and Xmmword.
998
999 * i386-opc.tbl: Add CheckSize|QWord to movq if IgnoreSize is
1000 used.
1001 * i386-tbl.h: Regenerated.
1002
3fe15143
MK		 10032008-01-02 Mark Kettenis <kettenis@gnu.org>
1004
1005 * m88k-dis.c (instructions): Fix fcvt.* instructions.
1006 From Miod Vallat.
1007
6c7ac64e 1008For older changes see ChangeLog-2007
252b5132
RH		 1009\f
1010Local Variables:
2f6d2f85
NC		 1011mode: change-log
1012left-margin: 8
1013fill-column: 74
252b5132
RH		 1014version-control: never
1015End:
GDB Binutils - Deliverables
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