2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
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12011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
2
3 * s390-opc.c: Replace S390_OPERAND_REG_EVEN with
4 S390_OPERAND_REG_PAIR. Fix INSTR_RRF_0UFEF instruction type.
5 * s390-opc.txt: Fix cxr instruction type.
6
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72011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
8
9 * s390-opc.c: Add new instruction types marking register pair
10 operands.
11 * s390-opc.txt: Match instructions having register pair operands
12 to the new instruction types.
13
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142011-05-19 Nick Clifton <nickc@redhat.com>
15
16 * v850-opc.c (cmpf.[sd]): Reverse the order of the reg1 and reg2
17 operands.
18
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192011-05-10 Quentin Neill <quentin.neill@amd.com>
20
21 * i386-gen.c (cpu_flag_init): Add new CPU_BDVER2_FLAGS.
22 * i386-init.h: Regenerated.
23
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242011-04-27 Nick Clifton <nickc@redhat.com>
25
26 * po/da.po: Updated Danish translation.
27
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282011-04-26 Anton Blanchard <anton@samba.org>
29
30 * ppc-opc.c: (powerpc_opcodes): Enable icswx for POWER7.
31
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322011-04-21 DJ Delorie <dj@redhat.com>
33
34 * rx-decode.opc (rx_decode_opcode): Set the syntax for multi-byte NOPs.
35 * rx-decode.c: Regenerate.
36
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372011-04-20 H.J. Lu <hongjiu.lu@intel.com>
38
39 * i386-init.h: Regenerated.
40
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412011-04-19 Quentin Neill <quentin.neill@amd.com>
42
43 * i386-gen.c (cpu_flag_init): Remove 3dnow and 3dnowa bits
44 from bdver1 flags.
45
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462011-04-13 Nick Clifton <nickc@redhat.com>
47
48 * v850-dis.c (disassemble): Always print a closing square brace if
49 an opening square brace was printed.
50
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512011-04-12 Nick Clifton <nickc@redhat.com>
52
53 PR binutils/12534
54 * arm-dis.c (thumb32_opcodes): Add %L suffix to LDRD and STRD insn
55 patterns.
56 (print_insn_thumb32): Handle %L.
57
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582011-04-11 Julian Brown <julian@codesourcery.com>
59
60 * arm-dis.c (psr_name): Fix typo for BASEPRI_MAX.
61 (print_insn_thumb32): Add APSR bitmask support.
62
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632011-04-07 Paul Carroll<pcarroll@codesourcery.com>
64
65 * arm-dis.c (print_insn): init vars moved into private_data structure.
66
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672011-03-24 Mike Frysinger <vapier@gentoo.org>
68
69 * bfin-dis.c (decode_dsp32mac_0): Move MM zeroing down to MAC0 logic.
70
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712011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
72
73 * avr-dis.c (avr_operand): Add opcode_str parameter. Check for
74 post-increment to support LPM Z+ instruction. Add support for 'E'
75 constraint for DES instruction.
76 (print_insn_avr): Adjust calls to avr_operand. Rename variable.
77
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782011-03-14 Richard Sandiford <richard.sandiford@linaro.org>
79
80 * arm-dis.c (get_sym_code_type): Treat STT_GNU_IFUNCs as code.
81
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822011-03-14 Richard Sandiford <richard.sandiford@linaro.org>
83
84 * arm-dis.c (get_sym_code_type): Don't check for STT_ARM_TFUNC.
85 Use branch types instead.
86 (print_insn): Likewise.
87
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882011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
89
90 * mips-opc.c (mips_builtin_opcodes): Correct register use
91 annotation of "alnv.ps".
92
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932011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
94
95 * mips-opc.c (mips_builtin_opcodes): Add "pref" macro.
96
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972011-02-22 Mike Frysinger <vapier@gentoo.org>
98
99 * bfin-dis.c (OUTS): Remove p NULL check and txt NUL check.
100
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1012011-02-22 Mike Frysinger <vapier@gentoo.org>
102
103 * bfin-dis.c (print_insn_bfin): Change outf->fprintf_func to OUTS.
104
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1052011-02-19 Mike Frysinger <vapier@gentoo.org>
106
107 * bfin-dis.c (saved_state): Mark static. Change a[01]x to ax[] and
108 a[01]w to aw[]. Delete ac0, ac0_copy, ac1, an, aq, av0, av0s, av1,
109 av1s, az, cc, v, v_copy, vs, rnd_mod, v_internal, pc, ticks, insts,
110 exception, end_of_registers, msize, memory, bfd_mach.
111 (CCREG, PCREG, A0XREG, A0WREG, A1XREG, A1WREG, LC0REG, LT0REG,
112 LB0REG, LC1REG, LT1REG, LB1REG): Delete
113 (AXREG, AWREG, LCREG, LTREG, LBREG): Define.
114 (get_allreg): Change to new defines. Fallback to abort().
115
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1162011-02-14 Mike Frysinger <vapier@gentoo.org>
117
118 * bfin-dis.c: Add whitespace/parenthesis where needed.
119
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1202011-02-14 Mike Frysinger <vapier@gentoo.org>
121
122 * bfin-dis.c (decode_LoopSetup_0): Return when reg is greater
123 than 7.
124
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1252011-02-13 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
126
127 * configure: Regenerate.
128
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1292011-02-13 Mike Frysinger <vapier@gentoo.org>
130
131 * bfin-dis.c (decode_dsp32alu_0): Fix typo with A1 reg.
132
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1332011-02-13 Mike Frysinger <vapier@gentoo.org>
134
135 * bfin-dis.c (decode_dsp32mult_0): Add 1 to dst for mac1. Output
136 dregs only when P is set, and dregs_lo otherwise.
137
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1382011-02-13 Mike Frysinger <vapier@gentoo.org>
139
140 * bfin-dis.c (decode_dsp32alu_0): Delete BYTEOP2M code.
141
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1422011-02-12 Mike Frysinger <vapier@gentoo.org>
143
144 * bfin-dis.c (decode_pseudoDEBUG_0): Add space after PRNT.
145
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1462011-02-12 Mike Frysinger <vapier@gentoo.org>
147
148 * bfin-dis.c (machine_registers): Delete REG_GP.
149 (reg_names): Delete "GP".
150 (decode_allregs): Change REG_GP to REG_LASTREG.
151
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1522011-02-12 Mike Frysinger <vapier@gentoo.org>
153
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154 * bfin-dis.c (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2,
155 M_IH, M_IU): Delete.
26bb3ddd 156
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1572011-02-11 Mike Frysinger <vapier@gentoo.org>
158
159 * bfin-dis.c (reg_names): Add const.
160 (decode_dregs_lo, decode_dregs_hi, decode_dregs, decode_dregs_byte,
161 decode_pregs, decode_iregs, decode_mregs, decode_dpregs, decode_gregs,
162 decode_regs, decode_regs_lo, decode_regs_hi, decode_statbits,
163 decode_counters, decode_allregs): Likewise.
164
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1652011-02-09 Michael Snyder <msnyder@vmware.com>
166
167 * i386-dis.c (OP_J): Parenthesize expression to prevent
168 truncated addresses.
169 (print_insn): Fix indentation off-by-one.
170
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1712011-02-01 Nick Clifton <nickc@redhat.com>
172
173 * po/da.po: Updated Danish translation.
174
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1752011-01-21 Dave Murphy <davem@devkitpro.org>
176
177 * ppc-opc.c (NON32, NO371): Remove PPC_OPCODE_PPCPS.
178
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1792011-01-18 H.J. Lu <hongjiu.lu@intel.com>
180
181 * i386-dis.c (sIbT): New.
182 (b_T_mode): Likewise.
183 (dis386): Replace sIb with sIbT on "pushT".
184 (x86_64_table): Replace sIb with Ib on "aam" and "aad".
185 (OP_sI): Handle b_T_mode. Properly sign-extend byte.
186
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1872011-01-18 Jan Kratochvil <jan.kratochvil@redhat.com>
188
189 * i386-init.h: Regenerated.
190 * i386-tbl.h: Regenerated
191
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1922011-01-17 Quentin Neill <quentin.neill@amd.com>
193
194 * i386-dis.c (REG_XOP_TBM_01): New.
195 (REG_XOP_TBM_02): New.
196 (reg_table): Add REG_XOP_TBM_01 and REG_XOP_TBM_02 tables.
197 (xop_table): Redirect to REG_XOP_TBM_01 and REG_XOP_TBM_02
198 entries, and add bextr instruction.
199
200 * i386-gen.c (cpu_flag_init): Add CPU_TBM_FLAGS, CpuTBM.
201 (cpu_flags): Add CpuTBM.
202
203 * i386-opc.h (CpuTBM) New.
204 (i386_cpu_flags): Add bit cputbm.
205
206 * i386-opc.tbl: Add bextr, blcfill, blci, blcic, blcmsk,
207 blcs, blsfill, blsic, t1mskc, and tzmsk.
208
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2092011-01-12 DJ Delorie <dj@redhat.com>
210
211 * rx-dis.c (print_insn_rx): Support RX_Operand_TwoReg.
212
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2132011-01-11 Mingjie Xing <mingjie.xing@gmail.com>
214
215 * mips-dis.c (print_insn_args): Adjust the value to print the real
216 offset for "+c" argument.
217
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2182011-01-10 Nick Clifton <nickc@redhat.com>
219
220 * po/da.po: Updated Danish translation.
221
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2222011-01-05 Nathan Sidwell <nathan@codesourcery.com>
223
224 * arm-dis.c (thumb32_opcodes): BLX must have bit zero clear.
225
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2262011-01-04 H.J. Lu <hongjiu.lu@intel.com>
227
228 * i386-dis.c (REG_VEX_38F3): New.
229 (PREFIX_0FBC): Likewise.
230 (PREFIX_VEX_38F2): Likewise.
231 (PREFIX_VEX_38F3_REG_1): Likewise.
232 (PREFIX_VEX_38F3_REG_2): Likewise.
233 (PREFIX_VEX_38F3_REG_3): Likewise.
234 (PREFIX_VEX_38F7): Likewise.
235 (VEX_LEN_38F2_P_0): Likewise.
236 (VEX_LEN_38F3_R_1_P_0): Likewise.
237 (VEX_LEN_38F3_R_2_P_0): Likewise.
238 (VEX_LEN_38F3_R_3_P_0): Likewise.
239 (VEX_LEN_38F7_P_0): Likewise.
240 (dis386_twobyte): Use PREFIX_0FBC.
241 (reg_table): Add REG_VEX_38F3.
242 (prefix_table): Add PREFIX_0FBC, PREFIX_VEX_38F2,
243 PREFIX_VEX_38F3_REG_1, PREFIX_VEX_38F3_REG_2,
244 PREFIX_VEX_38F3_REG_3 and PREFIX_VEX_38F7.
245 (vex_table): Use PREFIX_VEX_38F2, REG_VEX_38F3 and
246 PREFIX_VEX_38F7.
247 (vex_len_table): Add VEX_LEN_38F2_P_0, VEX_LEN_38F3_R_1_P_0,
248 VEX_LEN_38F3_R_2_P_0, VEX_LEN_38F3_R_3_P_0 and
249 VEX_LEN_38F7_P_0.
250
251 * i386-gen.c (cpu_flag_init): Add CPU_BMI_FLAGS.
252 (cpu_flags): Add CpuBMI.
253
254 * i386-opc.h (CpuBMI): New.
255 (i386_cpu_flags): Add cpubmi.
256
257 * i386-opc.tbl: Add andn, bextr, blsi, blsmsk, blsr and tzcnt.
258 * i386-init.h: Regenerated.
259 * i386-tbl.h: Likewise.
260
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2612011-01-04 H.J. Lu <hongjiu.lu@intel.com>
262
263 * i386-dis.c (VexGdq): New.
264 (OP_VEX): Handle dq_mode.
265
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2662011-01-01 H.J. Lu <hongjiu.lu@intel.com>
267
268 * i386-gen.c (process_copyright): Update copyright to 2011.
269
9e9e0820 270For older changes see ChangeLog-2010
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273mode: change-log
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275fill-column: 74
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