x86: VCVTNEPS2BF16{X,Y} should permit broadcasting
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
c906a69a
JB
12020-01-21 Jan Beulich <jbeulich@suse.com>
2
3 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
4 Dword.
5 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
6 * i386-tbl.h: Re-generate.
7
26916852
NC
82020-01-20 Nick Clifton <nickc@redhat.com>
9
10 * po/de.po: Updated German translation.
11 * po/pt_BR.po: Updated Brazilian Portuguese translation.
12 * po/uk.po: Updated Ukranian translation.
13
4d6cbb64
AM
142020-01-20 Alan Modra <amodra@gmail.com>
15
16 * hppa-dis.c (fput_const): Remove useless cast.
17
2bddb71a
AM
182020-01-20 Alan Modra <amodra@gmail.com>
19
20 * arm-dis.c (print_insn_arm): Wrap 'T' value.
21
1b1bb2c6
NC
222020-01-18 Nick Clifton <nickc@redhat.com>
23
24 * configure: Regenerate.
25 * po/opcodes.pot: Regenerate.
26
ae774686
NC
272020-01-18 Nick Clifton <nickc@redhat.com>
28
29 Binutils 2.34 branch created.
30
07f1f3aa
CB
312020-01-17 Christian Biesinger <cbiesinger@google.com>
32
33 * opintl.h: Fix spelling error (seperate).
34
42e04b36
L
352020-01-17 H.J. Lu <hongjiu.lu@intel.com>
36
37 * i386-opc.tbl: Add {vex} pseudo prefix.
38 * i386-tbl.h: Regenerated.
39
2da2eaf4
AV
402020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
41
42 PR 25376
43 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
44 (neon_opcodes): Likewise.
45 (select_arm_features): Make sure we enable MVE bits when selecting
46 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
47 any architecture.
48
d0849eed
JB
492020-01-16 Jan Beulich <jbeulich@suse.com>
50
51 * i386-opc.tbl: Drop stale comment from XOP section.
52
9cf70a44
JB
532020-01-16 Jan Beulich <jbeulich@suse.com>
54
55 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
56 (extractps): Add VexWIG to SSE2AVX forms.
57 * i386-tbl.h: Re-generate.
58
4814632e
JB
592020-01-16 Jan Beulich <jbeulich@suse.com>
60
61 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
62 Size64 from and use VexW1 on SSE2AVX forms.
63 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
64 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
65 * i386-tbl.h: Re-generate.
66
aad09917
AM
672020-01-15 Alan Modra <amodra@gmail.com>
68
69 * tic4x-dis.c (tic4x_version): Make unsigned long.
70 (optab, optab_special, registernames): New file scope vars.
71 (tic4x_print_register): Set up registernames rather than
72 malloc'd registertable.
73 (tic4x_disassemble): Delete optable and optable_special. Use
74 optab and optab_special instead. Throw away old optab,
75 optab_special and registernames when info->mach changes.
76
7a6bf3be
SB
772020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
78
79 PR 25377
80 * z80-dis.c (suffix): Use .db instruction to generate double
81 prefix.
82
ca1eaac0
AM
832020-01-14 Alan Modra <amodra@gmail.com>
84
85 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
86 values to unsigned before shifting.
87
1d67fe3b
TT
882020-01-13 Thomas Troeger <tstroege@gmx.de>
89
90 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
91 flow instructions.
92 (print_insn_thumb16, print_insn_thumb32): Likewise.
93 (print_insn): Initialize the insn info.
94 * i386-dis.c (print_insn): Initialize the insn info fields, and
95 detect jumps.
96
5e4f7e05
CZ
972012-01-13 Claudiu Zissulescu <claziss@gmail.com>
98
99 * arc-opc.c (C_NE): Make it required.
100
b9fe6b8a
CZ
1012012-01-13 Claudiu Zissulescu <claziss@gmail.com>
102
103 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
104 reserved register name.
105
90dee485
AM
1062020-01-13 Alan Modra <amodra@gmail.com>
107
108 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
109 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
110
febda64f
AM
1112020-01-13 Alan Modra <amodra@gmail.com>
112
113 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
114 result of wasm_read_leb128 in a uint64_t and check that bits
115 are not lost when copying to other locals. Use uint32_t for
116 most locals. Use PRId64 when printing int64_t.
117
df08b588
AM
1182020-01-13 Alan Modra <amodra@gmail.com>
119
120 * score-dis.c: Formatting.
121 * score7-dis.c: Formatting.
122
b2c759ce
AM
1232020-01-13 Alan Modra <amodra@gmail.com>
124
125 * score-dis.c (print_insn_score48): Use unsigned variables for
126 unsigned values. Don't left shift negative values.
127 (print_insn_score32): Likewise.
128 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
129
5496abe1
AM
1302020-01-13 Alan Modra <amodra@gmail.com>
131
132 * tic4x-dis.c (tic4x_print_register): Remove dead code.
133
202e762b
AM
1342020-01-13 Alan Modra <amodra@gmail.com>
135
136 * fr30-ibld.c: Regenerate.
137
7ef412cf
AM
1382020-01-13 Alan Modra <amodra@gmail.com>
139
140 * xgate-dis.c (print_insn): Don't left shift signed value.
141 (ripBits): Formatting, use 1u.
142
7f578b95
AM
1432020-01-10 Alan Modra <amodra@gmail.com>
144
145 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
146 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
147
441af85b
AM
1482020-01-10 Alan Modra <amodra@gmail.com>
149
150 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
151 and XRREG value earlier to avoid a shift with negative exponent.
152 * m10200-dis.c (disassemble): Similarly.
153
bce58db4
NC
1542020-01-09 Nick Clifton <nickc@redhat.com>
155
156 PR 25224
157 * z80-dis.c (ld_ii_ii): Use correct cast.
158
40c75bc8
SB
1592020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
160
161 PR 25224
162 * z80-dis.c (ld_ii_ii): Use character constant when checking
163 opcode byte value.
164
d835a58b
JB
1652020-01-09 Jan Beulich <jbeulich@suse.com>
166
167 * i386-dis.c (SEP_Fixup): New.
168 (SEP): Define.
169 (dis386_twobyte): Use it for sysenter/sysexit.
170 (enum x86_64_isa): Change amd64 enumerator to value 1.
171 (OP_J): Compare isa64 against intel64 instead of amd64.
172 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
173 forms.
174 * i386-tbl.h: Re-generate.
175
030a2e78
AM
1762020-01-08 Alan Modra <amodra@gmail.com>
177
178 * z8k-dis.c: Include libiberty.h
179 (instr_data_s): Make max_fetched unsigned.
180 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
181 Don't exceed byte_info bounds.
182 (output_instr): Make num_bytes unsigned.
183 (unpack_instr): Likewise for nibl_count and loop.
184 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
185 idx unsigned.
186 * z8k-opc.h: Regenerate.
187
bb82aefe
SV
1882020-01-07 Shahab Vahedi <shahab@synopsys.com>
189
190 * arc-tbl.h (llock): Use 'LLOCK' as class.
191 (llockd): Likewise.
192 (scond): Use 'SCOND' as class.
193 (scondd): Likewise.
194 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
195 (scondd): Likewise.
196
cc6aa1a6
AM
1972020-01-06 Alan Modra <amodra@gmail.com>
198
199 * m32c-ibld.c: Regenerate.
200
660e62b1
AM
2012020-01-06 Alan Modra <amodra@gmail.com>
202
203 PR 25344
204 * z80-dis.c (suffix): Don't use a local struct buffer copy.
205 Peek at next byte to prevent recursion on repeated prefix bytes.
206 Ensure uninitialised "mybuf" is not accessed.
207 (print_insn_z80): Don't zero n_fetch and n_used here,..
208 (print_insn_z80_buf): ..do it here instead.
209
c9ae58fe
AM
2102020-01-04 Alan Modra <amodra@gmail.com>
211
212 * m32r-ibld.c: Regenerate.
213
5f57d4ec
AM
2142020-01-04 Alan Modra <amodra@gmail.com>
215
216 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
217
2c5c1196
AM
2182020-01-04 Alan Modra <amodra@gmail.com>
219
220 * crx-dis.c (match_opcode): Avoid shift left of signed value.
221
2e98c6c5
AM
2222020-01-04 Alan Modra <amodra@gmail.com>
223
224 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
225
567dfba2
JB
2262020-01-03 Jan Beulich <jbeulich@suse.com>
227
5437a02a
JB
228 * aarch64-tbl.h (aarch64_opcode_table): Use
229 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
230
2312020-01-03 Jan Beulich <jbeulich@suse.com>
232
233 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
567dfba2
JB
234 forms of SUDOT and USDOT.
235
8c45011a
JB
2362020-01-03 Jan Beulich <jbeulich@suse.com>
237
5437a02a 238 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
8c45011a
JB
239 uzip{1,2}.
240 * opcodes/aarch64-dis-2.c: Re-generate.
241
f4950f76
JB
2422020-01-03 Jan Beulich <jbeulich@suse.com>
243
5437a02a 244 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
f4950f76
JB
245 FMMLA encoding.
246 * opcodes/aarch64-dis-2.c: Re-generate.
247
6655dba2
SB
2482020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
249
250 * z80-dis.c: Add support for eZ80 and Z80 instructions.
251
b14ce8bf
AM
2522020-01-01 Alan Modra <amodra@gmail.com>
253
254 Update year range in copyright notice of all files.
255
0b114740 256For older changes see ChangeLog-2019
3499769a 257\f
0b114740 258Copyright (C) 2020 Free Software Foundation, Inc.
3499769a
AM
259
260Copying and distribution of this file, with or without modification,
261are permitted in any medium without royalty provided the copyright
262notice and this notice are preserved.
263
264Local Variables:
265mode: change-log
266left-margin: 8
267fill-column: 74
268version-control: never
269End:
This page took 0.237627 seconds and 4 git commands to generate.