projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Prevent address violation problem when disassembling corrupt aarch64 binary.
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
cd3ea7c6
NC		 12017-06-15 Nick Clifton <nickc@redhat.com>
2
3 PR binutils/21595
4 * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
5 range value.
6
63323b5b
NC		 72017-06-15 Nick Clifton <nickc@redhat.com>
8
9 PR binutils/21588
10 * rl78-decode.opc (OP_BUF_LEN): Define.
11 (GETBYTE): Check for the index exceeding OP_BUF_LEN.
12 (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
13 array.
14 * rl78-decode.c: Regenerate.
15
08c7881b
NC		 162017-06-15 Nick Clifton <nickc@redhat.com>
17
18 PR binutils/21586
19 * bfin-dis.c (gregs): Clip index to prevent overflow.
20 (regs): Likewise.
21 (regs_lo): Likewise.
22 (regs_hi): Likewise.
23
e64519d1
NC		 242017-06-14 Nick Clifton <nickc@redhat.com>
25
26 PR binutils/21576
27 * score7-dis.c (score_opcodes): Add sentinel.
28
6394c606
YQ		 292017-06-14 Yao Qi <yao.qi@linaro.org>
30
31 * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
32 * arm-dis.c: Likewise.
33 * ia64-dis.c: Likewise.
34 * mips-dis.c: Likewise.
35 * spu-dis.c: Likewise.
36 * disassemble.h (print_insn_aarch64): New declaration, moved from
37 include/dis-asm.h.
38 (print_insn_big_arm, print_insn_big_mips): Likewise.
39 (print_insn_i386, print_insn_ia64): Likewise.
40 (print_insn_little_arm, print_insn_little_mips): Likewise.
41
db5fa770
NC		 422017-06-14 Nick Clifton <nickc@redhat.com>
43
44 PR binutils/21587
45 * rx-decode.opc: Include libiberty.h
46 (GET_SCALE): New macro - validates access to SCALE array.
47 (GET_PSCALE): New macro - validates access to PSCALE array.
48 (DIs, SIs, S2Is, rx_disp): Use new macros.
49 * rx-decode.c: Regenerate.
50
05c966f3
AV		 512017-07-14 Andre Vieira <andre.simoesdiasvieira@arm.com>
52
53 * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
54
10045478
AK		 552017-05-30 Anton Kolesov <anton.kolesov@synopsys.com>
56
57 * arc-dis.c (enforced_isa_mask): Declare.
58 (cpu_types): Likewise.
59 (parse_cpu_option): New function.
60 (parse_disassembler_options): Use it.
61 (print_insn_arc): Use enforced_isa_mask.
62 (print_arc_disassembler_options): Document new options.
63
88c1242d
YQ		 642017-05-24 Yao Qi <yao.qi@linaro.org>
65
66 * alpha-dis.c: Include disassemble.h, don't include
67 dis-asm.h.
68 * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
69 * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
70 * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
71 * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
72 * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
73 * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
74 * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
75 * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
76 * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
77 * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
78 * moxie-dis.c, msp430-dis.c, mt-dis.c:
79 * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
80 * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
81 * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
82 * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
83 * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
84 * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
85 * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
86 * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
87 * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
88 * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
89 * z80-dis.c, z8k-dis.c: Likewise.
90 * disassemble.h: New file.
91
ab20fa4a
YQ		 922017-05-24 Yao Qi <yao.qi@linaro.org>
93
94 * rl78-dis.c (rl78_get_disassembler): If parameter abfd
95 is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
96
003ca0fd
YQ		 972017-05-24 Yao Qi <yao.qi@linaro.org>
98
99 * disassemble.c (disassembler): Add arguments a, big and mach.
100 Use them.
101
04ef582a
L		 1022017-05-22 H.J. Lu <hongjiu.lu@intel.com>
103
104 * i386-dis.c (NOTRACK_Fixup): New.
105 (NOTRACK): Likewise.
106 (NOTRACK_PREFIX): Likewise.
107 (last_active_prefix): Likewise.
108 (reg_table): Use NOTRACK on indirect call and jmp.
109 (ckprefix): Set last_active_prefix.
110 (prefix_name): Return "notrack" for NOTRACK_PREFIX.
111 * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
112 * i386-opc.h (NoTrackPrefixOk): New.
113 (i386_opcode_modifier): Add notrackprefixok.
114 * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
115 Add notrack.
116 * i386-tbl.h: Regenerated.
117
64517994
JM		 1182017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
119
120 * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
121 (X_IMM2): Define.
122 (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
123 bfd_mach_sparc_v9m8.
124 (print_insn_sparc): Handle new operand types.
125 * sparc-opc.c (MASK_M8): Define.
126 (v6): Add MASK_M8.
127 (v6notlet): Likewise.
128 (v7): Likewise.
129 (v8): Likewise.
130 (v9): Likewise.
131 (v9a): Likewise.
132 (v9b): Likewise.
133 (v9c): Likewise.
134 (v9d): Likewise.
135 (v9e): Likewise.
136 (v9v): Likewise.
137 (v9m): Likewise.
138 (v9andleon): Likewise.
139 (m8): Define.
140 (HWS_VM8): Define.
141 (HWS2_VM8): Likewise.
142 (sparc_opcode_archs): Add entry for "m8".
143 (sparc_opcodes): Add OSA2017 and M8 instructions
144 dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
145 fpx{ll,ra,rl}64x,
146 ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
147 ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
148 revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
149 stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
150 (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
151 ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
152 ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
153 ASI_CORE_SELECT_COMMIT_NHT.
154
535b785f
AM		 1552017-05-18 Alan Modra <amodra@gmail.com>
156
157 * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
158 * aarch64-dis.c: Likewise.
159 * aarch64-gen.c: Likewise.
160 * aarch64-opc.c: Likewise.
161
25499ac7
MR		 1622017-05-15 Maciej W. Rozycki <macro@imgtec.com>
163 Matthew Fortune <matthew.fortune@imgtec.com>
164
165 * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
166 ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
167 (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
168 (print_insn_arg) <OP_REG28>: Add handler.
169 (validate_insn_args) <OP_REG28>: Handle.
170 (print_mips16_insn_arg): Handle MIPS16 instructions that require
171 32-bit encoding and 9-bit immediates.
172 (print_insn_mips16): Handle MIPS16 instructions that require
173 32-bit encoding and MFC0/MTC0 operand decoding.
174 * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
175 <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
176 (RD_C0, WR_C0, E2, E2MT): New macros.
177 (mips16_opcodes): Add entries for MIPS16e2 instructions:
178 GP-relative "addiu" and its "addu" spelling, "andi", "cache",
179 "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
180 "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
181 "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
182 "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
183 instructions, "swl", "swr", "sync" and its "sync_acquire",
184 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
185 "xori", "dmt", "dvpe", "emt" and "evpe". Add split
186 regular/extended entries for original MIPS16 ISA revision
187 instructions whose extended forms are subdecoded in the MIPS16e2
188 ISA revision: "li", "sll" and "srl".
189
fdfb4752
MR		 1902017-05-15 Maciej W. Rozycki <macro@imgtec.com>
191
192 * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
193 reference in CP0 move operand decoding.
194
a4f89915
MR		 1952017-05-12 Maciej W. Rozycki <macro@imgtec.com>
196
197 * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
198 type to hexadecimal.
199 (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
200
99e2d67a
MR		 2012017-05-11 Maciej W. Rozycki <macro@imgtec.com>
202
203 * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
204 "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
205 "sync_rmb" and "sync_wmb" as aliases.
206 * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
207 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
208
53a346d8
CZ		 2092017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
210
211 * arc-dis.c (parse_option): Update quarkse_em option..
212 * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
213 QUARKSE1.
214 (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
215
f91d48de
KC		 2162017-05-03 Kito Cheng <kito.cheng@gmail.com>
217
218 * riscv-dis.c (print_insn_args): Handle 'Co' operands.
219
43e379d7
MC		 2202017-05-01 Michael Clark <michaeljclark@mac.com>
221
222 * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
223 register.
224
a4ddc54e
MR		 2252017-05-02 Maciej W. Rozycki <macro@imgtec.com>
226
227 * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
228 and branches and not synthetic data instructions.
229
fe50e98c
BE		 2302017-05-02 Bernd Edlinger <bernd.edlinger@hotmail.de>
231
232 * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
233
126124cc
CZ		 2342017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
235
236 * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
237 * arc-opc.c (insert_r13el): New function.
238 (R13_EL): Define.
239 * arc-tbl.h: Add new enter/leave variants.
240
be6a24d8
CZ		 2412017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
242
243 * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
244
0348fd79
MR		 2452017-04-25 Maciej W. Rozycki <macro@imgtec.com>
246
247 * mips-dis.c (print_mips_disassembler_options): Add
248 `no-aliases'.
249
6e3d1f07
MR		 2502017-04-25 Maciej W. Rozycki <macro@imgtec.com>
251
252 * mips16-opc.c (AL): New macro.
253 (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
254 of "ld" and "lw" as aliases.
255
957f6b39
TC		 2562017-04-24 Tamar Christina <tamar.christina@arm.com>
257
258 * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
259 arguments.
260
a8cc8a54
AM		 2612017-04-22 Alexander Fedotov <alfedotov@gmail.com>
262 Alan Modra <amodra@gmail.com>
263
264 * ppc-opc.c (ELEV): Define.
265 (vle_opcodes): Add se_rfgi and e_sc.
266 (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
267 for E200Z4.
268
3ab87b68
JM		 2692017-04-21 Jose E. Marchesi <jose.marchesi@oracle.com>
270
271 * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
272
792f174f
NC		 2732017-04-21 Nick Clifton <nickc@redhat.com>
274
275 PR binutils/21380
276 * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
277 LD3R and LD4R.
278
42742084
AM		 2792017-04-13 Alan Modra <amodra@gmail.com>
280
281 * epiphany-desc.c: Regenerate.
282 * fr30-desc.c: Regenerate.
283 * frv-desc.c: Regenerate.
284 * ip2k-desc.c: Regenerate.
285 * iq2000-desc.c: Regenerate.
286 * lm32-desc.c: Regenerate.
287 * m32c-desc.c: Regenerate.
288 * m32r-desc.c: Regenerate.
289 * mep-desc.c: Regenerate.
290 * mt-desc.c: Regenerate.
291 * or1k-desc.c: Regenerate.
292 * xc16x-desc.c: Regenerate.
293 * xstormy16-desc.c: Regenerate.
294
9a85b496
AM		 2952017-04-11 Alan Modra <amodra@gmail.com>
296
ef85eab0 297 * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
c03dc33b
AM		 298 PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm". Formatting. Set
299 PPC_OPCODE_TMR for e6500.
9a85b496
AM		 300 * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
301 (PPCVEC3): Define as PPC_OPCODE_POWER9.
9570835e
AM		 302 (PPCVSX2): Define as PPC_OPCODE_POWER8.
303 (PPCVSX3): Define as PPC_OPCODE_POWER9.
ef85eab0 304 (PPCHTM): Define as PPC_OPCODE_POWER8.
c03dc33b 305 (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
9a85b496 306
62adc510
AM		 3072017-04-10 Alan Modra <amodra@gmail.com>
308
309 * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
310 * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
311 (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
312 removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
313
aa808707
PC		 3142017-04-09 Pip Cet <pipcet@gmail.com>
315
316 * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
317 appropriate floating-point precision directly.
318
ac8f0f72
AM		 3192017-04-07 Alan Modra <amodra@gmail.com>
320
321 * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
322 lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
323 lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
324 lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
325 vector instructions with E6500 not PPCVEC2.
326
62ecb94c
PC		 3272017-04-06 Pip Cet <pipcet@gmail.com>
328
329 * Makefile.am: Add wasm32-dis.c.
330 * configure.ac: Add wasm32-dis.c to wasm32 target.
331 * disassemble.c: Add wasm32 disassembler code.
332 * wasm32-dis.c: New file.
333 * Makefile.in: Regenerate.
334 * configure: Regenerate.
335 * po/POTFILES.in: Regenerate.
336 * po/opcodes.pot: Regenerate.
337
f995bbe8
PA		 3382017-04-05 Pedro Alves <palves@redhat.com>
339
340 * arc-dis.c (parse_option, parse_disassembler_options): Constify.
341 * arm-dis.c (parse_arm_disassembler_options): Constify.
342 * ppc-dis.c (powerpc_init_dialect): Constify local.
343 * vax-dis.c (parse_disassembler_options): Constify.
344
b5292032
PD		 3452017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
346
347 * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
348 RISCV_GP_SYMBOL.
349
f96bd6c2
PC		 3502017-03-30 Pip Cet <pipcet@gmail.com>
351
352 * configure.ac: Add (empty) bfd_wasm32_arch target.
353 * configure: Regenerate
354 * po/opcodes.pot: Regenerate.
355
f7c514a3
JM		 3562017-03-29 Sheldon Lobo <sheldon.lobo@oracle.com>
357
358 Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
359 OSA2015.
360 * opcodes/sparc-opc.c (asi_table): New ASIs.
361
52be03fd
AM		 3622017-03-29 Alan Modra <amodra@gmail.com>
363
364 * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add
365 "raw" option.
366 (lookup_powerpc): Don't special case -1 dialect. Handle
367 PPC_OPCODE_RAW.
368 (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
369 lookup_powerpc call, pass it on second.
370
9b753937
AM		 3712017-03-27 Alan Modra <amodra@gmail.com>
372
373 PR 21303
374 * ppc-dis.c (struct ppc_mopt): Comment.
375 (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
376
c0c31e91
RZ		 3772017-03-27 Rinat Zelig <rinat@mellanox.com>
378
379 * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
380 * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
381 F_NPS_M, F_NPS_CORE, F_NPS_ALL.
382 (insert_nps_misc_imm_offset): New function.
383 (extract_nps_misc imm_offset): New function.
384 (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
385 (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
386
2253c8f0
AK		 3872017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
388
389 * s390-mkopc.c (main): Remove vx2 check.
390 * s390-opc.txt: Remove vx2 instruction flags.
391
645d3342
RZ		 3922017-03-21 Rinat Zelig <rinat@mellanox.com>
393
394 * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
395 * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
396 (insert_nps_imm_offset): New function.
397 (extract_nps_imm_offset): New function.
398 (insert_nps_imm_entry): New function.
399 (extract_nps_imm_entry): New function.
400
4b94dd2d
AM		 4012017-03-17 Alan Modra <amodra@gmail.com>
402
403 PR 21248
404 * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
405 mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after
406 those spr mnemonics they alias. Similarly for mtibatl, mtibatu.
407
b416fe87
KC		 4082017-03-14 Kito Cheng <kito.cheng@gmail.com>
409
410 * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
411 <c.andi>: Likewise.
412 <c.addiw> Likewise.
413
03b039a5
KC		 4142017-03-14 Kito Cheng <kito.cheng@gmail.com>
415
416 * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
417
2c232b83
AW		 4182017-03-13 Andrew Waterman <andrew@sifive.com>
419
420 * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
421 <srl> Likewise.
422 <srai> Likewise.
423 <sra> Likewise.
424
86fa6981
L		 4252017-03-09 H.J. Lu <hongjiu.lu@intel.com>
426
427 * i386-gen.c (opcode_modifiers): Replace S with Load.
428 * i386-opc.h (S): Removed.
429 (Load): New.
430 (i386_opcode_modifier): Replace s with load.
431 * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
432 and {evex}. Replace S with Load.
433 * i386-tbl.h: Regenerated.
434
c1fe188b
L		 4352017-03-09 H.J. Lu <hongjiu.lu@intel.com>
436
437 * i386-opc.tbl: Use CpuCET on rdsspq.
438 * i386-tbl.h: Regenerated.
439
4b8b687e
PB		 4402017-03-08 Peter Bergner <bergner@vnet.ibm.com>
441
442 * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
443 <vsx>: Do not use PPC_OPCODE_VSX3;
444
1437d063
PB		 4452017-03-08 Peter Bergner <bergner@vnet.ibm.com>
446
447 * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
448
603555e5
L		 4492017-03-06 H.J. Lu <hongjiu.lu@intel.com>
450
451 * i386-dis.c (REG_0F1E_MOD_3): New enum.
452 (MOD_0F1E_PREFIX_1): Likewise.
453 (MOD_0F38F5_PREFIX_2): Likewise.
454 (MOD_0F38F6_PREFIX_0): Likewise.
455 (RM_0F1E_MOD_3_REG_7): Likewise.
456 (PREFIX_MOD_0_0F01_REG_5): Likewise.
457 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
458 (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
459 (PREFIX_0F1E): Likewise.
460 (PREFIX_MOD_0_0FAE_REG_5): Likewise.
461 (PREFIX_0F38F5): Likewise.
462 (dis386_twobyte): Use PREFIX_0F1E.
463 (reg_table): Add REG_0F1E_MOD_3.
464 (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
465 PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
466 PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
467 PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
468 (three_byte_table): Use PREFIX_0F38F5.
469 (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
470 Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
471 (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
472 RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
473 PREFIX_MOD_3_0F01_REG_5_RM_2.
474 * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
475 (cpu_flags): Add CpuCET.
476 * i386-opc.h (CpuCET): New enum.
477 (CpuUnused): Commented out.
478 (i386_cpu_flags): Add cpucet.
479 * i386-opc.tbl: Add Intel CET instructions.
480 * i386-init.h: Regenerated.
481 * i386-tbl.h: Likewise.
482
73f07bff
AM		 4832017-03-06 Alan Modra <amodra@gmail.com>
484
485 PR 21124
486 * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
487 (extract_raq, extract_ras, extract_rbx): New functions.
488 (powerpc_operands): Use opposite corresponding insert function.
489 (Q_MASK): Define.
490 (powerpc_opcodes): Apply Q_MASK to all quad insns with even
491 register restriction.
492
65b48a81
PB		 4932017-02-28 Peter Bergner <bergner@vnet.ibm.com>
494
495 * disassemble.c Include "safe-ctype.h".
496 (disassemble_init_for_target): Handle s390 init.
497 (remove_whitespace_and_extra_commas): New function.
498 (disassembler_options_cmp): Likewise.
499 * arm-dis.c: Include "libiberty.h".
500 (NUM_ELEM): Delete.
501 (regnames): Use long disassembler style names.
502 Add force-thumb and no-force-thumb options.
503 (NUM_ARM_REGNAMES): Rename from this...
504 (NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE.
505 (get_arm_regname_num_options): Delete.
506 (set_arm_regname_option): Likewise.
507 (get_arm_regnames): Likewise.
508 (parse_disassembler_options): Likewise.
509 (parse_arm_disassembler_option): Rename from this...
510 (parse_arm_disassembler_options): ...to this. Make static.
511 Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
512 (print_insn): Use parse_arm_disassembler_options.
513 (disassembler_options_arm): New function.
514 (print_arm_disassembler_options): Handle updated regnames.
515 * ppc-dis.c: Include "libiberty.h".
516 (ppc_opts): Add "32" and "64" entries.
517 (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
518 (powerpc_init_dialect): Add break to switch statement.
519 Use new FOR_EACH_DISASSEMBLER_OPTION macro.
520 (disassembler_options_powerpc): New function.
521 (print_ppc_disassembler_options): Use ARRAY_SIZE.
522 Remove printing of "32" and "64".
523 * s390-dis.c: Include "libiberty.h".
524 (init_flag): Remove unneeded variable.
525 (struct s390_options_t): New structure type.
526 (options): New structure.
527 (init_disasm): Rename from this...
528 (disassemble_init_s390): ...to this. Add initializations for
529 current_arch_mask and option_use_insn_len_bits_p. Remove init_flag.
530 (print_insn_s390): Delete call to init_disasm.
531 (disassembler_options_s390): New function.
532 (print_s390_disassembler_options): Print using information from
533 struct 'options'.
534 * po/opcodes.pot: Regenerate.
535
15c7c1d8
JB		 5362017-02-28 Jan Beulich <jbeulich@suse.com>
537
538 * i386-dis.c (PCMPESTR_Fixup): New.
539 (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
540 (prefix_table): Use PCMPESTR_Fixup.
541 (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
542 PCMPESTR_Fixup.
543 (vex_w_table): Delete VPCMPESTR{I,M} entries.
544 * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
545 Split 64-bit and non-64-bit variants.
546 * opcodes/i386-tbl.h: Re-generate.
547
582e12bf
RS		 5482017-02-24 Richard Sandiford <richard.sandiford@arm.com>
549
550 * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
551 (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
552 (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
553 (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
554 (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
555 (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
556 (OP_SVE_V_HSD): New macros.
557 (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
558 (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
559 (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
560 (aarch64_opcode_table): Add new SVE instructions.
561 (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
562 for rotation operands. Add new SVE operands.
563 * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
564 (ins_sve_quad_index): Likewise.
565 (ins_imm_rotate): Split into...
566 (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
567 * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
568 (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
569 functions.
570 (aarch64_ins_sve_addr_ri_s4): New function.
571 (aarch64_ins_sve_quad_index): Likewise.
572 (do_misc_encoding): Handle "MOV Zn.Q, Qm".
573 * aarch64-asm-2.c: Regenerate.
574 * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
575 (ext_sve_quad_index): Likewise.
576 (ext_imm_rotate): Split into...
577 (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
578 * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
579 (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
580 functions.
581 (aarch64_ext_sve_addr_ri_s4): New function.
582 (aarch64_ext_sve_quad_index): Likewise.
583 (aarch64_ext_sve_index): Allow quad indices.
584 (do_misc_decoding): Likewise.
585 * aarch64-dis-2.c: Regenerate.
586 * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
587 aarch64_field_kinds.
588 (OPD_F_OD_MASK): Widen by one bit.
589 (OPD_F_NO_ZR): Bump accordingly.
590 (get_operand_field_width): New function.
591 * aarch64-opc.c (fields): Add new SVE fields.
592 (operand_general_constraint_met_p): Handle new SVE operands.
593 (aarch64_print_operand): Likewise.
594 * aarch64-opc-2.c: Regenerate.
595
f482d304
RS		 5962017-02-24 Richard Sandiford <richard.sandiford@arm.com>
597
598 * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
599 (aarch64_feature_compnum): ...this.
600 (SIMD_V8_3): Replace with...
601 (COMPNUM): ...this.
602 (CNUM_INSN): New macro.
603 (aarch64_opcode_table): Use it for the complex number instructions.
604
7db2c588
JB		 6052017-02-24 Jan Beulich <jbeulich@suse.com>
606
607 * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
608
1e9d41d4
SL		 6092017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
610
611 Add support for associating SPARC ASIs with an architecture level.
612 * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
613 * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
614 decoding of SPARC ASIs.
615
53c4d625
JB		 6162017-02-23 Jan Beulich <jbeulich@suse.com>
617
618 * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
619 82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
620
11648de5
JB		 6212017-02-21 Jan Beulich <jbeulich@suse.com>
622
623 * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
624 1 (instead of to itself). Correct typo.
625
f98d33be
AW		 6262017-02-14 Andrew Waterman <andrew@sifive.com>
627
628 * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
629 pseudoinstructions.
630
773fb663
RS		 6312017-02-15 Richard Sandiford <richard.sandiford@arm.com>
632
633 * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
634 (aarch64_sys_reg_supported_p): Handle them.
635
cc07cda6
CZ		 6362017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
637
638 * arc-opc.c (UIMM6_20R): Define.
639 (SIMM12_20): Use above.
640 (SIMM12_20R): Define.
641 (SIMM3_5_S): Use above.
642 (UIMM7_A32_11R_S): Define.
643 (UIMM7_9_S): Use above.
644 (UIMM3_13R_S): Define.
645 (SIMM11_A32_7_S): Use above.
646 (SIMM9_8R): Define.
647 (UIMM10_A32_8_S): Use above.
648 (UIMM8_8R_S): Define.
649 (W6): Use above.
650 (arc_relax_opcodes): Use all above defines.
651
66a5a740
VG		 6522017-02-15 Vineet Gupta <vgupta@synopsys.com>
653
654 * arc-regs.h: Distinguish some of the registers different on
655 ARC700 and HS38 cpus.
656
7e0de605
AM		 6572017-02-14 Alan Modra <amodra@gmail.com>
658
659 PR 21118
660 * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
661 with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
662
54064fdb
AM		 6632017-02-11 Stafford Horne <shorne@gmail.com>
664 Alan Modra <amodra@gmail.com>
665
666 * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
667 Use insn_bytes_value and insn_int_value directly instead. Don't
668 free allocated memory until function exit.
669
dce75bf9
NP		 6702017-02-10 Nicholas Piggin <npiggin@gmail.com>
671
672 * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
673
1b7e3d2f
NC		 6742017-02-03 Nick Clifton <nickc@redhat.com>
675
676 PR 21096
677 * aarch64-opc.c (print_register_list): Ensure that the register
678 list index will fir into the tb buffer.
679 (print_register_offset_address): Likewise.
680 * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
681
8ec5cf65
AD		 6822017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
683
684 PR 21056
685 * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
686 instructions when the previous fetch packet ends with a 32-bit
687 instruction.
688
a1aa5e81
DD		 6892017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
690
691 * pru-opc.c: Remove vague reference to a future GDB port.
692
add3afb2
NC		 6932017-01-20 Nick Clifton <nickc@redhat.com>
694
695 * po/ga.po: Updated Irish translation.
696
c13a63b0
SN		 6972017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
698
699 * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
700
9608051a
YQ		 7012017-01-13 Yao Qi <yao.qi@linaro.org>
702
703 * m68k-dis.c (match_insn_m68k): Extend comments. Return -1
704 if FETCH_DATA returns 0.
705 (m68k_scan_mask): Likewise.
706 (print_insn_m68k): Update code to handle -1 return value.
707
f622ea96
YQ		 7082017-01-13 Yao Qi <yao.qi@linaro.org>
709
710 * m68k-dis.c (enum print_insn_arg_error): New.
711 (NEXTBYTE): Replace -3 with
712 PRINT_INSN_ARG_MEMORY_ERROR.
713 (NEXTULONG): Likewise.
714 (NEXTSINGLE): Likewise.
715 (NEXTDOUBLE): Likewise.
716 (NEXTDOUBLE): Likewise.
717 (NEXTPACKED): Likewise.
718 (FETCH_ARG): Likewise.
719 (FETCH_DATA): Update comments.
720 (print_insn_arg): Update comments. Replace magic numbers with
721 enum.
722 (match_insn_m68k): Likewise.
723
620214f7
IT		 7242017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
725
726 * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
727 * i386-dis-evex.h (evex_table): Updated.
728 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
729 CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
730 (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
731 * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
732 (i386_cpu_flags): Add cpuavx512_vpopcntdq.
733 * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
734 * i386-init.h: Regenerate.
735 * i386-tbl.h: Ditto.
736
d95014a2
YQ		 7372017-01-12 Yao Qi <yao.qi@linaro.org>
738
739 * msp430-dis.c (msp430_singleoperand): Return -1 if
740 msp430dis_opcode_signed returns false.
741 (msp430_doubleoperand): Likewise.
742 (msp430_branchinstr): Return -1 if
743 msp430dis_opcode_unsigned returns false.
744 (msp430x_calla_instr): Likewise.
745 (print_insn_msp430): Likewise.
746
0ae60c3e
NC		 7472017-01-05 Nick Clifton <nickc@redhat.com>
748
749 PR 20946
750 * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
751 could not be matched.
752 (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
753 NULL.
754
d74d4880
SN		 7552017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
756
757 * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
758 (aarch64_opcode_table): Use RCPC_INSN.
759
cc917fd9
KC		 7602017-01-03 Kito Cheng <kito.cheng@gmail.com>
761
762 * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
763 extension.
764 * riscv-opcodes/all-opcodes: Likewise.
765
b52d3cfc
DP		 7662017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
767
768 * riscv-dis.c (print_insn_args): Add fall through comment.
769
f90c58d5
NC		 7702017-01-03 Nick Clifton <nickc@redhat.com>
771
772 * po/sr.po: New Serbian translation.
773 * configure.ac (ALL_LINGUAS): Add sr.
774 * configure: Regenerate.
775
f47b0d4a
AM		 7762017-01-02 Alan Modra <amodra@gmail.com>
777
778 * epiphany-desc.h: Regenerate.
779 * epiphany-opc.h: Regenerate.
780 * fr30-desc.h: Regenerate.
781 * fr30-opc.h: Regenerate.
782 * frv-desc.h: Regenerate.
783 * frv-opc.h: Regenerate.
784 * ip2k-desc.h: Regenerate.
785 * ip2k-opc.h: Regenerate.
786 * iq2000-desc.h: Regenerate.
787 * iq2000-opc.h: Regenerate.
788 * lm32-desc.h: Regenerate.
789 * lm32-opc.h: Regenerate.
790 * m32c-desc.h: Regenerate.
791 * m32c-opc.h: Regenerate.
792 * m32r-desc.h: Regenerate.
793 * m32r-opc.h: Regenerate.
794 * mep-desc.h: Regenerate.
795 * mep-opc.h: Regenerate.
796 * mt-desc.h: Regenerate.
797 * mt-opc.h: Regenerate.
798 * or1k-desc.h: Regenerate.
799 * or1k-opc.h: Regenerate.
800 * xc16x-desc.h: Regenerate.
801 * xc16x-opc.h: Regenerate.
802 * xstormy16-desc.h: Regenerate.
803 * xstormy16-opc.h: Regenerate.
804
2571583a
AM		 8052017-01-02 Alan Modra <amodra@gmail.com>
806
807 Update year range in copyright notice of all files.
808
5c1ad6b5 809For older changes see ChangeLog-2016
3499769a 810\f
5c1ad6b5 811Copyright (C) 2017 Free Software Foundation, Inc.
3499769a
AM		 812
813Copying and distribution of this file, with or without modification,
814are permitted in any medium without royalty provided the copyright
815notice and this notice are preserved.
816
817Local Variables:
818mode: change-log
819left-margin: 8
820fill-column: 74
821version-control: never
822End:
GDB Binutils - Deliverables
This page took 0.162973 seconds and 4 git commands to generate.