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* gdbint.texinfo (Raw and Virtual Register Representations): Fix
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
323ee3f4
AM		 12008-08-04 Alan Modra <amodra@bigpond.net.au>
2
3 * Makefile.am (POTFILES.in): Set LC_ALL=C.
4 * Makefile.in: Regenerate.
5 * po/POTFILES.in: Regenerate.
6
9b4e5766
PB		 72008-08-01 Peter Bergner <bergner@vnet.ibm.com>
8
9 * ppc-dis.c (powerpc_init_dialect): Handle power7 and vsx options.
10 (print_insn_powerpc): Prepend 'vs' when printing VSX registers.
11 (print_ppc_disassembler_options): Document -Mpower7 and -Mvsx.
12 * ppc-opc.c (insert_xt6): New static function.
13 (extract_xt6): Likewise.
14 (insert_xa6): Likewise.
15 (extract_xa6: Likewise.
16 (insert_xb6): Likewise.
17 (extract_xb6): Likewise.
18 (insert_xb6s): Likewise.
19 (extract_xb6s): Likewise.
20 (XS6, XT6, XA6, XB6, XB6S, DM, XX3, XX3DM, XX1_MASK, XX3_MASK,
21 XX3DM_MASK, PPCVSX): New.
22 (powerpc_opcodes): Add opcodes "lxvd2x", "lxvd2ux", "stxvd2x",
23 "stxvd2ux", "xxmrghd", "xxmrgld", "xxpermdi", "xvmovdp", "xvcpsgndp".
24
20fd6e2e
PA		 252008-08-01 Pedro Alves <pedro@codesourcery.com>
26
27 * Makefile.am ($(srcdir)/ia64-asmtab.c): Remove line continuation.
28 * Makefile.in: Regenerate.
29
a656ed5b
L		 302008-08-01 H.J. Lu <hongjiu.lu@intel.com>
31
32 * i386-reg.tbl: Use Dw2Inval on AVX registers.
33 * i386-tbl.h: Regenerated.
34
081ba1b3
AM		 352008-07-30 Michael J. Eager <eager@eagercon.com>
36
37 * ppc-dis.c (print_insn_powerpc): Disassemble FSL/FCR/UDI fields.
38 * ppc-opc.c (powerpc_operands): Add Xilinx APU related operands.
39 (insert_sprg, PPC405): Use PPC_OPCODE_405.
40 (powerpc_opcodes): Add Xilinx APU related opcodes.
41
0af1713e
AM		 422008-07-30 Alan Modra <amodra@bigpond.net.au>
43
44 * bfin-dis.c, cris-dis.c, i386-dis.c, or32-opc.c: Silence gcc warnings.
45
30c09090
RS		 462008-07-10 Richard Sandiford <rdsandiford@googlemail.com>
47
48 * mips-dis.c (_print_insn_mips): Use ELF_ST_IS_MIPS16.
49
c27e721e
AN		 502008-07-07 Adam Nemet <anemet@caviumnetworks.com>
51
52 * mips-opc.c (CP): New macro.
53 (mips_builtin_opcodes): Mark c0, c2 and c3 as CP. Add Octeon to the
54 membership of di, dmfc0, dmtc0, ei, mfc0 and mtc0. Add dmfc2 and
55 dmtc2 Octeon instructions.
56
bd2e2557
SS		 572008-07-07 Stan Shebs <stan@codesourcery.com>
58
59 * dis-init.c (init_disassemble_info): Init endian_code field.
60 * arm-dis.c (print_insn): Disassemble code according to
61 setting of endian_code.
62 (print_insn_big_arm): Detect when BE8 extension flag has been set.
63
6ba2a415
RS		 642008-06-30 Richard Sandiford <rdsandiford@googlemail.com>
65
66 * mips-dis.c (_print_insn_mips): Use bfd_asymbol_flavour to check
67 for ELF symbols.
68
c8187e15
PB		 692008-06-25 Peter Bergner <bergner@vnet.ibm.com>
70
71 * ppc-dis.c (powerpc_init_dialect): Handle -M464.
72 (print_ppc_disassembler_options): Likewise.
73 * ppc-opc.c (PPC464): Define.
74 (powerpc_opcodes): Add mfdcrux and mtdcrux.
75
7a283e07
RW		 762008-06-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
77
78 * configure: Regenerate.
79
fa452fa6
PB		 802008-06-13 Peter Bergner <bergner@vnet.ibm.com>
81
82 * ppc-dis.c (print_insn_powerpc): Update prototye to use new
83 ppc_cpu_t typedef.
84 (struct dis_private): New.
85 (POWERPC_DIALECT): New define.
86 (powerpc_dialect): Renamed to...
87 (powerpc_init_dialect): This. Update to use ppc_cpu_t and
88 struct dis_private.
89 (print_insn_big_powerpc): Update for using structure in
90 info->private_data.
91 (print_insn_little_powerpc): Likewise.
92 (operand_value_powerpc): Change type of dialect param to ppc_cpu_t.
93 (skip_optional_operands): Likewise.
94 (print_insn_powerpc): Likewise. Remove initialization of dialect.
95 * ppc-opc.c (extract_bat, extract_bba, extract_bdm, extract_bdp,
96 extract_bo, extract_boe, extract_fxm, extract_mb6, extract_mbe,
97 extract_nb, extract_nsi, extract_rbs, extract_sh6, extract_spr,
98 extract_sprg, extract_tbr insert_bat, insert_bba, insert_bdm,
99 insert_bdp, insert_bo, insert_boe, insert_fxm, insert_mb6, insert_mbe,
100 insert_nsi, insert_ral, insert_ram, insert_raq, insert_ras, insert_rbs,
101 insert_sh6, insert_spr, insert_sprg, insert_tbr): Change the dialect
102 param to be of type ppc_cpu_t. Update prototype.
103
bb35fb24
NC		 1042008-06-12 Adam Nemet <anemet@caviumnetworks.com>
105
106 * mips-dis.c (print_insn_args): Handle field descriptors +x, +p,
107 +s, +S.
108 * mips-opc.c (mips_builtin_opcodes): Add Octeon instructions
109 baddu, bbit*, cins*, dmul, pop, dpop, exts*, mtm*, mtp*, syncs,
110 syncw, syncws, vm3mulu, vm0 and vmulu.
111
dd3cbb7e
NC		 112 * mips-dis.c (print_insn_args): Handle field descriptor +Q.
113 * mips-opc.c (mips_builtin_opcodes): Add Octeon instructions seq,
114 seqi, sne and snei.
115
a5dabbb0
L		 1162008-05-30 H.J. Lu <hongjiu.lu@intel.com>
117
118 * i386-opc.tbl: Add vmovd with 64bit operand.
119 * i386-tbl.h: Regenerated.
120
725a9891
MS		 1212008-05-27 Martin Schwidefsky <schwidefsky@de.ibm.com>
122
123 * s390-opc.c (INSTR_RRF_R0RR): Fix RRF_R0RR operand format.
124
cbc80391
L		 1252008-05-22 H.J. Lu <hongjiu.lu@intel.com>
126
127 * i386-opc.tbl: Add NoAVX to cvtpd2pi, cvtpi2pd and cvttpd2pi.
128 * i386-tbl.h: Regenerated.
129
116615c5
L		 1302008-05-22 H.J. Lu <hongjiu.lu@intel.com>
131
132 PR gas/6517
133 * i386-opc.tbl: Break cvtsi2ss/cvtsi2sd/vcvtsi2sd/vcvtsi2ss
134 into 32bit and 64bit. Remove Reg64|Qword and add
135 IgnoreSize|No_qSuf on 32bit version.
136 * i386-tbl.h: Regenerated.
137
d9479f2d
L		 1382008-05-21 H.J. Lu <hongjiu.lu@intel.com>
139
140 * i386-opc.tbl: Add NoAVX to movdq2q and movq2dq.
141 * i386-tbl.h: Regenerated.
142
3ce6fddb
NC		 1432008-05-21 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
144
145 * cr16-dis.c (build_mask): Adjust the mask for 32-bit bcond.
146
8944f3c2
AM		 1472008-05-14 Alan Modra <amodra@bigpond.net.au>
148
149 * Makefile.am: Run "make dep-am".
150 * Makefile.in: Regenerate.
151
f1f8f695
L		 1522008-05-02 H.J. Lu <hongjiu.lu@intel.com>
153
154 * i386-dis.c (MOVBE_Fixup): New.
155 (Mo): Likewise.
156 (PREFIX_0F3880): Likewise.
157 (PREFIX_0F3881): Likewise.
158 (PREFIX_0F38F0): Updated.
159 (prefix_table): Add PREFIX_0F3880 and PREFIX_0F3881. Update
160 PREFIX_0F38F0 and PREFIX_0F38F1 for movbe.
161 (three_byte_table): Use PREFIX_0F3880 and PREFIX_0F3881.
162
163 * i386-gen.c (cpu_flag_init): Add CPU_MOVBE_FLAGS and
164 CPU_EPT_FLAGS.
165 (cpu_flags): Add CpuMovbe and CpuEPT.
166
167 * i386-opc.h (CpuMovbe): New.
168 (CpuEPT): Likewise.
169 (CpuLM): Updated.
170 (i386_cpu_flags): Add cpumovbe and cpuept.
171
172 * i386-opc.tbl: Add entries for movbe and EPT instructions.
173 * i386-init.h: Regenerated.
174 * i386-tbl.h: Likewise.
175
89aa3097
AN		 1762008-04-29 Adam Nemet <anemet@caviumnetworks.com>
177
178 * mips-opc.c (mips_builtin_opcodes): Set field `match' to 0 for
179 the two drem and the two dremu macros.
180
39c5c168
AN		 1812008-04-28 Adam Nemet <anemet@caviumnetworks.com>
182
183 * mips-opc.c (mips_builtin_opcodes): Mark prefx and c1
184 instructions FP_S. Mark l.s, li.s, lwc1, swc1, s.s, trunc.w.s and
185 cop1 macros INSN2_M_FP_S. Mark l.d, li.d, ldc1 and sdc1 macros
186 INSN2_M_FP_D. Mark trunc.w.d macro INSN2_M_FP_S and INSN2_M_FP_D.
187
f04d18b7
DM		 1882008-04-25 David S. Miller <davem@davemloft.net>
189
190 * sparc-dis.c: Emit %stick instead of %sys_tick, and %stick_cmpr
191 instead of %sys_tick_cmpr, as suggested in architecture manuals.
192
6194aaab
L		 1932008-04-23 Paolo Bonzini <bonzini@gnu.org>
194
195 * aclocal.m4: Regenerate.
196 * configure: Regenerate.
197
1a6b486f
DM		 1982008-04-23 David S. Miller <davem@davemloft.net>
199
200 * sparc-opc.c (asi_table): Add UltraSPARC and Niagara
201 extended values.
202 (prefetch_table): Add missing values.
203
81f8a913
L		 2042008-04-22 H.J. Lu <hongjiu.lu@intel.com>
205
206 * i386-gen.c (opcode_modifiers): Add NoAVX.
207
208 * i386-opc.h (NoAVX): New.
209 (OldGcc): Updated.
210 (i386_opcode_modifier): Add noavx.
211
212 * i386-opc.tbl: Add NoAVX to SSE, SSE2, SSE3 and SSSE3
213 instructions which don't have AVX equivalent.
214 * i386-tbl.h: Regenerated.
215
dae39acc
L		 2162008-04-18 H.J. Lu <hongjiu.lu@intel.com>
217
218 * i386-dis.c (OP_VEX_FMA): New.
219 (OP_EX_VexImmW): Likewise.
220 (VexFMA): Likewise.
221 (Vex128FMA): Likewise.
222 (EXVexImmW): Likewise.
223 (get_vex_imm8): Likewise.
224 (OP_EX_VexReg): Likewise.
225 (vex_i4_done): Renamed to ...
226 (vex_w_done): This.
227 (prefix_table): Replace EXVexW with EXVexImmW on vpermil2ps
228 and vpermil2pd. Replace Vex/Vex128 with VexFMA/Vex128FMA on
229 FMA instructions.
230 (print_insn): Updated.
231 (OP_EX_VexW): Rewrite to swap register in VEX with EX.
232 (OP_REG_VexI4): Check invalid high registers.
233
ce886ab1
DR		 2342008-04-16 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
235 Michael Meissner <michael.meissner@amd.com>
236
237 * i386-opc.tbl: Fix protX to allow memory in the middle operand.
238 * i386-tbl.h: Regenerate from i386-opc.tbl.
8944f3c2 239
19a6653c
AM		 2402008-04-14 Edmar Wienskoski <edmar@freescale.com>
241
242 * ppc-dis.c (powerpc_dialect): Handle "e500mc". Extend "e500" to
243 accept Power E500MC instructions.
244 (print_ppc_disassembler_options): Document -Me500mc.
245 * ppc-opc.c (DUIS, DUI, T): New.
246 (XRT, XRTRA): Likewise.
247 (E500MC): Likewise.
248 (powerpc_opcodes): Add new Power E500MC instructions.
249
112b7c50
AK		 2502008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
251
252 * s390-dis.c (init_disasm): Evaluate disassembler_options.
253 (print_s390_disassembler_options): New function.
254 * disassemble.c (disassembler_usage): Invoke
255 print_s390_disassembler_options.
256
7ff42648
AK		 2572008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
258
259 * s390-mkopc.c (insertExpandedMnemonic): Expand string sizes
260 of local variables used for mnemonic parsing: prefix, suffix and
261 number.
262
45a5551e
AK		 2632008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
264
265 * s390-mkopc.c (s390_cond_ext_format): Add back the mnemonic
266 extensions for conditional jumps (o, p, m, nz, z, nm, np, no).
267 (s390_crb_extensions): New extensions table.
268 (insertExpandedMnemonic): Handle '$' tag.
269 * s390-opc.txt: Remove conditional jump variants which can now
270 be expanded automatically.
271 Replace '*' tag with '$' in the compare and branch instructions.
272
06c8514a
L		 2732008-04-07 H.J. Lu <hongjiu.lu@intel.com>
274
275 * i386-dis.c (PREFIX_VEX_38XX): Add a tab.
276 (PREFIX_VEX_3AXX): Likewis.
277
b122c285
L		 2782008-04-07 H.J. Lu <hongjiu.lu@intel.com>
279
280 * i386-opc.tbl: Remove 4 extra blank lines.
281
594ab6a3
L		 2822008-04-04 H.J. Lu <hongjiu.lu@intel.com>
283
284 * i386-gen.c (cpu_flag_init): Replace CPU_CLMUL_FLAGS/CpuCLMUL
285 with CPU_PCLMUL_FLAGS/CpuPCLMUL.
286 (cpu_flags): Replace CpuCLMUL with CpuPCLMUL.
287 * i386-opc.tbl: Likewise.
288
289 * i386-opc.h (CpuCLMUL): Renamed to ...
290 (CpuPCLMUL): This.
291 (CpuFMA): Updated.
292 (i386_cpu_flags): Replace cpuclmul with cpupclmul.
293
294 * i386-init.h: Regenerated.
295
c0f3af97
L		 2962008-04-03 H.J. Lu <hongjiu.lu@intel.com>
297
298 * i386-dis.c (OP_E_register): New.
299 (OP_E_memory): Likewise.
300 (OP_VEX): Likewise.
301 (OP_EX_Vex): Likewise.
302 (OP_EX_VexW): Likewise.
303 (OP_XMM_Vex): Likewise.
304 (OP_XMM_VexW): Likewise.
305 (OP_REG_VexI4): Likewise.
306 (PCLMUL_Fixup): Likewise.
307 (VEXI4_Fixup): Likewise.
308 (VZERO_Fixup): Likewise.
309 (VCMP_Fixup): Likewise.
310 (VPERMIL2_Fixup): Likewise.
311 (rex_original): Likewise.
312 (rex_ignored): Likewise.
313 (Mxmm): Likewise.
314 (XMM): Likewise.
315 (EXxmm): Likewise.
316 (EXxmmq): Likewise.
317 (EXymmq): Likewise.
318 (Vex): Likewise.
319 (Vex128): Likewise.
320 (Vex256): Likewise.
321 (VexI4): Likewise.
322 (EXdVex): Likewise.
323 (EXqVex): Likewise.
324 (EXVexW): Likewise.
325 (EXdVexW): Likewise.
326 (EXqVexW): Likewise.
327 (XMVex): Likewise.
328 (XMVexW): Likewise.
329 (XMVexI4): Likewise.
330 (PCLMUL): Likewise.
331 (VZERO): Likewise.
332 (VCMP): Likewise.
333 (VPERMIL2): Likewise.
334 (xmm_mode): Likewise.
335 (xmmq_mode): Likewise.
336 (ymmq_mode): Likewise.
337 (vex_mode): Likewise.
338 (vex128_mode): Likewise.
339 (vex256_mode): Likewise.
340 (USE_VEX_C4_TABLE): Likewise.
341 (USE_VEX_C5_TABLE): Likewise.
342 (USE_VEX_LEN_TABLE): Likewise.
343 (VEX_C4_TABLE): Likewise.
344 (VEX_C5_TABLE): Likewise.
345 (VEX_LEN_TABLE): Likewise.
346 (REG_VEX_XX): Likewise.
347 (MOD_VEX_XXX): Likewise.
348 (PREFIX_0F38DB..PREFIX_0F38DF): Likewise.
349 (PREFIX_0F3A44): Likewise.
350 (PREFIX_0F3ADF): Likewise.
351 (PREFIX_VEX_XXX): Likewise.
352 (VEX_OF): Likewise.
353 (VEX_OF38): Likewise.
354 (VEX_OF3A): Likewise.
355 (VEX_LEN_XXX): Likewise.
356 (vex): Likewise.
357 (need_vex): Likewise.
358 (need_vex_reg): Likewise.
359 (vex_i4_done): Likewise.
360 (vex_table): Likewise.
361 (vex_len_table): Likewise.
362 (OP_REG_VexI4): Likewise.
363 (vex_cmp_op): Likewise.
364 (pclmul_op): Likewise.
365 (vpermil2_op): Likewise.
366 (m_mode): Updated.
367 (es_reg): Likewise.
368 (PREFIX_0F38F0): Likewise.
369 (PREFIX_0F3A60): Likewise.
370 (reg_table): Add REG_VEX_71...REG_VEX_73 and REG_VEX_AE.
371 (prefix_table): Add PREFIX_0F38DB..PREFIX_0F38DF, PREFIX_0F3ADF
372 and PREFIX_VEX_XXX entries.
373 (x86_64_table): Use VEX_C4_TABLE and VEX_C5_TABLE.
374 (three_byte_table): Use PREFIX_0F38DB..PREFIX_0F38DF and
375 PREFIX_0F3ADF.
376 (mod_table): Use VEX_C4_TABLE, VEX_C5_TABLE and VEX_LEN_TABLE.
377 Add MOD_VEX_XXX entries.
378 (ckprefix): Initialize rex_original and rex_ignored. Store the
379 REX byte in rex_original.
380 (get_valid_dis386): Handle the implicit prefix in VEX prefix
381 bytes and USE_VEX_LEN_TABLE/USE_VEX_C4_TABLE/USE_VEX_C5_TABLE.
382 (print_insn): Set need_vex/need_vex_reg/vex_i4_done to 0 before
383 calling get_valid_dis386. Use rex_original and rex_ignored when
384 printing out REX.
385 (putop): Handle "XY".
386 (intel_operand_size): Handle VEX, xmm_mode, xmmq_mode and
387 ymmq_mode.
388 (OP_E_extended): Updated to use OP_E_register and
389 OP_E_memory.
390 (OP_XMM): Handle VEX.
391 (OP_EX): Likewise.
392 (XMM_Fixup): Likewise.
393 (CMP_Fixup): Use ARRAY_SIZE.
394
395 * i386-gen.c (cpu_flag_init): Add CpuAES, CPU_CLMUL_FLAGS,
396 CPU_FMA_FLAGS and CPU_AVX_FLAGS.
397 (operand_type_init): Add OPERAND_TYPE_REGYMM and
398 OPERAND_TYPE_VEX_IMM4.
399 (cpu_flags): Add CpuAVX, CpuAES, CpuCLMUL and CpuFMA.
400 (opcode_modifiers): Add Implicit1stXmm0, Vex, Vex256, VexNDD,
401 VexNDS, VexW0, VexW1, Vex0F, Vex0F38, Vex0F3A, Vex3Sources,
402 VexImmExt and SSE2AVX.
403 (operand_types): Add RegYMM, Ymmword and Vex_Imm4.
404
405 * i386-opc.h (CpuAVX): New.
406 (CpuAES): Likewise.
407 (CpuCLMUL): Likewise.
408 (CpuFMA): Likewise.
409 (Vex): Likewise.
410 (Vex256): Likewise.
411 (VexNDS): Likewise.
412 (VexNDD): Likewise.
413 (VexW0): Likewise.
414 (VexW1): Likewise.
415 (Vex0F): Likewise.
416 (Vex0F38): Likewise.
417 (Vex0F3A): Likewise.
418 (Vex3Sources): Likewise.
419 (VexImmExt): Likewise.
420 (SSE2AVX): Likewise.
421 (RegYMM): Likewise.
422 (Ymmword): Likewise.
423 (Vex_Imm4): Likewise.
424 (Implicit1stXmm0): Likewise.
425 (CpuXsave): Updated.
426 (CpuLM): Likewise.
427 (ByteOkIntel): Likewise.
428 (OldGcc): Likewise.
429 (Control): Likewise.
430 (Unspecified): Likewise.
431 (OTMax): Likewise.
432 (i386_cpu_flags): Add cpuavx, cpuaes, cpuclmul and cpufma.
433 (i386_opcode_modifier): Add implicit1stxmm0, vex, vex256,
434 vexnds, vexndd, vexw0, vexw1, vex0f, vex0f38, vex0f3a,
435 vex3sources, veximmext and sse2avx.
436 (i386_operand_type): Add regymm, ymmword and vex_imm4.
437
438 * i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions.
439
440 * i386-reg.tbl: Add AVX registers, ymm0..ymm15.
441
442 * i386-init.h: Regenerated.
443 * i386-tbl.h: Likewise.
444
b21c9cb4
BS		 4452008-03-26 Bernd Schmidt <bernd.schmidt@analog.com>
446
447 From Robin Getz <robin.getz@analog.com>
448 * bfin-dis.c (bu32): Typedef.
449 (enum const_forms_t): Add c_uimm32 and c_huimm32.
450 (constant_formats[]): Add uimm32 and huimm16.
451 (fmtconst_val): New.
452 (uimm32): Define.
453 (huimm32): Define.
454 (imm16_val): Define.
455 (luimm16_val): Define.
456 (struct saved_state): Define.
457 (GREG, DPREG, DREG, PREG, SPREG, FPREG, IREG, MREG, BREG, LREG,
458 A0XREG, A0WREG, A1XREG, A1WREG,CCREG, LC0REG, LT0REG, LB0REG,
459 LC1REG, LT1REG, LB1REG, RETSREG, PCREG): Define.
460 (get_allreg): New.
461 (decode_LDIMMhalf_0): Print out the whole register value.
462
ee171c8f
BS		 463 From Jie Zhang <jie.zhang@analog.com>
464 * bfin-dis.c (decode_dsp32mac_0): Decode (IU) option for
465 multiply and multiply-accumulate to data register instruction.
466
086134ec
BS		 467 * bfin-dis.c: (c_uimm4s4d, c_imm5d, c_imm7d, c_imm16d, c_uimm16s4d,
468 c_imm32, c_huimm32e): Define.
469 (constant_formats): Add flags for printing decimal, leading spaces, and
470 exact symbols.
471 (comment, parallel): Add global flags in all disassembly.
472 (fmtconst): Take advantage of new flags, and print default in hex.
473 (fmtconst_val): Likewise.
474 (decode_macfunc): Be consistant with spaces, tabs, comments,
475 capitalization in disassembly, fix minor coding style issues.
476 (reg_names, amod0, amod1, amod0amod2, aligndir, get_allreg): Likewise.
477 (decode_ProgCtrl_0, decode_PushPopMultiple_0, decode_CCflag_0,
478 decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0,
479 decode_REGMV_0, decode_ALU2op_0, decode_PTR2op_0, decode_LOGI2op_0,
480 decode_COMP3op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
481 decode_LDSTpmod_0, decode_dagMODim_0, decode_dagMODik_0,
482 decode_dspLDST_0, decode_LDST_0, decode_LDSTiiFP_0, decode_LDSTii_0,
483 decode_LoopSetup_0, decode_LDIMMhalf_0, decode_CALLa_0,
484 decode_LDSTidxI_0, decode_linkage_0, decode_dsp32alu_0,
485 decode_dsp32shift_0, decode_dsp32shiftimm_0, decode_pseudodbg_assert_0,
486 _print_insn_bfin, print_insn_bfin): Likewise.
487
58c85be7
RW		 4882008-03-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
489
490 * aclocal.m4: Regenerate.
491 * configure: Likewise.
492 * Makefile.in: Likewise.
493
50e7d84b
AM		 4942008-03-13 Alan Modra <amodra@bigpond.net.au>
495
496 * Makefile.am: Run "make dep-am".
497 * Makefile.in: Regenerate.
498 * configure: Regenerate.
499
de866fcc
AM		 5002008-03-07 Alan Modra <amodra@bigpond.net.au>
501
502 * ppc-opc.c (powerpc_opcodes): Order and format.
503
28dbc079
L		 5042008-03-01 H.J. Lu <hongjiu.lu@intel.com>
505
506 * i386-opc.tbl: Allow 16-bit near indirect branches for x86-64.
507 * i386-tbl.h: Regenerated.
508
849830bd
L		 5092008-02-23 H.J. Lu <hongjiu.lu@intel.com>
510
511 * i386-opc.tbl: Disallow 16-bit near indirect branches for
512 x86-64.
513 * i386-tbl.h: Regenerated.
514
743ddb6b
JB		 5152008-02-21 Jan Beulich <jbeulich@novell.com>
516
517 * i386-opc.tbl: Allow Dword for far indirect call. Allow Dword
518 and Fword for far indirect jmp. Allow Reg16 and Word for near
519 indirect jmp on x86-64. Disallow Fword for lcall.
520 * i386-tbl.h: Re-generate.
521
796d5313
NC		 5222008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
523
524 * cr16-opc.c (cr16_num_optab): Defined
525
65da13b5
L		 5262008-02-16 H.J. Lu <hongjiu.lu@intel.com>
527
528 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_INOUTPORTREG.
529 * i386-init.h: Regenerated.
530
0e336180
NC		 5312008-02-14 Nick Clifton <nickc@redhat.com>
532
533 PR binutils/5524
534 * configure.in (SHARED_LIBADD): Select the correct host specific
535 file extension for shared libraries.
536 * configure: Regenerate.
537
b7240065
JB		 5382008-02-13 Jan Beulich <jbeulich@novell.com>
539
540 * i386-opc.h (RegFlat): New.
541 * i386-reg.tbl (flat): Add.
542 * i386-tbl.h: Re-generate.
543
34b772a6
JB		 5442008-02-13 Jan Beulich <jbeulich@novell.com>
545
546 * i386-dis.c (a_mode): New.
547 (cond_jump_mode): Adjust.
548 (Ma): Change to a_mode.
549 (intel_operand_size): Handle a_mode.
550 * i386-opc.tbl: Allow Dword and Qword for bound.
551 * i386-tbl.h: Re-generate.
552
a60de03c
JB		 5532008-02-13 Jan Beulich <jbeulich@novell.com>
554
555 * i386-gen.c (process_i386_registers): Process new fields.
556 * i386-opc.h (reg_entry): Shrink reg_flags and reg_num to
557 unsigned char. Add dw2_regnum and Dw2Inval.
558 * i386-reg.tbl: Provide initializers for dw2_regnum. Add pseudo
559 register names.
560 * i386-tbl.h: Re-generate.
561
f03fe4c1
L		 5622008-02-11 H.J. Lu <hongjiu.lu@intel.com>
563
4b6bc8eb 564 * i386-gen.c (cpu_flag_init): Add CPU_XSAVE_FLAGS.
f03fe4c1
L		 565 * i386-init.h: Updated.
566
475a2301
L		 5672008-02-11 H.J. Lu <hongjiu.lu@intel.com>
568
569 * i386-gen.c (cpu_flags): Add CpuXsave.
570
571 * i386-opc.h (CpuXsave): New.
4b6bc8eb 572 (CpuLM): Updated.
475a2301
L		 573 (i386_cpu_flags): Add cpuxsave.
574
575 * i386-dis.c (MOD_0FAE_REG_4): New.
576 (RM_0F01_REG_2): Likewise.
577 (MOD_0FAE_REG_5): Updated.
578 (RM_0F01_REG_3): Likewise.
579 (reg_table): Use MOD_0FAE_REG_4.
580 (mod_table): Use RM_0F01_REG_2. Add MOD_0FAE_REG_4. Updated
581 for xrstor.
582 (rm_table): Add RM_0F01_REG_2.
583
584 * i386-opc.tbl: Add xsave, xrstor, xgetbv and xsetbv.
585 * i386-init.h: Regenerated.
586 * i386-tbl.h: Likewise.
587
595785c6 5882008-02-11 Jan Beulich <jbeulich@novell.com>
041179fc 589
595785c6
JB		 590 * i386-opc.tbl: Remove Disp32S from CpuNo64 opcodes. Remove
591 Disp16 from Cpu64 non-jump opcodes (including loop and j?cxz).
592 * i386-tbl.h: Re-generate.
593
bb8541b9
L		 5942008-02-04 H.J. Lu <hongjiu.lu@intel.com>
595
596 PR 5715
597 * configure: Regenerated.
598
57b592a3
AN		 5992008-02-04 Adam Nemet <anemet@caviumnetworks.com>
600
601 * mips-dis.c: Update copyright.
602 (mips_arch_choices): Add Octeon.
603 * mips-opc.c: Update copyright.
604 (IOCT): New macro.
605 (mips_builtin_opcodes): Add Octeon instruction synciobdma.
606
930bb4cf
AM		 6072008-01-29 Alan Modra <amodra@bigpond.net.au>
608
609 * ppc-opc.c: Support optional L form mtmsr.
610
82c18208
L		 6112008-01-24 H.J. Lu <hongjiu.lu@intel.com>
612
613 * i386-dis.c (OP_E_extended): Handle r12 like rsp.
614
599121aa
L		 6152008-01-23 H.J. Lu <hongjiu.lu@intel.com>
616
617 * i386-gen.c (cpu_flag_init): Add CpuLM to CPU_GENERIC64_FLAGS.
618 * i386-init.h: Regenerated.
619
80098f51
TG		 6202008-01-23 Tristan Gingold <gingold@adacore.com>
621
622 * ia64-dis.c (print_insn_ia64): Display symbolic name of ar.fcr,
623 ar.eflag, ar.csd, ar.ssd, ar.cflg, ar.fsr, ar.fir and ar.fdr.
624
115c7c25
L		 6252008-01-22 H.J. Lu <hongjiu.lu@intel.com>
626
627 * i386-gen.c (cpu_flag_init): Remove CpuMMX2.
628 (cpu_flags): Likewise.
629
630 * i386-opc.h (CpuMMX2): Removed.
631 (CpuSSE): Updated.
632
633 * i386-opc.tbl: Replace CpuMMX2 with CpuSSE|Cpu3dnowA.
634 * i386-init.h: Regenerated.
635 * i386-tbl.h: Likewise.
636
6305a203
L		 6372008-01-22 H.J. Lu <hongjiu.lu@intel.com>
638
639 * i386-gen.c (cpu_flag_init): Add CPU_VMX_FLAGS and
640 CPU_SMX_FLAGS.
641 * i386-init.h: Regenerated.
642
fd07a1c8
L		 6432008-01-15 H.J. Lu <hongjiu.lu@intel.com>
644
645 * i386-opc.tbl: Use Qword on movddup.
646 * i386-tbl.h: Regenerated.
647
321fd21e
L		 6482008-01-15 H.J. Lu <hongjiu.lu@intel.com>
649
650 * i386-opc.tbl: Put back 16bit movsx/movzx for AT&T syntax.
651 * i386-tbl.h: Regenerated.
652
4ee52178
L		 6532008-01-15 H.J. Lu <hongjiu.lu@intel.com>
654
655 * i386-dis.c (Mx): New.
656 (PREFIX_0FC3): Likewise.
657 (PREFIX_0FC7_REG_6): Updated.
658 (dis386_twobyte): Use PREFIX_0FC3.
659 (prefix_table): Add PREFIX_0FC3. Use Mq on movntq and movntsd.
660 Use Mx on movntps, movntpd, movntdq and movntdqa. Use Md on
661 movntss.
662
5c07affc
L		 6632008-01-14 H.J. Lu <hongjiu.lu@intel.com>
664
665 * i386-gen.c (opcode_modifiers): Add IntelSyntax.
666 (operand_types): Add Mem.
667
668 * i386-opc.h (IntelSyntax): New.
669 * i386-opc.h (Mem): New.
670 (Byte): Updated.
671 (Opcode_Modifier_Max): Updated.
672 (i386_opcode_modifier): Add intelsyntax.
673 (i386_operand_type): Add mem.
674
675 * i386-opc.tbl: Remove Reg16 from movnti. Add sizes to more
676 instructions.
677
678 * i386-reg.tbl: Add size for accumulator.
679
680 * i386-init.h: Regenerated.
681 * i386-tbl.h: Likewise.
682
0d6a2f58
L		 6832008-01-13 H.J. Lu <hongjiu.lu@intel.com>
684
685 * i386-opc.h (Byte): Fix a typo.
686
7d5e4556
L		 6872008-01-12 H.J. Lu <hongjiu.lu@intel.com>
688
689 PR gas/5534
690 * i386-gen.c (operand_type_init): Add Dword to
691 OPERAND_TYPE_ACC32. Add Qword to OPERAND_TYPE_ACC64.
692 (opcode_modifiers): Remove CheckSize, Byte, Word, Dword,
693 Qword and Xmmword.
694 (operand_types): Add Byte, Word, Dword, Fword, Qword, Tbyte,
695 Xmmword, Unspecified and Anysize.
696 (set_bitfield): Make Mmword an alias of Qword. Make Oword
697 an alias of Xmmword.
698
699 * i386-opc.h (CheckSize): Removed.
700 (Byte): Updated.
701 (Word): Likewise.
702 (Dword): Likewise.
703 (Qword): Likewise.
704 (Xmmword): Likewise.
705 (FWait): Updated.
706 (OTMax): Likewise.
707 (i386_opcode_modifier): Remove checksize, byte, word, dword,
708 qword and xmmword.
709 (Fword): New.
710 (TBYTE): Likewise.
711 (Unspecified): Likewise.
712 (Anysize): Likewise.
713 (i386_operand_type): Add byte, word, dword, fword, qword,
714 tbyte xmmword, unspecified and anysize.
715
716 * i386-opc.tbl: Updated to use Byte, Word, Dword, Fword, Qword,
717 Tbyte, Xmmword, Unspecified and Anysize.
718
719 * i386-reg.tbl: Add size for accumulator.
720
721 * i386-init.h: Regenerated.
722 * i386-tbl.h: Likewise.
723
b5b1fc4f
L		 7242008-01-10 H.J. Lu <hongjiu.lu@intel.com>
725
726 * i386-dis.c (REG_0F0E): Renamed to REG_0F0D.
727 (REG_0F18): Updated.
728 (reg_table): Updated.
729 (dis386_twobyte): Updated. Use "nopQ" on 0x19 to 0x1e.
730 (twobyte_has_modrm): Set 1 for 0x19 to 0x1e.
731
50e8458f
L		 7322008-01-08 H.J. Lu <hongjiu.lu@intel.com>
733
734 * i386-gen.c (set_bitfield): Use fail () on error.
735
3d4d5afa
L		 7362008-01-08 H.J. Lu <hongjiu.lu@intel.com>
737
738 * i386-gen.c (lineno): New.
739 (filename): Likewise.
740 (set_bitfield): Report filename and line numer on error.
741 (process_i386_opcodes): Set filename and update lineno.
742 (process_i386_registers): Likewise.
743
e1d4d893
L		 7442008-01-05 H.J. Lu <hongjiu.lu@intel.com>
745
746 * i386-gen.c (opcode_modifiers): Rename IntelMnemonic to
747 ATTSyntax.
748
749 * i386-opc.h (IntelMnemonic): Renamed to ..
750 (ATTSyntax): This
751 (Opcode_Modifier_Max): Updated.
752 (i386_opcode_modifier): Remove intelmnemonic. Add attsyntax
753 and intelsyntax.
754
8944f3c2 755 * i386-opc.tbl: Remove IntelMnemonic and update with ATTSyntax
e1d4d893
L		 756 on fsub, fubp, fsubr, fsubrp, div, fdivp, fdivr and fdivrp.
757 * i386-tbl.h: Regenerated.
758
6f143e4d
L		 7592008-01-04 H.J. Lu <hongjiu.lu@intel.com>
760
761 * i386-gen.c: Update copyright to 2008.
762 * i386-opc.h: Likewise.
763 * i386-opc.tbl: Likewise.
764
765 * i386-init.h: Regenerated.
766 * i386-tbl.h: Likewise.
767
c6add537
L		 7682008-01-04 H.J. Lu <hongjiu.lu@intel.com>
769
770 * i386-opc.tbl: Add NoRex64 to extractps, movmskpd, movmskps,
771 pextrb, pextrw, pinsrb, pinsrw and pmovmskb.
772 * i386-tbl.h: Regenerated.
773
3629bb00
L		 7742008-01-03 H.J. Lu <hongjiu.lu@intel.com>
775
776 * i386-gen.c (cpu_flag_init): Remove CpuSSE4_1_Or_5 and
777 CpuSSE4_2_Or_ABM.
778 (cpu_flags): Likewise.
779
780 * i386-opc.h (CpuSSE4_1_Or_5): Removed.
781 (CpuSSE4_2_Or_ABM): Likewise.
782 (CpuLM): Updated.
783 (i386_cpu_flags): Remove cpusse4_1_or_5 and cpusse4_2_or_abm.
784
785 * i386-opc.tbl: Replace CpuSSE4_1_Or_5, CpuSSE4_2_Or_ABM and
786 Cpu686|CpuPadLock with CpuSSE4_1|CpuSSE5, CpuABM|CpuSSE4_2
787 and CpuPadLock, respectively.
788 * i386-init.h: Regenerated.
789 * i386-tbl.h: Likewise.
790
24995bd6
L		 7912008-01-03 H.J. Lu <hongjiu.lu@intel.com>
792
793 * i386-gen.c (opcode_modifiers): Remove No_xSuf.
794
795 * i386-opc.h (No_xSuf): Removed.
796 (CheckSize): Updated.
797
798 * i386-tbl.h: Regenerated.
799
e0329a22
L		 8002008-01-02 H.J. Lu <hongjiu.lu@intel.com>
801
802 * i386-gen.c (cpu_flag_init): Add CpuSSE4_2_Or_ABM to
803 CPU_AMDFAM10_FLAGS, CPU_SSE4_2_FLAGS, CpuABM and
804 CPU_SSE5_FLAGS.
805 (cpu_flags): Add CpuSSE4_2_Or_ABM.
806
807 * i386-opc.h (CpuSSE4_2_Or_ABM): New.
808 (CpuLM): Updated.
809 (i386_cpu_flags): Add cpusse4_2_or_abm.
810
811 * i386-opc.tbl: Use CpuSSE4_2_Or_ABM instead of
812 CpuABM|CpuSSE4_2 on popcnt.
813 * i386-init.h: Regenerated.
814 * i386-tbl.h: Likewise.
815
f2a9c676
L		 8162008-01-02 H.J. Lu <hongjiu.lu@intel.com>
817
818 * i386-opc.h: Update comments.
819
d978b5be
L		 8202008-01-02 H.J. Lu <hongjiu.lu@intel.com>
821
822 * i386-gen.c (opcode_modifiers): Use Qword instead of QWord.
823 * i386-opc.h: Likewise.
824 * i386-opc.tbl: Likewise.
825
582d5edd
L		 8262008-01-02 H.J. Lu <hongjiu.lu@intel.com>
827
828 PR gas/5534
829 * i386-gen.c (opcode_modifiers): Add No_xSuf, CheckSize,
830 Byte, Word, Dword, QWord and Xmmword.
831
832 * i386-opc.h (No_xSuf): New.
833 (CheckSize): Likewise.
834 (Byte): Likewise.
835 (Word): Likewise.
836 (Dword): Likewise.
837 (QWord): Likewise.
838 (Xmmword): Likewise.
839 (FWait): Updated.
840 (i386_opcode_modifier): Add No_xSuf, CheckSize, Byte, Word,
841 Dword, QWord and Xmmword.
842
843 * i386-opc.tbl: Add CheckSize|QWord to movq if IgnoreSize is
844 used.
845 * i386-tbl.h: Regenerated.
846
3fe15143
MK		 8472008-01-02 Mark Kettenis <kettenis@gnu.org>
848
849 * m88k-dis.c (instructions): Fix fcvt.* instructions.
850 From Miod Vallat.
851
6c7ac64e 852For older changes see ChangeLog-2007
252b5132
RH		 853\f
854Local Variables:
2f6d2f85
NC		 855mode: change-log
856left-margin: 8
857fill-column: 74
252b5132
RH		 858version-control: never
859End:
GDB Binutils - Deliverables
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