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* mips.h (INSN_MACRO): Move it up to the the pinfo macros.
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
f04d18b7
DM		 12008-04-25 David S. Miller <davem@davemloft.net>
2
3 * sparc-dis.c: Emit %stick instead of %sys_tick, and %stick_cmpr
4 instead of %sys_tick_cmpr, as suggested in architecture manuals.
5
6194aaab
L		 62008-04-23 Paolo Bonzini <bonzini@gnu.org>
7
8 * aclocal.m4: Regenerate.
9 * configure: Regenerate.
10
1a6b486f
DM		 112008-04-23 David S. Miller <davem@davemloft.net>
12
13 * sparc-opc.c (asi_table): Add UltraSPARC and Niagara
14 extended values.
15 (prefetch_table): Add missing values.
16
81f8a913
L		 172008-04-22 H.J. Lu <hongjiu.lu@intel.com>
18
19 * i386-gen.c (opcode_modifiers): Add NoAVX.
20
21 * i386-opc.h (NoAVX): New.
22 (OldGcc): Updated.
23 (i386_opcode_modifier): Add noavx.
24
25 * i386-opc.tbl: Add NoAVX to SSE, SSE2, SSE3 and SSSE3
26 instructions which don't have AVX equivalent.
27 * i386-tbl.h: Regenerated.
28
dae39acc
L		 292008-04-18 H.J. Lu <hongjiu.lu@intel.com>
30
31 * i386-dis.c (OP_VEX_FMA): New.
32 (OP_EX_VexImmW): Likewise.
33 (VexFMA): Likewise.
34 (Vex128FMA): Likewise.
35 (EXVexImmW): Likewise.
36 (get_vex_imm8): Likewise.
37 (OP_EX_VexReg): Likewise.
38 (vex_i4_done): Renamed to ...
39 (vex_w_done): This.
40 (prefix_table): Replace EXVexW with EXVexImmW on vpermil2ps
41 and vpermil2pd. Replace Vex/Vex128 with VexFMA/Vex128FMA on
42 FMA instructions.
43 (print_insn): Updated.
44 (OP_EX_VexW): Rewrite to swap register in VEX with EX.
45 (OP_REG_VexI4): Check invalid high registers.
46
ce886ab1
DR		 472008-04-16 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
48 Michael Meissner <michael.meissner@amd.com>
49
50 * i386-opc.tbl: Fix protX to allow memory in the middle operand.
51 * i386-tbl.h: Regenerate from i386-opc.tbl.
52
19a6653c
AM		 532008-04-14 Edmar Wienskoski <edmar@freescale.com>
54
55 * ppc-dis.c (powerpc_dialect): Handle "e500mc". Extend "e500" to
56 accept Power E500MC instructions.
57 (print_ppc_disassembler_options): Document -Me500mc.
58 * ppc-opc.c (DUIS, DUI, T): New.
59 (XRT, XRTRA): Likewise.
60 (E500MC): Likewise.
61 (powerpc_opcodes): Add new Power E500MC instructions.
62
112b7c50
AK		 632008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
64
65 * s390-dis.c (init_disasm): Evaluate disassembler_options.
66 (print_s390_disassembler_options): New function.
67 * disassemble.c (disassembler_usage): Invoke
68 print_s390_disassembler_options.
69
7ff42648
AK		 702008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
71
72 * s390-mkopc.c (insertExpandedMnemonic): Expand string sizes
73 of local variables used for mnemonic parsing: prefix, suffix and
74 number.
75
45a5551e
AK		 762008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
77
78 * s390-mkopc.c (s390_cond_ext_format): Add back the mnemonic
79 extensions for conditional jumps (o, p, m, nz, z, nm, np, no).
80 (s390_crb_extensions): New extensions table.
81 (insertExpandedMnemonic): Handle '$' tag.
82 * s390-opc.txt: Remove conditional jump variants which can now
83 be expanded automatically.
84 Replace '*' tag with '$' in the compare and branch instructions.
85
06c8514a
L		 862008-04-07 H.J. Lu <hongjiu.lu@intel.com>
87
88 * i386-dis.c (PREFIX_VEX_38XX): Add a tab.
89 (PREFIX_VEX_3AXX): Likewis.
90
b122c285
L		 912008-04-07 H.J. Lu <hongjiu.lu@intel.com>
92
93 * i386-opc.tbl: Remove 4 extra blank lines.
94
594ab6a3
L		 952008-04-04 H.J. Lu <hongjiu.lu@intel.com>
96
97 * i386-gen.c (cpu_flag_init): Replace CPU_CLMUL_FLAGS/CpuCLMUL
98 with CPU_PCLMUL_FLAGS/CpuPCLMUL.
99 (cpu_flags): Replace CpuCLMUL with CpuPCLMUL.
100 * i386-opc.tbl: Likewise.
101
102 * i386-opc.h (CpuCLMUL): Renamed to ...
103 (CpuPCLMUL): This.
104 (CpuFMA): Updated.
105 (i386_cpu_flags): Replace cpuclmul with cpupclmul.
106
107 * i386-init.h: Regenerated.
108
c0f3af97
L		 1092008-04-03 H.J. Lu <hongjiu.lu@intel.com>
110
111 * i386-dis.c (OP_E_register): New.
112 (OP_E_memory): Likewise.
113 (OP_VEX): Likewise.
114 (OP_EX_Vex): Likewise.
115 (OP_EX_VexW): Likewise.
116 (OP_XMM_Vex): Likewise.
117 (OP_XMM_VexW): Likewise.
118 (OP_REG_VexI4): Likewise.
119 (PCLMUL_Fixup): Likewise.
120 (VEXI4_Fixup): Likewise.
121 (VZERO_Fixup): Likewise.
122 (VCMP_Fixup): Likewise.
123 (VPERMIL2_Fixup): Likewise.
124 (rex_original): Likewise.
125 (rex_ignored): Likewise.
126 (Mxmm): Likewise.
127 (XMM): Likewise.
128 (EXxmm): Likewise.
129 (EXxmmq): Likewise.
130 (EXymmq): Likewise.
131 (Vex): Likewise.
132 (Vex128): Likewise.
133 (Vex256): Likewise.
134 (VexI4): Likewise.
135 (EXdVex): Likewise.
136 (EXqVex): Likewise.
137 (EXVexW): Likewise.
138 (EXdVexW): Likewise.
139 (EXqVexW): Likewise.
140 (XMVex): Likewise.
141 (XMVexW): Likewise.
142 (XMVexI4): Likewise.
143 (PCLMUL): Likewise.
144 (VZERO): Likewise.
145 (VCMP): Likewise.
146 (VPERMIL2): Likewise.
147 (xmm_mode): Likewise.
148 (xmmq_mode): Likewise.
149 (ymmq_mode): Likewise.
150 (vex_mode): Likewise.
151 (vex128_mode): Likewise.
152 (vex256_mode): Likewise.
153 (USE_VEX_C4_TABLE): Likewise.
154 (USE_VEX_C5_TABLE): Likewise.
155 (USE_VEX_LEN_TABLE): Likewise.
156 (VEX_C4_TABLE): Likewise.
157 (VEX_C5_TABLE): Likewise.
158 (VEX_LEN_TABLE): Likewise.
159 (REG_VEX_XX): Likewise.
160 (MOD_VEX_XXX): Likewise.
161 (PREFIX_0F38DB..PREFIX_0F38DF): Likewise.
162 (PREFIX_0F3A44): Likewise.
163 (PREFIX_0F3ADF): Likewise.
164 (PREFIX_VEX_XXX): Likewise.
165 (VEX_OF): Likewise.
166 (VEX_OF38): Likewise.
167 (VEX_OF3A): Likewise.
168 (VEX_LEN_XXX): Likewise.
169 (vex): Likewise.
170 (need_vex): Likewise.
171 (need_vex_reg): Likewise.
172 (vex_i4_done): Likewise.
173 (vex_table): Likewise.
174 (vex_len_table): Likewise.
175 (OP_REG_VexI4): Likewise.
176 (vex_cmp_op): Likewise.
177 (pclmul_op): Likewise.
178 (vpermil2_op): Likewise.
179 (m_mode): Updated.
180 (es_reg): Likewise.
181 (PREFIX_0F38F0): Likewise.
182 (PREFIX_0F3A60): Likewise.
183 (reg_table): Add REG_VEX_71...REG_VEX_73 and REG_VEX_AE.
184 (prefix_table): Add PREFIX_0F38DB..PREFIX_0F38DF, PREFIX_0F3ADF
185 and PREFIX_VEX_XXX entries.
186 (x86_64_table): Use VEX_C4_TABLE and VEX_C5_TABLE.
187 (three_byte_table): Use PREFIX_0F38DB..PREFIX_0F38DF and
188 PREFIX_0F3ADF.
189 (mod_table): Use VEX_C4_TABLE, VEX_C5_TABLE and VEX_LEN_TABLE.
190 Add MOD_VEX_XXX entries.
191 (ckprefix): Initialize rex_original and rex_ignored. Store the
192 REX byte in rex_original.
193 (get_valid_dis386): Handle the implicit prefix in VEX prefix
194 bytes and USE_VEX_LEN_TABLE/USE_VEX_C4_TABLE/USE_VEX_C5_TABLE.
195 (print_insn): Set need_vex/need_vex_reg/vex_i4_done to 0 before
196 calling get_valid_dis386. Use rex_original and rex_ignored when
197 printing out REX.
198 (putop): Handle "XY".
199 (intel_operand_size): Handle VEX, xmm_mode, xmmq_mode and
200 ymmq_mode.
201 (OP_E_extended): Updated to use OP_E_register and
202 OP_E_memory.
203 (OP_XMM): Handle VEX.
204 (OP_EX): Likewise.
205 (XMM_Fixup): Likewise.
206 (CMP_Fixup): Use ARRAY_SIZE.
207
208 * i386-gen.c (cpu_flag_init): Add CpuAES, CPU_CLMUL_FLAGS,
209 CPU_FMA_FLAGS and CPU_AVX_FLAGS.
210 (operand_type_init): Add OPERAND_TYPE_REGYMM and
211 OPERAND_TYPE_VEX_IMM4.
212 (cpu_flags): Add CpuAVX, CpuAES, CpuCLMUL and CpuFMA.
213 (opcode_modifiers): Add Implicit1stXmm0, Vex, Vex256, VexNDD,
214 VexNDS, VexW0, VexW1, Vex0F, Vex0F38, Vex0F3A, Vex3Sources,
215 VexImmExt and SSE2AVX.
216 (operand_types): Add RegYMM, Ymmword and Vex_Imm4.
217
218 * i386-opc.h (CpuAVX): New.
219 (CpuAES): Likewise.
220 (CpuCLMUL): Likewise.
221 (CpuFMA): Likewise.
222 (Vex): Likewise.
223 (Vex256): Likewise.
224 (VexNDS): Likewise.
225 (VexNDD): Likewise.
226 (VexW0): Likewise.
227 (VexW1): Likewise.
228 (Vex0F): Likewise.
229 (Vex0F38): Likewise.
230 (Vex0F3A): Likewise.
231 (Vex3Sources): Likewise.
232 (VexImmExt): Likewise.
233 (SSE2AVX): Likewise.
234 (RegYMM): Likewise.
235 (Ymmword): Likewise.
236 (Vex_Imm4): Likewise.
237 (Implicit1stXmm0): Likewise.
238 (CpuXsave): Updated.
239 (CpuLM): Likewise.
240 (ByteOkIntel): Likewise.
241 (OldGcc): Likewise.
242 (Control): Likewise.
243 (Unspecified): Likewise.
244 (OTMax): Likewise.
245 (i386_cpu_flags): Add cpuavx, cpuaes, cpuclmul and cpufma.
246 (i386_opcode_modifier): Add implicit1stxmm0, vex, vex256,
247 vexnds, vexndd, vexw0, vexw1, vex0f, vex0f38, vex0f3a,
248 vex3sources, veximmext and sse2avx.
249 (i386_operand_type): Add regymm, ymmword and vex_imm4.
250
251 * i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions.
252
253 * i386-reg.tbl: Add AVX registers, ymm0..ymm15.
254
255 * i386-init.h: Regenerated.
256 * i386-tbl.h: Likewise.
257
b21c9cb4
BS		 2582008-03-26 Bernd Schmidt <bernd.schmidt@analog.com>
259
260 From Robin Getz <robin.getz@analog.com>
261 * bfin-dis.c (bu32): Typedef.
262 (enum const_forms_t): Add c_uimm32 and c_huimm32.
263 (constant_formats[]): Add uimm32 and huimm16.
264 (fmtconst_val): New.
265 (uimm32): Define.
266 (huimm32): Define.
267 (imm16_val): Define.
268 (luimm16_val): Define.
269 (struct saved_state): Define.
270 (GREG, DPREG, DREG, PREG, SPREG, FPREG, IREG, MREG, BREG, LREG,
271 A0XREG, A0WREG, A1XREG, A1WREG,CCREG, LC0REG, LT0REG, LB0REG,
272 LC1REG, LT1REG, LB1REG, RETSREG, PCREG): Define.
273 (get_allreg): New.
274 (decode_LDIMMhalf_0): Print out the whole register value.
275
ee171c8f
BS		 276 From Jie Zhang <jie.zhang@analog.com>
277 * bfin-dis.c (decode_dsp32mac_0): Decode (IU) option for
278 multiply and multiply-accumulate to data register instruction.
279
086134ec
BS		 280 * bfin-dis.c: (c_uimm4s4d, c_imm5d, c_imm7d, c_imm16d, c_uimm16s4d,
281 c_imm32, c_huimm32e): Define.
282 (constant_formats): Add flags for printing decimal, leading spaces, and
283 exact symbols.
284 (comment, parallel): Add global flags in all disassembly.
285 (fmtconst): Take advantage of new flags, and print default in hex.
286 (fmtconst_val): Likewise.
287 (decode_macfunc): Be consistant with spaces, tabs, comments,
288 capitalization in disassembly, fix minor coding style issues.
289 (reg_names, amod0, amod1, amod0amod2, aligndir, get_allreg): Likewise.
290 (decode_ProgCtrl_0, decode_PushPopMultiple_0, decode_CCflag_0,
291 decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0,
292 decode_REGMV_0, decode_ALU2op_0, decode_PTR2op_0, decode_LOGI2op_0,
293 decode_COMP3op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
294 decode_LDSTpmod_0, decode_dagMODim_0, decode_dagMODik_0,
295 decode_dspLDST_0, decode_LDST_0, decode_LDSTiiFP_0, decode_LDSTii_0,
296 decode_LoopSetup_0, decode_LDIMMhalf_0, decode_CALLa_0,
297 decode_LDSTidxI_0, decode_linkage_0, decode_dsp32alu_0,
298 decode_dsp32shift_0, decode_dsp32shiftimm_0, decode_pseudodbg_assert_0,
299 _print_insn_bfin, print_insn_bfin): Likewise.
300
58c85be7
RW		 3012008-03-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
302
303 * aclocal.m4: Regenerate.
304 * configure: Likewise.
305 * Makefile.in: Likewise.
306
50e7d84b
AM		 3072008-03-13 Alan Modra <amodra@bigpond.net.au>
308
309 * Makefile.am: Run "make dep-am".
310 * Makefile.in: Regenerate.
311 * configure: Regenerate.
312
de866fcc
AM		 3132008-03-07 Alan Modra <amodra@bigpond.net.au>
314
315 * ppc-opc.c (powerpc_opcodes): Order and format.
316
28dbc079
L		 3172008-03-01 H.J. Lu <hongjiu.lu@intel.com>
318
319 * i386-opc.tbl: Allow 16-bit near indirect branches for x86-64.
320 * i386-tbl.h: Regenerated.
321
849830bd
L		 3222008-02-23 H.J. Lu <hongjiu.lu@intel.com>
323
324 * i386-opc.tbl: Disallow 16-bit near indirect branches for
325 x86-64.
326 * i386-tbl.h: Regenerated.
327
743ddb6b
JB		 3282008-02-21 Jan Beulich <jbeulich@novell.com>
329
330 * i386-opc.tbl: Allow Dword for far indirect call. Allow Dword
331 and Fword for far indirect jmp. Allow Reg16 and Word for near
332 indirect jmp on x86-64. Disallow Fword for lcall.
333 * i386-tbl.h: Re-generate.
334
796d5313
NC		 3352008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
336
337 * cr16-opc.c (cr16_num_optab): Defined
338
65da13b5
L		 3392008-02-16 H.J. Lu <hongjiu.lu@intel.com>
340
341 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_INOUTPORTREG.
342 * i386-init.h: Regenerated.
343
0e336180
NC		 3442008-02-14 Nick Clifton <nickc@redhat.com>
345
346 PR binutils/5524
347 * configure.in (SHARED_LIBADD): Select the correct host specific
348 file extension for shared libraries.
349 * configure: Regenerate.
350
b7240065
JB		 3512008-02-13 Jan Beulich <jbeulich@novell.com>
352
353 * i386-opc.h (RegFlat): New.
354 * i386-reg.tbl (flat): Add.
355 * i386-tbl.h: Re-generate.
356
34b772a6
JB		 3572008-02-13 Jan Beulich <jbeulich@novell.com>
358
359 * i386-dis.c (a_mode): New.
360 (cond_jump_mode): Adjust.
361 (Ma): Change to a_mode.
362 (intel_operand_size): Handle a_mode.
363 * i386-opc.tbl: Allow Dword and Qword for bound.
364 * i386-tbl.h: Re-generate.
365
a60de03c
JB		 3662008-02-13 Jan Beulich <jbeulich@novell.com>
367
368 * i386-gen.c (process_i386_registers): Process new fields.
369 * i386-opc.h (reg_entry): Shrink reg_flags and reg_num to
370 unsigned char. Add dw2_regnum and Dw2Inval.
371 * i386-reg.tbl: Provide initializers for dw2_regnum. Add pseudo
372 register names.
373 * i386-tbl.h: Re-generate.
374
f03fe4c1
L		 3752008-02-11 H.J. Lu <hongjiu.lu@intel.com>
376
4b6bc8eb 377 * i386-gen.c (cpu_flag_init): Add CPU_XSAVE_FLAGS.
f03fe4c1
L		 378 * i386-init.h: Updated.
379
475a2301
L		 3802008-02-11 H.J. Lu <hongjiu.lu@intel.com>
381
382 * i386-gen.c (cpu_flags): Add CpuXsave.
383
384 * i386-opc.h (CpuXsave): New.
4b6bc8eb 385 (CpuLM): Updated.
475a2301
L		 386 (i386_cpu_flags): Add cpuxsave.
387
388 * i386-dis.c (MOD_0FAE_REG_4): New.
389 (RM_0F01_REG_2): Likewise.
390 (MOD_0FAE_REG_5): Updated.
391 (RM_0F01_REG_3): Likewise.
392 (reg_table): Use MOD_0FAE_REG_4.
393 (mod_table): Use RM_0F01_REG_2. Add MOD_0FAE_REG_4. Updated
394 for xrstor.
395 (rm_table): Add RM_0F01_REG_2.
396
397 * i386-opc.tbl: Add xsave, xrstor, xgetbv and xsetbv.
398 * i386-init.h: Regenerated.
399 * i386-tbl.h: Likewise.
400
595785c6 4012008-02-11 Jan Beulich <jbeulich@novell.com>
041179fc 402
595785c6
JB		 403 * i386-opc.tbl: Remove Disp32S from CpuNo64 opcodes. Remove
404 Disp16 from Cpu64 non-jump opcodes (including loop and j?cxz).
405 * i386-tbl.h: Re-generate.
406
bb8541b9
L		 4072008-02-04 H.J. Lu <hongjiu.lu@intel.com>
408
409 PR 5715
410 * configure: Regenerated.
411
57b592a3
AN		 4122008-02-04 Adam Nemet <anemet@caviumnetworks.com>
413
414 * mips-dis.c: Update copyright.
415 (mips_arch_choices): Add Octeon.
416 * mips-opc.c: Update copyright.
417 (IOCT): New macro.
418 (mips_builtin_opcodes): Add Octeon instruction synciobdma.
419
930bb4cf
AM		 4202008-01-29 Alan Modra <amodra@bigpond.net.au>
421
422 * ppc-opc.c: Support optional L form mtmsr.
423
82c18208
L		 4242008-01-24 H.J. Lu <hongjiu.lu@intel.com>
425
426 * i386-dis.c (OP_E_extended): Handle r12 like rsp.
427
599121aa
L		 4282008-01-23 H.J. Lu <hongjiu.lu@intel.com>
429
430 * i386-gen.c (cpu_flag_init): Add CpuLM to CPU_GENERIC64_FLAGS.
431 * i386-init.h: Regenerated.
432
80098f51
TG		 4332008-01-23 Tristan Gingold <gingold@adacore.com>
434
435 * ia64-dis.c (print_insn_ia64): Display symbolic name of ar.fcr,
436 ar.eflag, ar.csd, ar.ssd, ar.cflg, ar.fsr, ar.fir and ar.fdr.
437
115c7c25
L		 4382008-01-22 H.J. Lu <hongjiu.lu@intel.com>
439
440 * i386-gen.c (cpu_flag_init): Remove CpuMMX2.
441 (cpu_flags): Likewise.
442
443 * i386-opc.h (CpuMMX2): Removed.
444 (CpuSSE): Updated.
445
446 * i386-opc.tbl: Replace CpuMMX2 with CpuSSE|Cpu3dnowA.
447 * i386-init.h: Regenerated.
448 * i386-tbl.h: Likewise.
449
6305a203
L		 4502008-01-22 H.J. Lu <hongjiu.lu@intel.com>
451
452 * i386-gen.c (cpu_flag_init): Add CPU_VMX_FLAGS and
453 CPU_SMX_FLAGS.
454 * i386-init.h: Regenerated.
455
fd07a1c8
L		 4562008-01-15 H.J. Lu <hongjiu.lu@intel.com>
457
458 * i386-opc.tbl: Use Qword on movddup.
459 * i386-tbl.h: Regenerated.
460
321fd21e
L		 4612008-01-15 H.J. Lu <hongjiu.lu@intel.com>
462
463 * i386-opc.tbl: Put back 16bit movsx/movzx for AT&T syntax.
464 * i386-tbl.h: Regenerated.
465
4ee52178
L		 4662008-01-15 H.J. Lu <hongjiu.lu@intel.com>
467
468 * i386-dis.c (Mx): New.
469 (PREFIX_0FC3): Likewise.
470 (PREFIX_0FC7_REG_6): Updated.
471 (dis386_twobyte): Use PREFIX_0FC3.
472 (prefix_table): Add PREFIX_0FC3. Use Mq on movntq and movntsd.
473 Use Mx on movntps, movntpd, movntdq and movntdqa. Use Md on
474 movntss.
475
5c07affc
L		 4762008-01-14 H.J. Lu <hongjiu.lu@intel.com>
477
478 * i386-gen.c (opcode_modifiers): Add IntelSyntax.
479 (operand_types): Add Mem.
480
481 * i386-opc.h (IntelSyntax): New.
482 * i386-opc.h (Mem): New.
483 (Byte): Updated.
484 (Opcode_Modifier_Max): Updated.
485 (i386_opcode_modifier): Add intelsyntax.
486 (i386_operand_type): Add mem.
487
488 * i386-opc.tbl: Remove Reg16 from movnti. Add sizes to more
489 instructions.
490
491 * i386-reg.tbl: Add size for accumulator.
492
493 * i386-init.h: Regenerated.
494 * i386-tbl.h: Likewise.
495
0d6a2f58
L		 4962008-01-13 H.J. Lu <hongjiu.lu@intel.com>
497
498 * i386-opc.h (Byte): Fix a typo.
499
7d5e4556
L		 5002008-01-12 H.J. Lu <hongjiu.lu@intel.com>
501
502 PR gas/5534
503 * i386-gen.c (operand_type_init): Add Dword to
504 OPERAND_TYPE_ACC32. Add Qword to OPERAND_TYPE_ACC64.
505 (opcode_modifiers): Remove CheckSize, Byte, Word, Dword,
506 Qword and Xmmword.
507 (operand_types): Add Byte, Word, Dword, Fword, Qword, Tbyte,
508 Xmmword, Unspecified and Anysize.
509 (set_bitfield): Make Mmword an alias of Qword. Make Oword
510 an alias of Xmmword.
511
512 * i386-opc.h (CheckSize): Removed.
513 (Byte): Updated.
514 (Word): Likewise.
515 (Dword): Likewise.
516 (Qword): Likewise.
517 (Xmmword): Likewise.
518 (FWait): Updated.
519 (OTMax): Likewise.
520 (i386_opcode_modifier): Remove checksize, byte, word, dword,
521 qword and xmmword.
522 (Fword): New.
523 (TBYTE): Likewise.
524 (Unspecified): Likewise.
525 (Anysize): Likewise.
526 (i386_operand_type): Add byte, word, dword, fword, qword,
527 tbyte xmmword, unspecified and anysize.
528
529 * i386-opc.tbl: Updated to use Byte, Word, Dword, Fword, Qword,
530 Tbyte, Xmmword, Unspecified and Anysize.
531
532 * i386-reg.tbl: Add size for accumulator.
533
534 * i386-init.h: Regenerated.
535 * i386-tbl.h: Likewise.
536
b5b1fc4f
L		 5372008-01-10 H.J. Lu <hongjiu.lu@intel.com>
538
539 * i386-dis.c (REG_0F0E): Renamed to REG_0F0D.
540 (REG_0F18): Updated.
541 (reg_table): Updated.
542 (dis386_twobyte): Updated. Use "nopQ" on 0x19 to 0x1e.
543 (twobyte_has_modrm): Set 1 for 0x19 to 0x1e.
544
50e8458f
L		 5452008-01-08 H.J. Lu <hongjiu.lu@intel.com>
546
547 * i386-gen.c (set_bitfield): Use fail () on error.
548
3d4d5afa
L		 5492008-01-08 H.J. Lu <hongjiu.lu@intel.com>
550
551 * i386-gen.c (lineno): New.
552 (filename): Likewise.
553 (set_bitfield): Report filename and line numer on error.
554 (process_i386_opcodes): Set filename and update lineno.
555 (process_i386_registers): Likewise.
556
e1d4d893
L		 5572008-01-05 H.J. Lu <hongjiu.lu@intel.com>
558
559 * i386-gen.c (opcode_modifiers): Rename IntelMnemonic to
560 ATTSyntax.
561
562 * i386-opc.h (IntelMnemonic): Renamed to ..
563 (ATTSyntax): This
564 (Opcode_Modifier_Max): Updated.
565 (i386_opcode_modifier): Remove intelmnemonic. Add attsyntax
566 and intelsyntax.
567
568 * i386-opc.tbl: Remove IntelMnemonic and update with ATTSyntax
569 on fsub, fubp, fsubr, fsubrp, div, fdivp, fdivr and fdivrp.
570 * i386-tbl.h: Regenerated.
571
6f143e4d
L		 5722008-01-04 H.J. Lu <hongjiu.lu@intel.com>
573
574 * i386-gen.c: Update copyright to 2008.
575 * i386-opc.h: Likewise.
576 * i386-opc.tbl: Likewise.
577
578 * i386-init.h: Regenerated.
579 * i386-tbl.h: Likewise.
580
c6add537
L		 5812008-01-04 H.J. Lu <hongjiu.lu@intel.com>
582
583 * i386-opc.tbl: Add NoRex64 to extractps, movmskpd, movmskps,
584 pextrb, pextrw, pinsrb, pinsrw and pmovmskb.
585 * i386-tbl.h: Regenerated.
586
3629bb00
L		 5872008-01-03 H.J. Lu <hongjiu.lu@intel.com>
588
589 * i386-gen.c (cpu_flag_init): Remove CpuSSE4_1_Or_5 and
590 CpuSSE4_2_Or_ABM.
591 (cpu_flags): Likewise.
592
593 * i386-opc.h (CpuSSE4_1_Or_5): Removed.
594 (CpuSSE4_2_Or_ABM): Likewise.
595 (CpuLM): Updated.
596 (i386_cpu_flags): Remove cpusse4_1_or_5 and cpusse4_2_or_abm.
597
598 * i386-opc.tbl: Replace CpuSSE4_1_Or_5, CpuSSE4_2_Or_ABM and
599 Cpu686|CpuPadLock with CpuSSE4_1|CpuSSE5, CpuABM|CpuSSE4_2
600 and CpuPadLock, respectively.
601 * i386-init.h: Regenerated.
602 * i386-tbl.h: Likewise.
603
24995bd6
L		 6042008-01-03 H.J. Lu <hongjiu.lu@intel.com>
605
606 * i386-gen.c (opcode_modifiers): Remove No_xSuf.
607
608 * i386-opc.h (No_xSuf): Removed.
609 (CheckSize): Updated.
610
611 * i386-tbl.h: Regenerated.
612
e0329a22
L		 6132008-01-02 H.J. Lu <hongjiu.lu@intel.com>
614
615 * i386-gen.c (cpu_flag_init): Add CpuSSE4_2_Or_ABM to
616 CPU_AMDFAM10_FLAGS, CPU_SSE4_2_FLAGS, CpuABM and
617 CPU_SSE5_FLAGS.
618 (cpu_flags): Add CpuSSE4_2_Or_ABM.
619
620 * i386-opc.h (CpuSSE4_2_Or_ABM): New.
621 (CpuLM): Updated.
622 (i386_cpu_flags): Add cpusse4_2_or_abm.
623
624 * i386-opc.tbl: Use CpuSSE4_2_Or_ABM instead of
625 CpuABM|CpuSSE4_2 on popcnt.
626 * i386-init.h: Regenerated.
627 * i386-tbl.h: Likewise.
628
f2a9c676
L		 6292008-01-02 H.J. Lu <hongjiu.lu@intel.com>
630
631 * i386-opc.h: Update comments.
632
d978b5be
L		 6332008-01-02 H.J. Lu <hongjiu.lu@intel.com>
634
635 * i386-gen.c (opcode_modifiers): Use Qword instead of QWord.
636 * i386-opc.h: Likewise.
637 * i386-opc.tbl: Likewise.
638
582d5edd
L		 6392008-01-02 H.J. Lu <hongjiu.lu@intel.com>
640
641 PR gas/5534
642 * i386-gen.c (opcode_modifiers): Add No_xSuf, CheckSize,
643 Byte, Word, Dword, QWord and Xmmword.
644
645 * i386-opc.h (No_xSuf): New.
646 (CheckSize): Likewise.
647 (Byte): Likewise.
648 (Word): Likewise.
649 (Dword): Likewise.
650 (QWord): Likewise.
651 (Xmmword): Likewise.
652 (FWait): Updated.
653 (i386_opcode_modifier): Add No_xSuf, CheckSize, Byte, Word,
654 Dword, QWord and Xmmword.
655
656 * i386-opc.tbl: Add CheckSize|QWord to movq if IgnoreSize is
657 used.
658 * i386-tbl.h: Regenerated.
659
3fe15143
MK		 6602008-01-02 Mark Kettenis <kettenis@gnu.org>
661
662 * m88k-dis.c (instructions): Fix fcvt.* instructions.
663 From Miod Vallat.
664
6c7ac64e 665For older changes see ChangeLog-2007
252b5132
RH		 666\f
667Local Variables:
2f6d2f85
NC		 668mode: change-log
669left-margin: 8
670fill-column: 74
252b5132
RH		 671version-control: never
672End:
GDB Binutils - Deliverables
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