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Change gdbarch_wchar_bit for AArch64 and ARM
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
0348fd79
MR		 12017-04-25 Maciej W. Rozycki <macro@imgtec.com>
2
3 * mips-dis.c (print_mips_disassembler_options): Add
4 `no-aliases'.
5
6e3d1f07
MR		 62017-04-25 Maciej W. Rozycki <macro@imgtec.com>
7
8 * mips16-opc.c (AL): New macro.
9 (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
10 of "ld" and "lw" as aliases.
11
957f6b39
TC		 122017-04-24 Tamar Christina <tamar.christina@arm.com>
13
14 * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
15 arguments.
16
a8cc8a54
AM		 172017-04-22 Alexander Fedotov <alfedotov@gmail.com>
18 Alan Modra <amodra@gmail.com>
19
20 * ppc-opc.c (ELEV): Define.
21 (vle_opcodes): Add se_rfgi and e_sc.
22 (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
23 for E200Z4.
24
3ab87b68
JM		 252017-04-21 Jose E. Marchesi <jose.marchesi@oracle.com>
26
27 * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
28
792f174f
NC		 292017-04-21 Nick Clifton <nickc@redhat.com>
30
31 PR binutils/21380
32 * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
33 LD3R and LD4R.
34
42742084
AM		 352017-04-13 Alan Modra <amodra@gmail.com>
36
37 * epiphany-desc.c: Regenerate.
38 * fr30-desc.c: Regenerate.
39 * frv-desc.c: Regenerate.
40 * ip2k-desc.c: Regenerate.
41 * iq2000-desc.c: Regenerate.
42 * lm32-desc.c: Regenerate.
43 * m32c-desc.c: Regenerate.
44 * m32r-desc.c: Regenerate.
45 * mep-desc.c: Regenerate.
46 * mt-desc.c: Regenerate.
47 * or1k-desc.c: Regenerate.
48 * xc16x-desc.c: Regenerate.
49 * xstormy16-desc.c: Regenerate.
50
9a85b496
AM		 512017-04-11 Alan Modra <amodra@gmail.com>
52
ef85eab0 53 * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
c03dc33b
AM		 54 PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm". Formatting. Set
55 PPC_OPCODE_TMR for e6500.
9a85b496
AM		 56 * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
57 (PPCVEC3): Define as PPC_OPCODE_POWER9.
9570835e
AM		 58 (PPCVSX2): Define as PPC_OPCODE_POWER8.
59 (PPCVSX3): Define as PPC_OPCODE_POWER9.
ef85eab0 60 (PPCHTM): Define as PPC_OPCODE_POWER8.
c03dc33b 61 (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
9a85b496 62
62adc510
AM		 632017-04-10 Alan Modra <amodra@gmail.com>
64
65 * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
66 * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
67 (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
68 removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
69
aa808707
PC		 702017-04-09 Pip Cet <pipcet@gmail.com>
71
72 * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
73 appropriate floating-point precision directly.
74
ac8f0f72
AM		 752017-04-07 Alan Modra <amodra@gmail.com>
76
77 * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
78 lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
79 lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
80 lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
81 vector instructions with E6500 not PPCVEC2.
82
62ecb94c
PC		 832017-04-06 Pip Cet <pipcet@gmail.com>
84
85 * Makefile.am: Add wasm32-dis.c.
86 * configure.ac: Add wasm32-dis.c to wasm32 target.
87 * disassemble.c: Add wasm32 disassembler code.
88 * wasm32-dis.c: New file.
89 * Makefile.in: Regenerate.
90 * configure: Regenerate.
91 * po/POTFILES.in: Regenerate.
92 * po/opcodes.pot: Regenerate.
93
f995bbe8
PA		 942017-04-05 Pedro Alves <palves@redhat.com>
95
96 * arc-dis.c (parse_option, parse_disassembler_options): Constify.
97 * arm-dis.c (parse_arm_disassembler_options): Constify.
98 * ppc-dis.c (powerpc_init_dialect): Constify local.
99 * vax-dis.c (parse_disassembler_options): Constify.
100
b5292032
PD		 1012017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
102
103 * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
104 RISCV_GP_SYMBOL.
105
f96bd6c2
PC		 1062017-03-30 Pip Cet <pipcet@gmail.com>
107
108 * configure.ac: Add (empty) bfd_wasm32_arch target.
109 * configure: Regenerate
110 * po/opcodes.pot: Regenerate.
111
f7c514a3
JM		 1122017-03-29 Sheldon Lobo <sheldon.lobo@oracle.com>
113
114 Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
115 OSA2015.
116 * opcodes/sparc-opc.c (asi_table): New ASIs.
117
52be03fd
AM		 1182017-03-29 Alan Modra <amodra@gmail.com>
119
120 * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add
121 "raw" option.
122 (lookup_powerpc): Don't special case -1 dialect. Handle
123 PPC_OPCODE_RAW.
124 (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
125 lookup_powerpc call, pass it on second.
126
9b753937
AM		 1272017-03-27 Alan Modra <amodra@gmail.com>
128
129 PR 21303
130 * ppc-dis.c (struct ppc_mopt): Comment.
131 (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
132
c0c31e91
RZ		 1332017-03-27 Rinat Zelig <rinat@mellanox.com>
134
135 * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
136 * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
137 F_NPS_M, F_NPS_CORE, F_NPS_ALL.
138 (insert_nps_misc_imm_offset): New function.
139 (extract_nps_misc imm_offset): New function.
140 (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
141 (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
142
2253c8f0
AK		 1432017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
144
145 * s390-mkopc.c (main): Remove vx2 check.
146 * s390-opc.txt: Remove vx2 instruction flags.
147
645d3342
RZ		 1482017-03-21 Rinat Zelig <rinat@mellanox.com>
149
150 * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
151 * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
152 (insert_nps_imm_offset): New function.
153 (extract_nps_imm_offset): New function.
154 (insert_nps_imm_entry): New function.
155 (extract_nps_imm_entry): New function.
156
4b94dd2d
AM		 1572017-03-17 Alan Modra <amodra@gmail.com>
158
159 PR 21248
160 * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
161 mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after
162 those spr mnemonics they alias. Similarly for mtibatl, mtibatu.
163
b416fe87
KC		 1642017-03-14 Kito Cheng <kito.cheng@gmail.com>
165
166 * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
167 <c.andi>: Likewise.
168 <c.addiw> Likewise.
169
03b039a5
KC		 1702017-03-14 Kito Cheng <kito.cheng@gmail.com>
171
172 * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
173
2c232b83
AW		 1742017-03-13 Andrew Waterman <andrew@sifive.com>
175
176 * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
177 <srl> Likewise.
178 <srai> Likewise.
179 <sra> Likewise.
180
86fa6981
L		 1812017-03-09 H.J. Lu <hongjiu.lu@intel.com>
182
183 * i386-gen.c (opcode_modifiers): Replace S with Load.
184 * i386-opc.h (S): Removed.
185 (Load): New.
186 (i386_opcode_modifier): Replace s with load.
187 * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
188 and {evex}. Replace S with Load.
189 * i386-tbl.h: Regenerated.
190
c1fe188b
L		 1912017-03-09 H.J. Lu <hongjiu.lu@intel.com>
192
193 * i386-opc.tbl: Use CpuCET on rdsspq.
194 * i386-tbl.h: Regenerated.
195
4b8b687e
PB		 1962017-03-08 Peter Bergner <bergner@vnet.ibm.com>
197
198 * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
199 <vsx>: Do not use PPC_OPCODE_VSX3;
200
1437d063
PB		 2012017-03-08 Peter Bergner <bergner@vnet.ibm.com>
202
203 * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
204
603555e5
L		 2052017-03-06 H.J. Lu <hongjiu.lu@intel.com>
206
207 * i386-dis.c (REG_0F1E_MOD_3): New enum.
208 (MOD_0F1E_PREFIX_1): Likewise.
209 (MOD_0F38F5_PREFIX_2): Likewise.
210 (MOD_0F38F6_PREFIX_0): Likewise.
211 (RM_0F1E_MOD_3_REG_7): Likewise.
212 (PREFIX_MOD_0_0F01_REG_5): Likewise.
213 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
214 (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
215 (PREFIX_0F1E): Likewise.
216 (PREFIX_MOD_0_0FAE_REG_5): Likewise.
217 (PREFIX_0F38F5): Likewise.
218 (dis386_twobyte): Use PREFIX_0F1E.
219 (reg_table): Add REG_0F1E_MOD_3.
220 (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
221 PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
222 PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
223 PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
224 (three_byte_table): Use PREFIX_0F38F5.
225 (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
226 Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
227 (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
228 RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
229 PREFIX_MOD_3_0F01_REG_5_RM_2.
230 * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
231 (cpu_flags): Add CpuCET.
232 * i386-opc.h (CpuCET): New enum.
233 (CpuUnused): Commented out.
234 (i386_cpu_flags): Add cpucet.
235 * i386-opc.tbl: Add Intel CET instructions.
236 * i386-init.h: Regenerated.
237 * i386-tbl.h: Likewise.
238
73f07bff
AM		 2392017-03-06 Alan Modra <amodra@gmail.com>
240
241 PR 21124
242 * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
243 (extract_raq, extract_ras, extract_rbx): New functions.
244 (powerpc_operands): Use opposite corresponding insert function.
245 (Q_MASK): Define.
246 (powerpc_opcodes): Apply Q_MASK to all quad insns with even
247 register restriction.
248
65b48a81
PB		 2492017-02-28 Peter Bergner <bergner@vnet.ibm.com>
250
251 * disassemble.c Include "safe-ctype.h".
252 (disassemble_init_for_target): Handle s390 init.
253 (remove_whitespace_and_extra_commas): New function.
254 (disassembler_options_cmp): Likewise.
255 * arm-dis.c: Include "libiberty.h".
256 (NUM_ELEM): Delete.
257 (regnames): Use long disassembler style names.
258 Add force-thumb and no-force-thumb options.
259 (NUM_ARM_REGNAMES): Rename from this...
260 (NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE.
261 (get_arm_regname_num_options): Delete.
262 (set_arm_regname_option): Likewise.
263 (get_arm_regnames): Likewise.
264 (parse_disassembler_options): Likewise.
265 (parse_arm_disassembler_option): Rename from this...
266 (parse_arm_disassembler_options): ...to this. Make static.
267 Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
268 (print_insn): Use parse_arm_disassembler_options.
269 (disassembler_options_arm): New function.
270 (print_arm_disassembler_options): Handle updated regnames.
271 * ppc-dis.c: Include "libiberty.h".
272 (ppc_opts): Add "32" and "64" entries.
273 (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
274 (powerpc_init_dialect): Add break to switch statement.
275 Use new FOR_EACH_DISASSEMBLER_OPTION macro.
276 (disassembler_options_powerpc): New function.
277 (print_ppc_disassembler_options): Use ARRAY_SIZE.
278 Remove printing of "32" and "64".
279 * s390-dis.c: Include "libiberty.h".
280 (init_flag): Remove unneeded variable.
281 (struct s390_options_t): New structure type.
282 (options): New structure.
283 (init_disasm): Rename from this...
284 (disassemble_init_s390): ...to this. Add initializations for
285 current_arch_mask and option_use_insn_len_bits_p. Remove init_flag.
286 (print_insn_s390): Delete call to init_disasm.
287 (disassembler_options_s390): New function.
288 (print_s390_disassembler_options): Print using information from
289 struct 'options'.
290 * po/opcodes.pot: Regenerate.
291
15c7c1d8
JB		 2922017-02-28 Jan Beulich <jbeulich@suse.com>
293
294 * i386-dis.c (PCMPESTR_Fixup): New.
295 (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
296 (prefix_table): Use PCMPESTR_Fixup.
297 (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
298 PCMPESTR_Fixup.
299 (vex_w_table): Delete VPCMPESTR{I,M} entries.
300 * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
301 Split 64-bit and non-64-bit variants.
302 * opcodes/i386-tbl.h: Re-generate.
303
582e12bf
RS		 3042017-02-24 Richard Sandiford <richard.sandiford@arm.com>
305
306 * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
307 (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
308 (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
309 (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
310 (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
311 (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
312 (OP_SVE_V_HSD): New macros.
313 (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
314 (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
315 (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
316 (aarch64_opcode_table): Add new SVE instructions.
317 (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
318 for rotation operands. Add new SVE operands.
319 * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
320 (ins_sve_quad_index): Likewise.
321 (ins_imm_rotate): Split into...
322 (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
323 * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
324 (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
325 functions.
326 (aarch64_ins_sve_addr_ri_s4): New function.
327 (aarch64_ins_sve_quad_index): Likewise.
328 (do_misc_encoding): Handle "MOV Zn.Q, Qm".
329 * aarch64-asm-2.c: Regenerate.
330 * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
331 (ext_sve_quad_index): Likewise.
332 (ext_imm_rotate): Split into...
333 (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
334 * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
335 (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
336 functions.
337 (aarch64_ext_sve_addr_ri_s4): New function.
338 (aarch64_ext_sve_quad_index): Likewise.
339 (aarch64_ext_sve_index): Allow quad indices.
340 (do_misc_decoding): Likewise.
341 * aarch64-dis-2.c: Regenerate.
342 * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
343 aarch64_field_kinds.
344 (OPD_F_OD_MASK): Widen by one bit.
345 (OPD_F_NO_ZR): Bump accordingly.
346 (get_operand_field_width): New function.
347 * aarch64-opc.c (fields): Add new SVE fields.
348 (operand_general_constraint_met_p): Handle new SVE operands.
349 (aarch64_print_operand): Likewise.
350 * aarch64-opc-2.c: Regenerate.
351
f482d304
RS		 3522017-02-24 Richard Sandiford <richard.sandiford@arm.com>
353
354 * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
355 (aarch64_feature_compnum): ...this.
356 (SIMD_V8_3): Replace with...
357 (COMPNUM): ...this.
358 (CNUM_INSN): New macro.
359 (aarch64_opcode_table): Use it for the complex number instructions.
360
7db2c588
JB		 3612017-02-24 Jan Beulich <jbeulich@suse.com>
362
363 * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
364
1e9d41d4
SL		 3652017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
366
367 Add support for associating SPARC ASIs with an architecture level.
368 * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
369 * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
370 decoding of SPARC ASIs.
371
53c4d625
JB		 3722017-02-23 Jan Beulich <jbeulich@suse.com>
373
374 * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
375 82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
376
11648de5
JB		 3772017-02-21 Jan Beulich <jbeulich@suse.com>
378
379 * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
380 1 (instead of to itself). Correct typo.
381
f98d33be
AW		 3822017-02-14 Andrew Waterman <andrew@sifive.com>
383
384 * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
385 pseudoinstructions.
386
773fb663
RS		 3872017-02-15 Richard Sandiford <richard.sandiford@arm.com>
388
389 * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
390 (aarch64_sys_reg_supported_p): Handle them.
391
cc07cda6
CZ		 3922017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
393
394 * arc-opc.c (UIMM6_20R): Define.
395 (SIMM12_20): Use above.
396 (SIMM12_20R): Define.
397 (SIMM3_5_S): Use above.
398 (UIMM7_A32_11R_S): Define.
399 (UIMM7_9_S): Use above.
400 (UIMM3_13R_S): Define.
401 (SIMM11_A32_7_S): Use above.
402 (SIMM9_8R): Define.
403 (UIMM10_A32_8_S): Use above.
404 (UIMM8_8R_S): Define.
405 (W6): Use above.
406 (arc_relax_opcodes): Use all above defines.
407
66a5a740
VG		 4082017-02-15 Vineet Gupta <vgupta@synopsys.com>
409
410 * arc-regs.h: Distinguish some of the registers different on
411 ARC700 and HS38 cpus.
412
7e0de605
AM		 4132017-02-14 Alan Modra <amodra@gmail.com>
414
415 PR 21118
416 * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
417 with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
418
54064fdb
AM		 4192017-02-11 Stafford Horne <shorne@gmail.com>
420 Alan Modra <amodra@gmail.com>
421
422 * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
423 Use insn_bytes_value and insn_int_value directly instead. Don't
424 free allocated memory until function exit.
425
dce75bf9
NP		 4262017-02-10 Nicholas Piggin <npiggin@gmail.com>
427
428 * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
429
1b7e3d2f
NC		 4302017-02-03 Nick Clifton <nickc@redhat.com>
431
432 PR 21096
433 * aarch64-opc.c (print_register_list): Ensure that the register
434 list index will fir into the tb buffer.
435 (print_register_offset_address): Likewise.
436 * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
437
8ec5cf65
AD		 4382017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
439
440 PR 21056
441 * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
442 instructions when the previous fetch packet ends with a 32-bit
443 instruction.
444
a1aa5e81
DD		 4452017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
446
447 * pru-opc.c: Remove vague reference to a future GDB port.
448
add3afb2
NC		 4492017-01-20 Nick Clifton <nickc@redhat.com>
450
451 * po/ga.po: Updated Irish translation.
452
c13a63b0
SN		 4532017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
454
455 * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
456
9608051a
YQ		 4572017-01-13 Yao Qi <yao.qi@linaro.org>
458
459 * m68k-dis.c (match_insn_m68k): Extend comments. Return -1
460 if FETCH_DATA returns 0.
461 (m68k_scan_mask): Likewise.
462 (print_insn_m68k): Update code to handle -1 return value.
463
f622ea96
YQ		 4642017-01-13 Yao Qi <yao.qi@linaro.org>
465
466 * m68k-dis.c (enum print_insn_arg_error): New.
467 (NEXTBYTE): Replace -3 with
468 PRINT_INSN_ARG_MEMORY_ERROR.
469 (NEXTULONG): Likewise.
470 (NEXTSINGLE): Likewise.
471 (NEXTDOUBLE): Likewise.
472 (NEXTDOUBLE): Likewise.
473 (NEXTPACKED): Likewise.
474 (FETCH_ARG): Likewise.
475 (FETCH_DATA): Update comments.
476 (print_insn_arg): Update comments. Replace magic numbers with
477 enum.
478 (match_insn_m68k): Likewise.
479
620214f7
IT		 4802017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
481
482 * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
483 * i386-dis-evex.h (evex_table): Updated.
484 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
485 CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
486 (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
487 * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
488 (i386_cpu_flags): Add cpuavx512_vpopcntdq.
489 * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
490 * i386-init.h: Regenerate.
491 * i386-tbl.h: Ditto.
492
d95014a2
YQ		 4932017-01-12 Yao Qi <yao.qi@linaro.org>
494
495 * msp430-dis.c (msp430_singleoperand): Return -1 if
496 msp430dis_opcode_signed returns false.
497 (msp430_doubleoperand): Likewise.
498 (msp430_branchinstr): Return -1 if
499 msp430dis_opcode_unsigned returns false.
500 (msp430x_calla_instr): Likewise.
501 (print_insn_msp430): Likewise.
502
0ae60c3e
NC		 5032017-01-05 Nick Clifton <nickc@redhat.com>
504
505 PR 20946
506 * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
507 could not be matched.
508 (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
509 NULL.
510
d74d4880
SN		 5112017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
512
513 * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
514 (aarch64_opcode_table): Use RCPC_INSN.
515
cc917fd9
KC		 5162017-01-03 Kito Cheng <kito.cheng@gmail.com>
517
518 * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
519 extension.
520 * riscv-opcodes/all-opcodes: Likewise.
521
b52d3cfc
DP		 5222017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
523
524 * riscv-dis.c (print_insn_args): Add fall through comment.
525
f90c58d5
NC		 5262017-01-03 Nick Clifton <nickc@redhat.com>
527
528 * po/sr.po: New Serbian translation.
529 * configure.ac (ALL_LINGUAS): Add sr.
530 * configure: Regenerate.
531
f47b0d4a
AM		 5322017-01-02 Alan Modra <amodra@gmail.com>
533
534 * epiphany-desc.h: Regenerate.
535 * epiphany-opc.h: Regenerate.
536 * fr30-desc.h: Regenerate.
537 * fr30-opc.h: Regenerate.
538 * frv-desc.h: Regenerate.
539 * frv-opc.h: Regenerate.
540 * ip2k-desc.h: Regenerate.
541 * ip2k-opc.h: Regenerate.
542 * iq2000-desc.h: Regenerate.
543 * iq2000-opc.h: Regenerate.
544 * lm32-desc.h: Regenerate.
545 * lm32-opc.h: Regenerate.
546 * m32c-desc.h: Regenerate.
547 * m32c-opc.h: Regenerate.
548 * m32r-desc.h: Regenerate.
549 * m32r-opc.h: Regenerate.
550 * mep-desc.h: Regenerate.
551 * mep-opc.h: Regenerate.
552 * mt-desc.h: Regenerate.
553 * mt-opc.h: Regenerate.
554 * or1k-desc.h: Regenerate.
555 * or1k-opc.h: Regenerate.
556 * xc16x-desc.h: Regenerate.
557 * xc16x-opc.h: Regenerate.
558 * xstormy16-desc.h: Regenerate.
559 * xstormy16-opc.h: Regenerate.
560
2571583a
AM		 5612017-01-02 Alan Modra <amodra@gmail.com>
562
563 Update year range in copyright notice of all files.
564
5c1ad6b5 565For older changes see ChangeLog-2016
3499769a 566\f
5c1ad6b5 567Copyright (C) 2017 Free Software Foundation, Inc.
3499769a
AM		 568
569Copying and distribution of this file, with or without modification,
570are permitted in any medium without royalty provided the copyright
571notice and this notice are preserved.
572
573Local Variables:
574mode: change-log
575left-margin: 8
576fill-column: 74
577version-control: never
578End:
GDB Binutils - Deliverables
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