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[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
b40d5eb9
AK		 12008-09-26 Florian Krohm <fkrohm@us.ibm.com>
2
3 * s390-opc.txt (thder, thdr): Change RRE_RR to RRE_FF.
4 (cfxr, cfdr, cfer, clclu): Add esa flag.
5 (sqd): Instruction added.
6 (qadtr, qaxtr): Change RRF_FFFU to RRF_FUFF.
7 * s390-opc.c: (INSTR_RRF_FFFU, MASK_RRF_FFFU): Removed.
8
d0411736
AM		 92008-09-14 Arnold Metselaar <arnold.metselaar@planet.nl>
10
11 * z80-dis.c (prt_rr_nn): Fix register pair for two byte opcodes.
12 (tab_elt opc_ed): Add "ld r,a" and "ld r,a" instructions.
13
3e126784
L		 142008-09-11 H.J. Lu <hongjiu.lu@intel.com>
15
16 * i386-opc.tbl: Fix memory operand size for cmpXXXs[sd].
17 * i386-tbl.h: Regenerated.
18
ddab3d59
JB		 192008-08-28 Jan Beulich <jbeulich@novell.com>
20
21 * i386-dis.c (dis386): Adjust far return mnemonics.
22 * i386-opc.tbl: Add retf.
23 * i386-tbl.h: Re-generate.
24
b19d5385
JB		 252008-08-28 Jan Beulich <jbeulich@novell.com>
26
27 * i386-dis.c (dis386_twobyte): Adjust cmovXX mnemonics.
28
1ca35711
L		 292008-08-28 H.J. Lu <hongjiu.lu@intel.com>
30
31 * ia64-dis.c (print_insn_ia64): Handle cr.iib0 and cr.iib1.
32 * ia64-gen.c (lookup_specifier): Likewise.
33
34 * ia64-ic.tbl: Add support for cr.iib0 and cr.iib1.
35 * ia64-raw.tbl: Likewise.
36 * ia64-waw.tbl: Likewise.
37 * ia64-asmtab.c: Regenerated.
38
515c56e7
L		 392008-08-27 H.J. Lu <hongjiu.lu@intel.com>
40
41 * i386-opc.tbl: Correct fidivr operand size.
42
43 * i386-tbl.h: Regenerated.
44
da594c4a
AM		 452008-08-24 Alan Modra <amodra@bigpond.net.au>
46
47 * configure.in: Update a number of obsolete autoconf macros.
48 * aclocal.m4: Regenerate.
49
a5ff0eb2
L		 502008-08-20 H.J. Lu <hongjiu.lu@intel.com>
51
52 AVX Programming Reference (August, 2008)
53 * i386-dis.c (PREFIX_VEX_38DB): New.
54 (PREFIX_VEX_38DC): Likewise.
55 (PREFIX_VEX_38DD): Likewise.
56 (PREFIX_VEX_38DE): Likewise.
57 (PREFIX_VEX_38DF): Likewise.
58 (PREFIX_VEX_3ADF): Likewise.
59 (VEX_LEN_38DB_P_2): Likewise.
60 (VEX_LEN_38DC_P_2): Likewise.
61 (VEX_LEN_38DD_P_2): Likewise.
62 (VEX_LEN_38DE_P_2): Likewise.
63 (VEX_LEN_38DF_P_2): Likewise.
64 (VEX_LEN_3ADF_P_2): Likewise.
65 (PREFIX_VEX_3A04): Updated.
66 (VEX_LEN_3A06_P_2): Likewise.
67 (prefix_table): Add PREFIX_VEX_38DB, PREFIX_VEX_38DC,
68 PREFIX_VEX_38DD, PREFIX_VEX_38DE and PREFIX_VEX_3ADF.
69 (x86_64_table): Likewise.
70 (vex_len_table): Add VEX_LEN_38DB_P_2, VEX_LEN_38DC_P_2,
71 VEX_LEN_38DD_P_2, VEX_LEN_38DE_P_2, VEX_LEN_38DF_P_2 and
72 VEX_LEN_3ADF_P_2.
73
74 * i386-opc.tbl: Add AES + AVX instructions.
75 * i386-init.h: Regenerated.
76 * i386-tbl.h: Likewise.
77
7dc6076f
AK		 782008-08-15 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
79
80 * s390-opc.c (INSTR_RRF_FFRU, MASK_RRF_FFRU): New instruction format.
81 * s390-opc.txt (lxr, rrdtr, rrxtr): Fix instruction format.
82
7357c5b6
AM		 832008-08-15 Alan Modra <amodra@bigpond.net.au>
84
85 PR 6526
86 * configure.in: Invoke AC_USE_SYSTEM_EXTENSIONS.
87 * Makefile.in: Regenerate.
88 * aclocal.m4: Regenerate.
89 * config.in: Regenerate.
90 * configure: Regenerate.
91
899d85be
AM		 922008-08-14 Sebastian Huber <sebastian.huber@embedded-brains.de>
93
94 PR 6825
95 * ppc-opc.c (powerpc_opcodes): Enable rfci, mfpmr, mtpmr for e300.
96
dfb07592
L		 972008-08-12 H.J. Lu <hongjiu.lu@intel.com>
98
99 * i386-opc.tbl: Add syscall and sysret for Cpu64.
100
101 * i386-tbl.h: Regenerated.
102
323ee3f4
AM		 1032008-08-04 Alan Modra <amodra@bigpond.net.au>
104
105 * Makefile.am (POTFILES.in): Set LC_ALL=C.
106 * Makefile.in: Regenerate.
107 * po/POTFILES.in: Regenerate.
108
9b4e5766
PB		 1092008-08-01 Peter Bergner <bergner@vnet.ibm.com>
110
111 * ppc-dis.c (powerpc_init_dialect): Handle power7 and vsx options.
112 (print_insn_powerpc): Prepend 'vs' when printing VSX registers.
113 (print_ppc_disassembler_options): Document -Mpower7 and -Mvsx.
114 * ppc-opc.c (insert_xt6): New static function.
115 (extract_xt6): Likewise.
116 (insert_xa6): Likewise.
117 (extract_xa6: Likewise.
118 (insert_xb6): Likewise.
119 (extract_xb6): Likewise.
120 (insert_xb6s): Likewise.
121 (extract_xb6s): Likewise.
122 (XS6, XT6, XA6, XB6, XB6S, DM, XX3, XX3DM, XX1_MASK, XX3_MASK,
123 XX3DM_MASK, PPCVSX): New.
124 (powerpc_opcodes): Add opcodes "lxvd2x", "lxvd2ux", "stxvd2x",
125 "stxvd2ux", "xxmrghd", "xxmrgld", "xxpermdi", "xvmovdp", "xvcpsgndp".
126
20fd6e2e
PA		 1272008-08-01 Pedro Alves <pedro@codesourcery.com>
128
129 * Makefile.am ($(srcdir)/ia64-asmtab.c): Remove line continuation.
130 * Makefile.in: Regenerate.
131
a656ed5b
L		 1322008-08-01 H.J. Lu <hongjiu.lu@intel.com>
133
134 * i386-reg.tbl: Use Dw2Inval on AVX registers.
135 * i386-tbl.h: Regenerated.
136
081ba1b3
AM		 1372008-07-30 Michael J. Eager <eager@eagercon.com>
138
139 * ppc-dis.c (print_insn_powerpc): Disassemble FSL/FCR/UDI fields.
140 * ppc-opc.c (powerpc_operands): Add Xilinx APU related operands.
141 (insert_sprg, PPC405): Use PPC_OPCODE_405.
142 (powerpc_opcodes): Add Xilinx APU related opcodes.
143
0af1713e
AM		 1442008-07-30 Alan Modra <amodra@bigpond.net.au>
145
146 * bfin-dis.c, cris-dis.c, i386-dis.c, or32-opc.c: Silence gcc warnings.
147
30c09090
RS		 1482008-07-10 Richard Sandiford <rdsandiford@googlemail.com>
149
150 * mips-dis.c (_print_insn_mips): Use ELF_ST_IS_MIPS16.
151
c27e721e
AN		 1522008-07-07 Adam Nemet <anemet@caviumnetworks.com>
153
154 * mips-opc.c (CP): New macro.
155 (mips_builtin_opcodes): Mark c0, c2 and c3 as CP. Add Octeon to the
156 membership of di, dmfc0, dmtc0, ei, mfc0 and mtc0. Add dmfc2 and
157 dmtc2 Octeon instructions.
158
bd2e2557
SS		 1592008-07-07 Stan Shebs <stan@codesourcery.com>
160
161 * dis-init.c (init_disassemble_info): Init endian_code field.
162 * arm-dis.c (print_insn): Disassemble code according to
163 setting of endian_code.
164 (print_insn_big_arm): Detect when BE8 extension flag has been set.
165
6ba2a415
RS		 1662008-06-30 Richard Sandiford <rdsandiford@googlemail.com>
167
168 * mips-dis.c (_print_insn_mips): Use bfd_asymbol_flavour to check
169 for ELF symbols.
170
c8187e15
PB		 1712008-06-25 Peter Bergner <bergner@vnet.ibm.com>
172
173 * ppc-dis.c (powerpc_init_dialect): Handle -M464.
174 (print_ppc_disassembler_options): Likewise.
175 * ppc-opc.c (PPC464): Define.
176 (powerpc_opcodes): Add mfdcrux and mtdcrux.
177
7a283e07
RW		 1782008-06-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
179
180 * configure: Regenerate.
181
fa452fa6
PB		 1822008-06-13 Peter Bergner <bergner@vnet.ibm.com>
183
184 * ppc-dis.c (print_insn_powerpc): Update prototye to use new
185 ppc_cpu_t typedef.
186 (struct dis_private): New.
187 (POWERPC_DIALECT): New define.
188 (powerpc_dialect): Renamed to...
189 (powerpc_init_dialect): This. Update to use ppc_cpu_t and
190 struct dis_private.
191 (print_insn_big_powerpc): Update for using structure in
192 info->private_data.
193 (print_insn_little_powerpc): Likewise.
194 (operand_value_powerpc): Change type of dialect param to ppc_cpu_t.
195 (skip_optional_operands): Likewise.
196 (print_insn_powerpc): Likewise. Remove initialization of dialect.
197 * ppc-opc.c (extract_bat, extract_bba, extract_bdm, extract_bdp,
198 extract_bo, extract_boe, extract_fxm, extract_mb6, extract_mbe,
199 extract_nb, extract_nsi, extract_rbs, extract_sh6, extract_spr,
200 extract_sprg, extract_tbr insert_bat, insert_bba, insert_bdm,
201 insert_bdp, insert_bo, insert_boe, insert_fxm, insert_mb6, insert_mbe,
202 insert_nsi, insert_ral, insert_ram, insert_raq, insert_ras, insert_rbs,
203 insert_sh6, insert_spr, insert_sprg, insert_tbr): Change the dialect
204 param to be of type ppc_cpu_t. Update prototype.
205
bb35fb24
NC		 2062008-06-12 Adam Nemet <anemet@caviumnetworks.com>
207
208 * mips-dis.c (print_insn_args): Handle field descriptors +x, +p,
209 +s, +S.
210 * mips-opc.c (mips_builtin_opcodes): Add Octeon instructions
211 baddu, bbit*, cins*, dmul, pop, dpop, exts*, mtm*, mtp*, syncs,
212 syncw, syncws, vm3mulu, vm0 and vmulu.
213
dd3cbb7e
NC		 214 * mips-dis.c (print_insn_args): Handle field descriptor +Q.
215 * mips-opc.c (mips_builtin_opcodes): Add Octeon instructions seq,
216 seqi, sne and snei.
217
a5dabbb0
L		 2182008-05-30 H.J. Lu <hongjiu.lu@intel.com>
219
220 * i386-opc.tbl: Add vmovd with 64bit operand.
221 * i386-tbl.h: Regenerated.
222
725a9891
MS		 2232008-05-27 Martin Schwidefsky <schwidefsky@de.ibm.com>
224
225 * s390-opc.c (INSTR_RRF_R0RR): Fix RRF_R0RR operand format.
226
cbc80391
L		 2272008-05-22 H.J. Lu <hongjiu.lu@intel.com>
228
229 * i386-opc.tbl: Add NoAVX to cvtpd2pi, cvtpi2pd and cvttpd2pi.
230 * i386-tbl.h: Regenerated.
231
116615c5
L		 2322008-05-22 H.J. Lu <hongjiu.lu@intel.com>
233
234 PR gas/6517
235 * i386-opc.tbl: Break cvtsi2ss/cvtsi2sd/vcvtsi2sd/vcvtsi2ss
236 into 32bit and 64bit. Remove Reg64|Qword and add
237 IgnoreSize|No_qSuf on 32bit version.
238 * i386-tbl.h: Regenerated.
239
d9479f2d
L		 2402008-05-21 H.J. Lu <hongjiu.lu@intel.com>
241
242 * i386-opc.tbl: Add NoAVX to movdq2q and movq2dq.
243 * i386-tbl.h: Regenerated.
244
3ce6fddb
NC		 2452008-05-21 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
246
247 * cr16-dis.c (build_mask): Adjust the mask for 32-bit bcond.
248
8944f3c2
AM		 2492008-05-14 Alan Modra <amodra@bigpond.net.au>
250
251 * Makefile.am: Run "make dep-am".
252 * Makefile.in: Regenerate.
253
f1f8f695
L		 2542008-05-02 H.J. Lu <hongjiu.lu@intel.com>
255
256 * i386-dis.c (MOVBE_Fixup): New.
257 (Mo): Likewise.
258 (PREFIX_0F3880): Likewise.
259 (PREFIX_0F3881): Likewise.
260 (PREFIX_0F38F0): Updated.
261 (prefix_table): Add PREFIX_0F3880 and PREFIX_0F3881. Update
262 PREFIX_0F38F0 and PREFIX_0F38F1 for movbe.
263 (three_byte_table): Use PREFIX_0F3880 and PREFIX_0F3881.
264
265 * i386-gen.c (cpu_flag_init): Add CPU_MOVBE_FLAGS and
266 CPU_EPT_FLAGS.
267 (cpu_flags): Add CpuMovbe and CpuEPT.
268
269 * i386-opc.h (CpuMovbe): New.
270 (CpuEPT): Likewise.
271 (CpuLM): Updated.
272 (i386_cpu_flags): Add cpumovbe and cpuept.
273
274 * i386-opc.tbl: Add entries for movbe and EPT instructions.
275 * i386-init.h: Regenerated.
276 * i386-tbl.h: Likewise.
277
89aa3097
AN		 2782008-04-29 Adam Nemet <anemet@caviumnetworks.com>
279
280 * mips-opc.c (mips_builtin_opcodes): Set field `match' to 0 for
281 the two drem and the two dremu macros.
282
39c5c168
AN		 2832008-04-28 Adam Nemet <anemet@caviumnetworks.com>
284
285 * mips-opc.c (mips_builtin_opcodes): Mark prefx and c1
286 instructions FP_S. Mark l.s, li.s, lwc1, swc1, s.s, trunc.w.s and
287 cop1 macros INSN2_M_FP_S. Mark l.d, li.d, ldc1 and sdc1 macros
288 INSN2_M_FP_D. Mark trunc.w.d macro INSN2_M_FP_S and INSN2_M_FP_D.
289
f04d18b7
DM		 2902008-04-25 David S. Miller <davem@davemloft.net>
291
292 * sparc-dis.c: Emit %stick instead of %sys_tick, and %stick_cmpr
293 instead of %sys_tick_cmpr, as suggested in architecture manuals.
294
6194aaab
L		 2952008-04-23 Paolo Bonzini <bonzini@gnu.org>
296
297 * aclocal.m4: Regenerate.
298 * configure: Regenerate.
299
1a6b486f
DM		 3002008-04-23 David S. Miller <davem@davemloft.net>
301
302 * sparc-opc.c (asi_table): Add UltraSPARC and Niagara
303 extended values.
304 (prefetch_table): Add missing values.
305
81f8a913
L		 3062008-04-22 H.J. Lu <hongjiu.lu@intel.com>
307
308 * i386-gen.c (opcode_modifiers): Add NoAVX.
309
310 * i386-opc.h (NoAVX): New.
311 (OldGcc): Updated.
312 (i386_opcode_modifier): Add noavx.
313
314 * i386-opc.tbl: Add NoAVX to SSE, SSE2, SSE3 and SSSE3
315 instructions which don't have AVX equivalent.
316 * i386-tbl.h: Regenerated.
317
dae39acc
L		 3182008-04-18 H.J. Lu <hongjiu.lu@intel.com>
319
320 * i386-dis.c (OP_VEX_FMA): New.
321 (OP_EX_VexImmW): Likewise.
322 (VexFMA): Likewise.
323 (Vex128FMA): Likewise.
324 (EXVexImmW): Likewise.
325 (get_vex_imm8): Likewise.
326 (OP_EX_VexReg): Likewise.
327 (vex_i4_done): Renamed to ...
328 (vex_w_done): This.
329 (prefix_table): Replace EXVexW with EXVexImmW on vpermil2ps
330 and vpermil2pd. Replace Vex/Vex128 with VexFMA/Vex128FMA on
331 FMA instructions.
332 (print_insn): Updated.
333 (OP_EX_VexW): Rewrite to swap register in VEX with EX.
334 (OP_REG_VexI4): Check invalid high registers.
335
ce886ab1
DR		 3362008-04-16 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
337 Michael Meissner <michael.meissner@amd.com>
338
339 * i386-opc.tbl: Fix protX to allow memory in the middle operand.
340 * i386-tbl.h: Regenerate from i386-opc.tbl.
8944f3c2 341
19a6653c
AM		 3422008-04-14 Edmar Wienskoski <edmar@freescale.com>
343
344 * ppc-dis.c (powerpc_dialect): Handle "e500mc". Extend "e500" to
345 accept Power E500MC instructions.
346 (print_ppc_disassembler_options): Document -Me500mc.
347 * ppc-opc.c (DUIS, DUI, T): New.
348 (XRT, XRTRA): Likewise.
349 (E500MC): Likewise.
350 (powerpc_opcodes): Add new Power E500MC instructions.
351
112b7c50
AK		 3522008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
353
354 * s390-dis.c (init_disasm): Evaluate disassembler_options.
355 (print_s390_disassembler_options): New function.
356 * disassemble.c (disassembler_usage): Invoke
357 print_s390_disassembler_options.
358
7ff42648
AK		 3592008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
360
361 * s390-mkopc.c (insertExpandedMnemonic): Expand string sizes
362 of local variables used for mnemonic parsing: prefix, suffix and
363 number.
364
45a5551e
AK		 3652008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
366
367 * s390-mkopc.c (s390_cond_ext_format): Add back the mnemonic
368 extensions for conditional jumps (o, p, m, nz, z, nm, np, no).
369 (s390_crb_extensions): New extensions table.
370 (insertExpandedMnemonic): Handle '$' tag.
371 * s390-opc.txt: Remove conditional jump variants which can now
372 be expanded automatically.
373 Replace '*' tag with '$' in the compare and branch instructions.
374
06c8514a
L		 3752008-04-07 H.J. Lu <hongjiu.lu@intel.com>
376
377 * i386-dis.c (PREFIX_VEX_38XX): Add a tab.
378 (PREFIX_VEX_3AXX): Likewis.
379
b122c285
L		 3802008-04-07 H.J. Lu <hongjiu.lu@intel.com>
381
382 * i386-opc.tbl: Remove 4 extra blank lines.
383
594ab6a3
L		 3842008-04-04 H.J. Lu <hongjiu.lu@intel.com>
385
386 * i386-gen.c (cpu_flag_init): Replace CPU_CLMUL_FLAGS/CpuCLMUL
387 with CPU_PCLMUL_FLAGS/CpuPCLMUL.
388 (cpu_flags): Replace CpuCLMUL with CpuPCLMUL.
389 * i386-opc.tbl: Likewise.
390
391 * i386-opc.h (CpuCLMUL): Renamed to ...
392 (CpuPCLMUL): This.
393 (CpuFMA): Updated.
394 (i386_cpu_flags): Replace cpuclmul with cpupclmul.
395
396 * i386-init.h: Regenerated.
397
c0f3af97
L		 3982008-04-03 H.J. Lu <hongjiu.lu@intel.com>
399
400 * i386-dis.c (OP_E_register): New.
401 (OP_E_memory): Likewise.
402 (OP_VEX): Likewise.
403 (OP_EX_Vex): Likewise.
404 (OP_EX_VexW): Likewise.
405 (OP_XMM_Vex): Likewise.
406 (OP_XMM_VexW): Likewise.
407 (OP_REG_VexI4): Likewise.
408 (PCLMUL_Fixup): Likewise.
409 (VEXI4_Fixup): Likewise.
410 (VZERO_Fixup): Likewise.
411 (VCMP_Fixup): Likewise.
412 (VPERMIL2_Fixup): Likewise.
413 (rex_original): Likewise.
414 (rex_ignored): Likewise.
415 (Mxmm): Likewise.
416 (XMM): Likewise.
417 (EXxmm): Likewise.
418 (EXxmmq): Likewise.
419 (EXymmq): Likewise.
420 (Vex): Likewise.
421 (Vex128): Likewise.
422 (Vex256): Likewise.
423 (VexI4): Likewise.
424 (EXdVex): Likewise.
425 (EXqVex): Likewise.
426 (EXVexW): Likewise.
427 (EXdVexW): Likewise.
428 (EXqVexW): Likewise.
429 (XMVex): Likewise.
430 (XMVexW): Likewise.
431 (XMVexI4): Likewise.
432 (PCLMUL): Likewise.
433 (VZERO): Likewise.
434 (VCMP): Likewise.
435 (VPERMIL2): Likewise.
436 (xmm_mode): Likewise.
437 (xmmq_mode): Likewise.
438 (ymmq_mode): Likewise.
439 (vex_mode): Likewise.
440 (vex128_mode): Likewise.
441 (vex256_mode): Likewise.
442 (USE_VEX_C4_TABLE): Likewise.
443 (USE_VEX_C5_TABLE): Likewise.
444 (USE_VEX_LEN_TABLE): Likewise.
445 (VEX_C4_TABLE): Likewise.
446 (VEX_C5_TABLE): Likewise.
447 (VEX_LEN_TABLE): Likewise.
448 (REG_VEX_XX): Likewise.
449 (MOD_VEX_XXX): Likewise.
450 (PREFIX_0F38DB..PREFIX_0F38DF): Likewise.
451 (PREFIX_0F3A44): Likewise.
452 (PREFIX_0F3ADF): Likewise.
453 (PREFIX_VEX_XXX): Likewise.
454 (VEX_OF): Likewise.
455 (VEX_OF38): Likewise.
456 (VEX_OF3A): Likewise.
457 (VEX_LEN_XXX): Likewise.
458 (vex): Likewise.
459 (need_vex): Likewise.
460 (need_vex_reg): Likewise.
461 (vex_i4_done): Likewise.
462 (vex_table): Likewise.
463 (vex_len_table): Likewise.
464 (OP_REG_VexI4): Likewise.
465 (vex_cmp_op): Likewise.
466 (pclmul_op): Likewise.
467 (vpermil2_op): Likewise.
468 (m_mode): Updated.
469 (es_reg): Likewise.
470 (PREFIX_0F38F0): Likewise.
471 (PREFIX_0F3A60): Likewise.
472 (reg_table): Add REG_VEX_71...REG_VEX_73 and REG_VEX_AE.
473 (prefix_table): Add PREFIX_0F38DB..PREFIX_0F38DF, PREFIX_0F3ADF
474 and PREFIX_VEX_XXX entries.
475 (x86_64_table): Use VEX_C4_TABLE and VEX_C5_TABLE.
476 (three_byte_table): Use PREFIX_0F38DB..PREFIX_0F38DF and
477 PREFIX_0F3ADF.
478 (mod_table): Use VEX_C4_TABLE, VEX_C5_TABLE and VEX_LEN_TABLE.
479 Add MOD_VEX_XXX entries.
480 (ckprefix): Initialize rex_original and rex_ignored. Store the
481 REX byte in rex_original.
482 (get_valid_dis386): Handle the implicit prefix in VEX prefix
483 bytes and USE_VEX_LEN_TABLE/USE_VEX_C4_TABLE/USE_VEX_C5_TABLE.
484 (print_insn): Set need_vex/need_vex_reg/vex_i4_done to 0 before
485 calling get_valid_dis386. Use rex_original and rex_ignored when
486 printing out REX.
487 (putop): Handle "XY".
488 (intel_operand_size): Handle VEX, xmm_mode, xmmq_mode and
489 ymmq_mode.
490 (OP_E_extended): Updated to use OP_E_register and
491 OP_E_memory.
492 (OP_XMM): Handle VEX.
493 (OP_EX): Likewise.
494 (XMM_Fixup): Likewise.
495 (CMP_Fixup): Use ARRAY_SIZE.
496
497 * i386-gen.c (cpu_flag_init): Add CpuAES, CPU_CLMUL_FLAGS,
498 CPU_FMA_FLAGS and CPU_AVX_FLAGS.
499 (operand_type_init): Add OPERAND_TYPE_REGYMM and
500 OPERAND_TYPE_VEX_IMM4.
501 (cpu_flags): Add CpuAVX, CpuAES, CpuCLMUL and CpuFMA.
502 (opcode_modifiers): Add Implicit1stXmm0, Vex, Vex256, VexNDD,
503 VexNDS, VexW0, VexW1, Vex0F, Vex0F38, Vex0F3A, Vex3Sources,
504 VexImmExt and SSE2AVX.
505 (operand_types): Add RegYMM, Ymmword and Vex_Imm4.
506
507 * i386-opc.h (CpuAVX): New.
508 (CpuAES): Likewise.
509 (CpuCLMUL): Likewise.
510 (CpuFMA): Likewise.
511 (Vex): Likewise.
512 (Vex256): Likewise.
513 (VexNDS): Likewise.
514 (VexNDD): Likewise.
515 (VexW0): Likewise.
516 (VexW1): Likewise.
517 (Vex0F): Likewise.
518 (Vex0F38): Likewise.
519 (Vex0F3A): Likewise.
520 (Vex3Sources): Likewise.
521 (VexImmExt): Likewise.
522 (SSE2AVX): Likewise.
523 (RegYMM): Likewise.
524 (Ymmword): Likewise.
525 (Vex_Imm4): Likewise.
526 (Implicit1stXmm0): Likewise.
527 (CpuXsave): Updated.
528 (CpuLM): Likewise.
529 (ByteOkIntel): Likewise.
530 (OldGcc): Likewise.
531 (Control): Likewise.
532 (Unspecified): Likewise.
533 (OTMax): Likewise.
534 (i386_cpu_flags): Add cpuavx, cpuaes, cpuclmul and cpufma.
535 (i386_opcode_modifier): Add implicit1stxmm0, vex, vex256,
536 vexnds, vexndd, vexw0, vexw1, vex0f, vex0f38, vex0f3a,
537 vex3sources, veximmext and sse2avx.
538 (i386_operand_type): Add regymm, ymmword and vex_imm4.
539
540 * i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions.
541
542 * i386-reg.tbl: Add AVX registers, ymm0..ymm15.
543
544 * i386-init.h: Regenerated.
545 * i386-tbl.h: Likewise.
546
b21c9cb4
BS		 5472008-03-26 Bernd Schmidt <bernd.schmidt@analog.com>
548
549 From Robin Getz <robin.getz@analog.com>
550 * bfin-dis.c (bu32): Typedef.
551 (enum const_forms_t): Add c_uimm32 and c_huimm32.
552 (constant_formats[]): Add uimm32 and huimm16.
553 (fmtconst_val): New.
554 (uimm32): Define.
555 (huimm32): Define.
556 (imm16_val): Define.
557 (luimm16_val): Define.
558 (struct saved_state): Define.
559 (GREG, DPREG, DREG, PREG, SPREG, FPREG, IREG, MREG, BREG, LREG,
560 A0XREG, A0WREG, A1XREG, A1WREG,CCREG, LC0REG, LT0REG, LB0REG,
561 LC1REG, LT1REG, LB1REG, RETSREG, PCREG): Define.
562 (get_allreg): New.
563 (decode_LDIMMhalf_0): Print out the whole register value.
564
ee171c8f
BS		 565 From Jie Zhang <jie.zhang@analog.com>
566 * bfin-dis.c (decode_dsp32mac_0): Decode (IU) option for
567 multiply and multiply-accumulate to data register instruction.
568
086134ec
BS		 569 * bfin-dis.c: (c_uimm4s4d, c_imm5d, c_imm7d, c_imm16d, c_uimm16s4d,
570 c_imm32, c_huimm32e): Define.
571 (constant_formats): Add flags for printing decimal, leading spaces, and
572 exact symbols.
573 (comment, parallel): Add global flags in all disassembly.
574 (fmtconst): Take advantage of new flags, and print default in hex.
575 (fmtconst_val): Likewise.
576 (decode_macfunc): Be consistant with spaces, tabs, comments,
577 capitalization in disassembly, fix minor coding style issues.
578 (reg_names, amod0, amod1, amod0amod2, aligndir, get_allreg): Likewise.
579 (decode_ProgCtrl_0, decode_PushPopMultiple_0, decode_CCflag_0,
580 decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0,
581 decode_REGMV_0, decode_ALU2op_0, decode_PTR2op_0, decode_LOGI2op_0,
582 decode_COMP3op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
583 decode_LDSTpmod_0, decode_dagMODim_0, decode_dagMODik_0,
584 decode_dspLDST_0, decode_LDST_0, decode_LDSTiiFP_0, decode_LDSTii_0,
585 decode_LoopSetup_0, decode_LDIMMhalf_0, decode_CALLa_0,
586 decode_LDSTidxI_0, decode_linkage_0, decode_dsp32alu_0,
587 decode_dsp32shift_0, decode_dsp32shiftimm_0, decode_pseudodbg_assert_0,
588 _print_insn_bfin, print_insn_bfin): Likewise.
589
58c85be7
RW		 5902008-03-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
591
592 * aclocal.m4: Regenerate.
593 * configure: Likewise.
594 * Makefile.in: Likewise.
595
50e7d84b
AM		 5962008-03-13 Alan Modra <amodra@bigpond.net.au>
597
598 * Makefile.am: Run "make dep-am".
599 * Makefile.in: Regenerate.
600 * configure: Regenerate.
601
de866fcc
AM		 6022008-03-07 Alan Modra <amodra@bigpond.net.au>
603
604 * ppc-opc.c (powerpc_opcodes): Order and format.
605
28dbc079
L		 6062008-03-01 H.J. Lu <hongjiu.lu@intel.com>
607
608 * i386-opc.tbl: Allow 16-bit near indirect branches for x86-64.
609 * i386-tbl.h: Regenerated.
610
849830bd
L		 6112008-02-23 H.J. Lu <hongjiu.lu@intel.com>
612
613 * i386-opc.tbl: Disallow 16-bit near indirect branches for
614 x86-64.
615 * i386-tbl.h: Regenerated.
616
743ddb6b
JB		 6172008-02-21 Jan Beulich <jbeulich@novell.com>
618
619 * i386-opc.tbl: Allow Dword for far indirect call. Allow Dword
620 and Fword for far indirect jmp. Allow Reg16 and Word for near
621 indirect jmp on x86-64. Disallow Fword for lcall.
622 * i386-tbl.h: Re-generate.
623
796d5313
NC		 6242008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
625
626 * cr16-opc.c (cr16_num_optab): Defined
627
65da13b5
L		 6282008-02-16 H.J. Lu <hongjiu.lu@intel.com>
629
630 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_INOUTPORTREG.
631 * i386-init.h: Regenerated.
632
0e336180
NC		 6332008-02-14 Nick Clifton <nickc@redhat.com>
634
635 PR binutils/5524
636 * configure.in (SHARED_LIBADD): Select the correct host specific
637 file extension for shared libraries.
638 * configure: Regenerate.
639
b7240065
JB		 6402008-02-13 Jan Beulich <jbeulich@novell.com>
641
642 * i386-opc.h (RegFlat): New.
643 * i386-reg.tbl (flat): Add.
644 * i386-tbl.h: Re-generate.
645
34b772a6
JB		 6462008-02-13 Jan Beulich <jbeulich@novell.com>
647
648 * i386-dis.c (a_mode): New.
649 (cond_jump_mode): Adjust.
650 (Ma): Change to a_mode.
651 (intel_operand_size): Handle a_mode.
652 * i386-opc.tbl: Allow Dword and Qword for bound.
653 * i386-tbl.h: Re-generate.
654
a60de03c
JB		 6552008-02-13 Jan Beulich <jbeulich@novell.com>
656
657 * i386-gen.c (process_i386_registers): Process new fields.
658 * i386-opc.h (reg_entry): Shrink reg_flags and reg_num to
659 unsigned char. Add dw2_regnum and Dw2Inval.
660 * i386-reg.tbl: Provide initializers for dw2_regnum. Add pseudo
661 register names.
662 * i386-tbl.h: Re-generate.
663
f03fe4c1
L		 6642008-02-11 H.J. Lu <hongjiu.lu@intel.com>
665
4b6bc8eb 666 * i386-gen.c (cpu_flag_init): Add CPU_XSAVE_FLAGS.
f03fe4c1
L		 667 * i386-init.h: Updated.
668
475a2301
L		 6692008-02-11 H.J. Lu <hongjiu.lu@intel.com>
670
671 * i386-gen.c (cpu_flags): Add CpuXsave.
672
673 * i386-opc.h (CpuXsave): New.
4b6bc8eb 674 (CpuLM): Updated.
475a2301
L		 675 (i386_cpu_flags): Add cpuxsave.
676
677 * i386-dis.c (MOD_0FAE_REG_4): New.
678 (RM_0F01_REG_2): Likewise.
679 (MOD_0FAE_REG_5): Updated.
680 (RM_0F01_REG_3): Likewise.
681 (reg_table): Use MOD_0FAE_REG_4.
682 (mod_table): Use RM_0F01_REG_2. Add MOD_0FAE_REG_4. Updated
683 for xrstor.
684 (rm_table): Add RM_0F01_REG_2.
685
686 * i386-opc.tbl: Add xsave, xrstor, xgetbv and xsetbv.
687 * i386-init.h: Regenerated.
688 * i386-tbl.h: Likewise.
689
595785c6 6902008-02-11 Jan Beulich <jbeulich@novell.com>
041179fc 691
595785c6
JB		 692 * i386-opc.tbl: Remove Disp32S from CpuNo64 opcodes. Remove
693 Disp16 from Cpu64 non-jump opcodes (including loop and j?cxz).
694 * i386-tbl.h: Re-generate.
695
bb8541b9
L		 6962008-02-04 H.J. Lu <hongjiu.lu@intel.com>
697
698 PR 5715
699 * configure: Regenerated.
700
57b592a3
AN		 7012008-02-04 Adam Nemet <anemet@caviumnetworks.com>
702
703 * mips-dis.c: Update copyright.
704 (mips_arch_choices): Add Octeon.
705 * mips-opc.c: Update copyright.
706 (IOCT): New macro.
707 (mips_builtin_opcodes): Add Octeon instruction synciobdma.
708
930bb4cf
AM		 7092008-01-29 Alan Modra <amodra@bigpond.net.au>
710
711 * ppc-opc.c: Support optional L form mtmsr.
712
82c18208
L		 7132008-01-24 H.J. Lu <hongjiu.lu@intel.com>
714
715 * i386-dis.c (OP_E_extended): Handle r12 like rsp.
716
599121aa
L		 7172008-01-23 H.J. Lu <hongjiu.lu@intel.com>
718
719 * i386-gen.c (cpu_flag_init): Add CpuLM to CPU_GENERIC64_FLAGS.
720 * i386-init.h: Regenerated.
721
80098f51
TG		 7222008-01-23 Tristan Gingold <gingold@adacore.com>
723
724 * ia64-dis.c (print_insn_ia64): Display symbolic name of ar.fcr,
725 ar.eflag, ar.csd, ar.ssd, ar.cflg, ar.fsr, ar.fir and ar.fdr.
726
115c7c25
L		 7272008-01-22 H.J. Lu <hongjiu.lu@intel.com>
728
729 * i386-gen.c (cpu_flag_init): Remove CpuMMX2.
730 (cpu_flags): Likewise.
731
732 * i386-opc.h (CpuMMX2): Removed.
733 (CpuSSE): Updated.
734
735 * i386-opc.tbl: Replace CpuMMX2 with CpuSSE|Cpu3dnowA.
736 * i386-init.h: Regenerated.
737 * i386-tbl.h: Likewise.
738
6305a203
L		 7392008-01-22 H.J. Lu <hongjiu.lu@intel.com>
740
741 * i386-gen.c (cpu_flag_init): Add CPU_VMX_FLAGS and
742 CPU_SMX_FLAGS.
743 * i386-init.h: Regenerated.
744
fd07a1c8
L		 7452008-01-15 H.J. Lu <hongjiu.lu@intel.com>
746
747 * i386-opc.tbl: Use Qword on movddup.
748 * i386-tbl.h: Regenerated.
749
321fd21e
L		 7502008-01-15 H.J. Lu <hongjiu.lu@intel.com>
751
752 * i386-opc.tbl: Put back 16bit movsx/movzx for AT&T syntax.
753 * i386-tbl.h: Regenerated.
754
4ee52178
L		 7552008-01-15 H.J. Lu <hongjiu.lu@intel.com>
756
757 * i386-dis.c (Mx): New.
758 (PREFIX_0FC3): Likewise.
759 (PREFIX_0FC7_REG_6): Updated.
760 (dis386_twobyte): Use PREFIX_0FC3.
761 (prefix_table): Add PREFIX_0FC3. Use Mq on movntq and movntsd.
762 Use Mx on movntps, movntpd, movntdq and movntdqa. Use Md on
763 movntss.
764
5c07affc
L		 7652008-01-14 H.J. Lu <hongjiu.lu@intel.com>
766
767 * i386-gen.c (opcode_modifiers): Add IntelSyntax.
768 (operand_types): Add Mem.
769
770 * i386-opc.h (IntelSyntax): New.
771 * i386-opc.h (Mem): New.
772 (Byte): Updated.
773 (Opcode_Modifier_Max): Updated.
774 (i386_opcode_modifier): Add intelsyntax.
775 (i386_operand_type): Add mem.
776
777 * i386-opc.tbl: Remove Reg16 from movnti. Add sizes to more
778 instructions.
779
780 * i386-reg.tbl: Add size for accumulator.
781
782 * i386-init.h: Regenerated.
783 * i386-tbl.h: Likewise.
784
0d6a2f58
L		 7852008-01-13 H.J. Lu <hongjiu.lu@intel.com>
786
787 * i386-opc.h (Byte): Fix a typo.
788
7d5e4556
L		 7892008-01-12 H.J. Lu <hongjiu.lu@intel.com>
790
791 PR gas/5534
792 * i386-gen.c (operand_type_init): Add Dword to
793 OPERAND_TYPE_ACC32. Add Qword to OPERAND_TYPE_ACC64.
794 (opcode_modifiers): Remove CheckSize, Byte, Word, Dword,
795 Qword and Xmmword.
796 (operand_types): Add Byte, Word, Dword, Fword, Qword, Tbyte,
797 Xmmword, Unspecified and Anysize.
798 (set_bitfield): Make Mmword an alias of Qword. Make Oword
799 an alias of Xmmword.
800
801 * i386-opc.h (CheckSize): Removed.
802 (Byte): Updated.
803 (Word): Likewise.
804 (Dword): Likewise.
805 (Qword): Likewise.
806 (Xmmword): Likewise.
807 (FWait): Updated.
808 (OTMax): Likewise.
809 (i386_opcode_modifier): Remove checksize, byte, word, dword,
810 qword and xmmword.
811 (Fword): New.
812 (TBYTE): Likewise.
813 (Unspecified): Likewise.
814 (Anysize): Likewise.
815 (i386_operand_type): Add byte, word, dword, fword, qword,
816 tbyte xmmword, unspecified and anysize.
817
818 * i386-opc.tbl: Updated to use Byte, Word, Dword, Fword, Qword,
819 Tbyte, Xmmword, Unspecified and Anysize.
820
821 * i386-reg.tbl: Add size for accumulator.
822
823 * i386-init.h: Regenerated.
824 * i386-tbl.h: Likewise.
825
b5b1fc4f
L		 8262008-01-10 H.J. Lu <hongjiu.lu@intel.com>
827
828 * i386-dis.c (REG_0F0E): Renamed to REG_0F0D.
829 (REG_0F18): Updated.
830 (reg_table): Updated.
831 (dis386_twobyte): Updated. Use "nopQ" on 0x19 to 0x1e.
832 (twobyte_has_modrm): Set 1 for 0x19 to 0x1e.
833
50e8458f
L		 8342008-01-08 H.J. Lu <hongjiu.lu@intel.com>
835
836 * i386-gen.c (set_bitfield): Use fail () on error.
837
3d4d5afa
L		 8382008-01-08 H.J. Lu <hongjiu.lu@intel.com>
839
840 * i386-gen.c (lineno): New.
841 (filename): Likewise.
842 (set_bitfield): Report filename and line numer on error.
843 (process_i386_opcodes): Set filename and update lineno.
844 (process_i386_registers): Likewise.
845
e1d4d893
L		 8462008-01-05 H.J. Lu <hongjiu.lu@intel.com>
847
848 * i386-gen.c (opcode_modifiers): Rename IntelMnemonic to
849 ATTSyntax.
850
851 * i386-opc.h (IntelMnemonic): Renamed to ..
852 (ATTSyntax): This
853 (Opcode_Modifier_Max): Updated.
854 (i386_opcode_modifier): Remove intelmnemonic. Add attsyntax
855 and intelsyntax.
856
8944f3c2 857 * i386-opc.tbl: Remove IntelMnemonic and update with ATTSyntax
e1d4d893
L		 858 on fsub, fubp, fsubr, fsubrp, div, fdivp, fdivr and fdivrp.
859 * i386-tbl.h: Regenerated.
860
6f143e4d
L		 8612008-01-04 H.J. Lu <hongjiu.lu@intel.com>
862
863 * i386-gen.c: Update copyright to 2008.
864 * i386-opc.h: Likewise.
865 * i386-opc.tbl: Likewise.
866
867 * i386-init.h: Regenerated.
868 * i386-tbl.h: Likewise.
869
c6add537
L		 8702008-01-04 H.J. Lu <hongjiu.lu@intel.com>
871
872 * i386-opc.tbl: Add NoRex64 to extractps, movmskpd, movmskps,
873 pextrb, pextrw, pinsrb, pinsrw and pmovmskb.
874 * i386-tbl.h: Regenerated.
875
3629bb00
L		 8762008-01-03 H.J. Lu <hongjiu.lu@intel.com>
877
878 * i386-gen.c (cpu_flag_init): Remove CpuSSE4_1_Or_5 and
879 CpuSSE4_2_Or_ABM.
880 (cpu_flags): Likewise.
881
882 * i386-opc.h (CpuSSE4_1_Or_5): Removed.
883 (CpuSSE4_2_Or_ABM): Likewise.
884 (CpuLM): Updated.
885 (i386_cpu_flags): Remove cpusse4_1_or_5 and cpusse4_2_or_abm.
886
887 * i386-opc.tbl: Replace CpuSSE4_1_Or_5, CpuSSE4_2_Or_ABM and
888 Cpu686|CpuPadLock with CpuSSE4_1|CpuSSE5, CpuABM|CpuSSE4_2
889 and CpuPadLock, respectively.
890 * i386-init.h: Regenerated.
891 * i386-tbl.h: Likewise.
892
24995bd6
L		 8932008-01-03 H.J. Lu <hongjiu.lu@intel.com>
894
895 * i386-gen.c (opcode_modifiers): Remove No_xSuf.
896
897 * i386-opc.h (No_xSuf): Removed.
898 (CheckSize): Updated.
899
900 * i386-tbl.h: Regenerated.
901
e0329a22
L		 9022008-01-02 H.J. Lu <hongjiu.lu@intel.com>
903
904 * i386-gen.c (cpu_flag_init): Add CpuSSE4_2_Or_ABM to
905 CPU_AMDFAM10_FLAGS, CPU_SSE4_2_FLAGS, CpuABM and
906 CPU_SSE5_FLAGS.
907 (cpu_flags): Add CpuSSE4_2_Or_ABM.
908
909 * i386-opc.h (CpuSSE4_2_Or_ABM): New.
910 (CpuLM): Updated.
911 (i386_cpu_flags): Add cpusse4_2_or_abm.
912
913 * i386-opc.tbl: Use CpuSSE4_2_Or_ABM instead of
914 CpuABM|CpuSSE4_2 on popcnt.
915 * i386-init.h: Regenerated.
916 * i386-tbl.h: Likewise.
917
f2a9c676
L		 9182008-01-02 H.J. Lu <hongjiu.lu@intel.com>
919
920 * i386-opc.h: Update comments.
921
d978b5be
L		 9222008-01-02 H.J. Lu <hongjiu.lu@intel.com>
923
924 * i386-gen.c (opcode_modifiers): Use Qword instead of QWord.
925 * i386-opc.h: Likewise.
926 * i386-opc.tbl: Likewise.
927
582d5edd
L		 9282008-01-02 H.J. Lu <hongjiu.lu@intel.com>
929
930 PR gas/5534
931 * i386-gen.c (opcode_modifiers): Add No_xSuf, CheckSize,
932 Byte, Word, Dword, QWord and Xmmword.
933
934 * i386-opc.h (No_xSuf): New.
935 (CheckSize): Likewise.
936 (Byte): Likewise.
937 (Word): Likewise.
938 (Dword): Likewise.
939 (QWord): Likewise.
940 (Xmmword): Likewise.
941 (FWait): Updated.
942 (i386_opcode_modifier): Add No_xSuf, CheckSize, Byte, Word,
943 Dword, QWord and Xmmword.
944
945 * i386-opc.tbl: Add CheckSize|QWord to movq if IgnoreSize is
946 used.
947 * i386-tbl.h: Regenerated.
948
3fe15143
MK		 9492008-01-02 Mark Kettenis <kettenis@gnu.org>
950
951 * m88k-dis.c (instructions): Fix fcvt.* instructions.
952 From Miod Vallat.
953
6c7ac64e 954For older changes see ChangeLog-2007
252b5132
RH		 955\f
956Local Variables:
2f6d2f85
NC		 957mode: change-log
958left-margin: 8
959fill-column: 74
252b5132
RH		 960version-control: never
961End:
GDB Binutils - Deliverables
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