[deliverable/binutils-gdb.git] / opcodes / ChangeLog

2008-04-04  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (cpu_flag_init): Replace CPU_CLMUL_FLAGS/CpuCLMUL
	with CPU_PCLMUL_FLAGS/CpuPCLMUL.
	(cpu_flags): Replace CpuCLMUL with CpuPCLMUL.
	* i386-opc.tbl: Likewise.

	* i386-opc.h (CpuCLMUL): Renamed to ...
	(CpuPCLMUL): This.
	(CpuFMA): Updated.
	(i386_cpu_flags): Replace cpuclmul with cpupclmul.

	* i386-init.h: Regenerated.

2008-04-03  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (OP_E_register): New.
	(OP_E_memory): Likewise.
	(OP_VEX): Likewise.
	(OP_EX_Vex): Likewise.
	(OP_EX_VexW): Likewise.
	(OP_XMM_Vex): Likewise.
	(OP_XMM_VexW): Likewise.
	(OP_REG_VexI4): Likewise.
	(PCLMUL_Fixup): Likewise.
	(VEXI4_Fixup): Likewise.
	(VZERO_Fixup): Likewise.
	(VCMP_Fixup): Likewise.
	(VPERMIL2_Fixup): Likewise.
	(rex_original): Likewise.
	(rex_ignored): Likewise.
	(Mxmm): Likewise.
	(XMM): Likewise.
	(EXxmm): Likewise.
	(EXxmmq): Likewise.
	(EXymmq): Likewise.
	(Vex): Likewise.
	(Vex128): Likewise.
	(Vex256): Likewise.
	(VexI4): Likewise.
	(EXdVex): Likewise.
	(EXqVex): Likewise.
	(EXVexW): Likewise.
	(EXdVexW): Likewise.
	(EXqVexW): Likewise.
	(XMVex): Likewise.
	(XMVexW): Likewise.
	(XMVexI4): Likewise.
	(PCLMUL): Likewise.
	(VZERO): Likewise.
	(VCMP): Likewise.
	(VPERMIL2): Likewise.
	(xmm_mode): Likewise.
	(xmmq_mode): Likewise.
	(ymmq_mode): Likewise.
	(vex_mode): Likewise.
	(vex128_mode): Likewise.
	(vex256_mode): Likewise.
	(USE_VEX_C4_TABLE): Likewise.
	(USE_VEX_C5_TABLE): Likewise.
	(USE_VEX_LEN_TABLE): Likewise.
	(VEX_C4_TABLE): Likewise.
	(VEX_C5_TABLE): Likewise.
	(VEX_LEN_TABLE): Likewise.
	(REG_VEX_XX): Likewise.
	(MOD_VEX_XXX): Likewise.
	(PREFIX_0F38DB..PREFIX_0F38DF): Likewise.
	(PREFIX_0F3A44): Likewise.
	(PREFIX_0F3ADF): Likewise.
	(PREFIX_VEX_XXX): Likewise.
	(VEX_OF): Likewise.
	(VEX_OF38): Likewise.
	(VEX_OF3A): Likewise.
	(VEX_LEN_XXX): Likewise.
	(vex): Likewise.
	(need_vex): Likewise.
	(need_vex_reg): Likewise.
	(vex_i4_done): Likewise.
	(vex_table): Likewise.
	(vex_len_table): Likewise.
	(OP_REG_VexI4): Likewise.
	(vex_cmp_op): Likewise.
	(pclmul_op): Likewise.
	(vpermil2_op): Likewise.
	(m_mode): Updated.
	(es_reg): Likewise.
	(PREFIX_0F38F0): Likewise.
	(PREFIX_0F3A60): Likewise.
	(reg_table): Add REG_VEX_71...REG_VEX_73 and REG_VEX_AE.
	(prefix_table): Add PREFIX_0F38DB..PREFIX_0F38DF, PREFIX_0F3ADF
	and PREFIX_VEX_XXX entries.
	(x86_64_table): Use VEX_C4_TABLE and VEX_C5_TABLE.
	(three_byte_table): Use PREFIX_0F38DB..PREFIX_0F38DF and
	PREFIX_0F3ADF.
	(mod_table): Use VEX_C4_TABLE, VEX_C5_TABLE and VEX_LEN_TABLE.
	Add MOD_VEX_XXX entries.
	(ckprefix): Initialize rex_original and rex_ignored.  Store the
	REX byte in rex_original.
	(get_valid_dis386): Handle the implicit prefix in VEX prefix
	bytes and USE_VEX_LEN_TABLE/USE_VEX_C4_TABLE/USE_VEX_C5_TABLE.
	(print_insn): Set need_vex/need_vex_reg/vex_i4_done to 0 before
	calling get_valid_dis386.  Use rex_original and rex_ignored when
	printing out REX.
	(putop): Handle "XY".
	(intel_operand_size): Handle VEX, xmm_mode, xmmq_mode and
	ymmq_mode.
	(OP_E_extended): Updated to use OP_E_register and
	OP_E_memory.
	(OP_XMM): Handle VEX.
	(OP_EX): Likewise.
	(XMM_Fixup): Likewise.
	(CMP_Fixup): Use ARRAY_SIZE.

	* i386-gen.c (cpu_flag_init): Add CpuAES, CPU_CLMUL_FLAGS,
	CPU_FMA_FLAGS and CPU_AVX_FLAGS.
	(operand_type_init): Add OPERAND_TYPE_REGYMM and
	OPERAND_TYPE_VEX_IMM4.
	(cpu_flags): Add CpuAVX, CpuAES, CpuCLMUL and CpuFMA.
	(opcode_modifiers): Add Implicit1stXmm0, Vex, Vex256, VexNDD,
	VexNDS, VexW0, VexW1, Vex0F, Vex0F38, Vex0F3A, Vex3Sources,
	VexImmExt and SSE2AVX.
	(operand_types): Add RegYMM, Ymmword and Vex_Imm4.

	* i386-opc.h (CpuAVX): New.
	(CpuAES): Likewise.
	(CpuCLMUL): Likewise.
	(CpuFMA): Likewise.
	(Vex): Likewise.
	(Vex256): Likewise.
	(VexNDS): Likewise.
	(VexNDD): Likewise.
	(VexW0): Likewise.
	(VexW1): Likewise.
	(Vex0F): Likewise.
	(Vex0F38): Likewise.
	(Vex0F3A): Likewise.
	(Vex3Sources): Likewise.
	(VexImmExt): Likewise.
	(SSE2AVX): Likewise.
	(RegYMM): Likewise.
	(Ymmword): Likewise.
	(Vex_Imm4): Likewise.
	(Implicit1stXmm0): Likewise.
	(CpuXsave): Updated.
	(CpuLM): Likewise.
	(ByteOkIntel): Likewise.
	(OldGcc): Likewise.
	(Control): Likewise.
	(Unspecified): Likewise.
	(OTMax): Likewise.
	(i386_cpu_flags): Add cpuavx, cpuaes, cpuclmul and cpufma.
	(i386_opcode_modifier): Add implicit1stxmm0, vex, vex256,
	vexnds, vexndd, vexw0, vexw1, vex0f, vex0f38, vex0f3a,
	vex3sources, veximmext and sse2avx.
	(i386_operand_type): Add regymm, ymmword and vex_imm4.

	* i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions.

	* i386-reg.tbl: Add AVX registers, ymm0..ymm15.

	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2008-03-26  Bernd Schmidt  <bernd.schmidt@analog.com>

	From  Robin Getz  <robin.getz@analog.com>
	* bfin-dis.c (bu32): Typedef.
	(enum const_forms_t): Add c_uimm32 and c_huimm32.
	(constant_formats[]): Add uimm32 and huimm16.
	(fmtconst_val): New.
	(uimm32): Define.
	(huimm32): Define.
	(imm16_val): Define.
	(luimm16_val): Define.
	(struct saved_state): Define.
	(GREG, DPREG, DREG, PREG, SPREG, FPREG, IREG, MREG, BREG, LREG,
	A0XREG, A0WREG, A1XREG, A1WREG,CCREG, LC0REG, LT0REG, LB0REG,
	LC1REG, LT1REG, LB1REG, RETSREG, PCREG): Define.
	(get_allreg): New.
	(decode_LDIMMhalf_0): Print out the whole register value.

	From Jie Zhang  <jie.zhang@analog.com>
	* bfin-dis.c (decode_dsp32mac_0): Decode (IU) option for
	multiply and multiply-accumulate to data register instruction.

	* bfin-dis.c: (c_uimm4s4d, c_imm5d, c_imm7d, c_imm16d, c_uimm16s4d,
	c_imm32, c_huimm32e): Define.
	(constant_formats): Add flags for printing decimal, leading spaces, and
	exact symbols.
	(comment, parallel): Add global flags in all disassembly.
	(fmtconst): Take advantage of new flags, and print default in hex.
	(fmtconst_val): Likewise.
	(decode_macfunc): Be consistant with spaces, tabs, comments,
	capitalization in disassembly, fix minor coding style issues.
	(reg_names, amod0, amod1, amod0amod2, aligndir, get_allreg): Likewise.
	(decode_ProgCtrl_0, decode_PushPopMultiple_0, decode_CCflag_0,
	decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0,
	decode_REGMV_0, decode_ALU2op_0, decode_PTR2op_0, decode_LOGI2op_0,
	decode_COMP3op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
	decode_LDSTpmod_0, decode_dagMODim_0, decode_dagMODik_0,
	decode_dspLDST_0, decode_LDST_0, decode_LDSTiiFP_0, decode_LDSTii_0,
	decode_LoopSetup_0, decode_LDIMMhalf_0, decode_CALLa_0,
	decode_LDSTidxI_0, decode_linkage_0, decode_dsp32alu_0,
	decode_dsp32shift_0, decode_dsp32shiftimm_0, decode_pseudodbg_assert_0,
	_print_insn_bfin, print_insn_bfin): Likewise.

2008-03-17  Ralf Wildenhues  <Ralf.Wildenhues@gmx.de>

	* aclocal.m4: Regenerate.
	* configure: Likewise.
	* Makefile.in: Likewise.

2008-03-13  Alan Modra  <amodra@bigpond.net.au>

	* Makefile.am: Run "make dep-am".
	* Makefile.in: Regenerate.
	* configure: Regenerate.

2008-03-07  Alan Modra  <amodra@bigpond.net.au>

	* ppc-opc.c (powerpc_opcodes): Order and format.

2008-03-01  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.tbl: Allow 16-bit near indirect branches for x86-64.
	* i386-tbl.h: Regenerated.

2008-02-23  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.tbl: Disallow 16-bit near indirect branches for
	x86-64.
	* i386-tbl.h: Regenerated.

2008-02-21  Jan Beulich  <jbeulich@novell.com>

	* i386-opc.tbl: Allow Dword for far indirect call. Allow Dword
	and Fword for far indirect jmp. Allow Reg16 and Word for near
	indirect jmp on x86-64. Disallow Fword for lcall.
	* i386-tbl.h: Re-generate.

2008-02-18  M R Swami Reddy <MR.Swami.Reddy@nsc.com>

	* cr16-opc.c  (cr16_num_optab): Defined

2008-02-16  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c  (operand_type_init): Add OPERAND_TYPE_INOUTPORTREG.
	* i386-init.h: Regenerated.

2008-02-14  Nick Clifton  <nickc@redhat.com>

	PR binutils/5524
	* configure.in (SHARED_LIBADD): Select the correct host specific
	file extension for shared libraries.
	* configure: Regenerate.

2008-02-13  Jan Beulich  <jbeulich@novell.com>

	* i386-opc.h (RegFlat): New.
	* i386-reg.tbl (flat): Add.
	* i386-tbl.h: Re-generate.

2008-02-13  Jan Beulich  <jbeulich@novell.com>

	* i386-dis.c (a_mode): New.
	(cond_jump_mode): Adjust.
	(Ma): Change to a_mode.
	(intel_operand_size): Handle a_mode.
	* i386-opc.tbl: Allow Dword and Qword for bound.
	* i386-tbl.h: Re-generate.

2008-02-13  Jan Beulich  <jbeulich@novell.com>

	* i386-gen.c (process_i386_registers): Process new fields.
	* i386-opc.h (reg_entry): Shrink reg_flags and reg_num to
	unsigned char. Add dw2_regnum and Dw2Inval.
	* i386-reg.tbl: Provide initializers for dw2_regnum. Add pseudo
	register names.
	* i386-tbl.h: Re-generate.

2008-02-11  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (cpu_flag_init): Add CPU_XSAVE_FLAGS.
	* i386-init.h: Updated.

2008-02-11  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (cpu_flags): Add CpuXsave.

	* i386-opc.h (CpuXsave): New.
	(CpuLM): Updated.
	(i386_cpu_flags): Add cpuxsave.

	* i386-dis.c (MOD_0FAE_REG_4): New.
	(RM_0F01_REG_2): Likewise.
	(MOD_0FAE_REG_5): Updated.
	(RM_0F01_REG_3): Likewise.
	(reg_table): Use MOD_0FAE_REG_4.
	(mod_table): Use RM_0F01_REG_2.  Add MOD_0FAE_REG_4.  Updated
	for xrstor.
	(rm_table): Add RM_0F01_REG_2.

	* i386-opc.tbl: Add xsave, xrstor, xgetbv and xsetbv.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2008-02-11  Jan Beulich  <jbeulich@novell.com>

	* i386-opc.tbl: Remove Disp32S from CpuNo64 opcodes. Remove
	Disp16 from Cpu64 non-jump opcodes (including loop and j?cxz).
	* i386-tbl.h: Re-generate.

2008-02-04  H.J. Lu  <hongjiu.lu@intel.com>

	PR 5715
	* configure: Regenerated.

2008-02-04  Adam Nemet  <anemet@caviumnetworks.com>

	* mips-dis.c: Update copyright.
	(mips_arch_choices): Add Octeon.
	* mips-opc.c: Update copyright.
	(IOCT): New macro.
	(mips_builtin_opcodes): Add Octeon instruction synciobdma.

2008-01-29  Alan Modra  <amodra@bigpond.net.au>

	* ppc-opc.c: Support optional L form mtmsr.

2008-01-24  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (OP_E_extended): Handle r12 like rsp.

2008-01-23  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (cpu_flag_init): Add CpuLM to CPU_GENERIC64_FLAGS.
	* i386-init.h: Regenerated.

2008-01-23  Tristan Gingold  <gingold@adacore.com>

	* ia64-dis.c (print_insn_ia64): Display symbolic name of ar.fcr,
	ar.eflag, ar.csd, ar.ssd, ar.cflg, ar.fsr, ar.fir and ar.fdr.

2008-01-22  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (cpu_flag_init): Remove CpuMMX2.
	(cpu_flags): Likewise.

	* i386-opc.h (CpuMMX2): Removed.
	(CpuSSE): Updated.

	* i386-opc.tbl: Replace CpuMMX2 with CpuSSE|Cpu3dnowA.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2008-01-22  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (cpu_flag_init): Add CPU_VMX_FLAGS and
	CPU_SMX_FLAGS.
	* i386-init.h: Regenerated.

2008-01-15  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.tbl: Use Qword on movddup.
	* i386-tbl.h: Regenerated.

2008-01-15  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.tbl: Put back 16bit movsx/movzx for AT&T syntax.
	* i386-tbl.h: Regenerated.

2008-01-15  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (Mx): New.
	(PREFIX_0FC3): Likewise.
	(PREFIX_0FC7_REG_6): Updated.
	(dis386_twobyte): Use PREFIX_0FC3.
	(prefix_table): Add PREFIX_0FC3.  Use Mq on movntq and movntsd.
	Use Mx on movntps, movntpd, movntdq and movntdqa.  Use Md on
	movntss.

2008-01-14  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (opcode_modifiers): Add IntelSyntax.
	(operand_types): Add Mem.

	* i386-opc.h (IntelSyntax): New.
	* i386-opc.h (Mem): New.
	(Byte): Updated.
	(Opcode_Modifier_Max): Updated.
	(i386_opcode_modifier): Add intelsyntax.
	(i386_operand_type): Add mem.

	* i386-opc.tbl: Remove Reg16 from movnti.  Add sizes to more
	instructions.

	* i386-reg.tbl: Add size for accumulator.

	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2008-01-13  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.h (Byte): Fix a typo.

2008-01-12  H.J. Lu  <hongjiu.lu@intel.com>

	PR gas/5534
	* i386-gen.c (operand_type_init): Add Dword to
	OPERAND_TYPE_ACC32.  Add Qword to OPERAND_TYPE_ACC64.
	(opcode_modifiers): Remove CheckSize, Byte, Word, Dword,
	Qword and Xmmword.
	(operand_types): Add Byte, Word, Dword, Fword, Qword, Tbyte,
	Xmmword, Unspecified and Anysize.
	(set_bitfield): Make Mmword an alias of Qword.  Make Oword
	an alias of Xmmword.

	* i386-opc.h (CheckSize): Removed.
	(Byte): Updated.
	(Word): Likewise.
	(Dword): Likewise.
	(Qword): Likewise.
	(Xmmword): Likewise.
	(FWait): Updated.
	(OTMax): Likewise.
	(i386_opcode_modifier): Remove checksize, byte, word, dword,
	qword and xmmword.
	(Fword): New.
	(TBYTE): Likewise.
	(Unspecified): Likewise.
	(Anysize): Likewise.
	(i386_operand_type): Add byte, word, dword, fword, qword,
	tbyte xmmword, unspecified and anysize.

	* i386-opc.tbl: Updated to use Byte, Word, Dword, Fword, Qword,
	Tbyte, Xmmword, Unspecified and Anysize.

	* i386-reg.tbl: Add size for accumulator.

	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2008-01-10  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (REG_0F0E): Renamed to REG_0F0D.
	(REG_0F18): Updated.
	(reg_table): Updated.
	(dis386_twobyte): Updated.  Use "nopQ" on 0x19 to 0x1e.
	(twobyte_has_modrm): Set 1 for 0x19 to 0x1e.

2008-01-08  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (set_bitfield): Use fail () on error.

2008-01-08  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (lineno): New.
	(filename): Likewise.
	(set_bitfield): Report filename and line numer on error.
	(process_i386_opcodes): Set filename and update lineno.
	(process_i386_registers): Likewise.

2008-01-05  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (opcode_modifiers): Rename IntelMnemonic to
	ATTSyntax.

	* i386-opc.h (IntelMnemonic): Renamed to ..
	(ATTSyntax): This
	(Opcode_Modifier_Max): Updated.
	(i386_opcode_modifier): Remove intelmnemonic. Add attsyntax
	and intelsyntax.

	* i386-opc.tbl: Remove IntelMnemonic and update with ATTSyntax 
	on fsub, fubp, fsubr, fsubrp, div, fdivp, fdivr and fdivrp.
	* i386-tbl.h: Regenerated.

2008-01-04  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c: Update copyright to 2008.
	* i386-opc.h: Likewise.
	* i386-opc.tbl: Likewise.

	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2008-01-04  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.tbl: Add NoRex64 to extractps, movmskpd, movmskps,
	pextrb, pextrw, pinsrb, pinsrw and pmovmskb.
	* i386-tbl.h: Regenerated.

2008-01-03  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (cpu_flag_init): Remove CpuSSE4_1_Or_5 and
	CpuSSE4_2_Or_ABM.
	(cpu_flags): Likewise.

	* i386-opc.h (CpuSSE4_1_Or_5): Removed.
	(CpuSSE4_2_Or_ABM): Likewise.
	(CpuLM): Updated.
	(i386_cpu_flags): Remove cpusse4_1_or_5 and cpusse4_2_or_abm.

	* i386-opc.tbl: Replace CpuSSE4_1_Or_5, CpuSSE4_2_Or_ABM and
	Cpu686|CpuPadLock with CpuSSE4_1|CpuSSE5, CpuABM|CpuSSE4_2
	and CpuPadLock, respectively.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2008-01-03  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (opcode_modifiers): Remove No_xSuf.

	* i386-opc.h (No_xSuf): Removed.
	(CheckSize): Updated.

	* i386-tbl.h: Regenerated.

2008-01-02  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (cpu_flag_init): Add CpuSSE4_2_Or_ABM to
	CPU_AMDFAM10_FLAGS, CPU_SSE4_2_FLAGS, CpuABM and
	CPU_SSE5_FLAGS.
	(cpu_flags): Add CpuSSE4_2_Or_ABM.

	* i386-opc.h (CpuSSE4_2_Or_ABM): New.
	(CpuLM): Updated.
	(i386_cpu_flags): Add cpusse4_2_or_abm.

	* i386-opc.tbl: Use CpuSSE4_2_Or_ABM instead of
	CpuABM|CpuSSE4_2 on popcnt.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2008-01-02  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.h: Update comments.

2008-01-02  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (opcode_modifiers): Use Qword instead of QWord.
	* i386-opc.h: Likewise.
	* i386-opc.tbl: Likewise.

2008-01-02  H.J. Lu  <hongjiu.lu@intel.com>

	PR gas/5534
	* i386-gen.c (opcode_modifiers): Add No_xSuf, CheckSize,
	Byte, Word, Dword, QWord and Xmmword.

	* i386-opc.h (No_xSuf): New.
	(CheckSize): Likewise.
	(Byte): Likewise.
	(Word): Likewise.
	(Dword): Likewise.
	(QWord): Likewise.
	(Xmmword): Likewise.
	(FWait): Updated.
	(i386_opcode_modifier): Add No_xSuf, CheckSize, Byte, Word,
	Dword, QWord and Xmmword.

	* i386-opc.tbl: Add CheckSize|QWord to movq if IgnoreSize is
	used.
	* i386-tbl.h: Regenerated.

2008-01-02  Mark Kettenis  <kettenis@gnu.org>

	* m88k-dis.c (instructions): Fix fcvt.* instructions.
	From Miod Vallat.

For older changes see ChangeLog-2007
\f
Local Variables:
mode: change-log
left-margin: 8
fill-column: 74
version-control: never
End:
Commit	Line	Data
594ab6a3 L	1	2008-04-04 H.J. Lu <hongjiu.lu@intel.com>
	2
	3	* i386-gen.c (cpu_flag_init): Replace CPU_CLMUL_FLAGS/CpuCLMUL
	4	with CPU_PCLMUL_FLAGS/CpuPCLMUL.
	5	(cpu_flags): Replace CpuCLMUL with CpuPCLMUL.
	6	* i386-opc.tbl: Likewise.
	7
	8	* i386-opc.h (CpuCLMUL): Renamed to ...
	9	(CpuPCLMUL): This.
	10	(CpuFMA): Updated.
	11	(i386_cpu_flags): Replace cpuclmul with cpupclmul.
	12
	13	* i386-init.h: Regenerated.
	14
c0f3af97 L	15	2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
	16
	17	* i386-dis.c (OP_E_register): New.
	18	(OP_E_memory): Likewise.
	19	(OP_VEX): Likewise.
	20	(OP_EX_Vex): Likewise.
	21	(OP_EX_VexW): Likewise.
	22	(OP_XMM_Vex): Likewise.
	23	(OP_XMM_VexW): Likewise.
	24	(OP_REG_VexI4): Likewise.
	25	(PCLMUL_Fixup): Likewise.
	26	(VEXI4_Fixup): Likewise.
	27	(VZERO_Fixup): Likewise.
	28	(VCMP_Fixup): Likewise.
	29	(VPERMIL2_Fixup): Likewise.
	30	(rex_original): Likewise.
	31	(rex_ignored): Likewise.
	32	(Mxmm): Likewise.
	33	(XMM): Likewise.
	34	(EXxmm): Likewise.
	35	(EXxmmq): Likewise.
	36	(EXymmq): Likewise.
	37	(Vex): Likewise.
	38	(Vex128): Likewise.
	39	(Vex256): Likewise.
	40	(VexI4): Likewise.
	41	(EXdVex): Likewise.
	42	(EXqVex): Likewise.
	43	(EXVexW): Likewise.
	44	(EXdVexW): Likewise.
	45	(EXqVexW): Likewise.
	46	(XMVex): Likewise.
	47	(XMVexW): Likewise.
	48	(XMVexI4): Likewise.
	49	(PCLMUL): Likewise.
	50	(VZERO): Likewise.
	51	(VCMP): Likewise.
	52	(VPERMIL2): Likewise.
	53	(xmm_mode): Likewise.
	54	(xmmq_mode): Likewise.
	55	(ymmq_mode): Likewise.
	56	(vex_mode): Likewise.
	57	(vex128_mode): Likewise.
	58	(vex256_mode): Likewise.
	59	(USE_VEX_C4_TABLE): Likewise.
	60	(USE_VEX_C5_TABLE): Likewise.
	61	(USE_VEX_LEN_TABLE): Likewise.
	62	(VEX_C4_TABLE): Likewise.
	63	(VEX_C5_TABLE): Likewise.
	64	(VEX_LEN_TABLE): Likewise.
	65	(REG_VEX_XX): Likewise.
	66	(MOD_VEX_XXX): Likewise.
	67	(PREFIX_0F38DB..PREFIX_0F38DF): Likewise.
	68	(PREFIX_0F3A44): Likewise.
	69	(PREFIX_0F3ADF): Likewise.
	70	(PREFIX_VEX_XXX): Likewise.
	71	(VEX_OF): Likewise.
	72	(VEX_OF38): Likewise.
	73	(VEX_OF3A): Likewise.
	74	(VEX_LEN_XXX): Likewise.
	75	(vex): Likewise.
	76	(need_vex): Likewise.
	77	(need_vex_reg): Likewise.
	78	(vex_i4_done): Likewise.
79	(vex_table): Likewise.
80	(vex_len_table): Likewise.
81	(OP_REG_VexI4): Likewise.
82	(vex_cmp_op): Likewise.
83	(pclmul_op): Likewise.
84	(vpermil2_op): Likewise.
85	(m_mode): Updated.
86	(es_reg): Likewise.
87	(PREFIX_0F38F0): Likewise.
88	(PREFIX_0F3A60): Likewise.
89	(reg_table): Add REG_VEX_71...REG_VEX_73 and REG_VEX_AE.
90	(prefix_table): Add PREFIX_0F38DB..PREFIX_0F38DF, PREFIX_0F3ADF
91	and PREFIX_VEX_XXX entries.
92	(x86_64_table): Use VEX_C4_TABLE and VEX_C5_TABLE.
93	(three_byte_table): Use PREFIX_0F38DB..PREFIX_0F38DF and
94	PREFIX_0F3ADF.
95	(mod_table): Use VEX_C4_TABLE, VEX_C5_TABLE and VEX_LEN_TABLE.
96	Add MOD_VEX_XXX entries.
97	(ckprefix): Initialize rex_original and rex_ignored. Store the
98	REX byte in rex_original.
99	(get_valid_dis386): Handle the implicit prefix in VEX prefix
100	bytes and USE_VEX_LEN_TABLE/USE_VEX_C4_TABLE/USE_VEX_C5_TABLE.
101	(print_insn): Set need_vex/need_vex_reg/vex_i4_done to 0 before
102	calling get_valid_dis386. Use rex_original and rex_ignored when
103	printing out REX.
104	(putop): Handle "XY".
105	(intel_operand_size): Handle VEX, xmm_mode, xmmq_mode and
106	ymmq_mode.
107	(OP_E_extended): Updated to use OP_E_register and
108	OP_E_memory.
109	(OP_XMM): Handle VEX.
110	(OP_EX): Likewise.
111	(XMM_Fixup): Likewise.
112	(CMP_Fixup): Use ARRAY_SIZE.
113
114	* i386-gen.c (cpu_flag_init): Add CpuAES, CPU_CLMUL_FLAGS,
115	CPU_FMA_FLAGS and CPU_AVX_FLAGS.
116	(operand_type_init): Add OPERAND_TYPE_REGYMM and
117	OPERAND_TYPE_VEX_IMM4.
118	(cpu_flags): Add CpuAVX, CpuAES, CpuCLMUL and CpuFMA.
119	(opcode_modifiers): Add Implicit1stXmm0, Vex, Vex256, VexNDD,
120	VexNDS, VexW0, VexW1, Vex0F, Vex0F38, Vex0F3A, Vex3Sources,
121	VexImmExt and SSE2AVX.
122	(operand_types): Add RegYMM, Ymmword and Vex_Imm4.
123
124	* i386-opc.h (CpuAVX): New.
125	(CpuAES): Likewise.
126	(CpuCLMUL): Likewise.
127	(CpuFMA): Likewise.
128	(Vex): Likewise.
129	(Vex256): Likewise.
130	(VexNDS): Likewise.
131	(VexNDD): Likewise.
132	(VexW0): Likewise.
133	(VexW1): Likewise.
134	(Vex0F): Likewise.
135	(Vex0F38): Likewise.
136	(Vex0F3A): Likewise.
137	(Vex3Sources): Likewise.
138	(VexImmExt): Likewise.
139	(SSE2AVX): Likewise.
140	(RegYMM): Likewise.
141	(Ymmword): Likewise.
142	(Vex_Imm4): Likewise.
143	(Implicit1stXmm0): Likewise.
144	(CpuXsave): Updated.
145	(CpuLM): Likewise.
146	(ByteOkIntel): Likewise.
147	(OldGcc): Likewise.
148	(Control): Likewise.
149	(Unspecified): Likewise.
150	(OTMax): Likewise.
151	(i386_cpu_flags): Add cpuavx, cpuaes, cpuclmul and cpufma.
152	(i386_opcode_modifier): Add implicit1stxmm0, vex, vex256,
153	vexnds, vexndd, vexw0, vexw1, vex0f, vex0f38, vex0f3a,
154	vex3sources, veximmext and sse2avx.
155	(i386_operand_type): Add regymm, ymmword and vex_imm4.
156
157	* i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions.
158
159	* i386-reg.tbl: Add AVX registers, ymm0..ymm15.
160
161	* i386-init.h: Regenerated.
162	* i386-tbl.h: Likewise.
163
b21c9cb4 BS	164	2008-03-26 Bernd Schmidt <bernd.schmidt@analog.com>
	165
	166	From Robin Getz <robin.getz@analog.com>
	167	* bfin-dis.c (bu32): Typedef.
	168	(enum const_forms_t): Add c_uimm32 and c_huimm32.
	169	(constant_formats[]): Add uimm32 and huimm16.
	170	(fmtconst_val): New.
	171	(uimm32): Define.
	172	(huimm32): Define.
	173	(imm16_val): Define.
	174	(luimm16_val): Define.
	175	(struct saved_state): Define.
	176	(GREG, DPREG, DREG, PREG, SPREG, FPREG, IREG, MREG, BREG, LREG,
	177	A0XREG, A0WREG, A1XREG, A1WREG,CCREG, LC0REG, LT0REG, LB0REG,
	178	LC1REG, LT1REG, LB1REG, RETSREG, PCREG): Define.
	179	(get_allreg): New.
	180	(decode_LDIMMhalf_0): Print out the whole register value.
	181
ee171c8f BS	182	From Jie Zhang <jie.zhang@analog.com>
	183	* bfin-dis.c (decode_dsp32mac_0): Decode (IU) option for
	184	multiply and multiply-accumulate to data register instruction.
	185
086134ec BS	186	* bfin-dis.c: (c_uimm4s4d, c_imm5d, c_imm7d, c_imm16d, c_uimm16s4d,
	187	c_imm32, c_huimm32e): Define.
	188	(constant_formats): Add flags for printing decimal, leading spaces, and
	189	exact symbols.
	190	(comment, parallel): Add global flags in all disassembly.
	191	(fmtconst): Take advantage of new flags, and print default in hex.
	192	(fmtconst_val): Likewise.
	193	(decode_macfunc): Be consistant with spaces, tabs, comments,
	194	capitalization in disassembly, fix minor coding style issues.
	195	(reg_names, amod0, amod1, amod0amod2, aligndir, get_allreg): Likewise.
	196	(decode_ProgCtrl_0, decode_PushPopMultiple_0, decode_CCflag_0,
	197	decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0,
	198	decode_REGMV_0, decode_ALU2op_0, decode_PTR2op_0, decode_LOGI2op_0,
	199	decode_COMP3op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
	200	decode_LDSTpmod_0, decode_dagMODim_0, decode_dagMODik_0,
	201	decode_dspLDST_0, decode_LDST_0, decode_LDSTiiFP_0, decode_LDSTii_0,
	202	decode_LoopSetup_0, decode_LDIMMhalf_0, decode_CALLa_0,
	203	decode_LDSTidxI_0, decode_linkage_0, decode_dsp32alu_0,
	204	decode_dsp32shift_0, decode_dsp32shiftimm_0, decode_pseudodbg_assert_0,
	205	_print_insn_bfin, print_insn_bfin): Likewise.
	206
58c85be7 RW	207	2008-03-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
	208
	209	* aclocal.m4: Regenerate.
	210	* configure: Likewise.
	211	* Makefile.in: Likewise.
	212
50e7d84b AM	213	2008-03-13 Alan Modra <amodra@bigpond.net.au>
	214
	215	* Makefile.am: Run "make dep-am".
	216	* Makefile.in: Regenerate.
	217	* configure: Regenerate.
	218
de866fcc AM	219	2008-03-07 Alan Modra <amodra@bigpond.net.au>
	220
	221	* ppc-opc.c (powerpc_opcodes): Order and format.
	222
28dbc079 L	223	2008-03-01 H.J. Lu <hongjiu.lu@intel.com>
	224
	225	* i386-opc.tbl: Allow 16-bit near indirect branches for x86-64.
	226	* i386-tbl.h: Regenerated.
	227
849830bd L	228	2008-02-23 H.J. Lu <hongjiu.lu@intel.com>
	229
	230	* i386-opc.tbl: Disallow 16-bit near indirect branches for
	231	x86-64.
	232	* i386-tbl.h: Regenerated.
	233
743ddb6b JB	234	2008-02-21 Jan Beulich <jbeulich@novell.com>
	235
	236	* i386-opc.tbl: Allow Dword for far indirect call. Allow Dword
	237	and Fword for far indirect jmp. Allow Reg16 and Word for near
	238	indirect jmp on x86-64. Disallow Fword for lcall.
	239	* i386-tbl.h: Re-generate.
	240
796d5313 NC	241	2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
	242
	243	* cr16-opc.c (cr16_num_optab): Defined
	244
65da13b5 L	245	2008-02-16 H.J. Lu <hongjiu.lu@intel.com>
	246
	247	* i386-gen.c (operand_type_init): Add OPERAND_TYPE_INOUTPORTREG.
	248	* i386-init.h: Regenerated.
	249
0e336180 NC	250	2008-02-14 Nick Clifton <nickc@redhat.com>
	251
	252	PR binutils/5524
	253	* configure.in (SHARED_LIBADD): Select the correct host specific
	254	file extension for shared libraries.
	255	* configure: Regenerate.
	256
b7240065 JB	257	2008-02-13 Jan Beulich <jbeulich@novell.com>
	258
	259	* i386-opc.h (RegFlat): New.
	260	* i386-reg.tbl (flat): Add.
	261	* i386-tbl.h: Re-generate.
	262
34b772a6 JB	263	2008-02-13 Jan Beulich <jbeulich@novell.com>
	264
	265	* i386-dis.c (a_mode): New.
	266	(cond_jump_mode): Adjust.
	267	(Ma): Change to a_mode.
	268	(intel_operand_size): Handle a_mode.
	269	* i386-opc.tbl: Allow Dword and Qword for bound.
	270	* i386-tbl.h: Re-generate.
	271
a60de03c JB	272	2008-02-13 Jan Beulich <jbeulich@novell.com>
	273
	274	* i386-gen.c (process_i386_registers): Process new fields.
	275	* i386-opc.h (reg_entry): Shrink reg_flags and reg_num to
	276	unsigned char. Add dw2_regnum and Dw2Inval.
	277	* i386-reg.tbl: Provide initializers for dw2_regnum. Add pseudo
	278	register names.
	279	* i386-tbl.h: Re-generate.
	280
f03fe4c1 L	281	2008-02-11 H.J. Lu <hongjiu.lu@intel.com>
f03fe4c1 L	282
4b6bc8eb	283	* i386-gen.c (cpu_flag_init): Add CPU_XSAVE_FLAGS.
f03fe4c1 L	284	* i386-init.h: Updated.
f03fe4c1 L	285
475a2301 L	286	2008-02-11 H.J. Lu <hongjiu.lu@intel.com>
	287
	288	* i386-gen.c (cpu_flags): Add CpuXsave.
	289
	290	* i386-opc.h (CpuXsave): New.
4b6bc8eb	291	(CpuLM): Updated.
475a2301 L	292	(i386_cpu_flags): Add cpuxsave.
	293
	294	* i386-dis.c (MOD_0FAE_REG_4): New.
	295	(RM_0F01_REG_2): Likewise.
	296	(MOD_0FAE_REG_5): Updated.
	297	(RM_0F01_REG_3): Likewise.
	298	(reg_table): Use MOD_0FAE_REG_4.
	299	(mod_table): Use RM_0F01_REG_2. Add MOD_0FAE_REG_4. Updated
	300	for xrstor.
	301	(rm_table): Add RM_0F01_REG_2.
	302
	303	* i386-opc.tbl: Add xsave, xrstor, xgetbv and xsetbv.
	304	* i386-init.h: Regenerated.
	305	* i386-tbl.h: Likewise.
	306
595785c6	307	2008-02-11 Jan Beulich <jbeulich@novell.com>
041179fc	308
595785c6 JB	309	* i386-opc.tbl: Remove Disp32S from CpuNo64 opcodes. Remove
	310	Disp16 from Cpu64 non-jump opcodes (including loop and j?cxz).
	311	* i386-tbl.h: Re-generate.
	312
bb8541b9 L	313	2008-02-04 H.J. Lu <hongjiu.lu@intel.com>
	314
	315	PR 5715
	316	* configure: Regenerated.
	317
57b592a3 AN	318	2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
	319
	320	* mips-dis.c: Update copyright.
	321	(mips_arch_choices): Add Octeon.
	322	* mips-opc.c: Update copyright.
	323	(IOCT): New macro.
	324	(mips_builtin_opcodes): Add Octeon instruction synciobdma.
	325
930bb4cf AM	326	2008-01-29 Alan Modra <amodra@bigpond.net.au>
	327
	328	* ppc-opc.c: Support optional L form mtmsr.
	329
82c18208 L	330	2008-01-24 H.J. Lu <hongjiu.lu@intel.com>
	331
	332	* i386-dis.c (OP_E_extended): Handle r12 like rsp.
	333
599121aa L	334	2008-01-23 H.J. Lu <hongjiu.lu@intel.com>
	335
	336	* i386-gen.c (cpu_flag_init): Add CpuLM to CPU_GENERIC64_FLAGS.
	337	* i386-init.h: Regenerated.
	338
80098f51 TG	339	2008-01-23 Tristan Gingold <gingold@adacore.com>
	340
	341	* ia64-dis.c (print_insn_ia64): Display symbolic name of ar.fcr,
	342	ar.eflag, ar.csd, ar.ssd, ar.cflg, ar.fsr, ar.fir and ar.fdr.
	343
115c7c25 L	344	2008-01-22 H.J. Lu <hongjiu.lu@intel.com>
	345
	346	* i386-gen.c (cpu_flag_init): Remove CpuMMX2.
	347	(cpu_flags): Likewise.
	348
	349	* i386-opc.h (CpuMMX2): Removed.
	350	(CpuSSE): Updated.
	351
	352	* i386-opc.tbl: Replace CpuMMX2 with CpuSSE\|Cpu3dnowA.
	353	* i386-init.h: Regenerated.
	354	* i386-tbl.h: Likewise.
	355
6305a203 L	356	2008-01-22 H.J. Lu <hongjiu.lu@intel.com>
	357
	358	* i386-gen.c (cpu_flag_init): Add CPU_VMX_FLAGS and
	359	CPU_SMX_FLAGS.
	360	* i386-init.h: Regenerated.
	361
fd07a1c8 L	362	2008-01-15 H.J. Lu <hongjiu.lu@intel.com>
	363
	364	* i386-opc.tbl: Use Qword on movddup.
	365	* i386-tbl.h: Regenerated.
	366
321fd21e L	367	2008-01-15 H.J. Lu <hongjiu.lu@intel.com>
	368
	369	* i386-opc.tbl: Put back 16bit movsx/movzx for AT&T syntax.
	370	* i386-tbl.h: Regenerated.
	371
4ee52178 L	372	2008-01-15 H.J. Lu <hongjiu.lu@intel.com>
	373
	374	* i386-dis.c (Mx): New.
	375	(PREFIX_0FC3): Likewise.
	376	(PREFIX_0FC7_REG_6): Updated.
	377	(dis386_twobyte): Use PREFIX_0FC3.
	378	(prefix_table): Add PREFIX_0FC3. Use Mq on movntq and movntsd.
	379	Use Mx on movntps, movntpd, movntdq and movntdqa. Use Md on
	380	movntss.
	381
5c07affc L	382	2008-01-14 H.J. Lu <hongjiu.lu@intel.com>
	383
	384	* i386-gen.c (opcode_modifiers): Add IntelSyntax.
	385	(operand_types): Add Mem.
	386
	387	* i386-opc.h (IntelSyntax): New.
	388	* i386-opc.h (Mem): New.
	389	(Byte): Updated.
	390	(Opcode_Modifier_Max): Updated.
	391	(i386_opcode_modifier): Add intelsyntax.
	392	(i386_operand_type): Add mem.
	393
	394	* i386-opc.tbl: Remove Reg16 from movnti. Add sizes to more
	395	instructions.
	396
	397	* i386-reg.tbl: Add size for accumulator.
	398
	399	* i386-init.h: Regenerated.
	400	* i386-tbl.h: Likewise.
	401
0d6a2f58 L	402	2008-01-13 H.J. Lu <hongjiu.lu@intel.com>
	403
	404	* i386-opc.h (Byte): Fix a typo.
	405
7d5e4556 L	406	2008-01-12 H.J. Lu <hongjiu.lu@intel.com>
	407
	408	PR gas/5534
	409	* i386-gen.c (operand_type_init): Add Dword to
	410	OPERAND_TYPE_ACC32. Add Qword to OPERAND_TYPE_ACC64.
	411	(opcode_modifiers): Remove CheckSize, Byte, Word, Dword,
	412	Qword and Xmmword.
	413	(operand_types): Add Byte, Word, Dword, Fword, Qword, Tbyte,
	414	Xmmword, Unspecified and Anysize.
	415	(set_bitfield): Make Mmword an alias of Qword. Make Oword
	416	an alias of Xmmword.
	417
	418	* i386-opc.h (CheckSize): Removed.
	419	(Byte): Updated.
	420	(Word): Likewise.
	421	(Dword): Likewise.
	422	(Qword): Likewise.
	423	(Xmmword): Likewise.
	424	(FWait): Updated.
	425	(OTMax): Likewise.
	426	(i386_opcode_modifier): Remove checksize, byte, word, dword,
	427	qword and xmmword.
	428	(Fword): New.
	429	(TBYTE): Likewise.
	430	(Unspecified): Likewise.
	431	(Anysize): Likewise.
	432	(i386_operand_type): Add byte, word, dword, fword, qword,
	433	tbyte xmmword, unspecified and anysize.
	434
	435	* i386-opc.tbl: Updated to use Byte, Word, Dword, Fword, Qword,
	436	Tbyte, Xmmword, Unspecified and Anysize.
	437
	438	* i386-reg.tbl: Add size for accumulator.
	439
	440	* i386-init.h: Regenerated.
	441	* i386-tbl.h: Likewise.
	442
b5b1fc4f L	443	2008-01-10 H.J. Lu <hongjiu.lu@intel.com>
	444
	445	* i386-dis.c (REG_0F0E): Renamed to REG_0F0D.
	446	(REG_0F18): Updated.
	447	(reg_table): Updated.
	448	(dis386_twobyte): Updated. Use "nopQ" on 0x19 to 0x1e.
	449	(twobyte_has_modrm): Set 1 for 0x19 to 0x1e.
	450
50e8458f L	451	2008-01-08 H.J. Lu <hongjiu.lu@intel.com>
	452
	453	* i386-gen.c (set_bitfield): Use fail () on error.
	454
3d4d5afa L	455	2008-01-08 H.J. Lu <hongjiu.lu@intel.com>
	456
	457	* i386-gen.c (lineno): New.
	458	(filename): Likewise.
	459	(set_bitfield): Report filename and line numer on error.
	460	(process_i386_opcodes): Set filename and update lineno.
	461	(process_i386_registers): Likewise.
	462
e1d4d893 L	463	2008-01-05 H.J. Lu <hongjiu.lu@intel.com>
	464
	465	* i386-gen.c (opcode_modifiers): Rename IntelMnemonic to
	466	ATTSyntax.
	467
	468	* i386-opc.h (IntelMnemonic): Renamed to ..
	469	(ATTSyntax): This
	470	(Opcode_Modifier_Max): Updated.
	471	(i386_opcode_modifier): Remove intelmnemonic. Add attsyntax
	472	and intelsyntax.
	473
	474	* i386-opc.tbl: Remove IntelMnemonic and update with ATTSyntax
	475	on fsub, fubp, fsubr, fsubrp, div, fdivp, fdivr and fdivrp.
	476	* i386-tbl.h: Regenerated.
	477
6f143e4d L	478	2008-01-04 H.J. Lu <hongjiu.lu@intel.com>
	479
	480	* i386-gen.c: Update copyright to 2008.
	481	* i386-opc.h: Likewise.
	482	* i386-opc.tbl: Likewise.
	483
	484	* i386-init.h: Regenerated.
	485	* i386-tbl.h: Likewise.
	486
c6add537 L	487	2008-01-04 H.J. Lu <hongjiu.lu@intel.com>
	488
	489	* i386-opc.tbl: Add NoRex64 to extractps, movmskpd, movmskps,
	490	pextrb, pextrw, pinsrb, pinsrw and pmovmskb.
	491	* i386-tbl.h: Regenerated.
	492
3629bb00 L	493	2008-01-03 H.J. Lu <hongjiu.lu@intel.com>
	494
	495	* i386-gen.c (cpu_flag_init): Remove CpuSSE4_1_Or_5 and
	496	CpuSSE4_2_Or_ABM.
	497	(cpu_flags): Likewise.
	498
	499	* i386-opc.h (CpuSSE4_1_Or_5): Removed.
	500	(CpuSSE4_2_Or_ABM): Likewise.
	501	(CpuLM): Updated.
	502	(i386_cpu_flags): Remove cpusse4_1_or_5 and cpusse4_2_or_abm.
	503
	504	* i386-opc.tbl: Replace CpuSSE4_1_Or_5, CpuSSE4_2_Or_ABM and
	505	Cpu686\|CpuPadLock with CpuSSE4_1\|CpuSSE5, CpuABM\|CpuSSE4_2
	506	and CpuPadLock, respectively.
	507	* i386-init.h: Regenerated.
	508	* i386-tbl.h: Likewise.
	509
24995bd6 L	510	2008-01-03 H.J. Lu <hongjiu.lu@intel.com>
	511
	512	* i386-gen.c (opcode_modifiers): Remove No_xSuf.
	513
	514	* i386-opc.h (No_xSuf): Removed.
	515	(CheckSize): Updated.
	516
	517	* i386-tbl.h: Regenerated.
	518
e0329a22 L	519	2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
	520
	521	* i386-gen.c (cpu_flag_init): Add CpuSSE4_2_Or_ABM to
	522	CPU_AMDFAM10_FLAGS, CPU_SSE4_2_FLAGS, CpuABM and
	523	CPU_SSE5_FLAGS.
	524	(cpu_flags): Add CpuSSE4_2_Or_ABM.
	525
	526	* i386-opc.h (CpuSSE4_2_Or_ABM): New.
	527	(CpuLM): Updated.
	528	(i386_cpu_flags): Add cpusse4_2_or_abm.
	529
	530	* i386-opc.tbl: Use CpuSSE4_2_Or_ABM instead of
	531	CpuABM\|CpuSSE4_2 on popcnt.
	532	* i386-init.h: Regenerated.
	533	* i386-tbl.h: Likewise.
	534
f2a9c676 L	535	2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
	536
	537	* i386-opc.h: Update comments.
	538
d978b5be L	539	2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
	540
	541	* i386-gen.c (opcode_modifiers): Use Qword instead of QWord.
	542	* i386-opc.h: Likewise.
	543	* i386-opc.tbl: Likewise.
	544
582d5edd L	545	2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
	546
	547	PR gas/5534
	548	* i386-gen.c (opcode_modifiers): Add No_xSuf, CheckSize,
	549	Byte, Word, Dword, QWord and Xmmword.
	550
	551	* i386-opc.h (No_xSuf): New.
	552	(CheckSize): Likewise.
	553	(Byte): Likewise.
	554	(Word): Likewise.
	555	(Dword): Likewise.
	556	(QWord): Likewise.
	557	(Xmmword): Likewise.
	558	(FWait): Updated.
	559	(i386_opcode_modifier): Add No_xSuf, CheckSize, Byte, Word,
	560	Dword, QWord and Xmmword.
	561
	562	* i386-opc.tbl: Add CheckSize\|QWord to movq if IgnoreSize is
	563	used.
	564	* i386-tbl.h: Regenerated.
	565
3fe15143 MK	566	2008-01-02 Mark Kettenis <kettenis@gnu.org>
	567
	568	* m88k-dis.c (instructions): Fix fcvt.* instructions.
	569	From Miod Vallat.
	570
6c7ac64e	571	For older changes see ChangeLog-2007
252b5132 RH	572	\f
252b5132 RH	573	Local Variables:
2f6d2f85 NC	574	mode: change-log
	575	left-margin: 8
	576	fill-column: 74
252b5132 RH	577	version-control: never
252b5132 RH	578	End: