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[deliverable/binutils-gdb.git] / opcodes / ChangeLog
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20fd6e2e
PA		 12008-08-01 Pedro Alves <pedro@codesourcery.com>
2
3 * Makefile.am ($(srcdir)/ia64-asmtab.c): Remove line continuation.
4 * Makefile.in: Regenerate.
5
a656ed5b
L		 62008-08-01 H.J. Lu <hongjiu.lu@intel.com>
7
8 * i386-reg.tbl: Use Dw2Inval on AVX registers.
9 * i386-tbl.h: Regenerated.
10
081ba1b3
AM		 112008-07-30 Michael J. Eager <eager@eagercon.com>
12
13 * ppc-dis.c (print_insn_powerpc): Disassemble FSL/FCR/UDI fields.
14 * ppc-opc.c (powerpc_operands): Add Xilinx APU related operands.
15 (insert_sprg, PPC405): Use PPC_OPCODE_405.
16 (powerpc_opcodes): Add Xilinx APU related opcodes.
17
0af1713e
AM		 182008-07-30 Alan Modra <amodra@bigpond.net.au>
19
20 * bfin-dis.c, cris-dis.c, i386-dis.c, or32-opc.c: Silence gcc warnings.
21
30c09090
RS		 222008-07-10 Richard Sandiford <rdsandiford@googlemail.com>
23
24 * mips-dis.c (_print_insn_mips): Use ELF_ST_IS_MIPS16.
25
c27e721e
AN		 262008-07-07 Adam Nemet <anemet@caviumnetworks.com>
27
28 * mips-opc.c (CP): New macro.
29 (mips_builtin_opcodes): Mark c0, c2 and c3 as CP. Add Octeon to the
30 membership of di, dmfc0, dmtc0, ei, mfc0 and mtc0. Add dmfc2 and
31 dmtc2 Octeon instructions.
32
bd2e2557
SS		 332008-07-07 Stan Shebs <stan@codesourcery.com>
34
35 * dis-init.c (init_disassemble_info): Init endian_code field.
36 * arm-dis.c (print_insn): Disassemble code according to
37 setting of endian_code.
38 (print_insn_big_arm): Detect when BE8 extension flag has been set.
39
6ba2a415
RS		 402008-06-30 Richard Sandiford <rdsandiford@googlemail.com>
41
42 * mips-dis.c (_print_insn_mips): Use bfd_asymbol_flavour to check
43 for ELF symbols.
44
c8187e15
PB		 452008-06-25 Peter Bergner <bergner@vnet.ibm.com>
46
47 * ppc-dis.c (powerpc_init_dialect): Handle -M464.
48 (print_ppc_disassembler_options): Likewise.
49 * ppc-opc.c (PPC464): Define.
50 (powerpc_opcodes): Add mfdcrux and mtdcrux.
51
7a283e07
RW		 522008-06-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
53
54 * configure: Regenerate.
55
fa452fa6
PB		 562008-06-13 Peter Bergner <bergner@vnet.ibm.com>
57
58 * ppc-dis.c (print_insn_powerpc): Update prototye to use new
59 ppc_cpu_t typedef.
60 (struct dis_private): New.
61 (POWERPC_DIALECT): New define.
62 (powerpc_dialect): Renamed to...
63 (powerpc_init_dialect): This. Update to use ppc_cpu_t and
64 struct dis_private.
65 (print_insn_big_powerpc): Update for using structure in
66 info->private_data.
67 (print_insn_little_powerpc): Likewise.
68 (operand_value_powerpc): Change type of dialect param to ppc_cpu_t.
69 (skip_optional_operands): Likewise.
70 (print_insn_powerpc): Likewise. Remove initialization of dialect.
71 * ppc-opc.c (extract_bat, extract_bba, extract_bdm, extract_bdp,
72 extract_bo, extract_boe, extract_fxm, extract_mb6, extract_mbe,
73 extract_nb, extract_nsi, extract_rbs, extract_sh6, extract_spr,
74 extract_sprg, extract_tbr insert_bat, insert_bba, insert_bdm,
75 insert_bdp, insert_bo, insert_boe, insert_fxm, insert_mb6, insert_mbe,
76 insert_nsi, insert_ral, insert_ram, insert_raq, insert_ras, insert_rbs,
77 insert_sh6, insert_spr, insert_sprg, insert_tbr): Change the dialect
78 param to be of type ppc_cpu_t. Update prototype.
79
bb35fb24
NC		 802008-06-12 Adam Nemet <anemet@caviumnetworks.com>
81
82 * mips-dis.c (print_insn_args): Handle field descriptors +x, +p,
83 +s, +S.
84 * mips-opc.c (mips_builtin_opcodes): Add Octeon instructions
85 baddu, bbit*, cins*, dmul, pop, dpop, exts*, mtm*, mtp*, syncs,
86 syncw, syncws, vm3mulu, vm0 and vmulu.
87
dd3cbb7e
NC		 88 * mips-dis.c (print_insn_args): Handle field descriptor +Q.
89 * mips-opc.c (mips_builtin_opcodes): Add Octeon instructions seq,
90 seqi, sne and snei.
91
a5dabbb0
L		 922008-05-30 H.J. Lu <hongjiu.lu@intel.com>
93
94 * i386-opc.tbl: Add vmovd with 64bit operand.
95 * i386-tbl.h: Regenerated.
96
725a9891
MS		 972008-05-27 Martin Schwidefsky <schwidefsky@de.ibm.com>
98
99 * s390-opc.c (INSTR_RRF_R0RR): Fix RRF_R0RR operand format.
100
cbc80391
L		 1012008-05-22 H.J. Lu <hongjiu.lu@intel.com>
102
103 * i386-opc.tbl: Add NoAVX to cvtpd2pi, cvtpi2pd and cvttpd2pi.
104 * i386-tbl.h: Regenerated.
105
116615c5
L		 1062008-05-22 H.J. Lu <hongjiu.lu@intel.com>
107
108 PR gas/6517
109 * i386-opc.tbl: Break cvtsi2ss/cvtsi2sd/vcvtsi2sd/vcvtsi2ss
110 into 32bit and 64bit. Remove Reg64|Qword and add
111 IgnoreSize|No_qSuf on 32bit version.
112 * i386-tbl.h: Regenerated.
113
d9479f2d
L		 1142008-05-21 H.J. Lu <hongjiu.lu@intel.com>
115
116 * i386-opc.tbl: Add NoAVX to movdq2q and movq2dq.
117 * i386-tbl.h: Regenerated.
118
3ce6fddb
NC		 1192008-05-21 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
120
121 * cr16-dis.c (build_mask): Adjust the mask for 32-bit bcond.
122
8944f3c2
AM		 1232008-05-14 Alan Modra <amodra@bigpond.net.au>
124
125 * Makefile.am: Run "make dep-am".
126 * Makefile.in: Regenerate.
127
f1f8f695
L		 1282008-05-02 H.J. Lu <hongjiu.lu@intel.com>
129
130 * i386-dis.c (MOVBE_Fixup): New.
131 (Mo): Likewise.
132 (PREFIX_0F3880): Likewise.
133 (PREFIX_0F3881): Likewise.
134 (PREFIX_0F38F0): Updated.
135 (prefix_table): Add PREFIX_0F3880 and PREFIX_0F3881. Update
136 PREFIX_0F38F0 and PREFIX_0F38F1 for movbe.
137 (three_byte_table): Use PREFIX_0F3880 and PREFIX_0F3881.
138
139 * i386-gen.c (cpu_flag_init): Add CPU_MOVBE_FLAGS and
140 CPU_EPT_FLAGS.
141 (cpu_flags): Add CpuMovbe and CpuEPT.
142
143 * i386-opc.h (CpuMovbe): New.
144 (CpuEPT): Likewise.
145 (CpuLM): Updated.
146 (i386_cpu_flags): Add cpumovbe and cpuept.
147
148 * i386-opc.tbl: Add entries for movbe and EPT instructions.
149 * i386-init.h: Regenerated.
150 * i386-tbl.h: Likewise.
151
89aa3097
AN		 1522008-04-29 Adam Nemet <anemet@caviumnetworks.com>
153
154 * mips-opc.c (mips_builtin_opcodes): Set field `match' to 0 for
155 the two drem and the two dremu macros.
156
39c5c168
AN		 1572008-04-28 Adam Nemet <anemet@caviumnetworks.com>
158
159 * mips-opc.c (mips_builtin_opcodes): Mark prefx and c1
160 instructions FP_S. Mark l.s, li.s, lwc1, swc1, s.s, trunc.w.s and
161 cop1 macros INSN2_M_FP_S. Mark l.d, li.d, ldc1 and sdc1 macros
162 INSN2_M_FP_D. Mark trunc.w.d macro INSN2_M_FP_S and INSN2_M_FP_D.
163
f04d18b7
DM		 1642008-04-25 David S. Miller <davem@davemloft.net>
165
166 * sparc-dis.c: Emit %stick instead of %sys_tick, and %stick_cmpr
167 instead of %sys_tick_cmpr, as suggested in architecture manuals.
168
6194aaab
L		 1692008-04-23 Paolo Bonzini <bonzini@gnu.org>
170
171 * aclocal.m4: Regenerate.
172 * configure: Regenerate.
173
1a6b486f
DM		 1742008-04-23 David S. Miller <davem@davemloft.net>
175
176 * sparc-opc.c (asi_table): Add UltraSPARC and Niagara
177 extended values.
178 (prefetch_table): Add missing values.
179
81f8a913
L		 1802008-04-22 H.J. Lu <hongjiu.lu@intel.com>
181
182 * i386-gen.c (opcode_modifiers): Add NoAVX.
183
184 * i386-opc.h (NoAVX): New.
185 (OldGcc): Updated.
186 (i386_opcode_modifier): Add noavx.
187
188 * i386-opc.tbl: Add NoAVX to SSE, SSE2, SSE3 and SSSE3
189 instructions which don't have AVX equivalent.
190 * i386-tbl.h: Regenerated.
191
dae39acc
L		 1922008-04-18 H.J. Lu <hongjiu.lu@intel.com>
193
194 * i386-dis.c (OP_VEX_FMA): New.
195 (OP_EX_VexImmW): Likewise.
196 (VexFMA): Likewise.
197 (Vex128FMA): Likewise.
198 (EXVexImmW): Likewise.
199 (get_vex_imm8): Likewise.
200 (OP_EX_VexReg): Likewise.
201 (vex_i4_done): Renamed to ...
202 (vex_w_done): This.
203 (prefix_table): Replace EXVexW with EXVexImmW on vpermil2ps
204 and vpermil2pd. Replace Vex/Vex128 with VexFMA/Vex128FMA on
205 FMA instructions.
206 (print_insn): Updated.
207 (OP_EX_VexW): Rewrite to swap register in VEX with EX.
208 (OP_REG_VexI4): Check invalid high registers.
209
ce886ab1
DR		 2102008-04-16 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
211 Michael Meissner <michael.meissner@amd.com>
212
213 * i386-opc.tbl: Fix protX to allow memory in the middle operand.
214 * i386-tbl.h: Regenerate from i386-opc.tbl.
8944f3c2 215
19a6653c
AM		 2162008-04-14 Edmar Wienskoski <edmar@freescale.com>
217
218 * ppc-dis.c (powerpc_dialect): Handle "e500mc". Extend "e500" to
219 accept Power E500MC instructions.
220 (print_ppc_disassembler_options): Document -Me500mc.
221 * ppc-opc.c (DUIS, DUI, T): New.
222 (XRT, XRTRA): Likewise.
223 (E500MC): Likewise.
224 (powerpc_opcodes): Add new Power E500MC instructions.
225
112b7c50
AK		 2262008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
227
228 * s390-dis.c (init_disasm): Evaluate disassembler_options.
229 (print_s390_disassembler_options): New function.
230 * disassemble.c (disassembler_usage): Invoke
231 print_s390_disassembler_options.
232
7ff42648
AK		 2332008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
234
235 * s390-mkopc.c (insertExpandedMnemonic): Expand string sizes
236 of local variables used for mnemonic parsing: prefix, suffix and
237 number.
238
45a5551e
AK		 2392008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
240
241 * s390-mkopc.c (s390_cond_ext_format): Add back the mnemonic
242 extensions for conditional jumps (o, p, m, nz, z, nm, np, no).
243 (s390_crb_extensions): New extensions table.
244 (insertExpandedMnemonic): Handle '$' tag.
245 * s390-opc.txt: Remove conditional jump variants which can now
246 be expanded automatically.
247 Replace '*' tag with '$' in the compare and branch instructions.
248
06c8514a
L		 2492008-04-07 H.J. Lu <hongjiu.lu@intel.com>
250
251 * i386-dis.c (PREFIX_VEX_38XX): Add a tab.
252 (PREFIX_VEX_3AXX): Likewis.
253
b122c285
L		 2542008-04-07 H.J. Lu <hongjiu.lu@intel.com>
255
256 * i386-opc.tbl: Remove 4 extra blank lines.
257
594ab6a3
L		 2582008-04-04 H.J. Lu <hongjiu.lu@intel.com>
259
260 * i386-gen.c (cpu_flag_init): Replace CPU_CLMUL_FLAGS/CpuCLMUL
261 with CPU_PCLMUL_FLAGS/CpuPCLMUL.
262 (cpu_flags): Replace CpuCLMUL with CpuPCLMUL.
263 * i386-opc.tbl: Likewise.
264
265 * i386-opc.h (CpuCLMUL): Renamed to ...
266 (CpuPCLMUL): This.
267 (CpuFMA): Updated.
268 (i386_cpu_flags): Replace cpuclmul with cpupclmul.
269
270 * i386-init.h: Regenerated.
271
c0f3af97
L		 2722008-04-03 H.J. Lu <hongjiu.lu@intel.com>
273
274 * i386-dis.c (OP_E_register): New.
275 (OP_E_memory): Likewise.
276 (OP_VEX): Likewise.
277 (OP_EX_Vex): Likewise.
278 (OP_EX_VexW): Likewise.
279 (OP_XMM_Vex): Likewise.
280 (OP_XMM_VexW): Likewise.
281 (OP_REG_VexI4): Likewise.
282 (PCLMUL_Fixup): Likewise.
283 (VEXI4_Fixup): Likewise.
284 (VZERO_Fixup): Likewise.
285 (VCMP_Fixup): Likewise.
286 (VPERMIL2_Fixup): Likewise.
287 (rex_original): Likewise.
288 (rex_ignored): Likewise.
289 (Mxmm): Likewise.
290 (XMM): Likewise.
291 (EXxmm): Likewise.
292 (EXxmmq): Likewise.
293 (EXymmq): Likewise.
294 (Vex): Likewise.
295 (Vex128): Likewise.
296 (Vex256): Likewise.
297 (VexI4): Likewise.
298 (EXdVex): Likewise.
299 (EXqVex): Likewise.
300 (EXVexW): Likewise.
301 (EXdVexW): Likewise.
302 (EXqVexW): Likewise.
303 (XMVex): Likewise.
304 (XMVexW): Likewise.
305 (XMVexI4): Likewise.
306 (PCLMUL): Likewise.
307 (VZERO): Likewise.
308 (VCMP): Likewise.
309 (VPERMIL2): Likewise.
310 (xmm_mode): Likewise.
311 (xmmq_mode): Likewise.
312 (ymmq_mode): Likewise.
313 (vex_mode): Likewise.
314 (vex128_mode): Likewise.
315 (vex256_mode): Likewise.
316 (USE_VEX_C4_TABLE): Likewise.
317 (USE_VEX_C5_TABLE): Likewise.
318 (USE_VEX_LEN_TABLE): Likewise.
319 (VEX_C4_TABLE): Likewise.
320 (VEX_C5_TABLE): Likewise.
321 (VEX_LEN_TABLE): Likewise.
322 (REG_VEX_XX): Likewise.
323 (MOD_VEX_XXX): Likewise.
324 (PREFIX_0F38DB..PREFIX_0F38DF): Likewise.
325 (PREFIX_0F3A44): Likewise.
326 (PREFIX_0F3ADF): Likewise.
327 (PREFIX_VEX_XXX): Likewise.
328 (VEX_OF): Likewise.
329 (VEX_OF38): Likewise.
330 (VEX_OF3A): Likewise.
331 (VEX_LEN_XXX): Likewise.
332 (vex): Likewise.
333 (need_vex): Likewise.
334 (need_vex_reg): Likewise.
335 (vex_i4_done): Likewise.
336 (vex_table): Likewise.
337 (vex_len_table): Likewise.
338 (OP_REG_VexI4): Likewise.
339 (vex_cmp_op): Likewise.
340 (pclmul_op): Likewise.
341 (vpermil2_op): Likewise.
342 (m_mode): Updated.
343 (es_reg): Likewise.
344 (PREFIX_0F38F0): Likewise.
345 (PREFIX_0F3A60): Likewise.
346 (reg_table): Add REG_VEX_71...REG_VEX_73 and REG_VEX_AE.
347 (prefix_table): Add PREFIX_0F38DB..PREFIX_0F38DF, PREFIX_0F3ADF
348 and PREFIX_VEX_XXX entries.
349 (x86_64_table): Use VEX_C4_TABLE and VEX_C5_TABLE.
350 (three_byte_table): Use PREFIX_0F38DB..PREFIX_0F38DF and
351 PREFIX_0F3ADF.
352 (mod_table): Use VEX_C4_TABLE, VEX_C5_TABLE and VEX_LEN_TABLE.
353 Add MOD_VEX_XXX entries.
354 (ckprefix): Initialize rex_original and rex_ignored. Store the
355 REX byte in rex_original.
356 (get_valid_dis386): Handle the implicit prefix in VEX prefix
357 bytes and USE_VEX_LEN_TABLE/USE_VEX_C4_TABLE/USE_VEX_C5_TABLE.
358 (print_insn): Set need_vex/need_vex_reg/vex_i4_done to 0 before
359 calling get_valid_dis386. Use rex_original and rex_ignored when
360 printing out REX.
361 (putop): Handle "XY".
362 (intel_operand_size): Handle VEX, xmm_mode, xmmq_mode and
363 ymmq_mode.
364 (OP_E_extended): Updated to use OP_E_register and
365 OP_E_memory.
366 (OP_XMM): Handle VEX.
367 (OP_EX): Likewise.
368 (XMM_Fixup): Likewise.
369 (CMP_Fixup): Use ARRAY_SIZE.
370
371 * i386-gen.c (cpu_flag_init): Add CpuAES, CPU_CLMUL_FLAGS,
372 CPU_FMA_FLAGS and CPU_AVX_FLAGS.
373 (operand_type_init): Add OPERAND_TYPE_REGYMM and
374 OPERAND_TYPE_VEX_IMM4.
375 (cpu_flags): Add CpuAVX, CpuAES, CpuCLMUL and CpuFMA.
376 (opcode_modifiers): Add Implicit1stXmm0, Vex, Vex256, VexNDD,
377 VexNDS, VexW0, VexW1, Vex0F, Vex0F38, Vex0F3A, Vex3Sources,
378 VexImmExt and SSE2AVX.
379 (operand_types): Add RegYMM, Ymmword and Vex_Imm4.
380
381 * i386-opc.h (CpuAVX): New.
382 (CpuAES): Likewise.
383 (CpuCLMUL): Likewise.
384 (CpuFMA): Likewise.
385 (Vex): Likewise.
386 (Vex256): Likewise.
387 (VexNDS): Likewise.
388 (VexNDD): Likewise.
389 (VexW0): Likewise.
390 (VexW1): Likewise.
391 (Vex0F): Likewise.
392 (Vex0F38): Likewise.
393 (Vex0F3A): Likewise.
394 (Vex3Sources): Likewise.
395 (VexImmExt): Likewise.
396 (SSE2AVX): Likewise.
397 (RegYMM): Likewise.
398 (Ymmword): Likewise.
399 (Vex_Imm4): Likewise.
400 (Implicit1stXmm0): Likewise.
401 (CpuXsave): Updated.
402 (CpuLM): Likewise.
403 (ByteOkIntel): Likewise.
404 (OldGcc): Likewise.
405 (Control): Likewise.
406 (Unspecified): Likewise.
407 (OTMax): Likewise.
408 (i386_cpu_flags): Add cpuavx, cpuaes, cpuclmul and cpufma.
409 (i386_opcode_modifier): Add implicit1stxmm0, vex, vex256,
410 vexnds, vexndd, vexw0, vexw1, vex0f, vex0f38, vex0f3a,
411 vex3sources, veximmext and sse2avx.
412 (i386_operand_type): Add regymm, ymmword and vex_imm4.
413
414 * i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions.
415
416 * i386-reg.tbl: Add AVX registers, ymm0..ymm15.
417
418 * i386-init.h: Regenerated.
419 * i386-tbl.h: Likewise.
420
b21c9cb4
BS		 4212008-03-26 Bernd Schmidt <bernd.schmidt@analog.com>
422
423 From Robin Getz <robin.getz@analog.com>
424 * bfin-dis.c (bu32): Typedef.
425 (enum const_forms_t): Add c_uimm32 and c_huimm32.
426 (constant_formats[]): Add uimm32 and huimm16.
427 (fmtconst_val): New.
428 (uimm32): Define.
429 (huimm32): Define.
430 (imm16_val): Define.
431 (luimm16_val): Define.
432 (struct saved_state): Define.
433 (GREG, DPREG, DREG, PREG, SPREG, FPREG, IREG, MREG, BREG, LREG,
434 A0XREG, A0WREG, A1XREG, A1WREG,CCREG, LC0REG, LT0REG, LB0REG,
435 LC1REG, LT1REG, LB1REG, RETSREG, PCREG): Define.
436 (get_allreg): New.
437 (decode_LDIMMhalf_0): Print out the whole register value.
438
ee171c8f
BS		 439 From Jie Zhang <jie.zhang@analog.com>
440 * bfin-dis.c (decode_dsp32mac_0): Decode (IU) option for
441 multiply and multiply-accumulate to data register instruction.
442
086134ec
BS		 443 * bfin-dis.c: (c_uimm4s4d, c_imm5d, c_imm7d, c_imm16d, c_uimm16s4d,
444 c_imm32, c_huimm32e): Define.
445 (constant_formats): Add flags for printing decimal, leading spaces, and
446 exact symbols.
447 (comment, parallel): Add global flags in all disassembly.
448 (fmtconst): Take advantage of new flags, and print default in hex.
449 (fmtconst_val): Likewise.
450 (decode_macfunc): Be consistant with spaces, tabs, comments,
451 capitalization in disassembly, fix minor coding style issues.
452 (reg_names, amod0, amod1, amod0amod2, aligndir, get_allreg): Likewise.
453 (decode_ProgCtrl_0, decode_PushPopMultiple_0, decode_CCflag_0,
454 decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0,
455 decode_REGMV_0, decode_ALU2op_0, decode_PTR2op_0, decode_LOGI2op_0,
456 decode_COMP3op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
457 decode_LDSTpmod_0, decode_dagMODim_0, decode_dagMODik_0,
458 decode_dspLDST_0, decode_LDST_0, decode_LDSTiiFP_0, decode_LDSTii_0,
459 decode_LoopSetup_0, decode_LDIMMhalf_0, decode_CALLa_0,
460 decode_LDSTidxI_0, decode_linkage_0, decode_dsp32alu_0,
461 decode_dsp32shift_0, decode_dsp32shiftimm_0, decode_pseudodbg_assert_0,
462 _print_insn_bfin, print_insn_bfin): Likewise.
463
58c85be7
RW		 4642008-03-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
465
466 * aclocal.m4: Regenerate.
467 * configure: Likewise.
468 * Makefile.in: Likewise.
469
50e7d84b
AM		 4702008-03-13 Alan Modra <amodra@bigpond.net.au>
471
472 * Makefile.am: Run "make dep-am".
473 * Makefile.in: Regenerate.
474 * configure: Regenerate.
475
de866fcc
AM		 4762008-03-07 Alan Modra <amodra@bigpond.net.au>
477
478 * ppc-opc.c (powerpc_opcodes): Order and format.
479
28dbc079
L		 4802008-03-01 H.J. Lu <hongjiu.lu@intel.com>
481
482 * i386-opc.tbl: Allow 16-bit near indirect branches for x86-64.
483 * i386-tbl.h: Regenerated.
484
849830bd
L		 4852008-02-23 H.J. Lu <hongjiu.lu@intel.com>
486
487 * i386-opc.tbl: Disallow 16-bit near indirect branches for
488 x86-64.
489 * i386-tbl.h: Regenerated.
490
743ddb6b
JB		 4912008-02-21 Jan Beulich <jbeulich@novell.com>
492
493 * i386-opc.tbl: Allow Dword for far indirect call. Allow Dword
494 and Fword for far indirect jmp. Allow Reg16 and Word for near
495 indirect jmp on x86-64. Disallow Fword for lcall.
496 * i386-tbl.h: Re-generate.
497
796d5313
NC		 4982008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
499
500 * cr16-opc.c (cr16_num_optab): Defined
501
65da13b5
L		 5022008-02-16 H.J. Lu <hongjiu.lu@intel.com>
503
504 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_INOUTPORTREG.
505 * i386-init.h: Regenerated.
506
0e336180
NC		 5072008-02-14 Nick Clifton <nickc@redhat.com>
508
509 PR binutils/5524
510 * configure.in (SHARED_LIBADD): Select the correct host specific
511 file extension for shared libraries.
512 * configure: Regenerate.
513
b7240065
JB		 5142008-02-13 Jan Beulich <jbeulich@novell.com>
515
516 * i386-opc.h (RegFlat): New.
517 * i386-reg.tbl (flat): Add.
518 * i386-tbl.h: Re-generate.
519
34b772a6
JB		 5202008-02-13 Jan Beulich <jbeulich@novell.com>
521
522 * i386-dis.c (a_mode): New.
523 (cond_jump_mode): Adjust.
524 (Ma): Change to a_mode.
525 (intel_operand_size): Handle a_mode.
526 * i386-opc.tbl: Allow Dword and Qword for bound.
527 * i386-tbl.h: Re-generate.
528
a60de03c
JB		 5292008-02-13 Jan Beulich <jbeulich@novell.com>
530
531 * i386-gen.c (process_i386_registers): Process new fields.
532 * i386-opc.h (reg_entry): Shrink reg_flags and reg_num to
533 unsigned char. Add dw2_regnum and Dw2Inval.
534 * i386-reg.tbl: Provide initializers for dw2_regnum. Add pseudo
535 register names.
536 * i386-tbl.h: Re-generate.
537
f03fe4c1
L		 5382008-02-11 H.J. Lu <hongjiu.lu@intel.com>
539
4b6bc8eb 540 * i386-gen.c (cpu_flag_init): Add CPU_XSAVE_FLAGS.
f03fe4c1
L		 541 * i386-init.h: Updated.
542
475a2301
L		 5432008-02-11 H.J. Lu <hongjiu.lu@intel.com>
544
545 * i386-gen.c (cpu_flags): Add CpuXsave.
546
547 * i386-opc.h (CpuXsave): New.
4b6bc8eb 548 (CpuLM): Updated.
475a2301
L		 549 (i386_cpu_flags): Add cpuxsave.
550
551 * i386-dis.c (MOD_0FAE_REG_4): New.
552 (RM_0F01_REG_2): Likewise.
553 (MOD_0FAE_REG_5): Updated.
554 (RM_0F01_REG_3): Likewise.
555 (reg_table): Use MOD_0FAE_REG_4.
556 (mod_table): Use RM_0F01_REG_2. Add MOD_0FAE_REG_4. Updated
557 for xrstor.
558 (rm_table): Add RM_0F01_REG_2.
559
560 * i386-opc.tbl: Add xsave, xrstor, xgetbv and xsetbv.
561 * i386-init.h: Regenerated.
562 * i386-tbl.h: Likewise.
563
595785c6 5642008-02-11 Jan Beulich <jbeulich@novell.com>
041179fc 565
595785c6
JB		 566 * i386-opc.tbl: Remove Disp32S from CpuNo64 opcodes. Remove
567 Disp16 from Cpu64 non-jump opcodes (including loop and j?cxz).
568 * i386-tbl.h: Re-generate.
569
bb8541b9
L		 5702008-02-04 H.J. Lu <hongjiu.lu@intel.com>
571
572 PR 5715
573 * configure: Regenerated.
574
57b592a3
AN		 5752008-02-04 Adam Nemet <anemet@caviumnetworks.com>
576
577 * mips-dis.c: Update copyright.
578 (mips_arch_choices): Add Octeon.
579 * mips-opc.c: Update copyright.
580 (IOCT): New macro.
581 (mips_builtin_opcodes): Add Octeon instruction synciobdma.
582
930bb4cf
AM		 5832008-01-29 Alan Modra <amodra@bigpond.net.au>
584
585 * ppc-opc.c: Support optional L form mtmsr.
586
82c18208
L		 5872008-01-24 H.J. Lu <hongjiu.lu@intel.com>
588
589 * i386-dis.c (OP_E_extended): Handle r12 like rsp.
590
599121aa
L		 5912008-01-23 H.J. Lu <hongjiu.lu@intel.com>
592
593 * i386-gen.c (cpu_flag_init): Add CpuLM to CPU_GENERIC64_FLAGS.
594 * i386-init.h: Regenerated.
595
80098f51
TG		 5962008-01-23 Tristan Gingold <gingold@adacore.com>
597
598 * ia64-dis.c (print_insn_ia64): Display symbolic name of ar.fcr,
599 ar.eflag, ar.csd, ar.ssd, ar.cflg, ar.fsr, ar.fir and ar.fdr.
600
115c7c25
L		 6012008-01-22 H.J. Lu <hongjiu.lu@intel.com>
602
603 * i386-gen.c (cpu_flag_init): Remove CpuMMX2.
604 (cpu_flags): Likewise.
605
606 * i386-opc.h (CpuMMX2): Removed.
607 (CpuSSE): Updated.
608
609 * i386-opc.tbl: Replace CpuMMX2 with CpuSSE|Cpu3dnowA.
610 * i386-init.h: Regenerated.
611 * i386-tbl.h: Likewise.
612
6305a203
L		 6132008-01-22 H.J. Lu <hongjiu.lu@intel.com>
614
615 * i386-gen.c (cpu_flag_init): Add CPU_VMX_FLAGS and
616 CPU_SMX_FLAGS.
617 * i386-init.h: Regenerated.
618
fd07a1c8
L		 6192008-01-15 H.J. Lu <hongjiu.lu@intel.com>
620
621 * i386-opc.tbl: Use Qword on movddup.
622 * i386-tbl.h: Regenerated.
623
321fd21e
L		 6242008-01-15 H.J. Lu <hongjiu.lu@intel.com>
625
626 * i386-opc.tbl: Put back 16bit movsx/movzx for AT&T syntax.
627 * i386-tbl.h: Regenerated.
628
4ee52178
L		 6292008-01-15 H.J. Lu <hongjiu.lu@intel.com>
630
631 * i386-dis.c (Mx): New.
632 (PREFIX_0FC3): Likewise.
633 (PREFIX_0FC7_REG_6): Updated.
634 (dis386_twobyte): Use PREFIX_0FC3.
635 (prefix_table): Add PREFIX_0FC3. Use Mq on movntq and movntsd.
636 Use Mx on movntps, movntpd, movntdq and movntdqa. Use Md on
637 movntss.
638
5c07affc
L		 6392008-01-14 H.J. Lu <hongjiu.lu@intel.com>
640
641 * i386-gen.c (opcode_modifiers): Add IntelSyntax.
642 (operand_types): Add Mem.
643
644 * i386-opc.h (IntelSyntax): New.
645 * i386-opc.h (Mem): New.
646 (Byte): Updated.
647 (Opcode_Modifier_Max): Updated.
648 (i386_opcode_modifier): Add intelsyntax.
649 (i386_operand_type): Add mem.
650
651 * i386-opc.tbl: Remove Reg16 from movnti. Add sizes to more
652 instructions.
653
654 * i386-reg.tbl: Add size for accumulator.
655
656 * i386-init.h: Regenerated.
657 * i386-tbl.h: Likewise.
658
0d6a2f58
L		 6592008-01-13 H.J. Lu <hongjiu.lu@intel.com>
660
661 * i386-opc.h (Byte): Fix a typo.
662
7d5e4556
L		 6632008-01-12 H.J. Lu <hongjiu.lu@intel.com>
664
665 PR gas/5534
666 * i386-gen.c (operand_type_init): Add Dword to
667 OPERAND_TYPE_ACC32. Add Qword to OPERAND_TYPE_ACC64.
668 (opcode_modifiers): Remove CheckSize, Byte, Word, Dword,
669 Qword and Xmmword.
670 (operand_types): Add Byte, Word, Dword, Fword, Qword, Tbyte,
671 Xmmword, Unspecified and Anysize.
672 (set_bitfield): Make Mmword an alias of Qword. Make Oword
673 an alias of Xmmword.
674
675 * i386-opc.h (CheckSize): Removed.
676 (Byte): Updated.
677 (Word): Likewise.
678 (Dword): Likewise.
679 (Qword): Likewise.
680 (Xmmword): Likewise.
681 (FWait): Updated.
682 (OTMax): Likewise.
683 (i386_opcode_modifier): Remove checksize, byte, word, dword,
684 qword and xmmword.
685 (Fword): New.
686 (TBYTE): Likewise.
687 (Unspecified): Likewise.
688 (Anysize): Likewise.
689 (i386_operand_type): Add byte, word, dword, fword, qword,
690 tbyte xmmword, unspecified and anysize.
691
692 * i386-opc.tbl: Updated to use Byte, Word, Dword, Fword, Qword,
693 Tbyte, Xmmword, Unspecified and Anysize.
694
695 * i386-reg.tbl: Add size for accumulator.
696
697 * i386-init.h: Regenerated.
698 * i386-tbl.h: Likewise.
699
b5b1fc4f
L		 7002008-01-10 H.J. Lu <hongjiu.lu@intel.com>
701
702 * i386-dis.c (REG_0F0E): Renamed to REG_0F0D.
703 (REG_0F18): Updated.
704 (reg_table): Updated.
705 (dis386_twobyte): Updated. Use "nopQ" on 0x19 to 0x1e.
706 (twobyte_has_modrm): Set 1 for 0x19 to 0x1e.
707
50e8458f
L		 7082008-01-08 H.J. Lu <hongjiu.lu@intel.com>
709
710 * i386-gen.c (set_bitfield): Use fail () on error.
711
3d4d5afa
L		 7122008-01-08 H.J. Lu <hongjiu.lu@intel.com>
713
714 * i386-gen.c (lineno): New.
715 (filename): Likewise.
716 (set_bitfield): Report filename and line numer on error.
717 (process_i386_opcodes): Set filename and update lineno.
718 (process_i386_registers): Likewise.
719
e1d4d893
L		 7202008-01-05 H.J. Lu <hongjiu.lu@intel.com>
721
722 * i386-gen.c (opcode_modifiers): Rename IntelMnemonic to
723 ATTSyntax.
724
725 * i386-opc.h (IntelMnemonic): Renamed to ..
726 (ATTSyntax): This
727 (Opcode_Modifier_Max): Updated.
728 (i386_opcode_modifier): Remove intelmnemonic. Add attsyntax
729 and intelsyntax.
730
8944f3c2 731 * i386-opc.tbl: Remove IntelMnemonic and update with ATTSyntax
e1d4d893
L		 732 on fsub, fubp, fsubr, fsubrp, div, fdivp, fdivr and fdivrp.
733 * i386-tbl.h: Regenerated.
734
6f143e4d
L		 7352008-01-04 H.J. Lu <hongjiu.lu@intel.com>
736
737 * i386-gen.c: Update copyright to 2008.
738 * i386-opc.h: Likewise.
739 * i386-opc.tbl: Likewise.
740
741 * i386-init.h: Regenerated.
742 * i386-tbl.h: Likewise.
743
c6add537
L		 7442008-01-04 H.J. Lu <hongjiu.lu@intel.com>
745
746 * i386-opc.tbl: Add NoRex64 to extractps, movmskpd, movmskps,
747 pextrb, pextrw, pinsrb, pinsrw and pmovmskb.
748 * i386-tbl.h: Regenerated.
749
3629bb00
L		 7502008-01-03 H.J. Lu <hongjiu.lu@intel.com>
751
752 * i386-gen.c (cpu_flag_init): Remove CpuSSE4_1_Or_5 and
753 CpuSSE4_2_Or_ABM.
754 (cpu_flags): Likewise.
755
756 * i386-opc.h (CpuSSE4_1_Or_5): Removed.
757 (CpuSSE4_2_Or_ABM): Likewise.
758 (CpuLM): Updated.
759 (i386_cpu_flags): Remove cpusse4_1_or_5 and cpusse4_2_or_abm.
760
761 * i386-opc.tbl: Replace CpuSSE4_1_Or_5, CpuSSE4_2_Or_ABM and
762 Cpu686|CpuPadLock with CpuSSE4_1|CpuSSE5, CpuABM|CpuSSE4_2
763 and CpuPadLock, respectively.
764 * i386-init.h: Regenerated.
765 * i386-tbl.h: Likewise.
766
24995bd6
L		 7672008-01-03 H.J. Lu <hongjiu.lu@intel.com>
768
769 * i386-gen.c (opcode_modifiers): Remove No_xSuf.
770
771 * i386-opc.h (No_xSuf): Removed.
772 (CheckSize): Updated.
773
774 * i386-tbl.h: Regenerated.
775
e0329a22
L		 7762008-01-02 H.J. Lu <hongjiu.lu@intel.com>
777
778 * i386-gen.c (cpu_flag_init): Add CpuSSE4_2_Or_ABM to
779 CPU_AMDFAM10_FLAGS, CPU_SSE4_2_FLAGS, CpuABM and
780 CPU_SSE5_FLAGS.
781 (cpu_flags): Add CpuSSE4_2_Or_ABM.
782
783 * i386-opc.h (CpuSSE4_2_Or_ABM): New.
784 (CpuLM): Updated.
785 (i386_cpu_flags): Add cpusse4_2_or_abm.
786
787 * i386-opc.tbl: Use CpuSSE4_2_Or_ABM instead of
788 CpuABM|CpuSSE4_2 on popcnt.
789 * i386-init.h: Regenerated.
790 * i386-tbl.h: Likewise.
791
f2a9c676
L		 7922008-01-02 H.J. Lu <hongjiu.lu@intel.com>
793
794 * i386-opc.h: Update comments.
795
d978b5be
L		 7962008-01-02 H.J. Lu <hongjiu.lu@intel.com>
797
798 * i386-gen.c (opcode_modifiers): Use Qword instead of QWord.
799 * i386-opc.h: Likewise.
800 * i386-opc.tbl: Likewise.
801
582d5edd
L		 8022008-01-02 H.J. Lu <hongjiu.lu@intel.com>
803
804 PR gas/5534
805 * i386-gen.c (opcode_modifiers): Add No_xSuf, CheckSize,
806 Byte, Word, Dword, QWord and Xmmword.
807
808 * i386-opc.h (No_xSuf): New.
809 (CheckSize): Likewise.
810 (Byte): Likewise.
811 (Word): Likewise.
812 (Dword): Likewise.
813 (QWord): Likewise.
814 (Xmmword): Likewise.
815 (FWait): Updated.
816 (i386_opcode_modifier): Add No_xSuf, CheckSize, Byte, Word,
817 Dword, QWord and Xmmword.
818
819 * i386-opc.tbl: Add CheckSize|QWord to movq if IgnoreSize is
820 used.
821 * i386-tbl.h: Regenerated.
822
3fe15143
MK		 8232008-01-02 Mark Kettenis <kettenis@gnu.org>
824
825 * m88k-dis.c (instructions): Fix fcvt.* instructions.
826 From Miod Vallat.
827
6c7ac64e 828For older changes see ChangeLog-2007
252b5132
RH		 829\f
830Local Variables:
2f6d2f85
NC		 831mode: change-log
832left-margin: 8
833fill-column: 74
252b5132
RH		 834version-control: never
835End:
GDB Binutils - Deliverables
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