Move cpu files from cgen/cpu to top level cpu directory.
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
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12011-08-22 Nick Clifton <nickc@redhat.com>
2
3 * Makefile.am (CPUDIR): Redfine to point to top level cpu
4 directory.
5 (stamp-frv): Use CPUDIR.
6 (stamp-iq2000): Likewise.
7 (stamp-lm32): Likewise.
8 (stamp-m32c): Likewise.
9 (stamp-mt): Likewise.
10 (stamp-xc16x): Likewise.
11 * Makefile.in: Regenerate.
12
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132011-08-09 Chao-ying Fu <fu@mips.com>
14 Maciej W. Rozycki <macro@codesourcery.com>
15
16 * mips-dis.c (mips_arch_choices): Enable MCU for "mips32r2"
17 and "mips64r2".
18 (print_insn_args, print_insn_micromips): Handle MCU.
19 * micromips-opc.c (MC): New macro.
20 (micromips_opcodes): Add "aclr", "aset" and "iret".
21 * mips-opc.c (MC): New macro.
22 (mips_builtin_opcodes): Add "aclr", "aset" and "iret".
23
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242011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
25
26 * micromips-opc.c (MOD_mb, MOD_mc, MOD_md): Remove macros.
27 (MOD_me, MOD_mf, MOD_mg, MOD_mhi, MOD_mj, MOD_ml): Likewise.
28 (MOD_mm, MOD_mn, MOD_mp, MOD_mq, MOD_sp): Likewise.
29 (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf): New macros.
30 (RD_mg, WR_mhi, RD_mj, WR_mj, RD_ml, RD_mmn): Likewise.
31 (RD_mp, WR_mp, RD_mq, RD_sp, WR_sp): Likewise.
32 (WR_s): Update macro.
33 (micromips_opcodes): Update register use flags of: "addiu",
34 "addiupc", "addiur1sp", "addiur2", "addius5", "addiusp", "addu",
35 "and", "andi", "beq", "beqz", "bne", "bnez", "di", "ei", "j",
36 "jalr", "jalrs", "jr", "jraddiusp", "jrc", "lbu", "lhu", "li",
37 "lui", "lw", "lwm", "mfhi", "mflo", "move", "movep", "not",
38 "nor", "or", "ori", "sb", "sh", "sll", "srl", "subu", "sw",
39 "swm" and "xor" instructions.
40
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412011-08-05 David S. Miller <davem@davemloft.net>
42
43 * sparc-dis.c (v9a_ast_reg_names): Add "cps".
44 (X_RS3): New macro.
45 (print_insn_sparc): Handle '4', '5', and '(' format codes.
46 Accept %asr numbers below 28.
47 * sparc-opc.c (sparc_opcodes): Add entries for HPC and VIS3
48 instructions.
49
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502011-08-02 Quentin Neill <quentin.neill@amd.com>
51
52 * i386-dis.c (xop_table): Remove spurious bextr insn.
53
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542011-08-01 H.J. Lu <hongjiu.lu@intel.com>
55
56 PR ld/13048
57 * i386-dis.c (print_insn): Optimize info->mach check.
58
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592011-08-01 H.J. Lu <hongjiu.lu@intel.com>
60
61 PR gas/13046
62 * i386-opc.tbl: Add Disp32S to 64bit call.
63 * i386-tbl.h: Regenerated.
64
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652011-07-24 Chao-ying Fu <fu@mips.com>
66 Maciej W. Rozycki <macro@codesourcery.com>
67
68 * micromips-opc.c: New file.
69 * mips-dis.c (micromips_to_32_reg_b_map): New array.
70 (micromips_to_32_reg_c_map, micromips_to_32_reg_d_map): Likewise.
71 (micromips_to_32_reg_e_map, micromips_to_32_reg_f_map): Likewise.
72 (micromips_to_32_reg_g_map, micromips_to_32_reg_l_map): Likewise.
73 (micromips_to_32_reg_q_map): Likewise.
74 (micromips_imm_b_map, micromips_imm_c_map): Likewise.
75 (micromips_ase): New variable.
76 (is_micromips): New function.
77 (set_default_mips_dis_options): Handle microMIPS ASE.
78 (print_insn_micromips): New function.
79 (is_compressed_mode_p): Likewise.
80 (_print_insn_mips): Handle microMIPS instructions.
81 * Makefile.am (CFILES): Add micromips-opc.c.
82 * configure.in (bfd_mips_arch): Add micromips-opc.lo.
83 * Makefile.in: Regenerate.
84 * configure: Regenerate.
85
86 * mips-dis.c (micromips_to_32_reg_h_map): New variable.
87 (micromips_to_32_reg_i_map): Likewise.
88 (micromips_to_32_reg_m_map): Likewise.
89 (micromips_to_32_reg_n_map): New macro.
90
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912011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
92
93 * mips-opc.c (NODS): New macro.
94 (TRAP): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT.
95 (DSP_VOLA): Likewise.
96 (mips_builtin_opcodes): Add NODS annotation to "deret" and
97 "eret". Replace INSN_SYNC with NODS throughout. Use NODS in
98 place of TRAP for "wait", "waiti" and "yield".
99 * mips16-opc.c (NODS): New macro.
100 (TRAP): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT.
101 (mips16_opcodes): Use NODS in place of TRAP for "jalrc", "jrc",
102 "restore" and "save".
103
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1042011-07-22 H.J. Lu <hongjiu.lu@intel.com>
105
106 * configure.in: Handle bfd_k1om_arch.
107 * configure: Regenerated.
108
109 * disassemble.c (disassembler): Handle bfd_k1om_arch.
110
111 * i386-dis.c (print_insn): Handle bfd_mach_k1om and
112 bfd_mach_k1om_intel_syntax.
113
114 * i386-gen.c (cpu_flag_init): Set CPU_UNKNOWN_FLAGS to
115 ~(CpuL1OM|CpuK1OM). Add CPU_K1OM_FLAGS.
116 (cpu_flags): Add CpuK1OM.
117
118 * i386-opc.h (CpuK1OM): New.
119 (i386_cpu_flags): Add cpuk1om.
120
121 * i386-init.h: Regenerated.
122 * i386-tbl.h: Likewise.
123
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1242011-07-12 Nick Clifton <nickc@redhat.com>
125
126 * arm-dis.c (print_insn_arm): Revert previous, undocumented,
127 accidental change.
128
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1292011-07-01 Nick Clifton <nickc@redhat.com>
130
131 PR binutils/12329
132 * avr-dis.c (avr_operand): Fix disassembly of ELPM, LPM and SPM
133 insns using post-increment addressing.
134
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1352011-06-30 H.J. Lu <hongjiu.lu@intel.com>
136
137 * i386-dis.c (vex_len_table): Update rorxS.
138
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1392011-06-30 H.J. Lu <hongjiu.lu@intel.com>
140
141 AVX Programming Reference (June, 2011)
142 * i386-dis.c (vex_len_table): Correct rorxS.
143
144 * i386-opc.tbl: Correct rorx.
145 * i386-tbl.h: Regenerated.
146
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1472011-06-29 H.J. Lu <hongjiu.lu@intel.com>
148
149 * tilegx-opc.c (find_opcode): Replace "index" with "i".
150 * tilepro-opc.c (find_opcode): Likewise.
151
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1522011-06-29 Richard Sandiford <rdsandiford@googlemail.com>
153
154 * mips16-opc.c (jalrc, jrc): Move earlier in file.
155
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1562011-06-21 H.J. Lu <hongjiu.lu@intel.com>
157
158 * i386-dis.c (prefix_table): Re-indent PREFIX_VEX_0F388C and
159 PREFIX_VEX_0F388E.
160
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1612011-06-17 Andreas Schwab <schwab@redhat.com>
162
163 * Makefile.am (MAINTAINERCLEANFILES): Move s390-opc.tab ...
164 (MOSTLYCLEANFILES): ... here.
165 * Makefile.in: Regenerate.
166
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1672011-06-14 Alan Modra <amodra@gmail.com>
168
169 * Makefile.in: Regenerate.
170
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1712011-06-13 Walter Lee <walt@tilera.com>
172
173 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add tilegx-dis.c,
174 tilegx-opc.c, tilepro-dis.c, and tilepro-opc.c.
175 * Makefile.in: Regenerate.
176 * configure.in: Handle bfd_tilegx_arch and bfd_tilepro_arch.
177 * configure: Regenerate.
178 * disassemble.c (disassembler): Add ARCH_tilegx and ARCH_tilepro.
179 * po/POTFILES.in: Regenerate.
180 * tilegx-dis.c: New file.
181 * tilegx-opc.c: New file.
182 * tilepro-dis.c: New file.
183 * tilepro-opc.c: New file.
184
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1852011-06-10 H.J. Lu <hongjiu.lu@intel.com>
186
187 AVX Programming Reference (June, 2011)
188 * i386-dis.c (XMGatherQ): New.
189 * i386-dis.c (EXxmm_mb): New.
190 (EXxmm_mb): Likewise.
191 (EXxmm_mw): Likewise.
192 (EXxmm_md): Likewise.
193 (EXxmm_mq): Likewise.
194 (EXxmmdw): Likewise.
195 (EXxmmqd): Likewise.
196 (VexGatherQ): Likewise.
197 (MVexVSIBDWpX): Likewise.
198 (MVexVSIBQWpX): Likewise.
199 (xmm_mb_mode): Likewise.
200 (xmm_mw_mode): Likewise.
201 (xmm_md_mode): Likewise.
202 (xmm_mq_mode): Likewise.
203 (xmmdw_mode): Likewise.
204 (xmmqd_mode): Likewise.
205 (ymmxmm_mode): Likewise.
206 (vex_vsib_d_w_dq_mode): Likewise.
207 (vex_vsib_q_w_dq_mode): Likewise.
208 (MOD_VEX_0F385A_PREFIX_2): Likewise.
209 (MOD_VEX_0F388C_PREFIX_2): Likewise.
210 (MOD_VEX_0F388E_PREFIX_2): Likewise.
211 (PREFIX_0F3882): Likewise.
212 (PREFIX_VEX_0F3816): Likewise.
213 (PREFIX_VEX_0F3836): Likewise.
214 (PREFIX_VEX_0F3845): Likewise.
215 (PREFIX_VEX_0F3846): Likewise.
216 (PREFIX_VEX_0F3847): Likewise.
217 (PREFIX_VEX_0F3858): Likewise.
218 (PREFIX_VEX_0F3859): Likewise.
219 (PREFIX_VEX_0F385A): Likewise.
220 (PREFIX_VEX_0F3878): Likewise.
221 (PREFIX_VEX_0F3879): Likewise.
222 (PREFIX_VEX_0F388C): Likewise.
223 (PREFIX_VEX_0F388E): Likewise.
224 (PREFIX_VEX_0F3890..PREFIX_VEX_0F3893): Likewise.
225 (PREFIX_VEX_0F38F5): Likewise.
226 (PREFIX_VEX_0F38F6): Likewise.
227 (PREFIX_VEX_0F3A00): Likewise.
228 (PREFIX_VEX_0F3A01): Likewise.
229 (PREFIX_VEX_0F3A02): Likewise.
230 (PREFIX_VEX_0F3A38): Likewise.
231 (PREFIX_VEX_0F3A39): Likewise.
232 (PREFIX_VEX_0F3A46): Likewise.
233 (PREFIX_VEX_0F3AF0): Likewise.
234 (VEX_LEN_0F3816_P_2): Likewise.
235 (VEX_LEN_0F3819_P_2): Likewise.
236 (VEX_LEN_0F3836_P_2): Likewise.
237 (VEX_LEN_0F385A_P_2_M_0): Likewise.
238 (VEX_LEN_0F38F5_P_0): Likewise.
239 (VEX_LEN_0F38F5_P_1): Likewise.
240 (VEX_LEN_0F38F5_P_3): Likewise.
241 (VEX_LEN_0F38F6_P_3): Likewise.
242 (VEX_LEN_0F38F7_P_1): Likewise.
243 (VEX_LEN_0F38F7_P_2): Likewise.
244 (VEX_LEN_0F38F7_P_3): Likewise.
245 (VEX_LEN_0F3A00_P_2): Likewise.
246 (VEX_LEN_0F3A01_P_2): Likewise.
247 (VEX_LEN_0F3A38_P_2): Likewise.
248 (VEX_LEN_0F3A39_P_2): Likewise.
249 (VEX_LEN_0F3A46_P_2): Likewise.
250 (VEX_LEN_0F3AF0_P_3): Likewise.
251 (VEX_W_0F3816_P_2): Likewise.
252 (VEX_W_0F3818_P_2): Likewise.
253 (VEX_W_0F3819_P_2): Likewise.
254 (VEX_W_0F3836_P_2): Likewise.
255 (VEX_W_0F3846_P_2): Likewise.
256 (VEX_W_0F3858_P_2): Likewise.
257 (VEX_W_0F3859_P_2): Likewise.
258 (VEX_W_0F385A_P_2_M_0): Likewise.
259 (VEX_W_0F3878_P_2): Likewise.
260 (VEX_W_0F3879_P_2): Likewise.
261 (VEX_W_0F3A00_P_2): Likewise.
262 (VEX_W_0F3A01_P_2): Likewise.
263 (VEX_W_0F3A02_P_2): Likewise.
264 (VEX_W_0F3A38_P_2): Likewise.
265 (VEX_W_0F3A39_P_2): Likewise.
266 (VEX_W_0F3A46_P_2): Likewise.
267 (MOD_VEX_0F3818_PREFIX_2): Removed.
268 (MOD_VEX_0F3819_PREFIX_2): Likewise.
269 (VEX_LEN_0F60_P_2..VEX_LEN_0F6D_P_2): Likewise.
270 (VEX_LEN_0F70_P_1..VEX_LEN_0F76_P_2): Likewise.
271 (VEX_LEN_0FD1_P_2..VEX_LEN_0FD5_P_2): Likewise.
272 (VEX_LEN_0FD7_P_2_M_1..VEX_LEN_0F3819_P_2_M_0): Likewise.
273 (VEX_LEN_0F381C_P_2..VEX_LEN_0F3840_P_2): Likewise.
274 (VEX_LEN_0F3A0E_P_2): Likewise.
275 (VEX_LEN_0F3A0F_P_2): Likewise.
276 (VEX_LEN_0F3A42_P_2): Likewise.
277 (VEX_LEN_0F3A4C_P_2): Likewise.
278 (VEX_W_0F3818_P_2_M_0): Likewise.
279 (VEX_W_0F3819_P_2_M_0): Likewise.
280 (prefix_table): Updated.
281 (three_byte_table): Likewise.
282 (vex_table): Likewise.
283 (vex_len_table): Likewise.
284 (vex_w_table): Likewise.
285 (mod_table): Likewise.
286 (putop): Handle "LW".
287 (intel_operand_size): Handle xmm_mb_mode, xmm_mw_mode,
288 xmm_md_mode, xmm_mq_mode, xmmdw_mode, xmmqd_mode, ymmxmm_mode,
289 vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode.
290 (OP_EX): Likewise.
291 (OP_E_memory): Handle vex_vsib_d_w_dq_mode and
292 vex_vsib_q_w_dq_mode.
293 (OP_XMM): Handle vex_vsib_q_w_dq_mode.
294 (OP_VEX): Likewise.
295
296 * i386-gen.c (cpu_flag_init): Add CpuAVX2 to CPU_ANY_SSE_FLAGS
297 and CPU_ANY_AVX_FLAGS. Add CPU_BMI2_FLAGS, CPU_LZCNT_FLAGS,
298 CPU_INVPCID_FLAGS and CPU_AVX2_FLAGS.
299 (cpu_flags): Add CpuAVX2, CpuBMI2, CpuLZCNT and CpuINVPCID.
300 (opcode_modifiers): Add VecSIB.
301
302 * i386-opc.h (CpuAVX2): New.
303 (CpuBMI2): Likewise.
304 (CpuLZCNT): Likewise.
305 (CpuINVPCID): Likewise.
306 (VecSIB128): Likewise.
307 (VecSIB256): Likewise.
308 (VecSIB): Likewise.
309 (i386_cpu_flags): Add cpuavx2, cpubmi2, cpulzcnt and cpuinvpcid.
310 (i386_opcode_modifier): Add vecsib.
311
312 * i386-opc.tbl: Add invpcid, AVX2 and BMI2 instructions.
313 * i386-init.h: Regenerated.
314 * i386-tbl.h: Likewise.
315
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3162011-06-03 Quentin Neill <quentin.neill@amd.com>
317
318 * i386-gen.c (cpu_flag_init): Add CpuF16C to CPU_BDVER2_FLAGS.
319 * i386-init.h: Regenerated.
320
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3212011-06-03 Nick Clifton <nickc@redhat.com>
322
323 PR binutils/12752
324 * arm-dis.c (print_insn_coprocessor): Use bfd_vma type for
325 computing address offsets.
326 (print_arm_address): Likewise.
327 (print_insn_arm): Likewise.
328 (print_insn_thumb16): Likewise.
329 (print_insn_thumb32): Likewise.
330
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3312011-06-02 Jie Zhang <jie@codesourcery.com>
332 Nathan Sidwell <nathan@codesourcery.com>
333 Maciej Rozycki <macro@codesourcery.com>
334
335 * arm-dis.c (print_insn_coprocessor): Explicitly print #-0
336 as address offset.
337 (print_arm_address): Likewise. Elide positive #0 appropriately.
338 (print_insn_arm): Likewise.
339
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3402011-06-02 Nick Clifton <nickc@redhat.com>
341
342 PR gas/12752
343 * arm-dis.c (print_insn_thumb32): Do not sign extend addresses
344 passed to print_address_func.
345
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3462011-06-02 Nick Clifton <nickc@redhat.com>
347
348 * arm-dis.c: Fix spelling mistakes.
349 * op/opcodes.pot: Regenerate.
350
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AK
3512011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
352
353 * s390-opc.c: Replace S390_OPERAND_REG_EVEN with
354 S390_OPERAND_REG_PAIR. Fix INSTR_RRF_0UFEF instruction type.
355 * s390-opc.txt: Fix cxr instruction type.
356
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3572011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
358
359 * s390-opc.c: Add new instruction types marking register pair
360 operands.
361 * s390-opc.txt: Match instructions having register pair operands
362 to the new instruction types.
363
fda544a2
NC
3642011-05-19 Nick Clifton <nickc@redhat.com>
365
366 * v850-opc.c (cmpf.[sd]): Reverse the order of the reg1 and reg2
367 operands.
368
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QN
3692011-05-10 Quentin Neill <quentin.neill@amd.com>
370
371 * i386-gen.c (cpu_flag_init): Add new CPU_BDVER2_FLAGS.
372 * i386-init.h: Regenerated.
373
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3742011-04-27 Nick Clifton <nickc@redhat.com>
375
376 * po/da.po: Updated Danish translation.
377
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3782011-04-26 Anton Blanchard <anton@samba.org>
379
380 * ppc-opc.c: (powerpc_opcodes): Enable icswx for POWER7.
381
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3822011-04-21 DJ Delorie <dj@redhat.com>
383
384 * rx-decode.opc (rx_decode_opcode): Set the syntax for multi-byte NOPs.
385 * rx-decode.c: Regenerate.
386
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L
3872011-04-20 H.J. Lu <hongjiu.lu@intel.com>
388
389 * i386-init.h: Regenerated.
390
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QN
3912011-04-19 Quentin Neill <quentin.neill@amd.com>
392
393 * i386-gen.c (cpu_flag_init): Remove 3dnow and 3dnowa bits
394 from bdver1 flags.
395
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3962011-04-13 Nick Clifton <nickc@redhat.com>
397
398 * v850-dis.c (disassemble): Always print a closing square brace if
399 an opening square brace was printed.
400
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NC
4012011-04-12 Nick Clifton <nickc@redhat.com>
402
403 PR binutils/12534
404 * arm-dis.c (thumb32_opcodes): Add %L suffix to LDRD and STRD insn
405 patterns.
406 (print_insn_thumb32): Handle %L.
407
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JB
4082011-04-11 Julian Brown <julian@codesourcery.com>
409
410 * arm-dis.c (psr_name): Fix typo for BASEPRI_MAX.
411 (print_insn_thumb32): Add APSR bitmask support.
412
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4132011-04-07 Paul Carroll<pcarroll@codesourcery.com>
414
415 * arm-dis.c (print_insn): init vars moved into private_data structure.
416
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MF
4172011-03-24 Mike Frysinger <vapier@gentoo.org>
418
419 * bfin-dis.c (decode_dsp32mac_0): Move MM zeroing down to MAC0 logic.
420
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EW
4212011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
422
423 * avr-dis.c (avr_operand): Add opcode_str parameter. Check for
424 post-increment to support LPM Z+ instruction. Add support for 'E'
425 constraint for DES instruction.
426 (print_insn_avr): Adjust calls to avr_operand. Rename variable.
427
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RS
4282011-03-14 Richard Sandiford <richard.sandiford@linaro.org>
429
430 * arm-dis.c (get_sym_code_type): Treat STT_GNU_IFUNCs as code.
431
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RS
4322011-03-14 Richard Sandiford <richard.sandiford@linaro.org>
433
434 * arm-dis.c (get_sym_code_type): Don't check for STT_ARM_TFUNC.
435 Use branch types instead.
436 (print_insn): Likewise.
437
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MR
4382011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
439
440 * mips-opc.c (mips_builtin_opcodes): Correct register use
441 annotation of "alnv.ps".
442
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MR
4432011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
444
445 * mips-opc.c (mips_builtin_opcodes): Add "pref" macro.
446
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MF
4472011-02-22 Mike Frysinger <vapier@gentoo.org>
448
449 * bfin-dis.c (OUTS): Remove p NULL check and txt NUL check.
450
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MF
4512011-02-22 Mike Frysinger <vapier@gentoo.org>
452
453 * bfin-dis.c (print_insn_bfin): Change outf->fprintf_func to OUTS.
454
e5bc4265
MF
4552011-02-19 Mike Frysinger <vapier@gentoo.org>
456
457 * bfin-dis.c (saved_state): Mark static. Change a[01]x to ax[] and
458 a[01]w to aw[]. Delete ac0, ac0_copy, ac1, an, aq, av0, av0s, av1,
459 av1s, az, cc, v, v_copy, vs, rnd_mod, v_internal, pc, ticks, insts,
460 exception, end_of_registers, msize, memory, bfd_mach.
461 (CCREG, PCREG, A0XREG, A0WREG, A1XREG, A1WREG, LC0REG, LT0REG,
462 LB0REG, LC1REG, LT1REG, LB1REG): Delete
463 (AXREG, AWREG, LCREG, LTREG, LBREG): Define.
464 (get_allreg): Change to new defines. Fallback to abort().
465
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MF
4662011-02-14 Mike Frysinger <vapier@gentoo.org>
467
468 * bfin-dis.c: Add whitespace/parenthesis where needed.
469
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MF
4702011-02-14 Mike Frysinger <vapier@gentoo.org>
471
472 * bfin-dis.c (decode_LoopSetup_0): Return when reg is greater
473 than 7.
474
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RW
4752011-02-13 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
476
477 * configure: Regenerate.
478
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MF
4792011-02-13 Mike Frysinger <vapier@gentoo.org>
480
481 * bfin-dis.c (decode_dsp32alu_0): Fix typo with A1 reg.
482
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MF
4832011-02-13 Mike Frysinger <vapier@gentoo.org>
484
485 * bfin-dis.c (decode_dsp32mult_0): Add 1 to dst for mac1. Output
486 dregs only when P is set, and dregs_lo otherwise.
487
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MF
4882011-02-13 Mike Frysinger <vapier@gentoo.org>
489
490 * bfin-dis.c (decode_dsp32alu_0): Delete BYTEOP2M code.
491
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MF
4922011-02-12 Mike Frysinger <vapier@gentoo.org>
493
494 * bfin-dis.c (decode_pseudoDEBUG_0): Add space after PRNT.
495
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MF
4962011-02-12 Mike Frysinger <vapier@gentoo.org>
497
498 * bfin-dis.c (machine_registers): Delete REG_GP.
499 (reg_names): Delete "GP".
500 (decode_allregs): Change REG_GP to REG_LASTREG.
501
26bb3ddd
MF
5022011-02-12 Mike Frysinger <vapier@gentoo.org>
503
89c0d58c
MR
504 * bfin-dis.c (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2,
505 M_IH, M_IU): Delete.
26bb3ddd 506
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MF
5072011-02-11 Mike Frysinger <vapier@gentoo.org>
508
509 * bfin-dis.c (reg_names): Add const.
510 (decode_dregs_lo, decode_dregs_hi, decode_dregs, decode_dregs_byte,
511 decode_pregs, decode_iregs, decode_mregs, decode_dpregs, decode_gregs,
512 decode_regs, decode_regs_lo, decode_regs_hi, decode_statbits,
513 decode_counters, decode_allregs): Likewise.
514
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MS
5152011-02-09 Michael Snyder <msnyder@vmware.com>
516
56300268 517 * i386-dis.c (OP_J): Parenthesize expression to prevent
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MS
518 truncated addresses.
519 (print_insn): Fix indentation off-by-one.
520
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NC
5212011-02-01 Nick Clifton <nickc@redhat.com>
522
523 * po/da.po: Updated Danish translation.
524
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AM
5252011-01-21 Dave Murphy <davem@devkitpro.org>
526
527 * ppc-opc.c (NON32, NO371): Remove PPC_OPCODE_PPCPS.
528
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L
5292011-01-18 H.J. Lu <hongjiu.lu@intel.com>
530
531 * i386-dis.c (sIbT): New.
532 (b_T_mode): Likewise.
533 (dis386): Replace sIb with sIbT on "pushT".
534 (x86_64_table): Replace sIb with Ib on "aam" and "aad".
535 (OP_sI): Handle b_T_mode. Properly sign-extend byte.
536
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JK
5372011-01-18 Jan Kratochvil <jan.kratochvil@redhat.com>
538
539 * i386-init.h: Regenerated.
540 * i386-tbl.h: Regenerated
541
2a2a0f38
QN
5422011-01-17 Quentin Neill <quentin.neill@amd.com>
543
544 * i386-dis.c (REG_XOP_TBM_01): New.
545 (REG_XOP_TBM_02): New.
546 (reg_table): Add REG_XOP_TBM_01 and REG_XOP_TBM_02 tables.
547 (xop_table): Redirect to REG_XOP_TBM_01 and REG_XOP_TBM_02
548 entries, and add bextr instruction.
549
550 * i386-gen.c (cpu_flag_init): Add CPU_TBM_FLAGS, CpuTBM.
551 (cpu_flags): Add CpuTBM.
552
553 * i386-opc.h (CpuTBM) New.
554 (i386_cpu_flags): Add bit cputbm.
555
556 * i386-opc.tbl: Add bextr, blcfill, blci, blcic, blcmsk,
557 blcs, blsfill, blsic, t1mskc, and tzmsk.
558
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5592011-01-12 DJ Delorie <dj@redhat.com>
560
561 * rx-dis.c (print_insn_rx): Support RX_Operand_TwoReg.
562
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MX
5632011-01-11 Mingjie Xing <mingjie.xing@gmail.com>
564
565 * mips-dis.c (print_insn_args): Adjust the value to print the real
566 offset for "+c" argument.
567
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5682011-01-10 Nick Clifton <nickc@redhat.com>
569
570 * po/da.po: Updated Danish translation.
571
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NS
5722011-01-05 Nathan Sidwell <nathan@codesourcery.com>
573
574 * arm-dis.c (thumb32_opcodes): BLX must have bit zero clear.
575
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L
5762011-01-04 H.J. Lu <hongjiu.lu@intel.com>
577
578 * i386-dis.c (REG_VEX_38F3): New.
579 (PREFIX_0FBC): Likewise.
580 (PREFIX_VEX_38F2): Likewise.
581 (PREFIX_VEX_38F3_REG_1): Likewise.
582 (PREFIX_VEX_38F3_REG_2): Likewise.
583 (PREFIX_VEX_38F3_REG_3): Likewise.
584 (PREFIX_VEX_38F7): Likewise.
585 (VEX_LEN_38F2_P_0): Likewise.
586 (VEX_LEN_38F3_R_1_P_0): Likewise.
587 (VEX_LEN_38F3_R_2_P_0): Likewise.
588 (VEX_LEN_38F3_R_3_P_0): Likewise.
589 (VEX_LEN_38F7_P_0): Likewise.
590 (dis386_twobyte): Use PREFIX_0FBC.
591 (reg_table): Add REG_VEX_38F3.
592 (prefix_table): Add PREFIX_0FBC, PREFIX_VEX_38F2,
593 PREFIX_VEX_38F3_REG_1, PREFIX_VEX_38F3_REG_2,
594 PREFIX_VEX_38F3_REG_3 and PREFIX_VEX_38F7.
595 (vex_table): Use PREFIX_VEX_38F2, REG_VEX_38F3 and
596 PREFIX_VEX_38F7.
597 (vex_len_table): Add VEX_LEN_38F2_P_0, VEX_LEN_38F3_R_1_P_0,
598 VEX_LEN_38F3_R_2_P_0, VEX_LEN_38F3_R_3_P_0 and
599 VEX_LEN_38F7_P_0.
600
601 * i386-gen.c (cpu_flag_init): Add CPU_BMI_FLAGS.
602 (cpu_flags): Add CpuBMI.
603
604 * i386-opc.h (CpuBMI): New.
605 (i386_cpu_flags): Add cpubmi.
606
607 * i386-opc.tbl: Add andn, bextr, blsi, blsmsk, blsr and tzcnt.
608 * i386-init.h: Regenerated.
609 * i386-tbl.h: Likewise.
610
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L
6112011-01-04 H.J. Lu <hongjiu.lu@intel.com>
612
613 * i386-dis.c (VexGdq): New.
614 (OP_VEX): Handle dq_mode.
615
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L
6162011-01-01 H.J. Lu <hongjiu.lu@intel.com>
617
618 * i386-gen.c (process_copyright): Update copyright to 2011.
619
9e9e0820 620For older changes see ChangeLog-2010
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621\f
622Local Variables:
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623mode: change-log
624left-margin: 8
625fill-column: 74
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626version-control: never
627End:
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