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fix typo in "set debug timetstamp"
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
c27e721e
AN		 12008-07-07 Adam Nemet <anemet@caviumnetworks.com>
2
3 * mips-opc.c (CP): New macro.
4 (mips_builtin_opcodes): Mark c0, c2 and c3 as CP. Add Octeon to the
5 membership of di, dmfc0, dmtc0, ei, mfc0 and mtc0. Add dmfc2 and
6 dmtc2 Octeon instructions.
7
bd2e2557
SS		 82008-07-07 Stan Shebs <stan@codesourcery.com>
9
10 * dis-init.c (init_disassemble_info): Init endian_code field.
11 * arm-dis.c (print_insn): Disassemble code according to
12 setting of endian_code.
13 (print_insn_big_arm): Detect when BE8 extension flag has been set.
14
6ba2a415
RS		 152008-06-30 Richard Sandiford <rdsandiford@googlemail.com>
16
17 * mips-dis.c (_print_insn_mips): Use bfd_asymbol_flavour to check
18 for ELF symbols.
19
c8187e15
PB		 202008-06-25 Peter Bergner <bergner@vnet.ibm.com>
21
22 * ppc-dis.c (powerpc_init_dialect): Handle -M464.
23 (print_ppc_disassembler_options): Likewise.
24 * ppc-opc.c (PPC464): Define.
25 (powerpc_opcodes): Add mfdcrux and mtdcrux.
26
7a283e07
RW		 272008-06-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
28
29 * configure: Regenerate.
30
fa452fa6
PB		 312008-06-13 Peter Bergner <bergner@vnet.ibm.com>
32
33 * ppc-dis.c (print_insn_powerpc): Update prototye to use new
34 ppc_cpu_t typedef.
35 (struct dis_private): New.
36 (POWERPC_DIALECT): New define.
37 (powerpc_dialect): Renamed to...
38 (powerpc_init_dialect): This. Update to use ppc_cpu_t and
39 struct dis_private.
40 (print_insn_big_powerpc): Update for using structure in
41 info->private_data.
42 (print_insn_little_powerpc): Likewise.
43 (operand_value_powerpc): Change type of dialect param to ppc_cpu_t.
44 (skip_optional_operands): Likewise.
45 (print_insn_powerpc): Likewise. Remove initialization of dialect.
46 * ppc-opc.c (extract_bat, extract_bba, extract_bdm, extract_bdp,
47 extract_bo, extract_boe, extract_fxm, extract_mb6, extract_mbe,
48 extract_nb, extract_nsi, extract_rbs, extract_sh6, extract_spr,
49 extract_sprg, extract_tbr insert_bat, insert_bba, insert_bdm,
50 insert_bdp, insert_bo, insert_boe, insert_fxm, insert_mb6, insert_mbe,
51 insert_nsi, insert_ral, insert_ram, insert_raq, insert_ras, insert_rbs,
52 insert_sh6, insert_spr, insert_sprg, insert_tbr): Change the dialect
53 param to be of type ppc_cpu_t. Update prototype.
54
bb35fb24
NC		 552008-06-12 Adam Nemet <anemet@caviumnetworks.com>
56
57 * mips-dis.c (print_insn_args): Handle field descriptors +x, +p,
58 +s, +S.
59 * mips-opc.c (mips_builtin_opcodes): Add Octeon instructions
60 baddu, bbit*, cins*, dmul, pop, dpop, exts*, mtm*, mtp*, syncs,
61 syncw, syncws, vm3mulu, vm0 and vmulu.
62
dd3cbb7e
NC		 63 * mips-dis.c (print_insn_args): Handle field descriptor +Q.
64 * mips-opc.c (mips_builtin_opcodes): Add Octeon instructions seq,
65 seqi, sne and snei.
66
a5dabbb0
L		 672008-05-30 H.J. Lu <hongjiu.lu@intel.com>
68
69 * i386-opc.tbl: Add vmovd with 64bit operand.
70 * i386-tbl.h: Regenerated.
71
725a9891
MS		 722008-05-27 Martin Schwidefsky <schwidefsky@de.ibm.com>
73
74 * s390-opc.c (INSTR_RRF_R0RR): Fix RRF_R0RR operand format.
75
cbc80391
L		 762008-05-22 H.J. Lu <hongjiu.lu@intel.com>
77
78 * i386-opc.tbl: Add NoAVX to cvtpd2pi, cvtpi2pd and cvttpd2pi.
79 * i386-tbl.h: Regenerated.
80
116615c5
L		 812008-05-22 H.J. Lu <hongjiu.lu@intel.com>
82
83 PR gas/6517
84 * i386-opc.tbl: Break cvtsi2ss/cvtsi2sd/vcvtsi2sd/vcvtsi2ss
85 into 32bit and 64bit. Remove Reg64|Qword and add
86 IgnoreSize|No_qSuf on 32bit version.
87 * i386-tbl.h: Regenerated.
88
d9479f2d
L		 892008-05-21 H.J. Lu <hongjiu.lu@intel.com>
90
91 * i386-opc.tbl: Add NoAVX to movdq2q and movq2dq.
92 * i386-tbl.h: Regenerated.
93
3ce6fddb
NC		 942008-05-21 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
95
96 * cr16-dis.c (build_mask): Adjust the mask for 32-bit bcond.
97
8944f3c2
AM		 982008-05-14 Alan Modra <amodra@bigpond.net.au>
99
100 * Makefile.am: Run "make dep-am".
101 * Makefile.in: Regenerate.
102
f1f8f695
L		 1032008-05-02 H.J. Lu <hongjiu.lu@intel.com>
104
105 * i386-dis.c (MOVBE_Fixup): New.
106 (Mo): Likewise.
107 (PREFIX_0F3880): Likewise.
108 (PREFIX_0F3881): Likewise.
109 (PREFIX_0F38F0): Updated.
110 (prefix_table): Add PREFIX_0F3880 and PREFIX_0F3881. Update
111 PREFIX_0F38F0 and PREFIX_0F38F1 for movbe.
112 (three_byte_table): Use PREFIX_0F3880 and PREFIX_0F3881.
113
114 * i386-gen.c (cpu_flag_init): Add CPU_MOVBE_FLAGS and
115 CPU_EPT_FLAGS.
116 (cpu_flags): Add CpuMovbe and CpuEPT.
117
118 * i386-opc.h (CpuMovbe): New.
119 (CpuEPT): Likewise.
120 (CpuLM): Updated.
121 (i386_cpu_flags): Add cpumovbe and cpuept.
122
123 * i386-opc.tbl: Add entries for movbe and EPT instructions.
124 * i386-init.h: Regenerated.
125 * i386-tbl.h: Likewise.
126
89aa3097
AN		 1272008-04-29 Adam Nemet <anemet@caviumnetworks.com>
128
129 * mips-opc.c (mips_builtin_opcodes): Set field `match' to 0 for
130 the two drem and the two dremu macros.
131
39c5c168
AN		 1322008-04-28 Adam Nemet <anemet@caviumnetworks.com>
133
134 * mips-opc.c (mips_builtin_opcodes): Mark prefx and c1
135 instructions FP_S. Mark l.s, li.s, lwc1, swc1, s.s, trunc.w.s and
136 cop1 macros INSN2_M_FP_S. Mark l.d, li.d, ldc1 and sdc1 macros
137 INSN2_M_FP_D. Mark trunc.w.d macro INSN2_M_FP_S and INSN2_M_FP_D.
138
f04d18b7
DM		 1392008-04-25 David S. Miller <davem@davemloft.net>
140
141 * sparc-dis.c: Emit %stick instead of %sys_tick, and %stick_cmpr
142 instead of %sys_tick_cmpr, as suggested in architecture manuals.
143
6194aaab
L		 1442008-04-23 Paolo Bonzini <bonzini@gnu.org>
145
146 * aclocal.m4: Regenerate.
147 * configure: Regenerate.
148
1a6b486f
DM		 1492008-04-23 David S. Miller <davem@davemloft.net>
150
151 * sparc-opc.c (asi_table): Add UltraSPARC and Niagara
152 extended values.
153 (prefetch_table): Add missing values.
154
81f8a913
L		 1552008-04-22 H.J. Lu <hongjiu.lu@intel.com>
156
157 * i386-gen.c (opcode_modifiers): Add NoAVX.
158
159 * i386-opc.h (NoAVX): New.
160 (OldGcc): Updated.
161 (i386_opcode_modifier): Add noavx.
162
163 * i386-opc.tbl: Add NoAVX to SSE, SSE2, SSE3 and SSSE3
164 instructions which don't have AVX equivalent.
165 * i386-tbl.h: Regenerated.
166
dae39acc
L		 1672008-04-18 H.J. Lu <hongjiu.lu@intel.com>
168
169 * i386-dis.c (OP_VEX_FMA): New.
170 (OP_EX_VexImmW): Likewise.
171 (VexFMA): Likewise.
172 (Vex128FMA): Likewise.
173 (EXVexImmW): Likewise.
174 (get_vex_imm8): Likewise.
175 (OP_EX_VexReg): Likewise.
176 (vex_i4_done): Renamed to ...
177 (vex_w_done): This.
178 (prefix_table): Replace EXVexW with EXVexImmW on vpermil2ps
179 and vpermil2pd. Replace Vex/Vex128 with VexFMA/Vex128FMA on
180 FMA instructions.
181 (print_insn): Updated.
182 (OP_EX_VexW): Rewrite to swap register in VEX with EX.
183 (OP_REG_VexI4): Check invalid high registers.
184
ce886ab1
DR		 1852008-04-16 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
186 Michael Meissner <michael.meissner@amd.com>
187
188 * i386-opc.tbl: Fix protX to allow memory in the middle operand.
189 * i386-tbl.h: Regenerate from i386-opc.tbl.
8944f3c2 190
19a6653c
AM		 1912008-04-14 Edmar Wienskoski <edmar@freescale.com>
192
193 * ppc-dis.c (powerpc_dialect): Handle "e500mc". Extend "e500" to
194 accept Power E500MC instructions.
195 (print_ppc_disassembler_options): Document -Me500mc.
196 * ppc-opc.c (DUIS, DUI, T): New.
197 (XRT, XRTRA): Likewise.
198 (E500MC): Likewise.
199 (powerpc_opcodes): Add new Power E500MC instructions.
200
112b7c50
AK		 2012008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
202
203 * s390-dis.c (init_disasm): Evaluate disassembler_options.
204 (print_s390_disassembler_options): New function.
205 * disassemble.c (disassembler_usage): Invoke
206 print_s390_disassembler_options.
207
7ff42648
AK		 2082008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
209
210 * s390-mkopc.c (insertExpandedMnemonic): Expand string sizes
211 of local variables used for mnemonic parsing: prefix, suffix and
212 number.
213
45a5551e
AK		 2142008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
215
216 * s390-mkopc.c (s390_cond_ext_format): Add back the mnemonic
217 extensions for conditional jumps (o, p, m, nz, z, nm, np, no).
218 (s390_crb_extensions): New extensions table.
219 (insertExpandedMnemonic): Handle '$' tag.
220 * s390-opc.txt: Remove conditional jump variants which can now
221 be expanded automatically.
222 Replace '*' tag with '$' in the compare and branch instructions.
223
06c8514a
L		 2242008-04-07 H.J. Lu <hongjiu.lu@intel.com>
225
226 * i386-dis.c (PREFIX_VEX_38XX): Add a tab.
227 (PREFIX_VEX_3AXX): Likewis.
228
b122c285
L		 2292008-04-07 H.J. Lu <hongjiu.lu@intel.com>
230
231 * i386-opc.tbl: Remove 4 extra blank lines.
232
594ab6a3
L		 2332008-04-04 H.J. Lu <hongjiu.lu@intel.com>
234
235 * i386-gen.c (cpu_flag_init): Replace CPU_CLMUL_FLAGS/CpuCLMUL
236 with CPU_PCLMUL_FLAGS/CpuPCLMUL.
237 (cpu_flags): Replace CpuCLMUL with CpuPCLMUL.
238 * i386-opc.tbl: Likewise.
239
240 * i386-opc.h (CpuCLMUL): Renamed to ...
241 (CpuPCLMUL): This.
242 (CpuFMA): Updated.
243 (i386_cpu_flags): Replace cpuclmul with cpupclmul.
244
245 * i386-init.h: Regenerated.
246
c0f3af97
L		 2472008-04-03 H.J. Lu <hongjiu.lu@intel.com>
248
249 * i386-dis.c (OP_E_register): New.
250 (OP_E_memory): Likewise.
251 (OP_VEX): Likewise.
252 (OP_EX_Vex): Likewise.
253 (OP_EX_VexW): Likewise.
254 (OP_XMM_Vex): Likewise.
255 (OP_XMM_VexW): Likewise.
256 (OP_REG_VexI4): Likewise.
257 (PCLMUL_Fixup): Likewise.
258 (VEXI4_Fixup): Likewise.
259 (VZERO_Fixup): Likewise.
260 (VCMP_Fixup): Likewise.
261 (VPERMIL2_Fixup): Likewise.
262 (rex_original): Likewise.
263 (rex_ignored): Likewise.
264 (Mxmm): Likewise.
265 (XMM): Likewise.
266 (EXxmm): Likewise.
267 (EXxmmq): Likewise.
268 (EXymmq): Likewise.
269 (Vex): Likewise.
270 (Vex128): Likewise.
271 (Vex256): Likewise.
272 (VexI4): Likewise.
273 (EXdVex): Likewise.
274 (EXqVex): Likewise.
275 (EXVexW): Likewise.
276 (EXdVexW): Likewise.
277 (EXqVexW): Likewise.
278 (XMVex): Likewise.
279 (XMVexW): Likewise.
280 (XMVexI4): Likewise.
281 (PCLMUL): Likewise.
282 (VZERO): Likewise.
283 (VCMP): Likewise.
284 (VPERMIL2): Likewise.
285 (xmm_mode): Likewise.
286 (xmmq_mode): Likewise.
287 (ymmq_mode): Likewise.
288 (vex_mode): Likewise.
289 (vex128_mode): Likewise.
290 (vex256_mode): Likewise.
291 (USE_VEX_C4_TABLE): Likewise.
292 (USE_VEX_C5_TABLE): Likewise.
293 (USE_VEX_LEN_TABLE): Likewise.
294 (VEX_C4_TABLE): Likewise.
295 (VEX_C5_TABLE): Likewise.
296 (VEX_LEN_TABLE): Likewise.
297 (REG_VEX_XX): Likewise.
298 (MOD_VEX_XXX): Likewise.
299 (PREFIX_0F38DB..PREFIX_0F38DF): Likewise.
300 (PREFIX_0F3A44): Likewise.
301 (PREFIX_0F3ADF): Likewise.
302 (PREFIX_VEX_XXX): Likewise.
303 (VEX_OF): Likewise.
304 (VEX_OF38): Likewise.
305 (VEX_OF3A): Likewise.
306 (VEX_LEN_XXX): Likewise.
307 (vex): Likewise.
308 (need_vex): Likewise.
309 (need_vex_reg): Likewise.
310 (vex_i4_done): Likewise.
311 (vex_table): Likewise.
312 (vex_len_table): Likewise.
313 (OP_REG_VexI4): Likewise.
314 (vex_cmp_op): Likewise.
315 (pclmul_op): Likewise.
316 (vpermil2_op): Likewise.
317 (m_mode): Updated.
318 (es_reg): Likewise.
319 (PREFIX_0F38F0): Likewise.
320 (PREFIX_0F3A60): Likewise.
321 (reg_table): Add REG_VEX_71...REG_VEX_73 and REG_VEX_AE.
322 (prefix_table): Add PREFIX_0F38DB..PREFIX_0F38DF, PREFIX_0F3ADF
323 and PREFIX_VEX_XXX entries.
324 (x86_64_table): Use VEX_C4_TABLE and VEX_C5_TABLE.
325 (three_byte_table): Use PREFIX_0F38DB..PREFIX_0F38DF and
326 PREFIX_0F3ADF.
327 (mod_table): Use VEX_C4_TABLE, VEX_C5_TABLE and VEX_LEN_TABLE.
328 Add MOD_VEX_XXX entries.
329 (ckprefix): Initialize rex_original and rex_ignored. Store the
330 REX byte in rex_original.
331 (get_valid_dis386): Handle the implicit prefix in VEX prefix
332 bytes and USE_VEX_LEN_TABLE/USE_VEX_C4_TABLE/USE_VEX_C5_TABLE.
333 (print_insn): Set need_vex/need_vex_reg/vex_i4_done to 0 before
334 calling get_valid_dis386. Use rex_original and rex_ignored when
335 printing out REX.
336 (putop): Handle "XY".
337 (intel_operand_size): Handle VEX, xmm_mode, xmmq_mode and
338 ymmq_mode.
339 (OP_E_extended): Updated to use OP_E_register and
340 OP_E_memory.
341 (OP_XMM): Handle VEX.
342 (OP_EX): Likewise.
343 (XMM_Fixup): Likewise.
344 (CMP_Fixup): Use ARRAY_SIZE.
345
346 * i386-gen.c (cpu_flag_init): Add CpuAES, CPU_CLMUL_FLAGS,
347 CPU_FMA_FLAGS and CPU_AVX_FLAGS.
348 (operand_type_init): Add OPERAND_TYPE_REGYMM and
349 OPERAND_TYPE_VEX_IMM4.
350 (cpu_flags): Add CpuAVX, CpuAES, CpuCLMUL and CpuFMA.
351 (opcode_modifiers): Add Implicit1stXmm0, Vex, Vex256, VexNDD,
352 VexNDS, VexW0, VexW1, Vex0F, Vex0F38, Vex0F3A, Vex3Sources,
353 VexImmExt and SSE2AVX.
354 (operand_types): Add RegYMM, Ymmword and Vex_Imm4.
355
356 * i386-opc.h (CpuAVX): New.
357 (CpuAES): Likewise.
358 (CpuCLMUL): Likewise.
359 (CpuFMA): Likewise.
360 (Vex): Likewise.
361 (Vex256): Likewise.
362 (VexNDS): Likewise.
363 (VexNDD): Likewise.
364 (VexW0): Likewise.
365 (VexW1): Likewise.
366 (Vex0F): Likewise.
367 (Vex0F38): Likewise.
368 (Vex0F3A): Likewise.
369 (Vex3Sources): Likewise.
370 (VexImmExt): Likewise.
371 (SSE2AVX): Likewise.
372 (RegYMM): Likewise.
373 (Ymmword): Likewise.
374 (Vex_Imm4): Likewise.
375 (Implicit1stXmm0): Likewise.
376 (CpuXsave): Updated.
377 (CpuLM): Likewise.
378 (ByteOkIntel): Likewise.
379 (OldGcc): Likewise.
380 (Control): Likewise.
381 (Unspecified): Likewise.
382 (OTMax): Likewise.
383 (i386_cpu_flags): Add cpuavx, cpuaes, cpuclmul and cpufma.
384 (i386_opcode_modifier): Add implicit1stxmm0, vex, vex256,
385 vexnds, vexndd, vexw0, vexw1, vex0f, vex0f38, vex0f3a,
386 vex3sources, veximmext and sse2avx.
387 (i386_operand_type): Add regymm, ymmword and vex_imm4.
388
389 * i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions.
390
391 * i386-reg.tbl: Add AVX registers, ymm0..ymm15.
392
393 * i386-init.h: Regenerated.
394 * i386-tbl.h: Likewise.
395
b21c9cb4
BS		 3962008-03-26 Bernd Schmidt <bernd.schmidt@analog.com>
397
398 From Robin Getz <robin.getz@analog.com>
399 * bfin-dis.c (bu32): Typedef.
400 (enum const_forms_t): Add c_uimm32 and c_huimm32.
401 (constant_formats[]): Add uimm32 and huimm16.
402 (fmtconst_val): New.
403 (uimm32): Define.
404 (huimm32): Define.
405 (imm16_val): Define.
406 (luimm16_val): Define.
407 (struct saved_state): Define.
408 (GREG, DPREG, DREG, PREG, SPREG, FPREG, IREG, MREG, BREG, LREG,
409 A0XREG, A0WREG, A1XREG, A1WREG,CCREG, LC0REG, LT0REG, LB0REG,
410 LC1REG, LT1REG, LB1REG, RETSREG, PCREG): Define.
411 (get_allreg): New.
412 (decode_LDIMMhalf_0): Print out the whole register value.
413
ee171c8f
BS		 414 From Jie Zhang <jie.zhang@analog.com>
415 * bfin-dis.c (decode_dsp32mac_0): Decode (IU) option for
416 multiply and multiply-accumulate to data register instruction.
417
086134ec
BS		 418 * bfin-dis.c: (c_uimm4s4d, c_imm5d, c_imm7d, c_imm16d, c_uimm16s4d,
419 c_imm32, c_huimm32e): Define.
420 (constant_formats): Add flags for printing decimal, leading spaces, and
421 exact symbols.
422 (comment, parallel): Add global flags in all disassembly.
423 (fmtconst): Take advantage of new flags, and print default in hex.
424 (fmtconst_val): Likewise.
425 (decode_macfunc): Be consistant with spaces, tabs, comments,
426 capitalization in disassembly, fix minor coding style issues.
427 (reg_names, amod0, amod1, amod0amod2, aligndir, get_allreg): Likewise.
428 (decode_ProgCtrl_0, decode_PushPopMultiple_0, decode_CCflag_0,
429 decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0,
430 decode_REGMV_0, decode_ALU2op_0, decode_PTR2op_0, decode_LOGI2op_0,
431 decode_COMP3op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
432 decode_LDSTpmod_0, decode_dagMODim_0, decode_dagMODik_0,
433 decode_dspLDST_0, decode_LDST_0, decode_LDSTiiFP_0, decode_LDSTii_0,
434 decode_LoopSetup_0, decode_LDIMMhalf_0, decode_CALLa_0,
435 decode_LDSTidxI_0, decode_linkage_0, decode_dsp32alu_0,
436 decode_dsp32shift_0, decode_dsp32shiftimm_0, decode_pseudodbg_assert_0,
437 _print_insn_bfin, print_insn_bfin): Likewise.
438
58c85be7
RW		 4392008-03-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
440
441 * aclocal.m4: Regenerate.
442 * configure: Likewise.
443 * Makefile.in: Likewise.
444
50e7d84b
AM		 4452008-03-13 Alan Modra <amodra@bigpond.net.au>
446
447 * Makefile.am: Run "make dep-am".
448 * Makefile.in: Regenerate.
449 * configure: Regenerate.
450
de866fcc
AM		 4512008-03-07 Alan Modra <amodra@bigpond.net.au>
452
453 * ppc-opc.c (powerpc_opcodes): Order and format.
454
28dbc079
L		 4552008-03-01 H.J. Lu <hongjiu.lu@intel.com>
456
457 * i386-opc.tbl: Allow 16-bit near indirect branches for x86-64.
458 * i386-tbl.h: Regenerated.
459
849830bd
L		 4602008-02-23 H.J. Lu <hongjiu.lu@intel.com>
461
462 * i386-opc.tbl: Disallow 16-bit near indirect branches for
463 x86-64.
464 * i386-tbl.h: Regenerated.
465
743ddb6b
JB		 4662008-02-21 Jan Beulich <jbeulich@novell.com>
467
468 * i386-opc.tbl: Allow Dword for far indirect call. Allow Dword
469 and Fword for far indirect jmp. Allow Reg16 and Word for near
470 indirect jmp on x86-64. Disallow Fword for lcall.
471 * i386-tbl.h: Re-generate.
472
796d5313
NC		 4732008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
474
475 * cr16-opc.c (cr16_num_optab): Defined
476
65da13b5
L		 4772008-02-16 H.J. Lu <hongjiu.lu@intel.com>
478
479 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_INOUTPORTREG.
480 * i386-init.h: Regenerated.
481
0e336180
NC		 4822008-02-14 Nick Clifton <nickc@redhat.com>
483
484 PR binutils/5524
485 * configure.in (SHARED_LIBADD): Select the correct host specific
486 file extension for shared libraries.
487 * configure: Regenerate.
488
b7240065
JB		 4892008-02-13 Jan Beulich <jbeulich@novell.com>
490
491 * i386-opc.h (RegFlat): New.
492 * i386-reg.tbl (flat): Add.
493 * i386-tbl.h: Re-generate.
494
34b772a6
JB		 4952008-02-13 Jan Beulich <jbeulich@novell.com>
496
497 * i386-dis.c (a_mode): New.
498 (cond_jump_mode): Adjust.
499 (Ma): Change to a_mode.
500 (intel_operand_size): Handle a_mode.
501 * i386-opc.tbl: Allow Dword and Qword for bound.
502 * i386-tbl.h: Re-generate.
503
a60de03c
JB		 5042008-02-13 Jan Beulich <jbeulich@novell.com>
505
506 * i386-gen.c (process_i386_registers): Process new fields.
507 * i386-opc.h (reg_entry): Shrink reg_flags and reg_num to
508 unsigned char. Add dw2_regnum and Dw2Inval.
509 * i386-reg.tbl: Provide initializers for dw2_regnum. Add pseudo
510 register names.
511 * i386-tbl.h: Re-generate.
512
f03fe4c1
L		 5132008-02-11 H.J. Lu <hongjiu.lu@intel.com>
514
4b6bc8eb 515 * i386-gen.c (cpu_flag_init): Add CPU_XSAVE_FLAGS.
f03fe4c1
L		 516 * i386-init.h: Updated.
517
475a2301
L		 5182008-02-11 H.J. Lu <hongjiu.lu@intel.com>
519
520 * i386-gen.c (cpu_flags): Add CpuXsave.
521
522 * i386-opc.h (CpuXsave): New.
4b6bc8eb 523 (CpuLM): Updated.
475a2301
L		 524 (i386_cpu_flags): Add cpuxsave.
525
526 * i386-dis.c (MOD_0FAE_REG_4): New.
527 (RM_0F01_REG_2): Likewise.
528 (MOD_0FAE_REG_5): Updated.
529 (RM_0F01_REG_3): Likewise.
530 (reg_table): Use MOD_0FAE_REG_4.
531 (mod_table): Use RM_0F01_REG_2. Add MOD_0FAE_REG_4. Updated
532 for xrstor.
533 (rm_table): Add RM_0F01_REG_2.
534
535 * i386-opc.tbl: Add xsave, xrstor, xgetbv and xsetbv.
536 * i386-init.h: Regenerated.
537 * i386-tbl.h: Likewise.
538
595785c6 5392008-02-11 Jan Beulich <jbeulich@novell.com>
041179fc 540
595785c6
JB		 541 * i386-opc.tbl: Remove Disp32S from CpuNo64 opcodes. Remove
542 Disp16 from Cpu64 non-jump opcodes (including loop and j?cxz).
543 * i386-tbl.h: Re-generate.
544
bb8541b9
L		 5452008-02-04 H.J. Lu <hongjiu.lu@intel.com>
546
547 PR 5715
548 * configure: Regenerated.
549
57b592a3
AN		 5502008-02-04 Adam Nemet <anemet@caviumnetworks.com>
551
552 * mips-dis.c: Update copyright.
553 (mips_arch_choices): Add Octeon.
554 * mips-opc.c: Update copyright.
555 (IOCT): New macro.
556 (mips_builtin_opcodes): Add Octeon instruction synciobdma.
557
930bb4cf
AM		 5582008-01-29 Alan Modra <amodra@bigpond.net.au>
559
560 * ppc-opc.c: Support optional L form mtmsr.
561
82c18208
L		 5622008-01-24 H.J. Lu <hongjiu.lu@intel.com>
563
564 * i386-dis.c (OP_E_extended): Handle r12 like rsp.
565
599121aa
L		 5662008-01-23 H.J. Lu <hongjiu.lu@intel.com>
567
568 * i386-gen.c (cpu_flag_init): Add CpuLM to CPU_GENERIC64_FLAGS.
569 * i386-init.h: Regenerated.
570
80098f51
TG		 5712008-01-23 Tristan Gingold <gingold@adacore.com>
572
573 * ia64-dis.c (print_insn_ia64): Display symbolic name of ar.fcr,
574 ar.eflag, ar.csd, ar.ssd, ar.cflg, ar.fsr, ar.fir and ar.fdr.
575
115c7c25
L		 5762008-01-22 H.J. Lu <hongjiu.lu@intel.com>
577
578 * i386-gen.c (cpu_flag_init): Remove CpuMMX2.
579 (cpu_flags): Likewise.
580
581 * i386-opc.h (CpuMMX2): Removed.
582 (CpuSSE): Updated.
583
584 * i386-opc.tbl: Replace CpuMMX2 with CpuSSE|Cpu3dnowA.
585 * i386-init.h: Regenerated.
586 * i386-tbl.h: Likewise.
587
6305a203
L		 5882008-01-22 H.J. Lu <hongjiu.lu@intel.com>
589
590 * i386-gen.c (cpu_flag_init): Add CPU_VMX_FLAGS and
591 CPU_SMX_FLAGS.
592 * i386-init.h: Regenerated.
593
fd07a1c8
L		 5942008-01-15 H.J. Lu <hongjiu.lu@intel.com>
595
596 * i386-opc.tbl: Use Qword on movddup.
597 * i386-tbl.h: Regenerated.
598
321fd21e
L		 5992008-01-15 H.J. Lu <hongjiu.lu@intel.com>
600
601 * i386-opc.tbl: Put back 16bit movsx/movzx for AT&T syntax.
602 * i386-tbl.h: Regenerated.
603
4ee52178
L		 6042008-01-15 H.J. Lu <hongjiu.lu@intel.com>
605
606 * i386-dis.c (Mx): New.
607 (PREFIX_0FC3): Likewise.
608 (PREFIX_0FC7_REG_6): Updated.
609 (dis386_twobyte): Use PREFIX_0FC3.
610 (prefix_table): Add PREFIX_0FC3. Use Mq on movntq and movntsd.
611 Use Mx on movntps, movntpd, movntdq and movntdqa. Use Md on
612 movntss.
613
5c07affc
L		 6142008-01-14 H.J. Lu <hongjiu.lu@intel.com>
615
616 * i386-gen.c (opcode_modifiers): Add IntelSyntax.
617 (operand_types): Add Mem.
618
619 * i386-opc.h (IntelSyntax): New.
620 * i386-opc.h (Mem): New.
621 (Byte): Updated.
622 (Opcode_Modifier_Max): Updated.
623 (i386_opcode_modifier): Add intelsyntax.
624 (i386_operand_type): Add mem.
625
626 * i386-opc.tbl: Remove Reg16 from movnti. Add sizes to more
627 instructions.
628
629 * i386-reg.tbl: Add size for accumulator.
630
631 * i386-init.h: Regenerated.
632 * i386-tbl.h: Likewise.
633
0d6a2f58
L		 6342008-01-13 H.J. Lu <hongjiu.lu@intel.com>
635
636 * i386-opc.h (Byte): Fix a typo.
637
7d5e4556
L		 6382008-01-12 H.J. Lu <hongjiu.lu@intel.com>
639
640 PR gas/5534
641 * i386-gen.c (operand_type_init): Add Dword to
642 OPERAND_TYPE_ACC32. Add Qword to OPERAND_TYPE_ACC64.
643 (opcode_modifiers): Remove CheckSize, Byte, Word, Dword,
644 Qword and Xmmword.
645 (operand_types): Add Byte, Word, Dword, Fword, Qword, Tbyte,
646 Xmmword, Unspecified and Anysize.
647 (set_bitfield): Make Mmword an alias of Qword. Make Oword
648 an alias of Xmmword.
649
650 * i386-opc.h (CheckSize): Removed.
651 (Byte): Updated.
652 (Word): Likewise.
653 (Dword): Likewise.
654 (Qword): Likewise.
655 (Xmmword): Likewise.
656 (FWait): Updated.
657 (OTMax): Likewise.
658 (i386_opcode_modifier): Remove checksize, byte, word, dword,
659 qword and xmmword.
660 (Fword): New.
661 (TBYTE): Likewise.
662 (Unspecified): Likewise.
663 (Anysize): Likewise.
664 (i386_operand_type): Add byte, word, dword, fword, qword,
665 tbyte xmmword, unspecified and anysize.
666
667 * i386-opc.tbl: Updated to use Byte, Word, Dword, Fword, Qword,
668 Tbyte, Xmmword, Unspecified and Anysize.
669
670 * i386-reg.tbl: Add size for accumulator.
671
672 * i386-init.h: Regenerated.
673 * i386-tbl.h: Likewise.
674
b5b1fc4f
L		 6752008-01-10 H.J. Lu <hongjiu.lu@intel.com>
676
677 * i386-dis.c (REG_0F0E): Renamed to REG_0F0D.
678 (REG_0F18): Updated.
679 (reg_table): Updated.
680 (dis386_twobyte): Updated. Use "nopQ" on 0x19 to 0x1e.
681 (twobyte_has_modrm): Set 1 for 0x19 to 0x1e.
682
50e8458f
L		 6832008-01-08 H.J. Lu <hongjiu.lu@intel.com>
684
685 * i386-gen.c (set_bitfield): Use fail () on error.
686
3d4d5afa
L		 6872008-01-08 H.J. Lu <hongjiu.lu@intel.com>
688
689 * i386-gen.c (lineno): New.
690 (filename): Likewise.
691 (set_bitfield): Report filename and line numer on error.
692 (process_i386_opcodes): Set filename and update lineno.
693 (process_i386_registers): Likewise.
694
e1d4d893
L		 6952008-01-05 H.J. Lu <hongjiu.lu@intel.com>
696
697 * i386-gen.c (opcode_modifiers): Rename IntelMnemonic to
698 ATTSyntax.
699
700 * i386-opc.h (IntelMnemonic): Renamed to ..
701 (ATTSyntax): This
702 (Opcode_Modifier_Max): Updated.
703 (i386_opcode_modifier): Remove intelmnemonic. Add attsyntax
704 and intelsyntax.
705
8944f3c2 706 * i386-opc.tbl: Remove IntelMnemonic and update with ATTSyntax
e1d4d893
L		 707 on fsub, fubp, fsubr, fsubrp, div, fdivp, fdivr and fdivrp.
708 * i386-tbl.h: Regenerated.
709
6f143e4d
L		 7102008-01-04 H.J. Lu <hongjiu.lu@intel.com>
711
712 * i386-gen.c: Update copyright to 2008.
713 * i386-opc.h: Likewise.
714 * i386-opc.tbl: Likewise.
715
716 * i386-init.h: Regenerated.
717 * i386-tbl.h: Likewise.
718
c6add537
L		 7192008-01-04 H.J. Lu <hongjiu.lu@intel.com>
720
721 * i386-opc.tbl: Add NoRex64 to extractps, movmskpd, movmskps,
722 pextrb, pextrw, pinsrb, pinsrw and pmovmskb.
723 * i386-tbl.h: Regenerated.
724
3629bb00
L		 7252008-01-03 H.J. Lu <hongjiu.lu@intel.com>
726
727 * i386-gen.c (cpu_flag_init): Remove CpuSSE4_1_Or_5 and
728 CpuSSE4_2_Or_ABM.
729 (cpu_flags): Likewise.
730
731 * i386-opc.h (CpuSSE4_1_Or_5): Removed.
732 (CpuSSE4_2_Or_ABM): Likewise.
733 (CpuLM): Updated.
734 (i386_cpu_flags): Remove cpusse4_1_or_5 and cpusse4_2_or_abm.
735
736 * i386-opc.tbl: Replace CpuSSE4_1_Or_5, CpuSSE4_2_Or_ABM and
737 Cpu686|CpuPadLock with CpuSSE4_1|CpuSSE5, CpuABM|CpuSSE4_2
738 and CpuPadLock, respectively.
739 * i386-init.h: Regenerated.
740 * i386-tbl.h: Likewise.
741
24995bd6
L		 7422008-01-03 H.J. Lu <hongjiu.lu@intel.com>
743
744 * i386-gen.c (opcode_modifiers): Remove No_xSuf.
745
746 * i386-opc.h (No_xSuf): Removed.
747 (CheckSize): Updated.
748
749 * i386-tbl.h: Regenerated.
750
e0329a22
L		 7512008-01-02 H.J. Lu <hongjiu.lu@intel.com>
752
753 * i386-gen.c (cpu_flag_init): Add CpuSSE4_2_Or_ABM to
754 CPU_AMDFAM10_FLAGS, CPU_SSE4_2_FLAGS, CpuABM and
755 CPU_SSE5_FLAGS.
756 (cpu_flags): Add CpuSSE4_2_Or_ABM.
757
758 * i386-opc.h (CpuSSE4_2_Or_ABM): New.
759 (CpuLM): Updated.
760 (i386_cpu_flags): Add cpusse4_2_or_abm.
761
762 * i386-opc.tbl: Use CpuSSE4_2_Or_ABM instead of
763 CpuABM|CpuSSE4_2 on popcnt.
764 * i386-init.h: Regenerated.
765 * i386-tbl.h: Likewise.
766
f2a9c676
L		 7672008-01-02 H.J. Lu <hongjiu.lu@intel.com>
768
769 * i386-opc.h: Update comments.
770
d978b5be
L		 7712008-01-02 H.J. Lu <hongjiu.lu@intel.com>
772
773 * i386-gen.c (opcode_modifiers): Use Qword instead of QWord.
774 * i386-opc.h: Likewise.
775 * i386-opc.tbl: Likewise.
776
582d5edd
L		 7772008-01-02 H.J. Lu <hongjiu.lu@intel.com>
778
779 PR gas/5534
780 * i386-gen.c (opcode_modifiers): Add No_xSuf, CheckSize,
781 Byte, Word, Dword, QWord and Xmmword.
782
783 * i386-opc.h (No_xSuf): New.
784 (CheckSize): Likewise.
785 (Byte): Likewise.
786 (Word): Likewise.
787 (Dword): Likewise.
788 (QWord): Likewise.
789 (Xmmword): Likewise.
790 (FWait): Updated.
791 (i386_opcode_modifier): Add No_xSuf, CheckSize, Byte, Word,
792 Dword, QWord and Xmmword.
793
794 * i386-opc.tbl: Add CheckSize|QWord to movq if IgnoreSize is
795 used.
796 * i386-tbl.h: Regenerated.
797
3fe15143
MK		 7982008-01-02 Mark Kettenis <kettenis@gnu.org>
799
800 * m88k-dis.c (instructions): Fix fcvt.* instructions.
801 From Miod Vallat.
802
6c7ac64e 803For older changes see ChangeLog-2007
252b5132
RH		 804\f
805Local Variables:
2f6d2f85
NC		 806mode: change-log
807left-margin: 8
808fill-column: 74
252b5132
RH		 809version-control: never
810End:
GDB Binutils - Deliverables
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