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* ppc-opc.c (extract_sprg): Correct operand range check.
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
e1c93c69
AM		 12008-11-27 Alan Modra <amodra@bigpond.net.au>
2
3 * ppc-opc.c (extract_sprg): Correct operand range check.
4
9f7678f6
AS		 52008-11-26 Andreas Schwab <schwab@suse.de>
6
7 * m68k-dis.c (NEXTBYTE, NEXTWORD, NEXTLONG, NEXTULONG, NEXTSINGLE)
8 (NEXTDOUBLE, NEXTEXTEND, NEXTPACKED): Fix error handling.
9 (save_printer, save_print_address): Remove.
10 (fetch_data): Don't use them.
11 (match_insn_m68k): Always restore printing functions.
12 (print_insn_m68k): Don't save/restore printing functions.
13
62443ade
NC		 142008-11-25 Nick Clifton <nickc@redhat.com>
15
16 * m68k-dis.c: Rewrite to remove use of setjmp/longjmp.
17
8e79c3df
CM		 182008-11-18 Catherine Moore <clm@codesourcery.com>
19
20 * arm-dis.c (coprocessor_opcodes): Add half-precision vcvt
21 instructions.
22 (neon_opcodes): Likewise.
23 (print_insn_coprocessor): Print 't' or 'b' for vcvt
24 instructions.
25
d387240a
TG		 262008-11-14 Tristan Gingold <gingold@adacore.com>
27
28 * makefile.vms (OBJS): Update list of objects.
29 (DEFS): Update
30 (CFLAGS): Update.
31
4dc48ef6
CF		 322008-11-06 Chao-ying Fu <fu@mips.com>
33
34 * mips-opc.c (synciobdma, syncs, syncw, syncws): Move these
35 before sync.
36 (sync): New instruction with 5-bit sync type.
3c6528a8 37 * mips-dis.c (print_insn_args): Add case '1' to print 5-bit values.
4dc48ef6 38
c8941035
NC		 392008-11-06 Nick Clifton <nickc@redhat.com>
40
41 * avr-dis.c: Replace uses of sprintf without a format string with
42 calls to strcpy.
43
a7bea99d
L		 442008-11-03 H.J. Lu <hongjiu.lu@intel.com>
45
46 * i386-opc.tbl: Add cmovpe and cmovpo.
47 * i386-tbl.h: Regenerated.
48
4267b19f
NC		 492008-10-22 Nick Clifton <nickc@redhat.com>
50
51 PR 6937
52 * configure.in (SHARED_LIBADD): Revert previous change.
53 Add a comment explaining why.
54 (SHARED_DEPENDENCIES): Revert previous change.
55 * configure: Regenerate.
56
8a9629d0
NC		 572008-10-10 Nick Clifton <nickc@redhat.com>
58
59 PR 6937
60 * configure.in (SHARED_LIBADD): Add libiberty.a.
61 (SHARED_DEPENDENCIES): Add libiberty.a.
62
c587b3f9
L		 632008-09-30 H.J. Lu <hongjiu.lu@intel.com>
64
65 * i386-gen.c: Include "hashtab.h".
66 (next_field): Take a new argument, last. Check last.
67 (process_i386_cpu_flag): Updated.
68 (process_i386_opcode_modifier): Likewise.
69 (process_i386_operand_type): Likewise.
70 (process_i386_registers): Likewise.
71 (output_i386_opcode): New.
72 (opcode_hash_entry): Likewise.
73 (opcode_hash_table): Likewise.
74 (opcode_hash_hash): Likewise.
75 (opcode_hash_eq): Likewise.
76 (process_i386_opcodes): Use opcode hash table and opcode array.
77
34b23dab
AK		 782008-09-30 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
79
80 * s390-opc.txt (stdy, stey): Fix description
81
782e11fd
AM		 822008-09-30 Alan Modra <amodra@bigpond.net.au>
83
84 * Makefile.am: Run "make dep-am".
85 * Makefile.in: Regenerate.
86
1927a18f
L		 872008-09-29 H.J. Lu <hongjiu.lu@intel.com>
88
89 * aclocal.m4: Regenerated.
90 * configure: Likewise.
91 * Makefile.in: Likewise.
92
afac680a
NC		 932008-09-29 Nick Clifton <nickc@redhat.com>
94
95 * po/vi.po: Updated Vietnamese translation.
96 * po/fr.po: Updated French translation.
97
b40d5eb9
AK		 982008-09-26 Florian Krohm <fkrohm@us.ibm.com>
99
100 * s390-opc.txt (thder, thdr): Change RRE_RR to RRE_FF.
101 (cfxr, cfdr, cfer, clclu): Add esa flag.
102 (sqd): Instruction added.
103 (qadtr, qaxtr): Change RRF_FFFU to RRF_FUFF.
104 * s390-opc.c: (INSTR_RRF_FFFU, MASK_RRF_FFFU): Removed.
105
d0411736
AM		 1062008-09-14 Arnold Metselaar <arnold.metselaar@planet.nl>
107
108 * z80-dis.c (prt_rr_nn): Fix register pair for two byte opcodes.
109 (tab_elt opc_ed): Add "ld r,a" and "ld r,a" instructions.
110
3e126784
L		 1112008-09-11 H.J. Lu <hongjiu.lu@intel.com>
112
113 * i386-opc.tbl: Fix memory operand size for cmpXXXs[sd].
114 * i386-tbl.h: Regenerated.
115
ddab3d59
JB		 1162008-08-28 Jan Beulich <jbeulich@novell.com>
117
118 * i386-dis.c (dis386): Adjust far return mnemonics.
119 * i386-opc.tbl: Add retf.
120 * i386-tbl.h: Re-generate.
121
b19d5385
JB		 1222008-08-28 Jan Beulich <jbeulich@novell.com>
123
124 * i386-dis.c (dis386_twobyte): Adjust cmovXX mnemonics.
125
1ca35711
L		 1262008-08-28 H.J. Lu <hongjiu.lu@intel.com>
127
128 * ia64-dis.c (print_insn_ia64): Handle cr.iib0 and cr.iib1.
129 * ia64-gen.c (lookup_specifier): Likewise.
130
131 * ia64-ic.tbl: Add support for cr.iib0 and cr.iib1.
132 * ia64-raw.tbl: Likewise.
133 * ia64-waw.tbl: Likewise.
134 * ia64-asmtab.c: Regenerated.
135
515c56e7
L		 1362008-08-27 H.J. Lu <hongjiu.lu@intel.com>
137
138 * i386-opc.tbl: Correct fidivr operand size.
139
140 * i386-tbl.h: Regenerated.
141
da594c4a
AM		 1422008-08-24 Alan Modra <amodra@bigpond.net.au>
143
144 * configure.in: Update a number of obsolete autoconf macros.
145 * aclocal.m4: Regenerate.
146
a5ff0eb2
L		 1472008-08-20 H.J. Lu <hongjiu.lu@intel.com>
148
149 AVX Programming Reference (August, 2008)
150 * i386-dis.c (PREFIX_VEX_38DB): New.
151 (PREFIX_VEX_38DC): Likewise.
152 (PREFIX_VEX_38DD): Likewise.
153 (PREFIX_VEX_38DE): Likewise.
154 (PREFIX_VEX_38DF): Likewise.
155 (PREFIX_VEX_3ADF): Likewise.
156 (VEX_LEN_38DB_P_2): Likewise.
157 (VEX_LEN_38DC_P_2): Likewise.
158 (VEX_LEN_38DD_P_2): Likewise.
159 (VEX_LEN_38DE_P_2): Likewise.
160 (VEX_LEN_38DF_P_2): Likewise.
161 (VEX_LEN_3ADF_P_2): Likewise.
162 (PREFIX_VEX_3A04): Updated.
163 (VEX_LEN_3A06_P_2): Likewise.
164 (prefix_table): Add PREFIX_VEX_38DB, PREFIX_VEX_38DC,
165 PREFIX_VEX_38DD, PREFIX_VEX_38DE and PREFIX_VEX_3ADF.
166 (x86_64_table): Likewise.
167 (vex_len_table): Add VEX_LEN_38DB_P_2, VEX_LEN_38DC_P_2,
168 VEX_LEN_38DD_P_2, VEX_LEN_38DE_P_2, VEX_LEN_38DF_P_2 and
169 VEX_LEN_3ADF_P_2.
170
171 * i386-opc.tbl: Add AES + AVX instructions.
172 * i386-init.h: Regenerated.
173 * i386-tbl.h: Likewise.
174
7dc6076f
AK		 1752008-08-15 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
176
177 * s390-opc.c (INSTR_RRF_FFRU, MASK_RRF_FFRU): New instruction format.
178 * s390-opc.txt (lxr, rrdtr, rrxtr): Fix instruction format.
179
7357c5b6
AM		 1802008-08-15 Alan Modra <amodra@bigpond.net.au>
181
182 PR 6526
183 * configure.in: Invoke AC_USE_SYSTEM_EXTENSIONS.
184 * Makefile.in: Regenerate.
185 * aclocal.m4: Regenerate.
186 * config.in: Regenerate.
187 * configure: Regenerate.
188
899d85be
AM		 1892008-08-14 Sebastian Huber <sebastian.huber@embedded-brains.de>
190
191 PR 6825
192 * ppc-opc.c (powerpc_opcodes): Enable rfci, mfpmr, mtpmr for e300.
193
dfb07592
L		 1942008-08-12 H.J. Lu <hongjiu.lu@intel.com>
195
196 * i386-opc.tbl: Add syscall and sysret for Cpu64.
197
198 * i386-tbl.h: Regenerated.
199
323ee3f4
AM		 2002008-08-04 Alan Modra <amodra@bigpond.net.au>
201
202 * Makefile.am (POTFILES.in): Set LC_ALL=C.
203 * Makefile.in: Regenerate.
204 * po/POTFILES.in: Regenerate.
205
9b4e5766
PB		 2062008-08-01 Peter Bergner <bergner@vnet.ibm.com>
207
208 * ppc-dis.c (powerpc_init_dialect): Handle power7 and vsx options.
209 (print_insn_powerpc): Prepend 'vs' when printing VSX registers.
210 (print_ppc_disassembler_options): Document -Mpower7 and -Mvsx.
211 * ppc-opc.c (insert_xt6): New static function.
212 (extract_xt6): Likewise.
213 (insert_xa6): Likewise.
214 (extract_xa6: Likewise.
215 (insert_xb6): Likewise.
216 (extract_xb6): Likewise.
217 (insert_xb6s): Likewise.
218 (extract_xb6s): Likewise.
219 (XS6, XT6, XA6, XB6, XB6S, DM, XX3, XX3DM, XX1_MASK, XX3_MASK,
220 XX3DM_MASK, PPCVSX): New.
221 (powerpc_opcodes): Add opcodes "lxvd2x", "lxvd2ux", "stxvd2x",
222 "stxvd2ux", "xxmrghd", "xxmrgld", "xxpermdi", "xvmovdp", "xvcpsgndp".
223
20fd6e2e
PA		 2242008-08-01 Pedro Alves <pedro@codesourcery.com>
225
226 * Makefile.am ($(srcdir)/ia64-asmtab.c): Remove line continuation.
227 * Makefile.in: Regenerate.
228
a656ed5b
L		 2292008-08-01 H.J. Lu <hongjiu.lu@intel.com>
230
231 * i386-reg.tbl: Use Dw2Inval on AVX registers.
232 * i386-tbl.h: Regenerated.
233
081ba1b3
AM		 2342008-07-30 Michael J. Eager <eager@eagercon.com>
235
236 * ppc-dis.c (print_insn_powerpc): Disassemble FSL/FCR/UDI fields.
237 * ppc-opc.c (powerpc_operands): Add Xilinx APU related operands.
238 (insert_sprg, PPC405): Use PPC_OPCODE_405.
239 (powerpc_opcodes): Add Xilinx APU related opcodes.
240
0af1713e
AM		 2412008-07-30 Alan Modra <amodra@bigpond.net.au>
242
243 * bfin-dis.c, cris-dis.c, i386-dis.c, or32-opc.c: Silence gcc warnings.
244
30c09090
RS		 2452008-07-10 Richard Sandiford <rdsandiford@googlemail.com>
246
247 * mips-dis.c (_print_insn_mips): Use ELF_ST_IS_MIPS16.
248
c27e721e
AN		 2492008-07-07 Adam Nemet <anemet@caviumnetworks.com>
250
251 * mips-opc.c (CP): New macro.
252 (mips_builtin_opcodes): Mark c0, c2 and c3 as CP. Add Octeon to the
253 membership of di, dmfc0, dmtc0, ei, mfc0 and mtc0. Add dmfc2 and
254 dmtc2 Octeon instructions.
255
bd2e2557
SS		 2562008-07-07 Stan Shebs <stan@codesourcery.com>
257
258 * dis-init.c (init_disassemble_info): Init endian_code field.
259 * arm-dis.c (print_insn): Disassemble code according to
260 setting of endian_code.
261 (print_insn_big_arm): Detect when BE8 extension flag has been set.
262
6ba2a415
RS		 2632008-06-30 Richard Sandiford <rdsandiford@googlemail.com>
264
265 * mips-dis.c (_print_insn_mips): Use bfd_asymbol_flavour to check
266 for ELF symbols.
267
c8187e15
PB		 2682008-06-25 Peter Bergner <bergner@vnet.ibm.com>
269
270 * ppc-dis.c (powerpc_init_dialect): Handle -M464.
271 (print_ppc_disassembler_options): Likewise.
272 * ppc-opc.c (PPC464): Define.
273 (powerpc_opcodes): Add mfdcrux and mtdcrux.
274
7a283e07
RW		 2752008-06-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
276
277 * configure: Regenerate.
278
fa452fa6
PB		 2792008-06-13 Peter Bergner <bergner@vnet.ibm.com>
280
281 * ppc-dis.c (print_insn_powerpc): Update prototye to use new
282 ppc_cpu_t typedef.
283 (struct dis_private): New.
284 (POWERPC_DIALECT): New define.
285 (powerpc_dialect): Renamed to...
286 (powerpc_init_dialect): This. Update to use ppc_cpu_t and
287 struct dis_private.
288 (print_insn_big_powerpc): Update for using structure in
289 info->private_data.
290 (print_insn_little_powerpc): Likewise.
291 (operand_value_powerpc): Change type of dialect param to ppc_cpu_t.
292 (skip_optional_operands): Likewise.
293 (print_insn_powerpc): Likewise. Remove initialization of dialect.
294 * ppc-opc.c (extract_bat, extract_bba, extract_bdm, extract_bdp,
295 extract_bo, extract_boe, extract_fxm, extract_mb6, extract_mbe,
296 extract_nb, extract_nsi, extract_rbs, extract_sh6, extract_spr,
297 extract_sprg, extract_tbr insert_bat, insert_bba, insert_bdm,
298 insert_bdp, insert_bo, insert_boe, insert_fxm, insert_mb6, insert_mbe,
299 insert_nsi, insert_ral, insert_ram, insert_raq, insert_ras, insert_rbs,
300 insert_sh6, insert_spr, insert_sprg, insert_tbr): Change the dialect
301 param to be of type ppc_cpu_t. Update prototype.
302
bb35fb24
NC		 3032008-06-12 Adam Nemet <anemet@caviumnetworks.com>
304
305 * mips-dis.c (print_insn_args): Handle field descriptors +x, +p,
306 +s, +S.
307 * mips-opc.c (mips_builtin_opcodes): Add Octeon instructions
308 baddu, bbit*, cins*, dmul, pop, dpop, exts*, mtm*, mtp*, syncs,
309 syncw, syncws, vm3mulu, vm0 and vmulu.
310
dd3cbb7e
NC		 311 * mips-dis.c (print_insn_args): Handle field descriptor +Q.
312 * mips-opc.c (mips_builtin_opcodes): Add Octeon instructions seq,
313 seqi, sne and snei.
314
a5dabbb0
L		 3152008-05-30 H.J. Lu <hongjiu.lu@intel.com>
316
317 * i386-opc.tbl: Add vmovd with 64bit operand.
318 * i386-tbl.h: Regenerated.
319
725a9891
MS		 3202008-05-27 Martin Schwidefsky <schwidefsky@de.ibm.com>
321
322 * s390-opc.c (INSTR_RRF_R0RR): Fix RRF_R0RR operand format.
323
cbc80391
L		 3242008-05-22 H.J. Lu <hongjiu.lu@intel.com>
325
326 * i386-opc.tbl: Add NoAVX to cvtpd2pi, cvtpi2pd and cvttpd2pi.
327 * i386-tbl.h: Regenerated.
328
116615c5
L		 3292008-05-22 H.J. Lu <hongjiu.lu@intel.com>
330
331 PR gas/6517
332 * i386-opc.tbl: Break cvtsi2ss/cvtsi2sd/vcvtsi2sd/vcvtsi2ss
3c6528a8 333 into 32bit and 64bit. Remove Reg64|Qword and add
116615c5
L		 334 IgnoreSize|No_qSuf on 32bit version.
335 * i386-tbl.h: Regenerated.
336
d9479f2d
L		 3372008-05-21 H.J. Lu <hongjiu.lu@intel.com>
338
339 * i386-opc.tbl: Add NoAVX to movdq2q and movq2dq.
340 * i386-tbl.h: Regenerated.
341
3ce6fddb
NC		 3422008-05-21 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
343
344 * cr16-dis.c (build_mask): Adjust the mask for 32-bit bcond.
345
8944f3c2
AM		 3462008-05-14 Alan Modra <amodra@bigpond.net.au>
347
348 * Makefile.am: Run "make dep-am".
349 * Makefile.in: Regenerate.
350
f1f8f695
L		 3512008-05-02 H.J. Lu <hongjiu.lu@intel.com>
352
353 * i386-dis.c (MOVBE_Fixup): New.
354 (Mo): Likewise.
355 (PREFIX_0F3880): Likewise.
356 (PREFIX_0F3881): Likewise.
357 (PREFIX_0F38F0): Updated.
358 (prefix_table): Add PREFIX_0F3880 and PREFIX_0F3881. Update
359 PREFIX_0F38F0 and PREFIX_0F38F1 for movbe.
360 (three_byte_table): Use PREFIX_0F3880 and PREFIX_0F3881.
361
362 * i386-gen.c (cpu_flag_init): Add CPU_MOVBE_FLAGS and
363 CPU_EPT_FLAGS.
364 (cpu_flags): Add CpuMovbe and CpuEPT.
365
366 * i386-opc.h (CpuMovbe): New.
367 (CpuEPT): Likewise.
368 (CpuLM): Updated.
369 (i386_cpu_flags): Add cpumovbe and cpuept.
370
371 * i386-opc.tbl: Add entries for movbe and EPT instructions.
372 * i386-init.h: Regenerated.
373 * i386-tbl.h: Likewise.
374
89aa3097
AN		 3752008-04-29 Adam Nemet <anemet@caviumnetworks.com>
376
377 * mips-opc.c (mips_builtin_opcodes): Set field `match' to 0 for
378 the two drem and the two dremu macros.
379
39c5c168
AN		 3802008-04-28 Adam Nemet <anemet@caviumnetworks.com>
381
382 * mips-opc.c (mips_builtin_opcodes): Mark prefx and c1
383 instructions FP_S. Mark l.s, li.s, lwc1, swc1, s.s, trunc.w.s and
384 cop1 macros INSN2_M_FP_S. Mark l.d, li.d, ldc1 and sdc1 macros
385 INSN2_M_FP_D. Mark trunc.w.d macro INSN2_M_FP_S and INSN2_M_FP_D.
386
f04d18b7
DM		 3872008-04-25 David S. Miller <davem@davemloft.net>
388
389 * sparc-dis.c: Emit %stick instead of %sys_tick, and %stick_cmpr
390 instead of %sys_tick_cmpr, as suggested in architecture manuals.
391
6194aaab
L		 3922008-04-23 Paolo Bonzini <bonzini@gnu.org>
393
394 * aclocal.m4: Regenerate.
395 * configure: Regenerate.
396
1a6b486f
DM		 3972008-04-23 David S. Miller <davem@davemloft.net>
398
399 * sparc-opc.c (asi_table): Add UltraSPARC and Niagara
400 extended values.
401 (prefetch_table): Add missing values.
402
81f8a913
L		 4032008-04-22 H.J. Lu <hongjiu.lu@intel.com>
404
405 * i386-gen.c (opcode_modifiers): Add NoAVX.
406
407 * i386-opc.h (NoAVX): New.
408 (OldGcc): Updated.
409 (i386_opcode_modifier): Add noavx.
410
411 * i386-opc.tbl: Add NoAVX to SSE, SSE2, SSE3 and SSSE3
412 instructions which don't have AVX equivalent.
413 * i386-tbl.h: Regenerated.
414
dae39acc
L		 4152008-04-18 H.J. Lu <hongjiu.lu@intel.com>
416
417 * i386-dis.c (OP_VEX_FMA): New.
418 (OP_EX_VexImmW): Likewise.
419 (VexFMA): Likewise.
420 (Vex128FMA): Likewise.
421 (EXVexImmW): Likewise.
422 (get_vex_imm8): Likewise.
423 (OP_EX_VexReg): Likewise.
424 (vex_i4_done): Renamed to ...
425 (vex_w_done): This.
426 (prefix_table): Replace EXVexW with EXVexImmW on vpermil2ps
427 and vpermil2pd. Replace Vex/Vex128 with VexFMA/Vex128FMA on
428 FMA instructions.
429 (print_insn): Updated.
430 (OP_EX_VexW): Rewrite to swap register in VEX with EX.
431 (OP_REG_VexI4): Check invalid high registers.
432
ce886ab1
DR		 4332008-04-16 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
434 Michael Meissner <michael.meissner@amd.com>
435
436 * i386-opc.tbl: Fix protX to allow memory in the middle operand.
437 * i386-tbl.h: Regenerate from i386-opc.tbl.
8944f3c2 438
19a6653c
AM		 4392008-04-14 Edmar Wienskoski <edmar@freescale.com>
440
441 * ppc-dis.c (powerpc_dialect): Handle "e500mc". Extend "e500" to
442 accept Power E500MC instructions.
443 (print_ppc_disassembler_options): Document -Me500mc.
444 * ppc-opc.c (DUIS, DUI, T): New.
445 (XRT, XRTRA): Likewise.
446 (E500MC): Likewise.
447 (powerpc_opcodes): Add new Power E500MC instructions.
448
112b7c50
AK		 4492008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
450
451 * s390-dis.c (init_disasm): Evaluate disassembler_options.
452 (print_s390_disassembler_options): New function.
453 * disassemble.c (disassembler_usage): Invoke
454 print_s390_disassembler_options.
455
7ff42648
AK		 4562008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
457
458 * s390-mkopc.c (insertExpandedMnemonic): Expand string sizes
459 of local variables used for mnemonic parsing: prefix, suffix and
460 number.
461
45a5551e
AK		 4622008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
463
464 * s390-mkopc.c (s390_cond_ext_format): Add back the mnemonic
465 extensions for conditional jumps (o, p, m, nz, z, nm, np, no).
466 (s390_crb_extensions): New extensions table.
467 (insertExpandedMnemonic): Handle '$' tag.
468 * s390-opc.txt: Remove conditional jump variants which can now
469 be expanded automatically.
470 Replace '*' tag with '$' in the compare and branch instructions.
471
06c8514a
L		 4722008-04-07 H.J. Lu <hongjiu.lu@intel.com>
473
474 * i386-dis.c (PREFIX_VEX_38XX): Add a tab.
475 (PREFIX_VEX_3AXX): Likewis.
476
b122c285
L		 4772008-04-07 H.J. Lu <hongjiu.lu@intel.com>
478
479 * i386-opc.tbl: Remove 4 extra blank lines.
480
594ab6a3
L		 4812008-04-04 H.J. Lu <hongjiu.lu@intel.com>
482
483 * i386-gen.c (cpu_flag_init): Replace CPU_CLMUL_FLAGS/CpuCLMUL
484 with CPU_PCLMUL_FLAGS/CpuPCLMUL.
485 (cpu_flags): Replace CpuCLMUL with CpuPCLMUL.
486 * i386-opc.tbl: Likewise.
487
488 * i386-opc.h (CpuCLMUL): Renamed to ...
489 (CpuPCLMUL): This.
490 (CpuFMA): Updated.
491 (i386_cpu_flags): Replace cpuclmul with cpupclmul.
492
493 * i386-init.h: Regenerated.
494
c0f3af97
L		 4952008-04-03 H.J. Lu <hongjiu.lu@intel.com>
496
497 * i386-dis.c (OP_E_register): New.
498 (OP_E_memory): Likewise.
499 (OP_VEX): Likewise.
500 (OP_EX_Vex): Likewise.
501 (OP_EX_VexW): Likewise.
502 (OP_XMM_Vex): Likewise.
503 (OP_XMM_VexW): Likewise.
504 (OP_REG_VexI4): Likewise.
505 (PCLMUL_Fixup): Likewise.
506 (VEXI4_Fixup): Likewise.
507 (VZERO_Fixup): Likewise.
508 (VCMP_Fixup): Likewise.
509 (VPERMIL2_Fixup): Likewise.
510 (rex_original): Likewise.
511 (rex_ignored): Likewise.
512 (Mxmm): Likewise.
513 (XMM): Likewise.
514 (EXxmm): Likewise.
515 (EXxmmq): Likewise.
516 (EXymmq): Likewise.
517 (Vex): Likewise.
518 (Vex128): Likewise.
519 (Vex256): Likewise.
520 (VexI4): Likewise.
521 (EXdVex): Likewise.
522 (EXqVex): Likewise.
523 (EXVexW): Likewise.
524 (EXdVexW): Likewise.
525 (EXqVexW): Likewise.
526 (XMVex): Likewise.
527 (XMVexW): Likewise.
528 (XMVexI4): Likewise.
529 (PCLMUL): Likewise.
530 (VZERO): Likewise.
531 (VCMP): Likewise.
532 (VPERMIL2): Likewise.
533 (xmm_mode): Likewise.
534 (xmmq_mode): Likewise.
535 (ymmq_mode): Likewise.
536 (vex_mode): Likewise.
537 (vex128_mode): Likewise.
538 (vex256_mode): Likewise.
539 (USE_VEX_C4_TABLE): Likewise.
540 (USE_VEX_C5_TABLE): Likewise.
541 (USE_VEX_LEN_TABLE): Likewise.
542 (VEX_C4_TABLE): Likewise.
543 (VEX_C5_TABLE): Likewise.
544 (VEX_LEN_TABLE): Likewise.
545 (REG_VEX_XX): Likewise.
546 (MOD_VEX_XXX): Likewise.
547 (PREFIX_0F38DB..PREFIX_0F38DF): Likewise.
548 (PREFIX_0F3A44): Likewise.
549 (PREFIX_0F3ADF): Likewise.
550 (PREFIX_VEX_XXX): Likewise.
551 (VEX_OF): Likewise.
552 (VEX_OF38): Likewise.
553 (VEX_OF3A): Likewise.
554 (VEX_LEN_XXX): Likewise.
555 (vex): Likewise.
556 (need_vex): Likewise.
557 (need_vex_reg): Likewise.
558 (vex_i4_done): Likewise.
559 (vex_table): Likewise.
560 (vex_len_table): Likewise.
561 (OP_REG_VexI4): Likewise.
562 (vex_cmp_op): Likewise.
563 (pclmul_op): Likewise.
564 (vpermil2_op): Likewise.
565 (m_mode): Updated.
566 (es_reg): Likewise.
567 (PREFIX_0F38F0): Likewise.
568 (PREFIX_0F3A60): Likewise.
569 (reg_table): Add REG_VEX_71...REG_VEX_73 and REG_VEX_AE.
570 (prefix_table): Add PREFIX_0F38DB..PREFIX_0F38DF, PREFIX_0F3ADF
571 and PREFIX_VEX_XXX entries.
572 (x86_64_table): Use VEX_C4_TABLE and VEX_C5_TABLE.
573 (three_byte_table): Use PREFIX_0F38DB..PREFIX_0F38DF and
574 PREFIX_0F3ADF.
575 (mod_table): Use VEX_C4_TABLE, VEX_C5_TABLE and VEX_LEN_TABLE.
576 Add MOD_VEX_XXX entries.
577 (ckprefix): Initialize rex_original and rex_ignored. Store the
578 REX byte in rex_original.
579 (get_valid_dis386): Handle the implicit prefix in VEX prefix
580 bytes and USE_VEX_LEN_TABLE/USE_VEX_C4_TABLE/USE_VEX_C5_TABLE.
581 (print_insn): Set need_vex/need_vex_reg/vex_i4_done to 0 before
582 calling get_valid_dis386. Use rex_original and rex_ignored when
583 printing out REX.
584 (putop): Handle "XY".
585 (intel_operand_size): Handle VEX, xmm_mode, xmmq_mode and
586 ymmq_mode.
587 (OP_E_extended): Updated to use OP_E_register and
588 OP_E_memory.
589 (OP_XMM): Handle VEX.
590 (OP_EX): Likewise.
591 (XMM_Fixup): Likewise.
592 (CMP_Fixup): Use ARRAY_SIZE.
593
594 * i386-gen.c (cpu_flag_init): Add CpuAES, CPU_CLMUL_FLAGS,
595 CPU_FMA_FLAGS and CPU_AVX_FLAGS.
596 (operand_type_init): Add OPERAND_TYPE_REGYMM and
597 OPERAND_TYPE_VEX_IMM4.
598 (cpu_flags): Add CpuAVX, CpuAES, CpuCLMUL and CpuFMA.
599 (opcode_modifiers): Add Implicit1stXmm0, Vex, Vex256, VexNDD,
600 VexNDS, VexW0, VexW1, Vex0F, Vex0F38, Vex0F3A, Vex3Sources,
601 VexImmExt and SSE2AVX.
602 (operand_types): Add RegYMM, Ymmword and Vex_Imm4.
603
604 * i386-opc.h (CpuAVX): New.
605 (CpuAES): Likewise.
606 (CpuCLMUL): Likewise.
607 (CpuFMA): Likewise.
608 (Vex): Likewise.
609 (Vex256): Likewise.
610 (VexNDS): Likewise.
611 (VexNDD): Likewise.
612 (VexW0): Likewise.
613 (VexW1): Likewise.
614 (Vex0F): Likewise.
615 (Vex0F38): Likewise.
616 (Vex0F3A): Likewise.
617 (Vex3Sources): Likewise.
618 (VexImmExt): Likewise.
619 (SSE2AVX): Likewise.
620 (RegYMM): Likewise.
621 (Ymmword): Likewise.
622 (Vex_Imm4): Likewise.
623 (Implicit1stXmm0): Likewise.
624 (CpuXsave): Updated.
625 (CpuLM): Likewise.
626 (ByteOkIntel): Likewise.
627 (OldGcc): Likewise.
628 (Control): Likewise.
629 (Unspecified): Likewise.
630 (OTMax): Likewise.
631 (i386_cpu_flags): Add cpuavx, cpuaes, cpuclmul and cpufma.
632 (i386_opcode_modifier): Add implicit1stxmm0, vex, vex256,
633 vexnds, vexndd, vexw0, vexw1, vex0f, vex0f38, vex0f3a,
634 vex3sources, veximmext and sse2avx.
635 (i386_operand_type): Add regymm, ymmword and vex_imm4.
636
637 * i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions.
638
639 * i386-reg.tbl: Add AVX registers, ymm0..ymm15.
640
641 * i386-init.h: Regenerated.
642 * i386-tbl.h: Likewise.
643
b21c9cb4
BS		 6442008-03-26 Bernd Schmidt <bernd.schmidt@analog.com>
645
646 From Robin Getz <robin.getz@analog.com>
647 * bfin-dis.c (bu32): Typedef.
648 (enum const_forms_t): Add c_uimm32 and c_huimm32.
649 (constant_formats[]): Add uimm32 and huimm16.
650 (fmtconst_val): New.
651 (uimm32): Define.
652 (huimm32): Define.
653 (imm16_val): Define.
654 (luimm16_val): Define.
655 (struct saved_state): Define.
656 (GREG, DPREG, DREG, PREG, SPREG, FPREG, IREG, MREG, BREG, LREG,
657 A0XREG, A0WREG, A1XREG, A1WREG,CCREG, LC0REG, LT0REG, LB0REG,
658 LC1REG, LT1REG, LB1REG, RETSREG, PCREG): Define.
659 (get_allreg): New.
660 (decode_LDIMMhalf_0): Print out the whole register value.
661
ee171c8f
BS		 662 From Jie Zhang <jie.zhang@analog.com>
663 * bfin-dis.c (decode_dsp32mac_0): Decode (IU) option for
664 multiply and multiply-accumulate to data register instruction.
665
086134ec
BS		 666 * bfin-dis.c: (c_uimm4s4d, c_imm5d, c_imm7d, c_imm16d, c_uimm16s4d,
667 c_imm32, c_huimm32e): Define.
668 (constant_formats): Add flags for printing decimal, leading spaces, and
669 exact symbols.
670 (comment, parallel): Add global flags in all disassembly.
671 (fmtconst): Take advantage of new flags, and print default in hex.
672 (fmtconst_val): Likewise.
673 (decode_macfunc): Be consistant with spaces, tabs, comments,
674 capitalization in disassembly, fix minor coding style issues.
675 (reg_names, amod0, amod1, amod0amod2, aligndir, get_allreg): Likewise.
676 (decode_ProgCtrl_0, decode_PushPopMultiple_0, decode_CCflag_0,
677 decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0,
678 decode_REGMV_0, decode_ALU2op_0, decode_PTR2op_0, decode_LOGI2op_0,
679 decode_COMP3op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
680 decode_LDSTpmod_0, decode_dagMODim_0, decode_dagMODik_0,
681 decode_dspLDST_0, decode_LDST_0, decode_LDSTiiFP_0, decode_LDSTii_0,
682 decode_LoopSetup_0, decode_LDIMMhalf_0, decode_CALLa_0,
683 decode_LDSTidxI_0, decode_linkage_0, decode_dsp32alu_0,
684 decode_dsp32shift_0, decode_dsp32shiftimm_0, decode_pseudodbg_assert_0,
685 _print_insn_bfin, print_insn_bfin): Likewise.
686
58c85be7
RW		 6872008-03-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
688
689 * aclocal.m4: Regenerate.
690 * configure: Likewise.
691 * Makefile.in: Likewise.
692
50e7d84b
AM		 6932008-03-13 Alan Modra <amodra@bigpond.net.au>
694
695 * Makefile.am: Run "make dep-am".
696 * Makefile.in: Regenerate.
697 * configure: Regenerate.
698
de866fcc
AM		 6992008-03-07 Alan Modra <amodra@bigpond.net.au>
700
701 * ppc-opc.c (powerpc_opcodes): Order and format.
702
28dbc079
L		 7032008-03-01 H.J. Lu <hongjiu.lu@intel.com>
704
705 * i386-opc.tbl: Allow 16-bit near indirect branches for x86-64.
706 * i386-tbl.h: Regenerated.
707
849830bd
L		 7082008-02-23 H.J. Lu <hongjiu.lu@intel.com>
709
710 * i386-opc.tbl: Disallow 16-bit near indirect branches for
711 x86-64.
712 * i386-tbl.h: Regenerated.
713
743ddb6b
JB		 7142008-02-21 Jan Beulich <jbeulich@novell.com>
715
716 * i386-opc.tbl: Allow Dword for far indirect call. Allow Dword
717 and Fword for far indirect jmp. Allow Reg16 and Word for near
718 indirect jmp on x86-64. Disallow Fword for lcall.
719 * i386-tbl.h: Re-generate.
720
796d5313
NC		 7212008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
722
723 * cr16-opc.c (cr16_num_optab): Defined
724
65da13b5
L		 7252008-02-16 H.J. Lu <hongjiu.lu@intel.com>
726
727 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_INOUTPORTREG.
728 * i386-init.h: Regenerated.
729
0e336180
NC		 7302008-02-14 Nick Clifton <nickc@redhat.com>
731
732 PR binutils/5524
733 * configure.in (SHARED_LIBADD): Select the correct host specific
734 file extension for shared libraries.
735 * configure: Regenerate.
736
b7240065
JB		 7372008-02-13 Jan Beulich <jbeulich@novell.com>
738
739 * i386-opc.h (RegFlat): New.
740 * i386-reg.tbl (flat): Add.
741 * i386-tbl.h: Re-generate.
742
34b772a6
JB		 7432008-02-13 Jan Beulich <jbeulich@novell.com>
744
745 * i386-dis.c (a_mode): New.
746 (cond_jump_mode): Adjust.
747 (Ma): Change to a_mode.
748 (intel_operand_size): Handle a_mode.
749 * i386-opc.tbl: Allow Dword and Qword for bound.
750 * i386-tbl.h: Re-generate.
751
a60de03c
JB		 7522008-02-13 Jan Beulich <jbeulich@novell.com>
753
754 * i386-gen.c (process_i386_registers): Process new fields.
755 * i386-opc.h (reg_entry): Shrink reg_flags and reg_num to
756 unsigned char. Add dw2_regnum and Dw2Inval.
757 * i386-reg.tbl: Provide initializers for dw2_regnum. Add pseudo
758 register names.
759 * i386-tbl.h: Re-generate.
760
f03fe4c1
L		 7612008-02-11 H.J. Lu <hongjiu.lu@intel.com>
762
4b6bc8eb 763 * i386-gen.c (cpu_flag_init): Add CPU_XSAVE_FLAGS.
f03fe4c1
L		 764 * i386-init.h: Updated.
765
475a2301
L		 7662008-02-11 H.J. Lu <hongjiu.lu@intel.com>
767
768 * i386-gen.c (cpu_flags): Add CpuXsave.
769
770 * i386-opc.h (CpuXsave): New.
4b6bc8eb 771 (CpuLM): Updated.
475a2301
L		 772 (i386_cpu_flags): Add cpuxsave.
773
774 * i386-dis.c (MOD_0FAE_REG_4): New.
775 (RM_0F01_REG_2): Likewise.
776 (MOD_0FAE_REG_5): Updated.
777 (RM_0F01_REG_3): Likewise.
778 (reg_table): Use MOD_0FAE_REG_4.
779 (mod_table): Use RM_0F01_REG_2. Add MOD_0FAE_REG_4. Updated
780 for xrstor.
781 (rm_table): Add RM_0F01_REG_2.
782
783 * i386-opc.tbl: Add xsave, xrstor, xgetbv and xsetbv.
784 * i386-init.h: Regenerated.
785 * i386-tbl.h: Likewise.
786
595785c6 7872008-02-11 Jan Beulich <jbeulich@novell.com>
041179fc 788
595785c6
JB		 789 * i386-opc.tbl: Remove Disp32S from CpuNo64 opcodes. Remove
790 Disp16 from Cpu64 non-jump opcodes (including loop and j?cxz).
791 * i386-tbl.h: Re-generate.
792
bb8541b9
L		 7932008-02-04 H.J. Lu <hongjiu.lu@intel.com>
794
795 PR 5715
796 * configure: Regenerated.
797
57b592a3
AN		 7982008-02-04 Adam Nemet <anemet@caviumnetworks.com>
799
800 * mips-dis.c: Update copyright.
801 (mips_arch_choices): Add Octeon.
802 * mips-opc.c: Update copyright.
803 (IOCT): New macro.
804 (mips_builtin_opcodes): Add Octeon instruction synciobdma.
805
930bb4cf
AM		 8062008-01-29 Alan Modra <amodra@bigpond.net.au>
807
808 * ppc-opc.c: Support optional L form mtmsr.
809
82c18208
L		 8102008-01-24 H.J. Lu <hongjiu.lu@intel.com>
811
812 * i386-dis.c (OP_E_extended): Handle r12 like rsp.
813
599121aa
L		 8142008-01-23 H.J. Lu <hongjiu.lu@intel.com>
815
816 * i386-gen.c (cpu_flag_init): Add CpuLM to CPU_GENERIC64_FLAGS.
817 * i386-init.h: Regenerated.
818
80098f51
TG		 8192008-01-23 Tristan Gingold <gingold@adacore.com>
820
821 * ia64-dis.c (print_insn_ia64): Display symbolic name of ar.fcr,
822 ar.eflag, ar.csd, ar.ssd, ar.cflg, ar.fsr, ar.fir and ar.fdr.
823
115c7c25
L		 8242008-01-22 H.J. Lu <hongjiu.lu@intel.com>
825
826 * i386-gen.c (cpu_flag_init): Remove CpuMMX2.
827 (cpu_flags): Likewise.
828
829 * i386-opc.h (CpuMMX2): Removed.
830 (CpuSSE): Updated.
831
832 * i386-opc.tbl: Replace CpuMMX2 with CpuSSE|Cpu3dnowA.
833 * i386-init.h: Regenerated.
834 * i386-tbl.h: Likewise.
835
6305a203
L		 8362008-01-22 H.J. Lu <hongjiu.lu@intel.com>
837
838 * i386-gen.c (cpu_flag_init): Add CPU_VMX_FLAGS and
839 CPU_SMX_FLAGS.
840 * i386-init.h: Regenerated.
841
fd07a1c8
L		 8422008-01-15 H.J. Lu <hongjiu.lu@intel.com>
843
844 * i386-opc.tbl: Use Qword on movddup.
845 * i386-tbl.h: Regenerated.
846
321fd21e
L		 8472008-01-15 H.J. Lu <hongjiu.lu@intel.com>
848
849 * i386-opc.tbl: Put back 16bit movsx/movzx for AT&T syntax.
850 * i386-tbl.h: Regenerated.
851
4ee52178
L		 8522008-01-15 H.J. Lu <hongjiu.lu@intel.com>
853
854 * i386-dis.c (Mx): New.
855 (PREFIX_0FC3): Likewise.
856 (PREFIX_0FC7_REG_6): Updated.
857 (dis386_twobyte): Use PREFIX_0FC3.
858 (prefix_table): Add PREFIX_0FC3. Use Mq on movntq and movntsd.
859 Use Mx on movntps, movntpd, movntdq and movntdqa. Use Md on
860 movntss.
861
5c07affc
L		 8622008-01-14 H.J. Lu <hongjiu.lu@intel.com>
863
864 * i386-gen.c (opcode_modifiers): Add IntelSyntax.
865 (operand_types): Add Mem.
866
867 * i386-opc.h (IntelSyntax): New.
868 * i386-opc.h (Mem): New.
869 (Byte): Updated.
870 (Opcode_Modifier_Max): Updated.
871 (i386_opcode_modifier): Add intelsyntax.
872 (i386_operand_type): Add mem.
873
874 * i386-opc.tbl: Remove Reg16 from movnti. Add sizes to more
875 instructions.
876
877 * i386-reg.tbl: Add size for accumulator.
878
879 * i386-init.h: Regenerated.
880 * i386-tbl.h: Likewise.
881
0d6a2f58
L		 8822008-01-13 H.J. Lu <hongjiu.lu@intel.com>
883
884 * i386-opc.h (Byte): Fix a typo.
885
7d5e4556
L		 8862008-01-12 H.J. Lu <hongjiu.lu@intel.com>
887
888 PR gas/5534
889 * i386-gen.c (operand_type_init): Add Dword to
890 OPERAND_TYPE_ACC32. Add Qword to OPERAND_TYPE_ACC64.
891 (opcode_modifiers): Remove CheckSize, Byte, Word, Dword,
892 Qword and Xmmword.
893 (operand_types): Add Byte, Word, Dword, Fword, Qword, Tbyte,
894 Xmmword, Unspecified and Anysize.
895 (set_bitfield): Make Mmword an alias of Qword. Make Oword
896 an alias of Xmmword.
897
898 * i386-opc.h (CheckSize): Removed.
899 (Byte): Updated.
900 (Word): Likewise.
901 (Dword): Likewise.
902 (Qword): Likewise.
903 (Xmmword): Likewise.
904 (FWait): Updated.
905 (OTMax): Likewise.
906 (i386_opcode_modifier): Remove checksize, byte, word, dword,
907 qword and xmmword.
908 (Fword): New.
909 (TBYTE): Likewise.
910 (Unspecified): Likewise.
911 (Anysize): Likewise.
912 (i386_operand_type): Add byte, word, dword, fword, qword,
913 tbyte xmmword, unspecified and anysize.
914
915 * i386-opc.tbl: Updated to use Byte, Word, Dword, Fword, Qword,
916 Tbyte, Xmmword, Unspecified and Anysize.
917
918 * i386-reg.tbl: Add size for accumulator.
919
920 * i386-init.h: Regenerated.
921 * i386-tbl.h: Likewise.
922
b5b1fc4f
L		 9232008-01-10 H.J. Lu <hongjiu.lu@intel.com>
924
925 * i386-dis.c (REG_0F0E): Renamed to REG_0F0D.
926 (REG_0F18): Updated.
927 (reg_table): Updated.
928 (dis386_twobyte): Updated. Use "nopQ" on 0x19 to 0x1e.
929 (twobyte_has_modrm): Set 1 for 0x19 to 0x1e.
930
50e8458f
L		 9312008-01-08 H.J. Lu <hongjiu.lu@intel.com>
932
933 * i386-gen.c (set_bitfield): Use fail () on error.
934
3d4d5afa
L		 9352008-01-08 H.J. Lu <hongjiu.lu@intel.com>
936
937 * i386-gen.c (lineno): New.
938 (filename): Likewise.
939 (set_bitfield): Report filename and line numer on error.
940 (process_i386_opcodes): Set filename and update lineno.
941 (process_i386_registers): Likewise.
942
e1d4d893
L		 9432008-01-05 H.J. Lu <hongjiu.lu@intel.com>
944
945 * i386-gen.c (opcode_modifiers): Rename IntelMnemonic to
946 ATTSyntax.
947
948 * i386-opc.h (IntelMnemonic): Renamed to ..
949 (ATTSyntax): This
950 (Opcode_Modifier_Max): Updated.
951 (i386_opcode_modifier): Remove intelmnemonic. Add attsyntax
952 and intelsyntax.
953
8944f3c2 954 * i386-opc.tbl: Remove IntelMnemonic and update with ATTSyntax
e1d4d893
L		 955 on fsub, fubp, fsubr, fsubrp, div, fdivp, fdivr and fdivrp.
956 * i386-tbl.h: Regenerated.
957
6f143e4d
L		 9582008-01-04 H.J. Lu <hongjiu.lu@intel.com>
959
960 * i386-gen.c: Update copyright to 2008.
961 * i386-opc.h: Likewise.
962 * i386-opc.tbl: Likewise.
963
964 * i386-init.h: Regenerated.
965 * i386-tbl.h: Likewise.
966
c6add537
L		 9672008-01-04 H.J. Lu <hongjiu.lu@intel.com>
968
969 * i386-opc.tbl: Add NoRex64 to extractps, movmskpd, movmskps,
970 pextrb, pextrw, pinsrb, pinsrw and pmovmskb.
971 * i386-tbl.h: Regenerated.
972
3629bb00
L		 9732008-01-03 H.J. Lu <hongjiu.lu@intel.com>
974
975 * i386-gen.c (cpu_flag_init): Remove CpuSSE4_1_Or_5 and
976 CpuSSE4_2_Or_ABM.
977 (cpu_flags): Likewise.
978
979 * i386-opc.h (CpuSSE4_1_Or_5): Removed.
980 (CpuSSE4_2_Or_ABM): Likewise.
981 (CpuLM): Updated.
982 (i386_cpu_flags): Remove cpusse4_1_or_5 and cpusse4_2_or_abm.
983
984 * i386-opc.tbl: Replace CpuSSE4_1_Or_5, CpuSSE4_2_Or_ABM and
985 Cpu686|CpuPadLock with CpuSSE4_1|CpuSSE5, CpuABM|CpuSSE4_2
986 and CpuPadLock, respectively.
987 * i386-init.h: Regenerated.
988 * i386-tbl.h: Likewise.
989
24995bd6
L		 9902008-01-03 H.J. Lu <hongjiu.lu@intel.com>
991
992 * i386-gen.c (opcode_modifiers): Remove No_xSuf.
993
994 * i386-opc.h (No_xSuf): Removed.
995 (CheckSize): Updated.
996
997 * i386-tbl.h: Regenerated.
998
e0329a22
L		 9992008-01-02 H.J. Lu <hongjiu.lu@intel.com>
1000
1001 * i386-gen.c (cpu_flag_init): Add CpuSSE4_2_Or_ABM to
1002 CPU_AMDFAM10_FLAGS, CPU_SSE4_2_FLAGS, CpuABM and
1003 CPU_SSE5_FLAGS.
1004 (cpu_flags): Add CpuSSE4_2_Or_ABM.
1005
1006 * i386-opc.h (CpuSSE4_2_Or_ABM): New.
1007 (CpuLM): Updated.
1008 (i386_cpu_flags): Add cpusse4_2_or_abm.
1009
1010 * i386-opc.tbl: Use CpuSSE4_2_Or_ABM instead of
1011 CpuABM|CpuSSE4_2 on popcnt.
1012 * i386-init.h: Regenerated.
1013 * i386-tbl.h: Likewise.
1014
f2a9c676
L		 10152008-01-02 H.J. Lu <hongjiu.lu@intel.com>
1016
1017 * i386-opc.h: Update comments.
1018
d978b5be
L		 10192008-01-02 H.J. Lu <hongjiu.lu@intel.com>
1020
1021 * i386-gen.c (opcode_modifiers): Use Qword instead of QWord.
1022 * i386-opc.h: Likewise.
1023 * i386-opc.tbl: Likewise.
1024
582d5edd
L		 10252008-01-02 H.J. Lu <hongjiu.lu@intel.com>
1026
1027 PR gas/5534
1028 * i386-gen.c (opcode_modifiers): Add No_xSuf, CheckSize,
1029 Byte, Word, Dword, QWord and Xmmword.
1030
1031 * i386-opc.h (No_xSuf): New.
1032 (CheckSize): Likewise.
1033 (Byte): Likewise.
1034 (Word): Likewise.
1035 (Dword): Likewise.
1036 (QWord): Likewise.
1037 (Xmmword): Likewise.
1038 (FWait): Updated.
1039 (i386_opcode_modifier): Add No_xSuf, CheckSize, Byte, Word,
1040 Dword, QWord and Xmmword.
1041
1042 * i386-opc.tbl: Add CheckSize|QWord to movq if IgnoreSize is
1043 used.
1044 * i386-tbl.h: Regenerated.
1045
3fe15143
MK		 10462008-01-02 Mark Kettenis <kettenis@gnu.org>
1047
1048 * m88k-dis.c (instructions): Fix fcvt.* instructions.
1049 From Miod Vallat.
1050
6c7ac64e 1051For older changes see ChangeLog-2007
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RH		 1052\f
1053Local Variables:
2f6d2f85
NC		 1054mode: change-log
1055left-margin: 8
1056fill-column: 74
252b5132
RH		 1057version-control: never
1058End:
GDB Binutils - Deliverables
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