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[deliverable/binutils-gdb.git] / opcodes / ChangeLog
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12012-05-17 Alan Modra <amodra@gmail.com>
2
3 * ppc_dis.c: Don't include elf/ppc.h.
4
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52012-05-16 Meador Inge <meadori@codesourcery.com>
6
7 * arm-dis.c (arm_opcodes): Don't disassemble STMFD/LDMIA sp!, {reg}
8 to PUSH/POP {reg}.
9
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102012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
11 Stephane Carrez <stcarrez@nerim.fr>
12
13 * configure.in: Add S12X and XGATE co-processor support to m68hc11
14 target.
15 * disassemble.c: Likewise.
16 * configure: Regenerate.
17 * m68hc11-dis.c: Make objdump output more consistent, use hex
18 instead of decimal and use 0x prefix for hex.
19 * m68hc11-opc.c: Add S12X and XGATE opcodes.
20
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212012-05-14 James Lemke <jwlemke@codesourcery.com>
22
23 * ppc-dis.c (get_powerpc_dialect): Use is_ppc_vle.
24 (PPC_OPCD_SEGS, VLE_OPCD_SEGS): New defines.
25 (vle_opcd_indices): New array.
26 (lookup_vle): New function.
27 (disassemble_init_powerpc): Revise for second (VLE) opcode table.
28 (print_insn_powerpc): Likewise.
29 * ppc-opc.c: Likewise.
30
312012-05-14 Catherine Moore <clm@codesourcery.com>
32 Maciej W. Rozycki <macro@codesourcery.com>
33 Rhonda Wittels <rhonda@codesourcery.com>
34 Nathan Froyd <froydnj@codesourcery.com>
35
36 * ppc-opc.c (insert_arx, extract_arx): New functions.
37 (insert_ary, extract_ary): New functions.
38 (insert_li20, extract_li20): New functions.
39 (insert_rx, extract_rx): New functions.
40 (insert_ry, extract_ry): New functions.
41 (insert_sci8, extract_sci8): New functions.
42 (insert_sci8n, extract_sci8n): New functions.
43 (insert_sd4h, extract_sd4h): New functions.
44 (insert_sd4w, extract_sd4w): New functions.
45 (insert_vlesi, extract_vlesi): New functions.
46 (insert_vlensi, extract_vlensi): New functions.
47 (insert_vleui, extract_vleui): New functions.
48 (insert_vleil, extract_vleil): New functions.
49 (BI_MASK, BB_MASK, BT): Use PPC_OPERAND_CR_BIT.
50 (BI16, BI32, BO32, B8): New.
51 (B15, B24, CRD32, CRS): New.
52 (CRD, OBF, BFA, CR, CRFS): Use PPC_OPERAND_CR_REG.
53 (DB, IMM20, RD, Rx, ARX, RY, RZ): New.
54 (ARY, SCLSCI8, SCLSCI8N, SE_SD, SE_SDH): New.
55 (SH6_MASK): Use PPC_OPSHIFT_INV.
56 (SI8, UI5, OIMM5, UI7, BO16): New.
57 (VLESIMM, VLENSIMM, VLEUIMM, VLEUIMML): New.
58 (XT6, XA6, XB6, XB6S, XC6): Use PPC_OPSHIFT_INV.
59 (ALLOW8_SPRG): New.
60 (insert_sprg, extract_sprg): Check ALLOW8_SPRG.
61 (OPVUP, OPVUP_MASK OPVUP): New
62 (BD8, BD8_MASK, BD8IO, BD8IO_MASK): New.
63 (EBD8IO, EBD8IO1_MASK, EBD8IO2_MASK, EBD8IO3_MASK): New.
64 (BD15, BD15_MASK, EBD15, EBD15_MASK, EBD15BI, EBD15BI_MASK): New.
65 (BD24,BD24_MASK, C_LK, C_LK_MASK, C, C_MASK): New.
66 (IA16, IA16_MASK, I16A, I16A_MASK, I16L, I16L_MASK): New.
67 (IM7, IM7_MASK, LI20, LI20_MASK, SCI8, SCI8_MASK): New.
68 (SCI8BF, SCI8BF_MASK, SD4, SD4_MASK): New.
69 (SE_IM5, SE_IM5_MASK): New.
70 (SE_R, SE_R_MASK, SE_RR, SE_RR_MASK): New.
71 (EX, EX_MASK, BO16F, BO16T, BO32F, BO32T): New.
72 (BO32DNZ, BO32DZ): New.
73 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW): Include PPC_OPCODE_VLE.
74 (PPCVLE): New.
75 (powerpc_opcodes): Add new VLE instructions. Update existing
76 instruction to include PPCVLE if supported.
77 * ppc-dis.c (ppc_opts): Add vle entry.
78 (get_powerpc_dialect): New function.
79 (powerpc_init_dialect): VLE support.
80 (print_insn_big_powerpc): Call get_powerpc_dialect.
81 (print_insn_little_powerpc): Likewise.
82 (operand_value_powerpc): Handle negative shift counts.
83 (print_insn_powerpc): Handle 2-byte instruction lengths.
84
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852012-05-11 Daniel Richard G. <skunk@iskunk.org>
86
87 PR binutils/14028
88 * configure.in: Invoke ACX_HEADER_STRING.
89 * configure: Regenerate.
90 * config.in: Regenerate.
91 * sysdep.h: If STRINGS_WITH_STRING is defined then include both
92 string.h and strings.h.
93
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942012-05-11 Nick Clifton <nickc@redhat.com>
95
96 PR binutils/14006
97 * arm-dis.c (print_insn): Fix detection of instruction mode in
98 files containing multiple executable sections.
99
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1002012-05-03 Sean Keys <skeys@ipdatasys.com>
101
102 * Makefile.in, configure: regenerate
103 * disassemble.c (disassembler): Recognize ARCH_XGATE.
104 * xgate-dis.c (read_memory, print_insn, print_insn_xgate):
105 New functions.
106 * configure.in: Recognize xgate.
107 * xgate-dis.c, xgate-opc.c: New files for support of xgate
108 * Makefile.am (CFILES, ALL_MACHINES): New files for disassembly
109 and opcode generation for xgate.
110
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1112012-04-30 DJ Delorie <dj@redhat.com>
112
113 * rx-decode.opc (MOV): Do not sign-extend immediates which are
114 already the maximum bit size.
115 * rx-decode.c: Regenerate.
116
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1172012-04-27 David S. Miller <davem@davemloft.net>
118
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119 * sparc-dis.c (v9a_asr_reg_names): Add 'cfr'.
120 * sparc-opc.c (sparc_opcodes): Add rd/wr cases for %cfr.
121
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122 * sparc-opc.c (sparc_opcodes): Add 'wr X, %pause' and 'pause'.
123 * sparc-dis.c (v9a_asr_reg_names): Add 'pause'.
124
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125 * sparc-opc.c (CBCOND): New define.
126 (CBCOND_XCC): Likewise.
127 (cbcond): New helper macro.
128 (sparc_opcodes): Add compare-and-branch instructions.
129
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130 * sparc-dis.c (print_insn_sparc): Handle ')'.
131 * sparc-opc.c (sparc_opcodes): Add crypto instructions.
132
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133 * sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
134 into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
135
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1362012-04-12 David S. Miller <davem@davemloft.net>
137
138 * sparc-dis.c (X_DISP10): Define.
139 (print_insn_sparc): Handle '='.
140
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1412012-04-01 Mike Frysinger <vapier@gentoo.org>
142
143 * bfin-dis.c (fmtconst): Replace decimal handling with a single
144 sprintf call and the '*' field width.
145
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1462012-03-23 Maxim Kuvyrkov <maxim@codesourcery.com>
147
148 * mips-dis.c (mips_arch_choices): Add entry for Broadcom XLP.
149
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1502012-03-16 Alan Modra <amodra@gmail.com>
151
152 * ppc-dis.c (PPC_OPC_SEGS, PPC_OP_TO_SEG): Delete.
153 (powerpc_opcd_indices): Bump array size.
154 (disassemble_init_powerpc): Set powerpc_opcd_indices entries
155 corresponding to unused opcodes to following entry.
156 (lookup_powerpc): New function, extracted and optimised from..
157 (print_insn_powerpc): ..here.
158
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1592012-03-15 Alan Modra <amodra@gmail.com>
160 James Lemke <jwlemke@codesourcery.com>
161
162 * disassemble.c (disassemble_init_for_target): Handle ppc init.
163 * ppc-dis.c (private): New var.
164 (powerpc_init_dialect): Don't return calloc failure, instead use
165 private.
166 (PPC_OPCD_SEGS, PPC_OP_TO_SEG): Define.
167 (powerpc_opcd_indices): New array.
168 (disassemble_init_powerpc): New function.
169 (print_insn_big_powerpc): Don't init dialect here.
170 (print_insn_little_powerpc): Likewise.
171 (print_insn_powerpc): Start search using powerpc_opcd_indices.
172
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1732012-03-10 Edmar Wienskoski <edmar@freescale.com>
174
175 * ppc-dis.c (ppc_opts): Add entries for "e5500" and "e6500".
176 * ppc-opc.c (insert_ls, TMR, ESYNC, XSYNCLE_MASK): New.
177 (PPCVEC2, PPCTMR, E6500): New short names.
178 (powerpc_opcodes): Add vabsdub, vabsduh, vabsduw, dni, mvidsplt,
179 mviwsplt, icblq., mftmr, mttmr, dcblq., miso, lvexbx, lvexhx,
180 lvexwx, stvexbx, stvexhx, stvexwx, lvepx, lvepxl, stvepx, stvepxl,
181 lvtrx, lvtrxl, lvtlx, lvtlxl, stvfrx, stvfrxl, stvflx, stvflxl,
182 lvswx, lvswxl, stvswx, stvswxl, lvsm mnemonics. Accept LS, ESYNC
183 optional operands on sync instruction for E6500 target.
184
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1852012-03-08 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
186
187 * s390-opc.txt: Set instruction type of pku to SS_L2RDRD.
188
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1892012-02-27 Alan Modra <amodra@gmail.com>
190
191 * mt-dis.c: Regenerate.
192
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1932012-02-27 Alan Modra <amodra@gmail.com>
194
195 * v850-opc.c (extract_v8): Rearrange to make it obvious this
196 is the inverse of corresponding insert function.
197 (extract_d22, extract_u9, extract_r4): Likewise.
198 (extract_d9): Correct sign extension.
199 (extract_d16_15): Don't assume "long" is 32 bits, and don't
200 rely on implementation defined behaviour for shift right of
201 signed types.
202 (extract_d16_16, extract_d17_16, extract_i9): Likewise.
203 (extract_d23): Likewise, and correct mask.
204
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2052012-02-27 Alan Modra <amodra@gmail.com>
206
207 * crx-dis.c (print_arg): Mask constant to 32 bits.
208 * crx-opc.c (cst4_map): Use int array.
209
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2102012-02-27 Alan Modra <amodra@gmail.com>
211
212 * arc-dis.c (BITS): Don't use shifts to mask off bits.
213 (FIELDD): Sign extend with xor,sub.
214
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2152012-02-25 Walter Lee <walt@tilera.com>
216
217 * tilegx-opc.c: Handle TILEGX_OPC_LD4S_TLS and TILEGX_OPC_LD_TLS.
218 * tilepro-opc.c: Handle TILEPRO_OPC_LW_TLS and
219 TILEPRO_OPC_LW_TLS_SN.
220
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2212012-02-21 H.J. Lu <hongjiu.lu@intel.com>
222
223 * i386-opc.h (HLEPrefixNone): New.
224 (HLEPrefixLock): Likewise.
225 (HLEPrefixAny): Likewise.
226 (HLEPrefixRelease): Likewise.
227
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2282012-02-08 H.J. Lu <hongjiu.lu@intel.com>
229
230 * i386-dis.c (HLE_Fixup1): New.
231 (HLE_Fixup2): Likewise.
232 (HLE_Fixup3): Likewise.
233 (Ebh1): Likewise.
234 (Evh1): Likewise.
235 (Ebh2): Likewise.
236 (Evh2): Likewise.
237 (Ebh3): Likewise.
238 (Evh3): Likewise.
239 (MOD_C6_REG_7): Likewise.
240 (MOD_C7_REG_7): Likewise.
241 (RM_C6_REG_7): Likewise.
242 (RM_C7_REG_7): Likewise.
243 (XACQUIRE_PREFIX): Likewise.
244 (XRELEASE_PREFIX): Likewise.
245 (dis386): Use Ebh1/Evh1 on add, adc, and, btc, btr, bts,
246 cmpxchg, dec, inc, neg, not, or, sbb, sub, xor and xadd. Use
247 Ebh2/Evh2 on xchg. Use Ebh3/Evh3 on mov.
248 (reg_table): Use Ebh1/Evh1 on add, adc, and, dec, inc, neg,
249 not, or, sbb, sub and xor. Use Ebh3/Evh3 on mov. Use
250 MOD_C6_REG_7 and MOD_C7_REG_7.
251 (mod_table): Add MOD_C6_REG_7 and MOD_C7_REG_7.
252 (rm_table): Add RM_C6_REG_7 and RM_C7_REG_7. Add xend and
253 xtest.
254 (prefix_name): Handle XACQUIRE_PREFIX and XRELEASE_PREFIX.
255 (CMPXCHG8B_Fixup): Handle HLE prefix on cmpxchg8b.
256
257 * i386-gen.c (cpu_flag_init): Add CPU_HLE_FLAGS and
258 CPU_RTM_FLAGS.
259 (cpu_flags): Add CpuHLE and CpuRTM.
260 (opcode_modifiers): Add HLEPrefixOk.
261
262 * i386-opc.h (CpuHLE): New.
263 (CpuRTM): Likewise.
264 (HLEPrefixOk): Likewise.
265 (i386_cpu_flags): Add cpuhle and cpurtm.
266 (i386_opcode_modifier): Add hleprefixok.
267
268 * i386-opc.tbl: Add HLEPrefixOk=3 to mov. Add HLEPrefixOk to
269 add, adc, and, btc, btr, bts, cmpxchg, dec, inc, neg, not, or,
270 sbb, sub, xor and xadd. Add HLEPrefixOk=2 to xchg with memory
271 operand. Add xacquire, xrelease, xabort, xbegin, xend and
272 xtest.
273 * i386-init.h: Regenerated.
274 * i386-tbl.h: Likewise.
275
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2762012-01-24 DJ Delorie <dj@redhat.com>
277
278 * rl78-decode.opc (rl78_decode_opcode): Add NOT1.
279 * rl78-decode.c: Regenerate.
280
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2812012-01-17 James Murray <jsm@jsm-net.demon.co.uk>
282
283 PR binutils/10173
284 * cr16-dis.c (print_arg): Test symtab_size not num_symbols.
285
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2862012-01-17 Andreas Schwab <schwab@linux-m68k.org>
287
288 * m68k-opc.c (m68k_opcodes): Fix entries for pmove with BADx/BACx
289 register and move them after pmove with PSR/PCSR register.
290
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2912012-01-13 H.J. Lu <hongjiu.lu@intel.com>
292
293 * i386-dis.c (mod_table): Add vmfunc.
294
295 * i386-gen.c (cpu_flag_init): Add CPU_VMFUNC_FLAGS.
296 (cpu_flags): CpuVMFUNC.
297
298 * i386-opc.h (CpuVMFUNC): New.
299 (i386_cpu_flags): Add cpuvmfunc.
300
301 * i386-opc.tbl: Add vmfunc.
302 * i386-init.h: Regenerated.
303 * i386-tbl.h: Likewise.
5011093d 304
23e1d329 305For older changes see ChangeLog-2011
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306\f
307Local Variables:
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308mode: change-log
309left-margin: 8
310fill-column: 74
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311version-control: never
312End:
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