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Bi-endian patches for moxie
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
e202fa84
AG		 12012-09-13 Anthony Green <green@moxielogic.com>
2
3 * moxie-dis.c (print_insn_moxie): Handle bi-endian encodings.
4
00716ab1
AM		 52012-09-10 Matthias Klose <doko@ubuntu.com>
6
7 * config.in: Disable sanity check for kfreebsd.
8
6d2920c8
L		 92012-09-10 H.J. Lu <hongjiu.lu@intel.com>
10
11 * configure: Regenerated.
12
b3e14eda
L		 132012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
14
15 * ia64-asmtab.h (completer_index): Extend bitfield to full uint.
16 * ia64-gen.c: Promote completer index type to longlong.
17 (irf_operand): Add new register recognition.
18 (in_iclass_mov_x): Add an entry for the new mov_* instruction type.
19 (lookup_specifier): Add new resource recognition.
20 (insert_bit_table_ent): Relax abort condition according to the
21 changed completer index type.
22 (print_dis_table): Fix printf format for completer index.
23 * ia64-ic.tbl: Add a new instruction class.
24 * ia64-opc-i.c (ia64_opcodes_i): Define new I-instructions.
25 * ia64-opc-m.c (ia64_opcodes_m): Define new M-instructions.
26 * ia64-opc.h: Define short names for new operand types.
27 * ia64-raw.tbl: Add new RAW resource for DAHR register.
28 * ia64-waw.tbl: Add new WAW resource for DAHR register.
29 * ia64-asmtab.c: Regenerate.
30
382c72e9
PB		 312012-08-29 Peter Bergner <bergner@vnet.ibm.com>
32
33 * ppc-opc.c (VXASHB_MASK): New define.
34 (powerpc_opcodes) <vsldoi>: Use VXASHB_MASK.
35
fb048c26
PB		 362012-08-28 Peter Bergner <bergner@vnet.ibm.com>
37
38 * ppc-opc.c (UIMM4, UIMM3, UIMM2, VXVA_MASK, VXVB_MASK, VXVAVB_MASK,
39 VXVDVA_MASK, VXUIMM4_MASK, VXUIMM3_MASK, VXUIMM2_MASK): New defines.
40 (powerpc_opcodes) <vexptefp, vlogefp, vrefp, vrfim, vrfin, vrfip,
41 vrfiz, vrsqrtefp, vupkhpx, vupkhsb, vupkhsh, vupklpx, vupklsb,
42 vupklsh>: Use VXVA_MASK.
43 <vspltisb, vspltish, vspltisw>: Use VXVB_MASK.
44 <mfvscr>: Use VXVAVB_MASK.
45 <mtvscr>: Use VXVDVA_MASK.
46 <vspltb>: Use VXUIMM4_MASK.
47 <vsplth>: Use VXUIMM3_MASK.
48 <vspltw>: Use VXUIMM2_MASK.
49
3c9017d2
MGD		 502012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
51
52 * arm-dis.c (neon_opcodes): Add 2 operand sha instructions.
53
48adcd8e
MGD		 542012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
55
56 * arm-dis.c (neon_opcodes): Add SHA 3-operand instructions.
57
4f51b4bd
MGD		 582012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
59
60 * arm-dis.c (neon_opcodes): Handle VMULL.P64.
61
91ff7894
MGD		 622012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
63
64 * arm-dis.c (neon_opcodes): Add support for AES instructions.
65
c70a8987
MGD		 662012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
67
68 * arm-dis.c (coprocessor_opcodes): Add support for HP/DP
69 conversions.
70
30bdf752
MGD		 712012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
72
73 * arm-dis.c (coprocessor_opcodes): Add VRINT.
74 (neon_opcodes): Likewise.
75
7e8e6784
MGD		 762012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
77
78 * arm-dis.c (coprocessor_opcodes): Add support for new VCVT
79 variants.
80 (neon_opcodes): Likewise.
81
73924fbc
MGD		 822012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
83
84 * arm-dis.c (coprocessor_opcodes): Add VMAXNM/VMINNM.
85 (neon_opcodes): Likewise.
86
33399f07
MGD		 872012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
88
89 * arm-dis.c (coprocessor_opcodes): Add VSEL.
90 (print_insn_coprocessor): Add new %<>c bitfield format
91 specifier.
92
9eb6c0f1
MGD		 932012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
94
95 * arm-dis.c (arm_opcodes): Add LDRA/STRL instructions.
96 (thumb32_opcodes): Likewise.
97 (print_arm_insn): Add support for %<>T formatter.
98
8884b720
MGD		 992012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
100
101 * arm-dis.c (arm_opcodes): Add HLT.
102 (thumb_opcodes): Likewise.
103
b79f7053
MGD		 1042012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
105
106 * arm-dis.c (thumb32_opcodes): Add DCPS instruction.
107
53c4b28b
MGD		 1082012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
109
110 * arm-dis.c (arm_opcodes): Add SEVL.
111 (thumb_opcodes): Likewise.
112 (thumb32_opcodes): Likewise.
113
e797f7e0
MGD		 1142012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
115
116 * arm-dis.c (data_barrier_option): New function.
117 (print_insn_arm): Use data_barrier_option.
118 (print_insn_thumb32): Use data_barrier_option.
119
e2efe87d
MGD		 1202012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com
121
122 * arm-dis.c (COND_UNCOND): New constant.
123 (print_insn_coprocessor): Add support for %u format specifier.
124 (print_insn_neon): Likewise.
125
2c63854f
DM		 1262012-08-21 David S. Miller <davem@davemloft.net>
127
128 * sparc-opc.c (4-argument crypto instructions): Fix encoding using
129 F3F4 macro.
130
e67ed0e8
AM		 1312012-08-20 Edmar Wienskoski <edmar@freescale.com>
132
133 * ppc-opc.c (powerpc_opcodes): Changed opcode for vabsdub,
134 vabsduh, vabsduw, mviwsplt.
135
7b458c12
L		 1362012-08-17 Nagajyothi Eggone <nagajyothi.eggone@amd.com>
137
138 * i386-gen.c (cpu_flag_init): Add CPU_BTVER1_FLAGS and
139 CPU_BTVER2_FLAGS.
140
e67ed0e8 141 * i386-opc.h: Update CpuPRFCHW comment.
7b458c12
L		 142
143 * i386-opc.tbl: Enable prefetch instruction for CpuPRFCHW.
144 * i386-init.h: Regenerated.
145 * i386-tbl.h: Likewise.
146
eb80cb87
NC		 1472012-08-17 Nick Clifton <nickc@redhat.com>
148
149 * po/uk.po: New Ukranian translation.
150 * configure.in (ALL_LINGUAS): Add uk.
151 * configure: Regenerate.
152
8baf7b78
PB		 1532012-08-16 Peter Bergner <bergner@vnet.ibm.com>
154
155 * ppc-opc.c (powerpc_opcodes) <"lswx">: Use RAX for the second and
156 RBX for the third operand.
157 <"lswi">: Use RAX for second and NBI for the third operand.
158
3d557b4c
DD		 1592012-08-15 DJ Delorie <dj@redhat.com>
160
161 * rl78-decode.opc (rl78_decode_opcode): Merge %e and %[01]
162 operands, so that data addresses can be corrected when not
163 ES-overridden.
164 * rl78-decode.c: Regenerate.
165 * rl78-dis.c (print_insn_rl78): Make order of modifiers
166 irrelevent. When the 'e' specifier is used on an operand and no
167 ES prefix is provided, adjust address to make it absolute.
168
588925d0
PB		 1692012-08-15 Peter Bergner <bergner@vnet.ibm.com>
170
171 * ppc-opc.c <RSQ, RTQ>: Use PPC_OPERAND_GPR.
172
9f6a6cc0
PB		 1732012-08-15 Peter Bergner <bergner@vnet.ibm.com>
174
175 * ppc-opc.c <xnop, yield, mdoio, mdoom>: New extended mnemonics.
176
fc8c4fd1
MR		 1772012-08-14 Maciej W. Rozycki <macro@codesourcery.com>
178
179 * mips-dis.c (print_insn_args): Add GET_OP and GET_OP_S local
180 macros, use local variables for info struct member accesses,
181 update the type of the variable used to hold the instruction
182 word.
183 (print_insn_mips, print_mips16_insn_arg): Likewise.
184 (print_insn_mips16): Add GET_OP and GET_OP_S local macros, use
185 local variables for info struct member accesses.
186 (print_insn_micromips): Add GET_OP_S local macro.
187 (_print_insn_mips): Update the type of the variable used to hold
188 the instruction word.
189
a06ea964 1902012-08-13 Ian Bolton <ian.bolton@arm.com>
e67ed0e8
AM		 191 Laurent Desnogues <laurent.desnogues@arm.com>
192 Jim MacArthur <jim.macarthur@arm.com>
193 Marcus Shawcroft <marcus.shawcroft@arm.com>
194 Nigel Stephens <nigel.stephens@arm.com>
195 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
196 Richard Earnshaw <rearnsha@arm.com>
197 Sofiane Naci <sofiane.naci@arm.com>
198 Tejas Belagod <tejas.belagod@arm.com>
199 Yufeng Zhang <yufeng.zhang@arm.com>
a06ea964
NC		 200
201 * Makefile.am: Add AArch64.
202 * Makefile.in: Regenerate.
203 * aarch64-asm.c: New file.
204 * aarch64-asm.h: New file.
205 * aarch64-dis.c: New file.
206 * aarch64-dis.h: New file.
207 * aarch64-gen.c: New file.
208 * aarch64-opc.c: New file.
209 * aarch64-opc.h: New file.
210 * aarch64-tbl.h: New file.
211 * configure.in: Add AArch64.
212 * configure: Regenerate.
213 * disassemble.c: Add AArch64.
214 * aarch64-asm-2.c: New file (automatically generated).
215 * aarch64-dis-2.c: New file (automatically generated).
216 * aarch64-opc-2.c: New file (automatically generated).
217 * po/POTFILES.in: Regenerate.
218
35d0a169
MR		 2192012-08-13 Maciej W. Rozycki <macro@codesourcery.com>
220
221 * micromips-opc.c (micromips_opcodes): Update comment.
222 * mips-opc.c (mips_builtin_opcodes): Likewise. Mark coprocessor
223 instructions for IOCT as appropriate.
224 * mips-dis.c (print_insn_mips): Replace OPCODE_IS_MEMBER with
225 opcode_is_member.
226 * configure.in: Substitute NO_WMISSING_FIELD_INITIALIZERS with
227 the result of a check for the -Wno-missing-field-initializers
228 GCC option.
229 * Makefile.am (NO_WMISSING_FIELD_INITIALIZERS): New variable.
230 (mips-opc.lo): Pass $(NO_WMISSING_FIELD_INITIALIZERS) to
231 compilation.
232 (mips16-opc.lo): Likewise.
233 (micromips-opc.lo): Likewise.
234 * aclocal.m4: Regenerate.
235 * configure: Regenerate.
236 * Makefile.in: Regenerate.
237
5c5acbbd
L		 2382012-08-11 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
239
240 PR gas/14423
241 * i386-gen.c (cpu_flag_init): Add CpuFMA in CPU_BDVER2_FLAGS.
242 * i386-init.h: Regenerated.
243
3c892704
NC		 2442012-08-09 Nick Clifton <nickc@redhat.com>
245
246 * po/vi.po: Updated Vietnamese translation.
247
d7189fa5
RM		 2482012-08-07 Roland McGrath <mcgrathr@google.com>
249
250 * i386-dis.c (reg_table): Fill out REG_0F0D table with
251 AMD-reserved cases as "prefetch".
252 (MOD_0F18_REG_4, MOD_0F18_REG_5): New enum constants.
253 (MOD_0F18_REG_6, MOD_0F18_REG_7): Likewise.
254 (reg_table): Use those under REG_0F18.
255 (mod_table): Add those cases as "nop/reserved".
256
4c692bc7
JB		 2572012-08-07 Jan Beulich <jbeulich@suse.com>
258
259 * i386-opc.tbl: Remove "FIXME" comments from SVME instructions.
260
de882298
RM		 2612012-08-06 Roland McGrath <mcgrathr@google.com>
262
263 * i386-dis.c (print_insn): Print spaces between multiple excess
264 prefixes. Return actual number of excess prefixes consumed,
265 not always one.
266
267 * i386-dis.c (OP_REG): Ignore REX_B for segment register cases.
268
7bb15c6f
RM		 2692012-08-06 Roland McGrath <mcgrathr@google.com>
270 Victor Khimenko <khim@google.com>
271 H.J. Lu <hongjiu.lu@intel.com>
272
273 * i386-dis.c (OP_sI): In b_T_mode and v_mode, REX_W trumps DFLAG.
274 (putop): For 'T', 'U', and 'V', treat REX_W like DFLAG.
275 (intel_operand_size): For stack_v_mode, treat REX_W like DFLAG.
276 (OP_E_register): Likewise.
277 (OP_REG): For low 8 whole registers, treat REX_W like DFLAG.
278
3843081d
JBG		 2792012-08-02 Jan-Benedict Glaw <jbglaw@lug-owl.de>
280
281 * configure.in: Formatting.
282 * configure: Regenerate.
283
48891606
AM		 2842012-08-01 Alan Modra <amodra@gmail.com>
285
286 * h8300-dis.c: Fix printf arg warnings.
287 * i960-dis.c: Likewise.
288 * mips-dis.c: Likewise.
289 * pdp11-dis.c: Likewise.
290 * sh-dis.c: Likewise.
291 * v850-dis.c: Likewise.
292 * configure.in: Formatting.
293 * configure: Regenerate.
294 * rl78-decode.c: Regenerate.
295 * po/POTFILES.in: Regenerate.
296
03f66e8a 2972012-07-31 Chao-Ying Fu <fu@mips.com>
e67ed0e8
AM		 298 Catherine Moore <clm@codesourcery.com>
299 Maciej W. Rozycki <macro@codesourcery.com>
03f66e8a
MR		 300
301 * micromips-opc.c (WR_a, RD_a, MOD_a): New macros.
302 (DSP_VOLA): Likewise.
303 (D32, D33): Likewise.
304 (micromips_opcodes): Add DSP ASE instructions.
48891606 305 * mips-dis.c (print_insn_micromips) <'2', '3'>: New cases.
03f66e8a
MR		 306 <'4', '5', '6', '7', '8', '0', '^', '@'>: Likewise.
307
94948e64
JB		 3082012-07-31 Jan Beulich <jbeulich@suse.com>
309
310 * i386-opc.tbl (vmovntdqa): Move up into 256-bit integer AVX2
311 instruction group. Mark as requiring AVX2.
312 * i386-tbl.h: Re-generate.
313
a6dc81d2
NC		 3142012-07-30 Nick Clifton <nickc@redhat.com>
315
316 * po/opcodes.pot: Updated template.
317 * po/es.po: Updated Spanish translation.
318 * po/fi.po: Updated Finnish translation.
319
c4dd807e
MF		 3202012-07-27 Mike Frysinger <vapier@gentoo.org>
321
322 * configure.in (BFD_VERSION): Run bfd/configure --version and
323 parse the output of that.
324 * configure: Regenerate.
325
03edbe3b
JL		 3262012-07-25 James Lemke <jwlemke@codesourcery.com>
327
328 * ppc-opc.c (powerpc_opcodes): Add/remove PPCVLE for some 32-bit insns.
329
63d08c68
NC		 3302012-07-24 Stephan McCamant <smcc@cs.berkeley.edu>
331 Dr David Alan Gilbert <dave@treblig.org>
d908c8af
NC		 332
333 PR binutils/13135
334 * arm-dis.c: Add necessary casts for printing integer values.
335 Use %s when printing string values.
336 * hppa-dis.c: Likewise.
337 * m68k-dis.c: Likewise.
338 * microblaze-dis.c: Likewise.
339 * mips-dis.c: Likewise.
340 * sparc-dis.c: Likewise.
341
ff688e1f
L		 3422012-07-19 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
343
344 PR binutils/14355
345 * i386-dis.c (VEX_LEN_0FXOP_08_CC): New.
346 (VEX_LEN_0FXOP_08_CD): Likewise.
347 (VEX_LEN_0FXOP_08_CE): Likewise.
348 (VEX_LEN_0FXOP_08_CF): Likewise.
349 (VEX_LEN_0FXOP_08_EC): Likewise.
350 (VEX_LEN_0FXOP_08_ED): Likewise.
351 (VEX_LEN_0FXOP_08_EE): Likewise.
352 (VEX_LEN_0FXOP_08_EF): Likewise.
353 (xop_table): Fix entries for vpcomb, vpcomw, vpcomd, vpcomq,
354 vpcomub, vpcomuw, vpcomud, vpcomuq.
355 (vex_len_table): Add entries for VEX_LEN_0FXOP_08_CC,
356 VEX_LEN_0FXOP_08_CD, VEX_LEN_0FXOP_08_CE, VEX_LEN_0FXOP_08_CF,
357 VEX_LEN_0FXOP_08_EC, VEX_LEN_0FXOP_08_ED, VEX_LEN_0FXOP_08_EE,
358 VEX_LEN_0FXOP_08_EF.
359
e2e1fcde
L		 3602012-07-16 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
361
362 * i386-dis.c (PREFIX_0F38F6): New.
363 (prefix_table): Add adcx, adox instructions.
364 (three_byte_table): Use PREFIX_0F38F6.
365 (mod_table): Add rdseed instruction.
366 * i386-gen.c (cpu_flag_init): Add CpuADX, CpuRDSEED, CpuPRFCHW.
367 (cpu_flags): Likewise.
368 * i386-opc.h: Add CpuADX, CpuRDSEED, CpuPRFCHW.
369 (i386_cpu_flags): Add fields cpurdseed, cpuadx, cpuprfchw.
370 * i386-opc.tbl: Add instrcutions adcx, adox, rdseed. Extend
371 prefetchw.
372 * i386-tbl.h: Regenerate.
373 * i386-init.h: Likewise.
374
8b99bf0b
TS		 3752012-07-05 Thomas Schwinge <thomas@codesourcery.com>
376
f4263ca2 377 * mips-dis.c: Remove gratuitous newline.
8b99bf0b 378
416cf80a
SK		 3792012-07-05 Sean Keys <skeys@ipdatasys.com>
380
381 * xgate-dis.c: Removed an IF statement that will
e67ed0e8
AM		 382 always be false due to overlapping operand masks.
383 * xgate-opc.c: Corrected 'com' opcode entry and
384 fixed spacing.
416cf80a 385
9fa0f14a
RM		 3862012-07-02 Roland McGrath <mcgrathr@google.com>
387
388 * i386-opc.tbl: Add RepPrefixOk to nop.
389 * i386-tbl.h: Regenerate.
390
4c6a93d3
NC		 3912012-06-28 Nick Clifton <nickc@redhat.com>
392
393 * po/vi.po: Updated Vietnamese translation.
394
29c048b6
RM		 3952012-06-22 Roland McGrath <mcgrathr@google.com>
396
fe13e45b
RM		 397 * i386-opc.tbl: Add RepPrefixOk to ret.
398 * i386-tbl.h: Regenerate.
399
29c048b6
RM		 400 * i386-opc.h (RepPrefixOk): New enum constant.
401 (i386_opcode_modifier): New bitfield 'repprefixok'.
402 * i386-gen.c (opcode_modifiers): Add RepPrefixOk.
403 * i386-opc.tbl: Add RepPrefixOk to bsf, bsr, and to all
404 instructions that have IsString.
405 * i386-tbl.h: Regenerate.
406
c7a8dbf9
AS		 4072012-06-11 Andreas Schwab <schwab@linux-m68k.org>
408
409 * ppc-opc.c (lvsl, lvebx, isellt, icbt, ldepx, lwepx, lvsr, lvehx)
410 (iselgt, lvewx, iseleq, isel, dcbst, dcbstep, dcbfl, dcbf, lbepx)
411 (lvx, dcbfep, dcbtstls, stvebx, dcbtstlse, stdepx, stwepx, dcbtls)
412 (stvehx, dcbtlse, stvewx, stbepx, icblc, stvx, dcbtstt, dcbtst)
413 (dcbtst, dcbtstep, dcbtt, dcbt, dcbt, lhepx, eciwx, dcbtep)
414 (dcread, lxvdsx, lvxl, dcblc, sthepx, ecowx, dcbi, dcread, icbtls)
415 (stvxl, lxsdx, lfdepx, stxsdx, stfdepx, dcba, dcbal, lxvw4x)
416 (tlbivax, lfdpx, lxvd2x, tlbsrx., stxvw4x, tlbsx, tlbsx., stfdpx)
417 (stfqx, stxvd2x, icbi, icbiep, icread, dcbzep): Change RA to RA0.
418
94caa966
AM		 4192012-05-19 Alan Modra <amodra@gmail.com>
420
421 * ppc-dis.c: Don't include elf32-ppc.h, do include elf/ppc.h.
422 (get_powerpc_dialect): Detect VLE sections from ELF sh_flags.
423
5eb3690e
AM		 4242012-05-18 Alan Modra <amodra@gmail.com>
425
71fe7bab
AM		 426 * ia64-opc.c: Remove #include "ansidecl.h".
427 * z8kgen.c: Include sysdep.h first.
428
5eb3690e
AM		 429 * arc-dis.c: Include sysdep.h first, remove some redundant includes.
430 * bfin-dis.c: Likewise.
431 * i860-dis.c: Likewise.
432 * ia64-dis.c: Likewise.
433 * ia64-gen.c: Likewise.
434 * m68hc11-dis.c: Likewise.
435 * mmix-dis.c: Likewise.
436 * msp430-dis.c: Likewise.
437 * or32-dis.c: Likewise.
438 * rl78-dis.c: Likewise.
439 * rx-dis.c: Likewise.
440 * tic4x-dis.c: Likewise.
441 * tilegx-opc.c: Likewise.
442 * tilepro-opc.c: Likewise.
443 * rx-decode.c: Regenerate.
444
a4ebc835
AM		 4452012-05-17 James Lemke <jwlemke@codesourcery.com>
446
447 * ppc-opc.c (powerpc_macros): Add entries for e_extlwi to e_clrlslwi.
448
98c76446
AM		 4492012-05-17 James Lemke <jwlemke@codesourcery.com>
450
451 * ppc-opc.c (extract_sprg): Use ALLOW8_SPRG to include VLE.
452
df7b86aa
NC		 4532012-05-17 Daniel Richard G. <skunk@iskunk.org>
454 Nick Clifton <nickc@redhat.com>
455
456 PR 14072
457 * configure.in: Add check that sysdep.h has been included before
458 any system header files.
459 * configure: Regenerate.
460 * config.in: Regenerate.
461 * sysdep.h: Generate an error if included before config.h.
462 * alpha-opc.c: Include sysdep.h before any other header file.
463 * alpha-dis.c: Likewise.
464 * avr-dis.c: Likewise.
465 * cgen-opc.c: Likewise.
466 * cr16-dis.c: Likewise.
467 * cris-dis.c: Likewise.
468 * crx-dis.c: Likewise.
469 * d10v-dis.c: Likewise.
470 * d10v-opc.c: Likewise.
471 * d30v-dis.c: Likewise.
472 * d30v-opc.c: Likewise.
473 * h8500-dis.c: Likewise.
474 * i370-dis.c: Likewise.
475 * i370-opc.c: Likewise.
476 * m10200-dis.c: Likewise.
477 * m10300-dis.c: Likewise.
478 * micromips-opc.c: Likewise.
479 * mips-opc.c: Likewise.
480 * mips61-opc.c: Likewise.
481 * moxie-dis.c: Likewise.
482 * or32-opc.c: Likewise.
483 * pj-dis.c: Likewise.
484 * ppc-dis.c: Likewise.
485 * ppc-opc.c: Likewise.
486 * s390-dis.c: Likewise.
487 * sh-dis.c: Likewise.
488 * sh64-dis.c: Likewise.
489 * sparc-dis.c: Likewise.
490 * sparc-opc.c: Likewise.
491 * spu-dis.c: Likewise.
492 * tic30-dis.c: Likewise.
493 * tic54x-dis.c: Likewise.
494 * tic80-dis.c: Likewise.
495 * tic80-opc.c: Likewise.
496 * tilegx-dis.c: Likewise.
497 * tilepro-dis.c: Likewise.
498 * v850-dis.c: Likewise.
499 * v850-opc.c: Likewise.
500 * vax-dis.c: Likewise.
501 * w65-dis.c: Likewise.
502 * xgate-dis.c: Likewise.
503 * xtensa-dis.c: Likewise.
504 * rl78-decode.opc: Likewise.
505 * rl78-decode.c: Regenerate.
506 * rx-decode.opc: Likewise.
507 * rx-decode.c: Regenerate.
508
e1dad58d
AM		 5092012-05-17 Alan Modra <amodra@gmail.com>
510
511 * ppc_dis.c: Don't include elf/ppc.h.
512
101af531
NC		 5132012-05-16 Meador Inge <meadori@codesourcery.com>
514
515 * arm-dis.c (arm_opcodes): Don't disassemble STMFD/LDMIA sp!, {reg}
516 to PUSH/POP {reg}.
517
6927f982
NC		 5182012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
519 Stephane Carrez <stcarrez@nerim.fr>
520
521 * configure.in: Add S12X and XGATE co-processor support to m68hc11
522 target.
523 * disassemble.c: Likewise.
524 * configure: Regenerate.
525 * m68hc11-dis.c: Make objdump output more consistent, use hex
526 instead of decimal and use 0x prefix for hex.
527 * m68hc11-opc.c: Add S12X and XGATE opcodes.
528
b9c361e0
JL		 5292012-05-14 James Lemke <jwlemke@codesourcery.com>
530
531 * ppc-dis.c (get_powerpc_dialect): Use is_ppc_vle.
532 (PPC_OPCD_SEGS, VLE_OPCD_SEGS): New defines.
533 (vle_opcd_indices): New array.
534 (lookup_vle): New function.
535 (disassemble_init_powerpc): Revise for second (VLE) opcode table.
536 (print_insn_powerpc): Likewise.
537 * ppc-opc.c: Likewise.
538
5392012-05-14 Catherine Moore <clm@codesourcery.com>
540 Maciej W. Rozycki <macro@codesourcery.com>
541 Rhonda Wittels <rhonda@codesourcery.com>
542 Nathan Froyd <froydnj@codesourcery.com>
543
544 * ppc-opc.c (insert_arx, extract_arx): New functions.
545 (insert_ary, extract_ary): New functions.
546 (insert_li20, extract_li20): New functions.
547 (insert_rx, extract_rx): New functions.
548 (insert_ry, extract_ry): New functions.
549 (insert_sci8, extract_sci8): New functions.
550 (insert_sci8n, extract_sci8n): New functions.
551 (insert_sd4h, extract_sd4h): New functions.
552 (insert_sd4w, extract_sd4w): New functions.
553 (insert_vlesi, extract_vlesi): New functions.
554 (insert_vlensi, extract_vlensi): New functions.
555 (insert_vleui, extract_vleui): New functions.
556 (insert_vleil, extract_vleil): New functions.
557 (BI_MASK, BB_MASK, BT): Use PPC_OPERAND_CR_BIT.
558 (BI16, BI32, BO32, B8): New.
559 (B15, B24, CRD32, CRS): New.
560 (CRD, OBF, BFA, CR, CRFS): Use PPC_OPERAND_CR_REG.
561 (DB, IMM20, RD, Rx, ARX, RY, RZ): New.
562 (ARY, SCLSCI8, SCLSCI8N, SE_SD, SE_SDH): New.
563 (SH6_MASK): Use PPC_OPSHIFT_INV.
564 (SI8, UI5, OIMM5, UI7, BO16): New.
565 (VLESIMM, VLENSIMM, VLEUIMM, VLEUIMML): New.
566 (XT6, XA6, XB6, XB6S, XC6): Use PPC_OPSHIFT_INV.
567 (ALLOW8_SPRG): New.
568 (insert_sprg, extract_sprg): Check ALLOW8_SPRG.
569 (OPVUP, OPVUP_MASK OPVUP): New
570 (BD8, BD8_MASK, BD8IO, BD8IO_MASK): New.
571 (EBD8IO, EBD8IO1_MASK, EBD8IO2_MASK, EBD8IO3_MASK): New.
572 (BD15, BD15_MASK, EBD15, EBD15_MASK, EBD15BI, EBD15BI_MASK): New.
573 (BD24,BD24_MASK, C_LK, C_LK_MASK, C, C_MASK): New.
574 (IA16, IA16_MASK, I16A, I16A_MASK, I16L, I16L_MASK): New.
575 (IM7, IM7_MASK, LI20, LI20_MASK, SCI8, SCI8_MASK): New.
576 (SCI8BF, SCI8BF_MASK, SD4, SD4_MASK): New.
577 (SE_IM5, SE_IM5_MASK): New.
578 (SE_R, SE_R_MASK, SE_RR, SE_RR_MASK): New.
579 (EX, EX_MASK, BO16F, BO16T, BO32F, BO32T): New.
580 (BO32DNZ, BO32DZ): New.
581 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW): Include PPC_OPCODE_VLE.
582 (PPCVLE): New.
583 (powerpc_opcodes): Add new VLE instructions. Update existing
584 instruction to include PPCVLE if supported.
585 * ppc-dis.c (ppc_opts): Add vle entry.
586 (get_powerpc_dialect): New function.
587 (powerpc_init_dialect): VLE support.
588 (print_insn_big_powerpc): Call get_powerpc_dialect.
589 (print_insn_little_powerpc): Likewise.
590 (operand_value_powerpc): Handle negative shift counts.
591 (print_insn_powerpc): Handle 2-byte instruction lengths.
592
208a4923
NC		 5932012-05-11 Daniel Richard G. <skunk@iskunk.org>
594
595 PR binutils/14028
596 * configure.in: Invoke ACX_HEADER_STRING.
597 * configure: Regenerate.
598 * config.in: Regenerate.
599 * sysdep.h: If STRINGS_WITH_STRING is defined then include both
600 string.h and strings.h.
601
6750a3a7
NC		 6022012-05-11 Nick Clifton <nickc@redhat.com>
603
604 PR binutils/14006
605 * arm-dis.c (print_insn): Fix detection of instruction mode in
606 files containing multiple executable sections.
607
f6c1a2d5
NC		 6082012-05-03 Sean Keys <skeys@ipdatasys.com>
609
610 * Makefile.in, configure: regenerate
611 * disassemble.c (disassembler): Recognize ARCH_XGATE.
612 * xgate-dis.c (read_memory, print_insn, print_insn_xgate):
613 New functions.
614 * configure.in: Recognize xgate.
615 * xgate-dis.c, xgate-opc.c: New files for support of xgate
616 * Makefile.am (CFILES, ALL_MACHINES): New files for disassembly
617 and opcode generation for xgate.
618
78e98aab
DD		 6192012-04-30 DJ Delorie <dj@redhat.com>
620
621 * rx-decode.opc (MOV): Do not sign-extend immediates which are
622 already the maximum bit size.
623 * rx-decode.c: Regenerate.
624
ec668d69
DM		 6252012-04-27 David S. Miller <davem@davemloft.net>
626
2e52845b
DM		 627 * sparc-dis.c (v9a_asr_reg_names): Add 'cfr'.
628 * sparc-opc.c (sparc_opcodes): Add rd/wr cases for %cfr.
629
58004e23
DM		 630 * sparc-opc.c (sparc_opcodes): Add 'wr X, %pause' and 'pause'.
631 * sparc-dis.c (v9a_asr_reg_names): Add 'pause'.
632
698544e1
DM		 633 * sparc-opc.c (CBCOND): New define.
634 (CBCOND_XCC): Likewise.
635 (cbcond): New helper macro.
636 (sparc_opcodes): Add compare-and-branch instructions.
637
6cda1326
DM		 638 * sparc-dis.c (print_insn_sparc): Handle ')'.
639 * sparc-opc.c (sparc_opcodes): Add crypto instructions.
640
ec668d69
DM		 641 * sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
642 into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
643
2615994e
DM		 6442012-04-12 David S. Miller <davem@davemloft.net>
645
646 * sparc-dis.c (X_DISP10): Define.
647 (print_insn_sparc): Handle '='.
648
5de10af0
MF		 6492012-04-01 Mike Frysinger <vapier@gentoo.org>
650
651 * bfin-dis.c (fmtconst): Replace decimal handling with a single
652 sprintf call and the '*' field width.
653
55a36193
MK		 6542012-03-23 Maxim Kuvyrkov <maxim@codesourcery.com>
655
656 * mips-dis.c (mips_arch_choices): Add entry for Broadcom XLP.
657
d6688282
AM		 6582012-03-16 Alan Modra <amodra@gmail.com>
659
660 * ppc-dis.c (PPC_OPC_SEGS, PPC_OP_TO_SEG): Delete.
661 (powerpc_opcd_indices): Bump array size.
662 (disassemble_init_powerpc): Set powerpc_opcd_indices entries
663 corresponding to unused opcodes to following entry.
664 (lookup_powerpc): New function, extracted and optimised from..
665 (print_insn_powerpc): ..here.
666
b240011a
AM		 6672012-03-15 Alan Modra <amodra@gmail.com>
668 James Lemke <jwlemke@codesourcery.com>
669
670 * disassemble.c (disassemble_init_for_target): Handle ppc init.
671 * ppc-dis.c (private): New var.
672 (powerpc_init_dialect): Don't return calloc failure, instead use
673 private.
674 (PPC_OPCD_SEGS, PPC_OP_TO_SEG): Define.
675 (powerpc_opcd_indices): New array.
676 (disassemble_init_powerpc): New function.
677 (print_insn_big_powerpc): Don't init dialect here.
678 (print_insn_little_powerpc): Likewise.
679 (print_insn_powerpc): Start search using powerpc_opcd_indices.
680
aea77599
AM		 6812012-03-10 Edmar Wienskoski <edmar@freescale.com>
682
683 * ppc-dis.c (ppc_opts): Add entries for "e5500" and "e6500".
684 * ppc-opc.c (insert_ls, TMR, ESYNC, XSYNCLE_MASK): New.
685 (PPCVEC2, PPCTMR, E6500): New short names.
686 (powerpc_opcodes): Add vabsdub, vabsduh, vabsduw, dni, mvidsplt,
687 mviwsplt, icblq., mftmr, mttmr, dcblq., miso, lvexbx, lvexhx,
688 lvexwx, stvexbx, stvexhx, stvexwx, lvepx, lvepxl, stvepx, stvepxl,
689 lvtrx, lvtrxl, lvtlx, lvtlxl, stvfrx, stvfrxl, stvflx, stvflxl,
690 lvswx, lvswxl, stvswx, stvswxl, lvsm mnemonics. Accept LS, ESYNC
691 optional operands on sync instruction for E6500 target.
692
5333187a
AK		 6932012-03-08 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
694
695 * s390-opc.txt: Set instruction type of pku to SS_L2RDRD.
696
a597d2d3
AM		 6972012-02-27 Alan Modra <amodra@gmail.com>
698
699 * mt-dis.c: Regenerate.
700
3f26eb3a
AM		 7012012-02-27 Alan Modra <amodra@gmail.com>
702
703 * v850-opc.c (extract_v8): Rearrange to make it obvious this
704 is the inverse of corresponding insert function.
705 (extract_d22, extract_u9, extract_r4): Likewise.
706 (extract_d9): Correct sign extension.
707 (extract_d16_15): Don't assume "long" is 32 bits, and don't
708 rely on implementation defined behaviour for shift right of
709 signed types.
710 (extract_d16_16, extract_d17_16, extract_i9): Likewise.
711 (extract_d23): Likewise, and correct mask.
712
1f42f8b3
AM		 7132012-02-27 Alan Modra <amodra@gmail.com>
714
715 * crx-dis.c (print_arg): Mask constant to 32 bits.
716 * crx-opc.c (cst4_map): Use int array.
717
cdb06235
AM		 7182012-02-27 Alan Modra <amodra@gmail.com>
719
720 * arc-dis.c (BITS): Don't use shifts to mask off bits.
721 (FIELDD): Sign extend with xor,sub.
722
6f7be959
WL		 7232012-02-25 Walter Lee <walt@tilera.com>
724
725 * tilegx-opc.c: Handle TILEGX_OPC_LD4S_TLS and TILEGX_OPC_LD_TLS.
726 * tilepro-opc.c: Handle TILEPRO_OPC_LW_TLS and
727 TILEPRO_OPC_LW_TLS_SN.
728
82c2def5
L		 7292012-02-21 H.J. Lu <hongjiu.lu@intel.com>
730
731 * i386-opc.h (HLEPrefixNone): New.
732 (HLEPrefixLock): Likewise.
733 (HLEPrefixAny): Likewise.
734 (HLEPrefixRelease): Likewise.
735
42164a71
L		 7362012-02-08 H.J. Lu <hongjiu.lu@intel.com>
737
738 * i386-dis.c (HLE_Fixup1): New.
739 (HLE_Fixup2): Likewise.
740 (HLE_Fixup3): Likewise.
741 (Ebh1): Likewise.
742 (Evh1): Likewise.
743 (Ebh2): Likewise.
744 (Evh2): Likewise.
745 (Ebh3): Likewise.
746 (Evh3): Likewise.
747 (MOD_C6_REG_7): Likewise.
748 (MOD_C7_REG_7): Likewise.
749 (RM_C6_REG_7): Likewise.
750 (RM_C7_REG_7): Likewise.
751 (XACQUIRE_PREFIX): Likewise.
752 (XRELEASE_PREFIX): Likewise.
753 (dis386): Use Ebh1/Evh1 on add, adc, and, btc, btr, bts,
754 cmpxchg, dec, inc, neg, not, or, sbb, sub, xor and xadd. Use
755 Ebh2/Evh2 on xchg. Use Ebh3/Evh3 on mov.
756 (reg_table): Use Ebh1/Evh1 on add, adc, and, dec, inc, neg,
757 not, or, sbb, sub and xor. Use Ebh3/Evh3 on mov. Use
758 MOD_C6_REG_7 and MOD_C7_REG_7.
759 (mod_table): Add MOD_C6_REG_7 and MOD_C7_REG_7.
760 (rm_table): Add RM_C6_REG_7 and RM_C7_REG_7. Add xend and
761 xtest.
762 (prefix_name): Handle XACQUIRE_PREFIX and XRELEASE_PREFIX.
763 (CMPXCHG8B_Fixup): Handle HLE prefix on cmpxchg8b.
764
765 * i386-gen.c (cpu_flag_init): Add CPU_HLE_FLAGS and
766 CPU_RTM_FLAGS.
767 (cpu_flags): Add CpuHLE and CpuRTM.
768 (opcode_modifiers): Add HLEPrefixOk.
769
770 * i386-opc.h (CpuHLE): New.
771 (CpuRTM): Likewise.
772 (HLEPrefixOk): Likewise.
773 (i386_cpu_flags): Add cpuhle and cpurtm.
774 (i386_opcode_modifier): Add hleprefixok.
775
776 * i386-opc.tbl: Add HLEPrefixOk=3 to mov. Add HLEPrefixOk to
777 add, adc, and, btc, btr, bts, cmpxchg, dec, inc, neg, not, or,
778 sbb, sub, xor and xadd. Add HLEPrefixOk=2 to xchg with memory
779 operand. Add xacquire, xrelease, xabort, xbegin, xend and
780 xtest.
781 * i386-init.h: Regenerated.
782 * i386-tbl.h: Likewise.
783
21abe33a
DD		 7842012-01-24 DJ Delorie <dj@redhat.com>
785
786 * rl78-decode.opc (rl78_decode_opcode): Add NOT1.
787 * rl78-decode.c: Regenerate.
788
e20cc039
AM		 7892012-01-17 James Murray <jsm@jsm-net.demon.co.uk>
790
791 PR binutils/10173
792 * cr16-dis.c (print_arg): Test symtab_size not num_symbols.
793
e143d25c
AS		 7942012-01-17 Andreas Schwab <schwab@linux-m68k.org>
795
796 * m68k-opc.c (m68k_opcodes): Fix entries for pmove with BADx/BACx
797 register and move them after pmove with PSR/PCSR register.
798
8729a6f6
L		 7992012-01-13 H.J. Lu <hongjiu.lu@intel.com>
800
801 * i386-dis.c (mod_table): Add vmfunc.
802
803 * i386-gen.c (cpu_flag_init): Add CPU_VMFUNC_FLAGS.
804 (cpu_flags): CpuVMFUNC.
805
806 * i386-opc.h (CpuVMFUNC): New.
807 (i386_cpu_flags): Add cpuvmfunc.
808
809 * i386-opc.tbl: Add vmfunc.
810 * i386-init.h: Regenerated.
811 * i386-tbl.h: Likewise.
5011093d 812
23e1d329 813For older changes see ChangeLog-2011
252b5132
RH		 814\f
815Local Variables:
2f6d2f85
NC		 816mode: change-log
817left-margin: 8
818fill-column: 74
252b5132
RH		 819version-control: never
820End:
GDB Binutils - Deliverables
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