[deliverable/binutils-gdb.git] / opcodes / ChangeLog

2008-04-10  Andreas Krebbel  <krebbel1@de.ibm.com>

	* s390-dis.c (init_disasm): Evaluate disassembler_options.
	(print_s390_disassembler_options): New function.
	* disassemble.c (disassembler_usage): Invoke
	print_s390_disassembler_options.

2008-04-10  Andreas Krebbel  <krebbel1@de.ibm.com>

	* s390-mkopc.c (insertExpandedMnemonic): Expand string sizes
	of local variables used for mnemonic parsing: prefix, suffix and
	number.

2008-04-10  Andreas Krebbel  <krebbel1@de.ibm.com>

	* s390-mkopc.c (s390_cond_ext_format): Add back the mnemonic
	extensions for conditional jumps (o, p, m, nz, z, nm, np, no).
	(s390_crb_extensions): New extensions table.
	(insertExpandedMnemonic): Handle '$' tag.
	* s390-opc.txt: Remove conditional jump variants which can now
	be expanded automatically.
	Replace '*' tag with '$' in the compare and branch instructions.

2008-04-07  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (PREFIX_VEX_38XX): Add a tab.
	(PREFIX_VEX_3AXX): Likewis.

2008-04-07  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.tbl: Remove 4 extra blank lines.

2008-04-04  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (cpu_flag_init): Replace CPU_CLMUL_FLAGS/CpuCLMUL
	with CPU_PCLMUL_FLAGS/CpuPCLMUL.
	(cpu_flags): Replace CpuCLMUL with CpuPCLMUL.
	* i386-opc.tbl: Likewise.

	* i386-opc.h (CpuCLMUL): Renamed to ...
	(CpuPCLMUL): This.
	(CpuFMA): Updated.
	(i386_cpu_flags): Replace cpuclmul with cpupclmul.

	* i386-init.h: Regenerated.

2008-04-03  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (OP_E_register): New.
	(OP_E_memory): Likewise.
	(OP_VEX): Likewise.
	(OP_EX_Vex): Likewise.
	(OP_EX_VexW): Likewise.
	(OP_XMM_Vex): Likewise.
	(OP_XMM_VexW): Likewise.
	(OP_REG_VexI4): Likewise.
	(PCLMUL_Fixup): Likewise.
	(VEXI4_Fixup): Likewise.
	(VZERO_Fixup): Likewise.
	(VCMP_Fixup): Likewise.
	(VPERMIL2_Fixup): Likewise.
	(rex_original): Likewise.
	(rex_ignored): Likewise.
	(Mxmm): Likewise.
	(XMM): Likewise.
	(EXxmm): Likewise.
	(EXxmmq): Likewise.
	(EXymmq): Likewise.
	(Vex): Likewise.
	(Vex128): Likewise.
	(Vex256): Likewise.
	(VexI4): Likewise.
	(EXdVex): Likewise.
	(EXqVex): Likewise.
	(EXVexW): Likewise.
	(EXdVexW): Likewise.
	(EXqVexW): Likewise.
	(XMVex): Likewise.
	(XMVexW): Likewise.
	(XMVexI4): Likewise.
	(PCLMUL): Likewise.
	(VZERO): Likewise.
	(VCMP): Likewise.
	(VPERMIL2): Likewise.
	(xmm_mode): Likewise.
	(xmmq_mode): Likewise.
	(ymmq_mode): Likewise.
	(vex_mode): Likewise.
	(vex128_mode): Likewise.
	(vex256_mode): Likewise.
	(USE_VEX_C4_TABLE): Likewise.
	(USE_VEX_C5_TABLE): Likewise.
	(USE_VEX_LEN_TABLE): Likewise.
	(VEX_C4_TABLE): Likewise.
	(VEX_C5_TABLE): Likewise.
	(VEX_LEN_TABLE): Likewise.
	(REG_VEX_XX): Likewise.
	(MOD_VEX_XXX): Likewise.
	(PREFIX_0F38DB..PREFIX_0F38DF): Likewise.
	(PREFIX_0F3A44): Likewise.
	(PREFIX_0F3ADF): Likewise.
	(PREFIX_VEX_XXX): Likewise.
	(VEX_OF): Likewise.
	(VEX_OF38): Likewise.
	(VEX_OF3A): Likewise.
	(VEX_LEN_XXX): Likewise.
	(vex): Likewise.
	(need_vex): Likewise.
	(need_vex_reg): Likewise.
	(vex_i4_done): Likewise.
	(vex_table): Likewise.
	(vex_len_table): Likewise.
	(OP_REG_VexI4): Likewise.
	(vex_cmp_op): Likewise.
	(pclmul_op): Likewise.
	(vpermil2_op): Likewise.
	(m_mode): Updated.
	(es_reg): Likewise.
	(PREFIX_0F38F0): Likewise.
	(PREFIX_0F3A60): Likewise.
	(reg_table): Add REG_VEX_71...REG_VEX_73 and REG_VEX_AE.
	(prefix_table): Add PREFIX_0F38DB..PREFIX_0F38DF, PREFIX_0F3ADF
	and PREFIX_VEX_XXX entries.
	(x86_64_table): Use VEX_C4_TABLE and VEX_C5_TABLE.
	(three_byte_table): Use PREFIX_0F38DB..PREFIX_0F38DF and
	PREFIX_0F3ADF.
	(mod_table): Use VEX_C4_TABLE, VEX_C5_TABLE and VEX_LEN_TABLE.
	Add MOD_VEX_XXX entries.
	(ckprefix): Initialize rex_original and rex_ignored.  Store the
	REX byte in rex_original.
	(get_valid_dis386): Handle the implicit prefix in VEX prefix
	bytes and USE_VEX_LEN_TABLE/USE_VEX_C4_TABLE/USE_VEX_C5_TABLE.
	(print_insn): Set need_vex/need_vex_reg/vex_i4_done to 0 before
	calling get_valid_dis386.  Use rex_original and rex_ignored when
	printing out REX.
	(putop): Handle "XY".
	(intel_operand_size): Handle VEX, xmm_mode, xmmq_mode and
	ymmq_mode.
	(OP_E_extended): Updated to use OP_E_register and
	OP_E_memory.
	(OP_XMM): Handle VEX.
	(OP_EX): Likewise.
	(XMM_Fixup): Likewise.
	(CMP_Fixup): Use ARRAY_SIZE.

	* i386-gen.c (cpu_flag_init): Add CpuAES, CPU_CLMUL_FLAGS,
	CPU_FMA_FLAGS and CPU_AVX_FLAGS.
	(operand_type_init): Add OPERAND_TYPE_REGYMM and
	OPERAND_TYPE_VEX_IMM4.
	(cpu_flags): Add CpuAVX, CpuAES, CpuCLMUL and CpuFMA.
	(opcode_modifiers): Add Implicit1stXmm0, Vex, Vex256, VexNDD,
	VexNDS, VexW0, VexW1, Vex0F, Vex0F38, Vex0F3A, Vex3Sources,
	VexImmExt and SSE2AVX.
	(operand_types): Add RegYMM, Ymmword and Vex_Imm4.

	* i386-opc.h (CpuAVX): New.
	(CpuAES): Likewise.
	(CpuCLMUL): Likewise.
	(CpuFMA): Likewise.
	(Vex): Likewise.
	(Vex256): Likewise.
	(VexNDS): Likewise.
	(VexNDD): Likewise.
	(VexW0): Likewise.
	(VexW1): Likewise.
	(Vex0F): Likewise.
	(Vex0F38): Likewise.
	(Vex0F3A): Likewise.
	(Vex3Sources): Likewise.
	(VexImmExt): Likewise.
	(SSE2AVX): Likewise.
	(RegYMM): Likewise.
	(Ymmword): Likewise.
	(Vex_Imm4): Likewise.
	(Implicit1stXmm0): Likewise.
	(CpuXsave): Updated.
	(CpuLM): Likewise.
	(ByteOkIntel): Likewise.
	(OldGcc): Likewise.
	(Control): Likewise.
	(Unspecified): Likewise.
	(OTMax): Likewise.
	(i386_cpu_flags): Add cpuavx, cpuaes, cpuclmul and cpufma.
	(i386_opcode_modifier): Add implicit1stxmm0, vex, vex256,
	vexnds, vexndd, vexw0, vexw1, vex0f, vex0f38, vex0f3a,
	vex3sources, veximmext and sse2avx.
	(i386_operand_type): Add regymm, ymmword and vex_imm4.

	* i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions.

	* i386-reg.tbl: Add AVX registers, ymm0..ymm15.

	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2008-03-26  Bernd Schmidt  <bernd.schmidt@analog.com>

	From  Robin Getz  <robin.getz@analog.com>
	* bfin-dis.c (bu32): Typedef.
	(enum const_forms_t): Add c_uimm32 and c_huimm32.
	(constant_formats[]): Add uimm32 and huimm16.
	(fmtconst_val): New.
	(uimm32): Define.
	(huimm32): Define.
	(imm16_val): Define.
	(luimm16_val): Define.
	(struct saved_state): Define.
	(GREG, DPREG, DREG, PREG, SPREG, FPREG, IREG, MREG, BREG, LREG,
	A0XREG, A0WREG, A1XREG, A1WREG,CCREG, LC0REG, LT0REG, LB0REG,
	LC1REG, LT1REG, LB1REG, RETSREG, PCREG): Define.
	(get_allreg): New.
	(decode_LDIMMhalf_0): Print out the whole register value.

	From Jie Zhang  <jie.zhang@analog.com>
	* bfin-dis.c (decode_dsp32mac_0): Decode (IU) option for
	multiply and multiply-accumulate to data register instruction.

	* bfin-dis.c: (c_uimm4s4d, c_imm5d, c_imm7d, c_imm16d, c_uimm16s4d,
	c_imm32, c_huimm32e): Define.
	(constant_formats): Add flags for printing decimal, leading spaces, and
	exact symbols.
	(comment, parallel): Add global flags in all disassembly.
	(fmtconst): Take advantage of new flags, and print default in hex.
	(fmtconst_val): Likewise.
	(decode_macfunc): Be consistant with spaces, tabs, comments,
	capitalization in disassembly, fix minor coding style issues.
	(reg_names, amod0, amod1, amod0amod2, aligndir, get_allreg): Likewise.
	(decode_ProgCtrl_0, decode_PushPopMultiple_0, decode_CCflag_0,
	decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0,
	decode_REGMV_0, decode_ALU2op_0, decode_PTR2op_0, decode_LOGI2op_0,
	decode_COMP3op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
	decode_LDSTpmod_0, decode_dagMODim_0, decode_dagMODik_0,
	decode_dspLDST_0, decode_LDST_0, decode_LDSTiiFP_0, decode_LDSTii_0,
	decode_LoopSetup_0, decode_LDIMMhalf_0, decode_CALLa_0,
	decode_LDSTidxI_0, decode_linkage_0, decode_dsp32alu_0,
	decode_dsp32shift_0, decode_dsp32shiftimm_0, decode_pseudodbg_assert_0,
	_print_insn_bfin, print_insn_bfin): Likewise.

2008-03-17  Ralf Wildenhues  <Ralf.Wildenhues@gmx.de>

	* aclocal.m4: Regenerate.
	* configure: Likewise.
	* Makefile.in: Likewise.

2008-03-13  Alan Modra  <amodra@bigpond.net.au>

	* Makefile.am: Run "make dep-am".
	* Makefile.in: Regenerate.
	* configure: Regenerate.

2008-03-07  Alan Modra  <amodra@bigpond.net.au>

	* ppc-opc.c (powerpc_opcodes): Order and format.

2008-03-01  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.tbl: Allow 16-bit near indirect branches for x86-64.
	* i386-tbl.h: Regenerated.

2008-02-23  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.tbl: Disallow 16-bit near indirect branches for
	x86-64.
	* i386-tbl.h: Regenerated.

2008-02-21  Jan Beulich  <jbeulich@novell.com>

	* i386-opc.tbl: Allow Dword for far indirect call. Allow Dword
	and Fword for far indirect jmp. Allow Reg16 and Word for near
	indirect jmp on x86-64. Disallow Fword for lcall.
	* i386-tbl.h: Re-generate.

2008-02-18  M R Swami Reddy <MR.Swami.Reddy@nsc.com>

	* cr16-opc.c  (cr16_num_optab): Defined

2008-02-16  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c  (operand_type_init): Add OPERAND_TYPE_INOUTPORTREG.
	* i386-init.h: Regenerated.

2008-02-14  Nick Clifton  <nickc@redhat.com>

	PR binutils/5524
	* configure.in (SHARED_LIBADD): Select the correct host specific
	file extension for shared libraries.
	* configure: Regenerate.

2008-02-13  Jan Beulich  <jbeulich@novell.com>

	* i386-opc.h (RegFlat): New.
	* i386-reg.tbl (flat): Add.
	* i386-tbl.h: Re-generate.

2008-02-13  Jan Beulich  <jbeulich@novell.com>

	* i386-dis.c (a_mode): New.
	(cond_jump_mode): Adjust.
	(Ma): Change to a_mode.
	(intel_operand_size): Handle a_mode.
	* i386-opc.tbl: Allow Dword and Qword for bound.
	* i386-tbl.h: Re-generate.

2008-02-13  Jan Beulich  <jbeulich@novell.com>

	* i386-gen.c (process_i386_registers): Process new fields.
	* i386-opc.h (reg_entry): Shrink reg_flags and reg_num to
	unsigned char. Add dw2_regnum and Dw2Inval.
	* i386-reg.tbl: Provide initializers for dw2_regnum. Add pseudo
	register names.
	* i386-tbl.h: Re-generate.

2008-02-11  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (cpu_flag_init): Add CPU_XSAVE_FLAGS.
	* i386-init.h: Updated.

2008-02-11  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (cpu_flags): Add CpuXsave.

	* i386-opc.h (CpuXsave): New.
	(CpuLM): Updated.
	(i386_cpu_flags): Add cpuxsave.

	* i386-dis.c (MOD_0FAE_REG_4): New.
	(RM_0F01_REG_2): Likewise.
	(MOD_0FAE_REG_5): Updated.
	(RM_0F01_REG_3): Likewise.
	(reg_table): Use MOD_0FAE_REG_4.
	(mod_table): Use RM_0F01_REG_2.  Add MOD_0FAE_REG_4.  Updated
	for xrstor.
	(rm_table): Add RM_0F01_REG_2.

	* i386-opc.tbl: Add xsave, xrstor, xgetbv and xsetbv.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2008-02-11  Jan Beulich  <jbeulich@novell.com>

	* i386-opc.tbl: Remove Disp32S from CpuNo64 opcodes. Remove
	Disp16 from Cpu64 non-jump opcodes (including loop and j?cxz).
	* i386-tbl.h: Re-generate.

2008-02-04  H.J. Lu  <hongjiu.lu@intel.com>

	PR 5715
	* configure: Regenerated.

2008-02-04  Adam Nemet  <anemet@caviumnetworks.com>

	* mips-dis.c: Update copyright.
	(mips_arch_choices): Add Octeon.
	* mips-opc.c: Update copyright.
	(IOCT): New macro.
	(mips_builtin_opcodes): Add Octeon instruction synciobdma.

2008-01-29  Alan Modra  <amodra@bigpond.net.au>

	* ppc-opc.c: Support optional L form mtmsr.

2008-01-24  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (OP_E_extended): Handle r12 like rsp.

2008-01-23  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (cpu_flag_init): Add CpuLM to CPU_GENERIC64_FLAGS.
	* i386-init.h: Regenerated.

2008-01-23  Tristan Gingold  <gingold@adacore.com>

	* ia64-dis.c (print_insn_ia64): Display symbolic name of ar.fcr,
	ar.eflag, ar.csd, ar.ssd, ar.cflg, ar.fsr, ar.fir and ar.fdr.

2008-01-22  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (cpu_flag_init): Remove CpuMMX2.
	(cpu_flags): Likewise.

	* i386-opc.h (CpuMMX2): Removed.
	(CpuSSE): Updated.

	* i386-opc.tbl: Replace CpuMMX2 with CpuSSE|Cpu3dnowA.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2008-01-22  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (cpu_flag_init): Add CPU_VMX_FLAGS and
	CPU_SMX_FLAGS.
	* i386-init.h: Regenerated.

2008-01-15  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.tbl: Use Qword on movddup.
	* i386-tbl.h: Regenerated.

2008-01-15  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.tbl: Put back 16bit movsx/movzx for AT&T syntax.
	* i386-tbl.h: Regenerated.

2008-01-15  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (Mx): New.
	(PREFIX_0FC3): Likewise.
	(PREFIX_0FC7_REG_6): Updated.
	(dis386_twobyte): Use PREFIX_0FC3.
	(prefix_table): Add PREFIX_0FC3.  Use Mq on movntq and movntsd.
	Use Mx on movntps, movntpd, movntdq and movntdqa.  Use Md on
	movntss.

2008-01-14  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (opcode_modifiers): Add IntelSyntax.
	(operand_types): Add Mem.

	* i386-opc.h (IntelSyntax): New.
	* i386-opc.h (Mem): New.
	(Byte): Updated.
	(Opcode_Modifier_Max): Updated.
	(i386_opcode_modifier): Add intelsyntax.
	(i386_operand_type): Add mem.

	* i386-opc.tbl: Remove Reg16 from movnti.  Add sizes to more
	instructions.

	* i386-reg.tbl: Add size for accumulator.

	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2008-01-13  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.h (Byte): Fix a typo.

2008-01-12  H.J. Lu  <hongjiu.lu@intel.com>

	PR gas/5534
	* i386-gen.c (operand_type_init): Add Dword to
	OPERAND_TYPE_ACC32.  Add Qword to OPERAND_TYPE_ACC64.
	(opcode_modifiers): Remove CheckSize, Byte, Word, Dword,
	Qword and Xmmword.
	(operand_types): Add Byte, Word, Dword, Fword, Qword, Tbyte,
	Xmmword, Unspecified and Anysize.
	(set_bitfield): Make Mmword an alias of Qword.  Make Oword
	an alias of Xmmword.

	* i386-opc.h (CheckSize): Removed.
	(Byte): Updated.
	(Word): Likewise.
	(Dword): Likewise.
	(Qword): Likewise.
	(Xmmword): Likewise.
	(FWait): Updated.
	(OTMax): Likewise.
	(i386_opcode_modifier): Remove checksize, byte, word, dword,
	qword and xmmword.
	(Fword): New.
	(TBYTE): Likewise.
	(Unspecified): Likewise.
	(Anysize): Likewise.
	(i386_operand_type): Add byte, word, dword, fword, qword,
	tbyte xmmword, unspecified and anysize.

	* i386-opc.tbl: Updated to use Byte, Word, Dword, Fword, Qword,
	Tbyte, Xmmword, Unspecified and Anysize.

	* i386-reg.tbl: Add size for accumulator.

	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2008-01-10  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (REG_0F0E): Renamed to REG_0F0D.
	(REG_0F18): Updated.
	(reg_table): Updated.
	(dis386_twobyte): Updated.  Use "nopQ" on 0x19 to 0x1e.
	(twobyte_has_modrm): Set 1 for 0x19 to 0x1e.

2008-01-08  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (set_bitfield): Use fail () on error.

2008-01-08  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (lineno): New.
	(filename): Likewise.
	(set_bitfield): Report filename and line numer on error.
	(process_i386_opcodes): Set filename and update lineno.
	(process_i386_registers): Likewise.

2008-01-05  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (opcode_modifiers): Rename IntelMnemonic to
	ATTSyntax.

	* i386-opc.h (IntelMnemonic): Renamed to ..
	(ATTSyntax): This
	(Opcode_Modifier_Max): Updated.
	(i386_opcode_modifier): Remove intelmnemonic. Add attsyntax
	and intelsyntax.

	* i386-opc.tbl: Remove IntelMnemonic and update with ATTSyntax 
	on fsub, fubp, fsubr, fsubrp, div, fdivp, fdivr and fdivrp.
	* i386-tbl.h: Regenerated.

2008-01-04  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c: Update copyright to 2008.
	* i386-opc.h: Likewise.
	* i386-opc.tbl: Likewise.

	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2008-01-04  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.tbl: Add NoRex64 to extractps, movmskpd, movmskps,
	pextrb, pextrw, pinsrb, pinsrw and pmovmskb.
	* i386-tbl.h: Regenerated.

2008-01-03  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (cpu_flag_init): Remove CpuSSE4_1_Or_5 and
	CpuSSE4_2_Or_ABM.
	(cpu_flags): Likewise.

	* i386-opc.h (CpuSSE4_1_Or_5): Removed.
	(CpuSSE4_2_Or_ABM): Likewise.
	(CpuLM): Updated.
	(i386_cpu_flags): Remove cpusse4_1_or_5 and cpusse4_2_or_abm.

	* i386-opc.tbl: Replace CpuSSE4_1_Or_5, CpuSSE4_2_Or_ABM and
	Cpu686|CpuPadLock with CpuSSE4_1|CpuSSE5, CpuABM|CpuSSE4_2
	and CpuPadLock, respectively.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2008-01-03  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (opcode_modifiers): Remove No_xSuf.

	* i386-opc.h (No_xSuf): Removed.
	(CheckSize): Updated.

	* i386-tbl.h: Regenerated.

2008-01-02  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (cpu_flag_init): Add CpuSSE4_2_Or_ABM to
	CPU_AMDFAM10_FLAGS, CPU_SSE4_2_FLAGS, CpuABM and
	CPU_SSE5_FLAGS.
	(cpu_flags): Add CpuSSE4_2_Or_ABM.

	* i386-opc.h (CpuSSE4_2_Or_ABM): New.
	(CpuLM): Updated.
	(i386_cpu_flags): Add cpusse4_2_or_abm.

	* i386-opc.tbl: Use CpuSSE4_2_Or_ABM instead of
	CpuABM|CpuSSE4_2 on popcnt.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2008-01-02  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.h: Update comments.

2008-01-02  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (opcode_modifiers): Use Qword instead of QWord.
	* i386-opc.h: Likewise.
	* i386-opc.tbl: Likewise.

2008-01-02  H.J. Lu  <hongjiu.lu@intel.com>

	PR gas/5534
	* i386-gen.c (opcode_modifiers): Add No_xSuf, CheckSize,
	Byte, Word, Dword, QWord and Xmmword.

	* i386-opc.h (No_xSuf): New.
	(CheckSize): Likewise.
	(Byte): Likewise.
	(Word): Likewise.
	(Dword): Likewise.
	(QWord): Likewise.
	(Xmmword): Likewise.
	(FWait): Updated.
	(i386_opcode_modifier): Add No_xSuf, CheckSize, Byte, Word,
	Dword, QWord and Xmmword.

	* i386-opc.tbl: Add CheckSize|QWord to movq if IgnoreSize is
	used.
	* i386-tbl.h: Regenerated.

2008-01-02  Mark Kettenis  <kettenis@gnu.org>

	* m88k-dis.c (instructions): Fix fcvt.* instructions.
	From Miod Vallat.

For older changes see ChangeLog-2007
\f
Local Variables:
mode: change-log
left-margin: 8
fill-column: 74
version-control: never
End:
Commit	Line	Data
112b7c50 AK	1	2008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
	2
	3	* s390-dis.c (init_disasm): Evaluate disassembler_options.
	4	(print_s390_disassembler_options): New function.
	5	* disassemble.c (disassembler_usage): Invoke
	6	print_s390_disassembler_options.
	7
7ff42648 AK	8	2008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
	9
	10	* s390-mkopc.c (insertExpandedMnemonic): Expand string sizes
	11	of local variables used for mnemonic parsing: prefix, suffix and
	12	number.
	13
45a5551e AK	14	2008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
	15
	16	* s390-mkopc.c (s390_cond_ext_format): Add back the mnemonic
	17	extensions for conditional jumps (o, p, m, nz, z, nm, np, no).
	18	(s390_crb_extensions): New extensions table.
	19	(insertExpandedMnemonic): Handle '$' tag.
	20	* s390-opc.txt: Remove conditional jump variants which can now
	21	be expanded automatically.
	22	Replace '*' tag with '$' in the compare and branch instructions.
	23
06c8514a L	24	2008-04-07 H.J. Lu <hongjiu.lu@intel.com>
	25
	26	* i386-dis.c (PREFIX_VEX_38XX): Add a tab.
	27	(PREFIX_VEX_3AXX): Likewis.
	28
b122c285 L	29	2008-04-07 H.J. Lu <hongjiu.lu@intel.com>
	30
	31	* i386-opc.tbl: Remove 4 extra blank lines.
	32
594ab6a3 L	33	2008-04-04 H.J. Lu <hongjiu.lu@intel.com>
	34
	35	* i386-gen.c (cpu_flag_init): Replace CPU_CLMUL_FLAGS/CpuCLMUL
	36	with CPU_PCLMUL_FLAGS/CpuPCLMUL.
	37	(cpu_flags): Replace CpuCLMUL with CpuPCLMUL.
	38	* i386-opc.tbl: Likewise.
	39
	40	* i386-opc.h (CpuCLMUL): Renamed to ...
	41	(CpuPCLMUL): This.
	42	(CpuFMA): Updated.
	43	(i386_cpu_flags): Replace cpuclmul with cpupclmul.
	44
	45	* i386-init.h: Regenerated.
	46
c0f3af97 L	47	2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
	48
	49	* i386-dis.c (OP_E_register): New.
	50	(OP_E_memory): Likewise.
	51	(OP_VEX): Likewise.
	52	(OP_EX_Vex): Likewise.
	53	(OP_EX_VexW): Likewise.
	54	(OP_XMM_Vex): Likewise.
	55	(OP_XMM_VexW): Likewise.
	56	(OP_REG_VexI4): Likewise.
	57	(PCLMUL_Fixup): Likewise.
	58	(VEXI4_Fixup): Likewise.
	59	(VZERO_Fixup): Likewise.
	60	(VCMP_Fixup): Likewise.
	61	(VPERMIL2_Fixup): Likewise.
	62	(rex_original): Likewise.
	63	(rex_ignored): Likewise.
	64	(Mxmm): Likewise.
	65	(XMM): Likewise.
	66	(EXxmm): Likewise.
	67	(EXxmmq): Likewise.
	68	(EXymmq): Likewise.
	69	(Vex): Likewise.
	70	(Vex128): Likewise.
	71	(Vex256): Likewise.
	72	(VexI4): Likewise.
	73	(EXdVex): Likewise.
	74	(EXqVex): Likewise.
	75	(EXVexW): Likewise.
	76	(EXdVexW): Likewise.
	77	(EXqVexW): Likewise.
	78	(XMVex): Likewise.
	79	(XMVexW): Likewise.
	80	(XMVexI4): Likewise.
	81	(PCLMUL): Likewise.
	82	(VZERO): Likewise.
	83	(VCMP): Likewise.
	84	(VPERMIL2): Likewise.
	85	(xmm_mode): Likewise.
	86	(xmmq_mode): Likewise.
	87	(ymmq_mode): Likewise.
	88	(vex_mode): Likewise.
	89	(vex128_mode): Likewise.
	90	(vex256_mode): Likewise.
	91	(USE_VEX_C4_TABLE): Likewise.
	92	(USE_VEX_C5_TABLE): Likewise.
	93	(USE_VEX_LEN_TABLE): Likewise.
	94	(VEX_C4_TABLE): Likewise.
	95	(VEX_C5_TABLE): Likewise.
	96	(VEX_LEN_TABLE): Likewise.
	97	(REG_VEX_XX): Likewise.
	98	(MOD_VEX_XXX): Likewise.
	99	(PREFIX_0F38DB..PREFIX_0F38DF): Likewise.
	100	(PREFIX_0F3A44): Likewise.
	101	(PREFIX_0F3ADF): Likewise.
	102	(PREFIX_VEX_XXX): Likewise.
	103	(VEX_OF): Likewise.
	104	(VEX_OF38): Likewise.
	105	(VEX_OF3A): Likewise.
	106	(VEX_LEN_XXX): Likewise.
	107	(vex): Likewise.
	108	(need_vex): Likewise.
	109	(need_vex_reg): Likewise.
	110	(vex_i4_done): Likewise.
111	(vex_table): Likewise.
112	(vex_len_table): Likewise.
113	(OP_REG_VexI4): Likewise.
114	(vex_cmp_op): Likewise.
115	(pclmul_op): Likewise.
116	(vpermil2_op): Likewise.
117	(m_mode): Updated.
118	(es_reg): Likewise.
119	(PREFIX_0F38F0): Likewise.
120	(PREFIX_0F3A60): Likewise.
121	(reg_table): Add REG_VEX_71...REG_VEX_73 and REG_VEX_AE.
122	(prefix_table): Add PREFIX_0F38DB..PREFIX_0F38DF, PREFIX_0F3ADF
123	and PREFIX_VEX_XXX entries.
124	(x86_64_table): Use VEX_C4_TABLE and VEX_C5_TABLE.
125	(three_byte_table): Use PREFIX_0F38DB..PREFIX_0F38DF and
126	PREFIX_0F3ADF.
127	(mod_table): Use VEX_C4_TABLE, VEX_C5_TABLE and VEX_LEN_TABLE.
128	Add MOD_VEX_XXX entries.
129	(ckprefix): Initialize rex_original and rex_ignored. Store the
130	REX byte in rex_original.
131	(get_valid_dis386): Handle the implicit prefix in VEX prefix
132	bytes and USE_VEX_LEN_TABLE/USE_VEX_C4_TABLE/USE_VEX_C5_TABLE.
133	(print_insn): Set need_vex/need_vex_reg/vex_i4_done to 0 before
134	calling get_valid_dis386. Use rex_original and rex_ignored when
135	printing out REX.
136	(putop): Handle "XY".
137	(intel_operand_size): Handle VEX, xmm_mode, xmmq_mode and
138	ymmq_mode.
139	(OP_E_extended): Updated to use OP_E_register and
140	OP_E_memory.
141	(OP_XMM): Handle VEX.
142	(OP_EX): Likewise.
143	(XMM_Fixup): Likewise.
144	(CMP_Fixup): Use ARRAY_SIZE.
145
146	* i386-gen.c (cpu_flag_init): Add CpuAES, CPU_CLMUL_FLAGS,
147	CPU_FMA_FLAGS and CPU_AVX_FLAGS.
148	(operand_type_init): Add OPERAND_TYPE_REGYMM and
149	OPERAND_TYPE_VEX_IMM4.
150	(cpu_flags): Add CpuAVX, CpuAES, CpuCLMUL and CpuFMA.
151	(opcode_modifiers): Add Implicit1stXmm0, Vex, Vex256, VexNDD,
152	VexNDS, VexW0, VexW1, Vex0F, Vex0F38, Vex0F3A, Vex3Sources,
153	VexImmExt and SSE2AVX.
154	(operand_types): Add RegYMM, Ymmword and Vex_Imm4.
155
156	* i386-opc.h (CpuAVX): New.
157	(CpuAES): Likewise.
158	(CpuCLMUL): Likewise.
159	(CpuFMA): Likewise.
160	(Vex): Likewise.
161	(Vex256): Likewise.
162	(VexNDS): Likewise.
163	(VexNDD): Likewise.
164	(VexW0): Likewise.
165	(VexW1): Likewise.
166	(Vex0F): Likewise.
167	(Vex0F38): Likewise.
168	(Vex0F3A): Likewise.
169	(Vex3Sources): Likewise.
170	(VexImmExt): Likewise.
171	(SSE2AVX): Likewise.
172	(RegYMM): Likewise.
173	(Ymmword): Likewise.
174	(Vex_Imm4): Likewise.
175	(Implicit1stXmm0): Likewise.
176	(CpuXsave): Updated.
177	(CpuLM): Likewise.
178	(ByteOkIntel): Likewise.
179	(OldGcc): Likewise.
180	(Control): Likewise.
181	(Unspecified): Likewise.
182	(OTMax): Likewise.
183	(i386_cpu_flags): Add cpuavx, cpuaes, cpuclmul and cpufma.
184	(i386_opcode_modifier): Add implicit1stxmm0, vex, vex256,
185	vexnds, vexndd, vexw0, vexw1, vex0f, vex0f38, vex0f3a,
186	vex3sources, veximmext and sse2avx.
187	(i386_operand_type): Add regymm, ymmword and vex_imm4.
188
189	* i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions.
190
191	* i386-reg.tbl: Add AVX registers, ymm0..ymm15.
192
193	* i386-init.h: Regenerated.
194	* i386-tbl.h: Likewise.
195
b21c9cb4 BS	196	2008-03-26 Bernd Schmidt <bernd.schmidt@analog.com>
	197
	198	From Robin Getz <robin.getz@analog.com>
	199	* bfin-dis.c (bu32): Typedef.
	200	(enum const_forms_t): Add c_uimm32 and c_huimm32.
	201	(constant_formats[]): Add uimm32 and huimm16.
	202	(fmtconst_val): New.
	203	(uimm32): Define.
	204	(huimm32): Define.
	205	(imm16_val): Define.
	206	(luimm16_val): Define.
	207	(struct saved_state): Define.
	208	(GREG, DPREG, DREG, PREG, SPREG, FPREG, IREG, MREG, BREG, LREG,
	209	A0XREG, A0WREG, A1XREG, A1WREG,CCREG, LC0REG, LT0REG, LB0REG,
	210	LC1REG, LT1REG, LB1REG, RETSREG, PCREG): Define.
	211	(get_allreg): New.
	212	(decode_LDIMMhalf_0): Print out the whole register value.
	213
ee171c8f BS	214	From Jie Zhang <jie.zhang@analog.com>
	215	* bfin-dis.c (decode_dsp32mac_0): Decode (IU) option for
	216	multiply and multiply-accumulate to data register instruction.
	217
086134ec BS	218	* bfin-dis.c: (c_uimm4s4d, c_imm5d, c_imm7d, c_imm16d, c_uimm16s4d,
	219	c_imm32, c_huimm32e): Define.
	220	(constant_formats): Add flags for printing decimal, leading spaces, and
	221	exact symbols.
	222	(comment, parallel): Add global flags in all disassembly.
	223	(fmtconst): Take advantage of new flags, and print default in hex.
	224	(fmtconst_val): Likewise.
	225	(decode_macfunc): Be consistant with spaces, tabs, comments,
	226	capitalization in disassembly, fix minor coding style issues.
	227	(reg_names, amod0, amod1, amod0amod2, aligndir, get_allreg): Likewise.
	228	(decode_ProgCtrl_0, decode_PushPopMultiple_0, decode_CCflag_0,
	229	decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0,
	230	decode_REGMV_0, decode_ALU2op_0, decode_PTR2op_0, decode_LOGI2op_0,
	231	decode_COMP3op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
	232	decode_LDSTpmod_0, decode_dagMODim_0, decode_dagMODik_0,
	233	decode_dspLDST_0, decode_LDST_0, decode_LDSTiiFP_0, decode_LDSTii_0,
	234	decode_LoopSetup_0, decode_LDIMMhalf_0, decode_CALLa_0,
	235	decode_LDSTidxI_0, decode_linkage_0, decode_dsp32alu_0,
	236	decode_dsp32shift_0, decode_dsp32shiftimm_0, decode_pseudodbg_assert_0,
	237	_print_insn_bfin, print_insn_bfin): Likewise.
	238
58c85be7 RW	239	2008-03-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
	240
	241	* aclocal.m4: Regenerate.
	242	* configure: Likewise.
	243	* Makefile.in: Likewise.
	244
50e7d84b AM	245	2008-03-13 Alan Modra <amodra@bigpond.net.au>
	246
	247	* Makefile.am: Run "make dep-am".
	248	* Makefile.in: Regenerate.
	249	* configure: Regenerate.
	250
de866fcc AM	251	2008-03-07 Alan Modra <amodra@bigpond.net.au>
	252
	253	* ppc-opc.c (powerpc_opcodes): Order and format.
	254
28dbc079 L	255	2008-03-01 H.J. Lu <hongjiu.lu@intel.com>
	256
	257	* i386-opc.tbl: Allow 16-bit near indirect branches for x86-64.
	258	* i386-tbl.h: Regenerated.
	259
849830bd L	260	2008-02-23 H.J. Lu <hongjiu.lu@intel.com>
	261
	262	* i386-opc.tbl: Disallow 16-bit near indirect branches for
	263	x86-64.
	264	* i386-tbl.h: Regenerated.
	265
743ddb6b JB	266	2008-02-21 Jan Beulich <jbeulich@novell.com>
	267
	268	* i386-opc.tbl: Allow Dword for far indirect call. Allow Dword
	269	and Fword for far indirect jmp. Allow Reg16 and Word for near
	270	indirect jmp on x86-64. Disallow Fword for lcall.
	271	* i386-tbl.h: Re-generate.
	272
796d5313 NC	273	2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
	274
	275	* cr16-opc.c (cr16_num_optab): Defined
	276
65da13b5 L	277	2008-02-16 H.J. Lu <hongjiu.lu@intel.com>
	278
	279	* i386-gen.c (operand_type_init): Add OPERAND_TYPE_INOUTPORTREG.
	280	* i386-init.h: Regenerated.
	281
0e336180 NC	282	2008-02-14 Nick Clifton <nickc@redhat.com>
	283
	284	PR binutils/5524
	285	* configure.in (SHARED_LIBADD): Select the correct host specific
	286	file extension for shared libraries.
	287	* configure: Regenerate.
	288
b7240065 JB	289	2008-02-13 Jan Beulich <jbeulich@novell.com>
	290
	291	* i386-opc.h (RegFlat): New.
	292	* i386-reg.tbl (flat): Add.
	293	* i386-tbl.h: Re-generate.
	294
34b772a6 JB	295	2008-02-13 Jan Beulich <jbeulich@novell.com>
	296
	297	* i386-dis.c (a_mode): New.
	298	(cond_jump_mode): Adjust.
	299	(Ma): Change to a_mode.
	300	(intel_operand_size): Handle a_mode.
	301	* i386-opc.tbl: Allow Dword and Qword for bound.
	302	* i386-tbl.h: Re-generate.
	303
a60de03c JB	304	2008-02-13 Jan Beulich <jbeulich@novell.com>
	305
	306	* i386-gen.c (process_i386_registers): Process new fields.
	307	* i386-opc.h (reg_entry): Shrink reg_flags and reg_num to
	308	unsigned char. Add dw2_regnum and Dw2Inval.
	309	* i386-reg.tbl: Provide initializers for dw2_regnum. Add pseudo
	310	register names.
	311	* i386-tbl.h: Re-generate.
	312
f03fe4c1 L	313	2008-02-11 H.J. Lu <hongjiu.lu@intel.com>
f03fe4c1 L	314
4b6bc8eb	315	* i386-gen.c (cpu_flag_init): Add CPU_XSAVE_FLAGS.
f03fe4c1 L	316	* i386-init.h: Updated.
f03fe4c1 L	317
475a2301 L	318	2008-02-11 H.J. Lu <hongjiu.lu@intel.com>
	319
	320	* i386-gen.c (cpu_flags): Add CpuXsave.
	321
	322	* i386-opc.h (CpuXsave): New.
4b6bc8eb	323	(CpuLM): Updated.
475a2301 L	324	(i386_cpu_flags): Add cpuxsave.
	325
	326	* i386-dis.c (MOD_0FAE_REG_4): New.
	327	(RM_0F01_REG_2): Likewise.
	328	(MOD_0FAE_REG_5): Updated.
	329	(RM_0F01_REG_3): Likewise.
	330	(reg_table): Use MOD_0FAE_REG_4.
	331	(mod_table): Use RM_0F01_REG_2. Add MOD_0FAE_REG_4. Updated
	332	for xrstor.
	333	(rm_table): Add RM_0F01_REG_2.
	334
	335	* i386-opc.tbl: Add xsave, xrstor, xgetbv and xsetbv.
	336	* i386-init.h: Regenerated.
	337	* i386-tbl.h: Likewise.
	338
595785c6	339	2008-02-11 Jan Beulich <jbeulich@novell.com>
041179fc	340
595785c6 JB	341	* i386-opc.tbl: Remove Disp32S from CpuNo64 opcodes. Remove
	342	Disp16 from Cpu64 non-jump opcodes (including loop and j?cxz).
	343	* i386-tbl.h: Re-generate.
	344
bb8541b9 L	345	2008-02-04 H.J. Lu <hongjiu.lu@intel.com>
	346
	347	PR 5715
	348	* configure: Regenerated.
	349
57b592a3 AN	350	2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
	351
	352	* mips-dis.c: Update copyright.
	353	(mips_arch_choices): Add Octeon.
	354	* mips-opc.c: Update copyright.
	355	(IOCT): New macro.
	356	(mips_builtin_opcodes): Add Octeon instruction synciobdma.
	357
930bb4cf AM	358	2008-01-29 Alan Modra <amodra@bigpond.net.au>
	359
	360	* ppc-opc.c: Support optional L form mtmsr.
	361
82c18208 L	362	2008-01-24 H.J. Lu <hongjiu.lu@intel.com>
	363
	364	* i386-dis.c (OP_E_extended): Handle r12 like rsp.
	365
599121aa L	366	2008-01-23 H.J. Lu <hongjiu.lu@intel.com>
	367
	368	* i386-gen.c (cpu_flag_init): Add CpuLM to CPU_GENERIC64_FLAGS.
	369	* i386-init.h: Regenerated.
	370
80098f51 TG	371	2008-01-23 Tristan Gingold <gingold@adacore.com>
	372
	373	* ia64-dis.c (print_insn_ia64): Display symbolic name of ar.fcr,
	374	ar.eflag, ar.csd, ar.ssd, ar.cflg, ar.fsr, ar.fir and ar.fdr.
	375
115c7c25 L	376	2008-01-22 H.J. Lu <hongjiu.lu@intel.com>
	377
	378	* i386-gen.c (cpu_flag_init): Remove CpuMMX2.
	379	(cpu_flags): Likewise.
	380
	381	* i386-opc.h (CpuMMX2): Removed.
	382	(CpuSSE): Updated.
	383
	384	* i386-opc.tbl: Replace CpuMMX2 with CpuSSE\|Cpu3dnowA.
	385	* i386-init.h: Regenerated.
	386	* i386-tbl.h: Likewise.
	387
6305a203 L	388	2008-01-22 H.J. Lu <hongjiu.lu@intel.com>
	389
	390	* i386-gen.c (cpu_flag_init): Add CPU_VMX_FLAGS and
	391	CPU_SMX_FLAGS.
	392	* i386-init.h: Regenerated.
	393
fd07a1c8 L	394	2008-01-15 H.J. Lu <hongjiu.lu@intel.com>
	395
	396	* i386-opc.tbl: Use Qword on movddup.
	397	* i386-tbl.h: Regenerated.
	398
321fd21e L	399	2008-01-15 H.J. Lu <hongjiu.lu@intel.com>
	400
	401	* i386-opc.tbl: Put back 16bit movsx/movzx for AT&T syntax.
	402	* i386-tbl.h: Regenerated.
	403
4ee52178 L	404	2008-01-15 H.J. Lu <hongjiu.lu@intel.com>
	405
	406	* i386-dis.c (Mx): New.
	407	(PREFIX_0FC3): Likewise.
	408	(PREFIX_0FC7_REG_6): Updated.
	409	(dis386_twobyte): Use PREFIX_0FC3.
	410	(prefix_table): Add PREFIX_0FC3. Use Mq on movntq and movntsd.
	411	Use Mx on movntps, movntpd, movntdq and movntdqa. Use Md on
	412	movntss.
	413
5c07affc L	414	2008-01-14 H.J. Lu <hongjiu.lu@intel.com>
	415
	416	* i386-gen.c (opcode_modifiers): Add IntelSyntax.
	417	(operand_types): Add Mem.
	418
	419	* i386-opc.h (IntelSyntax): New.
	420	* i386-opc.h (Mem): New.
	421	(Byte): Updated.
	422	(Opcode_Modifier_Max): Updated.
	423	(i386_opcode_modifier): Add intelsyntax.
	424	(i386_operand_type): Add mem.
	425
	426	* i386-opc.tbl: Remove Reg16 from movnti. Add sizes to more
	427	instructions.
	428
	429	* i386-reg.tbl: Add size for accumulator.
	430
	431	* i386-init.h: Regenerated.
	432	* i386-tbl.h: Likewise.
	433
0d6a2f58 L	434	2008-01-13 H.J. Lu <hongjiu.lu@intel.com>
	435
	436	* i386-opc.h (Byte): Fix a typo.
	437
7d5e4556 L	438	2008-01-12 H.J. Lu <hongjiu.lu@intel.com>
	439
	440	PR gas/5534
	441	* i386-gen.c (operand_type_init): Add Dword to
	442	OPERAND_TYPE_ACC32. Add Qword to OPERAND_TYPE_ACC64.
	443	(opcode_modifiers): Remove CheckSize, Byte, Word, Dword,
	444	Qword and Xmmword.
	445	(operand_types): Add Byte, Word, Dword, Fword, Qword, Tbyte,
	446	Xmmword, Unspecified and Anysize.
	447	(set_bitfield): Make Mmword an alias of Qword. Make Oword
	448	an alias of Xmmword.
	449
	450	* i386-opc.h (CheckSize): Removed.
	451	(Byte): Updated.
	452	(Word): Likewise.
	453	(Dword): Likewise.
	454	(Qword): Likewise.
	455	(Xmmword): Likewise.
	456	(FWait): Updated.
	457	(OTMax): Likewise.
	458	(i386_opcode_modifier): Remove checksize, byte, word, dword,
	459	qword and xmmword.
	460	(Fword): New.
	461	(TBYTE): Likewise.
	462	(Unspecified): Likewise.
	463	(Anysize): Likewise.
	464	(i386_operand_type): Add byte, word, dword, fword, qword,
	465	tbyte xmmword, unspecified and anysize.
	466
	467	* i386-opc.tbl: Updated to use Byte, Word, Dword, Fword, Qword,
	468	Tbyte, Xmmword, Unspecified and Anysize.
	469
	470	* i386-reg.tbl: Add size for accumulator.
	471
	472	* i386-init.h: Regenerated.
	473	* i386-tbl.h: Likewise.
	474
b5b1fc4f L	475	2008-01-10 H.J. Lu <hongjiu.lu@intel.com>
	476
	477	* i386-dis.c (REG_0F0E): Renamed to REG_0F0D.
	478	(REG_0F18): Updated.
	479	(reg_table): Updated.
	480	(dis386_twobyte): Updated. Use "nopQ" on 0x19 to 0x1e.
	481	(twobyte_has_modrm): Set 1 for 0x19 to 0x1e.
	482
50e8458f L	483	2008-01-08 H.J. Lu <hongjiu.lu@intel.com>
	484
	485	* i386-gen.c (set_bitfield): Use fail () on error.
	486
3d4d5afa L	487	2008-01-08 H.J. Lu <hongjiu.lu@intel.com>
	488
	489	* i386-gen.c (lineno): New.
	490	(filename): Likewise.
	491	(set_bitfield): Report filename and line numer on error.
	492	(process_i386_opcodes): Set filename and update lineno.
	493	(process_i386_registers): Likewise.
	494
e1d4d893 L	495	2008-01-05 H.J. Lu <hongjiu.lu@intel.com>
	496
	497	* i386-gen.c (opcode_modifiers): Rename IntelMnemonic to
	498	ATTSyntax.
	499
	500	* i386-opc.h (IntelMnemonic): Renamed to ..
	501	(ATTSyntax): This
	502	(Opcode_Modifier_Max): Updated.
	503	(i386_opcode_modifier): Remove intelmnemonic. Add attsyntax
	504	and intelsyntax.
	505
	506	* i386-opc.tbl: Remove IntelMnemonic and update with ATTSyntax
	507	on fsub, fubp, fsubr, fsubrp, div, fdivp, fdivr and fdivrp.
	508	* i386-tbl.h: Regenerated.
	509
6f143e4d L	510	2008-01-04 H.J. Lu <hongjiu.lu@intel.com>
	511
	512	* i386-gen.c: Update copyright to 2008.
	513	* i386-opc.h: Likewise.
	514	* i386-opc.tbl: Likewise.
	515
	516	* i386-init.h: Regenerated.
	517	* i386-tbl.h: Likewise.
	518
c6add537 L	519	2008-01-04 H.J. Lu <hongjiu.lu@intel.com>
	520
	521	* i386-opc.tbl: Add NoRex64 to extractps, movmskpd, movmskps,
	522	pextrb, pextrw, pinsrb, pinsrw and pmovmskb.
	523	* i386-tbl.h: Regenerated.
	524
3629bb00 L	525	2008-01-03 H.J. Lu <hongjiu.lu@intel.com>
	526
	527	* i386-gen.c (cpu_flag_init): Remove CpuSSE4_1_Or_5 and
	528	CpuSSE4_2_Or_ABM.
	529	(cpu_flags): Likewise.
	530
	531	* i386-opc.h (CpuSSE4_1_Or_5): Removed.
	532	(CpuSSE4_2_Or_ABM): Likewise.
	533	(CpuLM): Updated.
	534	(i386_cpu_flags): Remove cpusse4_1_or_5 and cpusse4_2_or_abm.
	535
	536	* i386-opc.tbl: Replace CpuSSE4_1_Or_5, CpuSSE4_2_Or_ABM and
	537	Cpu686\|CpuPadLock with CpuSSE4_1\|CpuSSE5, CpuABM\|CpuSSE4_2
	538	and CpuPadLock, respectively.
	539	* i386-init.h: Regenerated.
	540	* i386-tbl.h: Likewise.
	541
24995bd6 L	542	2008-01-03 H.J. Lu <hongjiu.lu@intel.com>
	543
	544	* i386-gen.c (opcode_modifiers): Remove No_xSuf.
	545
	546	* i386-opc.h (No_xSuf): Removed.
	547	(CheckSize): Updated.
	548
	549	* i386-tbl.h: Regenerated.
	550
e0329a22 L	551	2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
	552
	553	* i386-gen.c (cpu_flag_init): Add CpuSSE4_2_Or_ABM to
	554	CPU_AMDFAM10_FLAGS, CPU_SSE4_2_FLAGS, CpuABM and
	555	CPU_SSE5_FLAGS.
	556	(cpu_flags): Add CpuSSE4_2_Or_ABM.
	557
	558	* i386-opc.h (CpuSSE4_2_Or_ABM): New.
	559	(CpuLM): Updated.
	560	(i386_cpu_flags): Add cpusse4_2_or_abm.
	561
	562	* i386-opc.tbl: Use CpuSSE4_2_Or_ABM instead of
	563	CpuABM\|CpuSSE4_2 on popcnt.
	564	* i386-init.h: Regenerated.
	565	* i386-tbl.h: Likewise.
	566
f2a9c676 L	567	2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
	568
	569	* i386-opc.h: Update comments.
	570
d978b5be L	571	2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
	572
	573	* i386-gen.c (opcode_modifiers): Use Qword instead of QWord.
	574	* i386-opc.h: Likewise.
	575	* i386-opc.tbl: Likewise.
	576
582d5edd L	577	2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
	578
	579	PR gas/5534
	580	* i386-gen.c (opcode_modifiers): Add No_xSuf, CheckSize,
	581	Byte, Word, Dword, QWord and Xmmword.
	582
	583	* i386-opc.h (No_xSuf): New.
	584	(CheckSize): Likewise.
	585	(Byte): Likewise.
	586	(Word): Likewise.
	587	(Dword): Likewise.
	588	(QWord): Likewise.
	589	(Xmmword): Likewise.
	590	(FWait): Updated.
	591	(i386_opcode_modifier): Add No_xSuf, CheckSize, Byte, Word,
	592	Dword, QWord and Xmmword.
	593
	594	* i386-opc.tbl: Add CheckSize\|QWord to movq if IgnoreSize is
	595	used.
	596	* i386-tbl.h: Regenerated.
	597
3fe15143 MK	598	2008-01-02 Mark Kettenis <kettenis@gnu.org>
	599
	600	* m88k-dis.c (instructions): Fix fcvt.* instructions.
	601	From Miod Vallat.
	602
6c7ac64e	603	For older changes see ChangeLog-2007
252b5132 RH	604	\f
252b5132 RH	605	Local Variables:
2f6d2f85 NC	606	mode: change-log
	607	left-margin: 8
	608	fill-column: 74
252b5132 RH	609	version-control: never
252b5132 RH	610	End: